1 #ifndef __SPARC64_PCI_H
2 #define __SPARC64_PCI_H
9 /* Can be used to override the logic in pci_scan_bus for skipping
10 * already-configured bus numbers - to be used for buggy BIOSes
11 * or architectures with incomplete PCI setup by the loader.
13 #define pcibios_assign_all_busses() 0
14 #define pcibios_scan_all_fns(a, b) 0
16 #define PCIBIOS_MIN_IO 0UL
17 #define PCIBIOS_MIN_MEM 0UL
19 #define PCI_IRQ_NONE 0xffffffff
21 #define PCI_CACHE_LINE_BYTES 64
23 static inline void pcibios_set_master(struct pci_dev *dev)
25 /* No special bus mastering setup handling */
28 static inline void pcibios_penalize_isa_irq(int irq, int active)
30 /* We don't do dynamic PCI IRQ allocation */
33 /* Dynamic DMA mapping stuff.
36 /* The PCI address space does not equal the physical memory
37 * address space. The networking and block device layers use
38 * this boolean for bounce buffer decisions.
40 #define PCI_DMA_BUS_IS_PHYS (0)
42 #include <asm/scatterlist.h>
46 struct pci_iommu_ops {
47 void *(*alloc_consistent)(struct pci_dev *, size_t, dma_addr_t *, gfp_t);
48 void (*free_consistent)(struct pci_dev *, size_t, void *, dma_addr_t);
49 dma_addr_t (*map_single)(struct pci_dev *, void *, size_t, int);
50 void (*unmap_single)(struct pci_dev *, dma_addr_t, size_t, int);
51 int (*map_sg)(struct pci_dev *, struct scatterlist *, int, int);
52 void (*unmap_sg)(struct pci_dev *, struct scatterlist *, int, int);
53 void (*dma_sync_single_for_cpu)(struct pci_dev *, dma_addr_t, size_t, int);
54 void (*dma_sync_sg_for_cpu)(struct pci_dev *, struct scatterlist *, int, int);
57 extern const struct pci_iommu_ops *pci_iommu_ops;
59 /* Allocate and map kernel buffer using consistent mode DMA for a device.
60 * hwdev should be valid struct pci_dev pointer for PCI devices.
62 static inline void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size, dma_addr_t *dma_handle)
64 return pci_iommu_ops->alloc_consistent(hwdev, size, dma_handle, GFP_ATOMIC);
67 /* Free and unmap a consistent DMA buffer.
68 * cpu_addr is what was returned from pci_alloc_consistent,
69 * size must be the same as what as passed into pci_alloc_consistent,
70 * and likewise dma_addr must be the same as what *dma_addrp was set to.
72 * References to the memory and mappings associated with cpu_addr/dma_addr
73 * past this call are illegal.
75 static inline void pci_free_consistent(struct pci_dev *hwdev, size_t size, void *vaddr, dma_addr_t dma_handle)
77 return pci_iommu_ops->free_consistent(hwdev, size, vaddr, dma_handle);
80 /* Map a single buffer of the indicated size for DMA in streaming mode.
81 * The 32-bit bus address to use is returned.
83 * Once the device is given the dma address, the device owns this memory
84 * until either pci_unmap_single or pci_dma_sync_single_for_cpu is performed.
86 static inline dma_addr_t pci_map_single(struct pci_dev *hwdev, void *ptr, size_t size, int direction)
88 return pci_iommu_ops->map_single(hwdev, ptr, size, direction);
91 /* Unmap a single streaming mode DMA translation. The dma_addr and size
92 * must match what was provided for in a previous pci_map_single call. All
93 * other usages are undefined.
95 * After this call, reads by the cpu to the buffer are guaranteed to see
96 * whatever the device wrote there.
98 static inline void pci_unmap_single(struct pci_dev *hwdev, dma_addr_t dma_addr, size_t size, int direction)
100 pci_iommu_ops->unmap_single(hwdev, dma_addr, size, direction);
103 /* No highmem on sparc64, plus we have an IOMMU, so mapping pages is easy. */
104 #define pci_map_page(dev, page, off, size, dir) \
105 pci_map_single(dev, (page_address(page) + (off)), size, dir)
106 #define pci_unmap_page(dev,addr,sz,dir) pci_unmap_single(dev,addr,sz,dir)
108 /* pci_unmap_{single,page} is not a nop, thus... */
109 #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \
110 dma_addr_t ADDR_NAME;
111 #define DECLARE_PCI_UNMAP_LEN(LEN_NAME) \
113 #define pci_unmap_addr(PTR, ADDR_NAME) \
115 #define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) \
116 (((PTR)->ADDR_NAME) = (VAL))
117 #define pci_unmap_len(PTR, LEN_NAME) \
119 #define pci_unmap_len_set(PTR, LEN_NAME, VAL) \
120 (((PTR)->LEN_NAME) = (VAL))
122 /* Map a set of buffers described by scatterlist in streaming
123 * mode for DMA. This is the scatter-gather version of the
124 * above pci_map_single interface. Here the scatter gather list
125 * elements are each tagged with the appropriate dma address
126 * and length. They are obtained via sg_dma_{address,length}(SG).
128 * NOTE: An implementation may be able to use a smaller number of
129 * DMA address/length pairs than there are SG table elements.
130 * (for example via virtual mapping capabilities)
131 * The routine returns the number of addr/length pairs actually
132 * used, at most nents.
134 * Device ownership issues as mentioned above for pci_map_single are
137 static inline int pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sg, int nents, int direction)
139 return pci_iommu_ops->map_sg(hwdev, sg, nents, direction);
142 /* Unmap a set of streaming mode DMA translations.
143 * Again, cpu read rules concerning calls here are the same as for
144 * pci_unmap_single() above.
146 static inline void pci_unmap_sg(struct pci_dev *hwdev, struct scatterlist *sg, int nhwents, int direction)
148 pci_iommu_ops->unmap_sg(hwdev, sg, nhwents, direction);
151 /* Make physical memory consistent for a single
152 * streaming mode DMA translation after a transfer.
154 * If you perform a pci_map_single() but wish to interrogate the
155 * buffer using the cpu, yet do not wish to teardown the PCI dma
156 * mapping, you must call this function before doing so. At the
157 * next point you give the PCI dma address back to the card, you
158 * must first perform a pci_dma_sync_for_device, and then the
159 * device again owns the buffer.
161 static inline void pci_dma_sync_single_for_cpu(struct pci_dev *hwdev, dma_addr_t dma_handle, size_t size, int direction)
163 pci_iommu_ops->dma_sync_single_for_cpu(hwdev, dma_handle, size, direction);
167 pci_dma_sync_single_for_device(struct pci_dev *hwdev, dma_addr_t dma_handle,
168 size_t size, int direction)
170 /* No flushing needed to sync cpu writes to the device. */
171 BUG_ON(direction == PCI_DMA_NONE);
174 /* Make physical memory consistent for a set of streaming
175 * mode DMA translations after a transfer.
177 * The same as pci_dma_sync_single_* but for a scatter-gather list,
178 * same rules and usage.
180 static inline void pci_dma_sync_sg_for_cpu(struct pci_dev *hwdev, struct scatterlist *sg, int nelems, int direction)
182 pci_iommu_ops->dma_sync_sg_for_cpu(hwdev, sg, nelems, direction);
186 pci_dma_sync_sg_for_device(struct pci_dev *hwdev, struct scatterlist *sg,
187 int nelems, int direction)
189 /* No flushing needed to sync cpu writes to the device. */
190 BUG_ON(direction == PCI_DMA_NONE);
193 /* Return whether the given PCI device DMA address mask can
194 * be supported properly. For example, if your device can
195 * only drive the low 24-bits during PCI bus mastering, then
196 * you would pass 0x00ffffff as the mask to this function.
198 extern int pci_dma_supported(struct pci_dev *hwdev, u64 mask);
200 /* PCI IOMMU mapping bypass support. */
202 /* PCI 64-bit addressing works for all slots on all controller
203 * types on sparc64. However, it requires that the device
204 * can drive enough of the 64 bits.
206 #define PCI64_REQUIRED_MASK (~(dma64_addr_t)0)
207 #define PCI64_ADDR_BASE 0xfffc000000000000UL
209 /* Usage of the pci_dac_foo interfaces is only valid if this
212 #define pci_dac_dma_supported(pci_dev, mask) \
213 ((((mask) & PCI64_REQUIRED_MASK) == PCI64_REQUIRED_MASK) ? 1 : 0)
215 static inline dma64_addr_t
216 pci_dac_page_to_dma(struct pci_dev *pdev, struct page *page, unsigned long offset, int direction)
218 return (PCI64_ADDR_BASE +
219 __pa(page_address(page)) + offset);
222 static inline struct page *
223 pci_dac_dma_to_page(struct pci_dev *pdev, dma64_addr_t dma_addr)
225 unsigned long paddr = (dma_addr & PAGE_MASK) - PCI64_ADDR_BASE;
227 return virt_to_page(__va(paddr));
230 static inline unsigned long
231 pci_dac_dma_to_offset(struct pci_dev *pdev, dma64_addr_t dma_addr)
233 return (dma_addr & ~PAGE_MASK);
237 pci_dac_dma_sync_single_for_cpu(struct pci_dev *pdev, dma64_addr_t dma_addr, size_t len, int direction)
239 /* DAC cycle addressing does not make use of the
240 * PCI controller's streaming cache, so nothing to do.
245 pci_dac_dma_sync_single_for_device(struct pci_dev *pdev, dma64_addr_t dma_addr, size_t len, int direction)
247 /* DAC cycle addressing does not make use of the
248 * PCI controller's streaming cache, so nothing to do.
252 #define PCI_DMA_ERROR_CODE (~(dma_addr_t)0x0)
254 static inline int pci_dma_mapping_error(dma_addr_t dma_addr)
256 return (dma_addr == PCI_DMA_ERROR_CODE);
260 static inline void pci_dma_burst_advice(struct pci_dev *pdev,
261 enum pci_dma_burst_strategy *strat,
262 unsigned long *strategy_parameter)
264 unsigned long cacheline_size;
267 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
269 cacheline_size = 1024;
271 cacheline_size = (int) byte * 4;
273 *strat = PCI_DMA_BURST_BOUNDARY;
274 *strategy_parameter = cacheline_size;
278 /* Return the index of the PCI controller for device PDEV. */
280 extern int pci_domain_nr(struct pci_bus *bus);
281 static inline int pci_proc_domain(struct pci_bus *bus)
286 /* Platform support for /proc/bus/pci/X/Y mmap()s. */
288 #define HAVE_PCI_MMAP
289 #define HAVE_ARCH_PCI_GET_UNMAPPED_AREA
290 #define get_pci_unmapped_area get_fb_unmapped_area
292 extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
293 enum pci_mmap_state mmap_state,
297 pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
298 struct resource *res);
301 pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
302 struct pci_bus_region *region);
304 extern struct resource *pcibios_select_root(struct pci_dev *, struct resource *);
306 static inline void pcibios_add_platform_entries(struct pci_dev *dev)
310 static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
316 extern struct device_node *pci_device_to_OF_node(struct pci_dev *pdev);
318 #endif /* __KERNEL__ */
320 #endif /* __SPARC64_PCI_H */