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   1 /*
   2  * linux/arch/arm/mach-omap1/fpga.c
   3  *
   4  * Interrupt handler for OMAP-1510 Innovator FPGA
   5  *
   6  * Copyright (C) 2001 RidgeRun, Inc.
   7  * Author: Greg Lonnon <glonnon@ridgerun.com>
   8  *
   9  * Copyright (C) 2002 MontaVista Software, Inc.
  10  *
  11  * Separated FPGA interrupts from innovator1510.c and cleaned up for 2.6
  12  * Copyright (C) 2004 Nokia Corporation by Tony Lindrgen <tony@atomide.com>
  13  *
  14  * This program is free software; you can redistribute it and/or modify
  15  * it under the terms of the GNU General Public License version 2 as
  16  * published by the Free Software Foundation.
  17  */
  18
  19 #include <linux/types.h>
  20 #include <linux/init.h>
  21 #include <linux/kernel.h>
  22 #include <linux/device.h>
  23 #include <linux/errno.h>
  24
  25 #include <asm/hardware.h>
  26 #include <asm/io.h>
  27 #include <asm/irq.h>
  28 #include <asm/mach/irq.h>
  29
  30 #include <asm/arch/fpga.h>
  31 #include <asm/arch/gpio.h>
  32
  33 static void fpga_mask_irq(unsigned int irq)
  34 {
  35         irq -= OMAP1510_IH_FPGA_BASE;
  36
  37         if (irq < 8)
  38                 __raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_LO)
  39                               & ~(1 << irq)), OMAP1510_FPGA_IMR_LO);
  40         else if (irq < 16)
  41                 __raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_HI)
  42                               & ~(1 << (irq - 8))), OMAP1510_FPGA_IMR_HI);
  43         else
  44                 __raw_writeb((__raw_readb(INNOVATOR_FPGA_IMR2)
  45                               & ~(1 << (irq - 16))), INNOVATOR_FPGA_IMR2);
  46 }
  47
  48
  49 static inline u32 get_fpga_unmasked_irqs(void)
  50 {
  51         return
  52                 ((__raw_readb(OMAP1510_FPGA_ISR_LO) &
  53                   __raw_readb(OMAP1510_FPGA_IMR_LO))) |
  54                 ((__raw_readb(OMAP1510_FPGA_ISR_HI) &
  55                   __raw_readb(OMAP1510_FPGA_IMR_HI)) << 8) |
  56                 ((__raw_readb(INNOVATOR_FPGA_ISR2) &
  57                   __raw_readb(INNOVATOR_FPGA_IMR2)) << 16);
  58 }
  59
  60
  61 static void fpga_ack_irq(unsigned int irq)
  62 {
  63         /* Don't need to explicitly ACK FPGA interrupts */
  64 }
  65
  66 static void fpga_unmask_irq(unsigned int irq)
  67 {
  68         irq -= OMAP1510_IH_FPGA_BASE;
  69
  70         if (irq < 8)
  71                 __raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_LO) | (1 << irq)),
  72                      OMAP1510_FPGA_IMR_LO);
  73         else if (irq < 16)
  74                 __raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_HI)
  75                               | (1 << (irq - 8))), OMAP1510_FPGA_IMR_HI);
  76         else
  77                 __raw_writeb((__raw_readb(INNOVATOR_FPGA_IMR2)
  78                               | (1 << (irq - 16))), INNOVATOR_FPGA_IMR2);
  79 }
  80
  81 static void fpga_mask_ack_irq(unsigned int irq)
  82 {
  83         fpga_mask_irq(irq);
  84         fpga_ack_irq(irq);
  85 }
  86
  87 void innovator_fpga_IRQ_demux(unsigned int irq, struct irqdesc *desc,
  88                               struct pt_regs *regs)
  89 {
  90         struct irqdesc *d;
  91         u32 stat;
  92         int fpga_irq;
  93
  94         stat = get_fpga_unmasked_irqs();
  95
  96         if (!stat)
  97                 return;
  98
  99         for (fpga_irq = OMAP1510_IH_FPGA_BASE;
 100              (fpga_irq < (OMAP1510_IH_FPGA_BASE + NR_FPGA_IRQS)) && stat;
 101              fpga_irq++, stat >>= 1) {
 102                 if (stat & 1) {
 103                         d = irq_desc + fpga_irq;
 104                         desc_handle_irq(fpga_irq, d, regs);
 105                 }
 106         }
 107 }
 108
 109 static struct irqchip omap_fpga_irq_ack = {
 110         .ack            = fpga_mask_ack_irq,
 111         .mask           = fpga_mask_irq,
 112         .unmask         = fpga_unmask_irq,
 113 };
 114
 115
 116 static struct irqchip omap_fpga_irq = {
 117         .ack            = fpga_ack_irq,
 118         .mask           = fpga_mask_irq,
 119         .unmask         = fpga_unmask_irq,
 120 };
 121
 122 /*
 123  * All of the FPGA interrupt request inputs except for the touchscreen are
 124  * edge-sensitive; the touchscreen is level-sensitive.  The edge-sensitive
 125  * interrupts are acknowledged as a side-effect of reading the interrupt
 126  * status register from the FPGA.  The edge-sensitive interrupt inputs
 127  * cause a problem with level interrupt requests, such as Ethernet.  The
 128  * problem occurs when a level interrupt request is asserted while its
 129  * interrupt input is masked in the FPGA, which results in a missed
 130  * interrupt.
 131  *
 132  * In an attempt to workaround the problem with missed interrupts, the
 133  * mask_ack routine for all of the FPGA interrupts has been changed from
 134  * fpga_mask_ack_irq() to fpga_ack_irq() so that the specific FPGA interrupt
 135  * being serviced is left unmasked.  We can do this because the FPGA cascade
 136  * interrupt is installed with the IRQF_DISABLED flag, which leaves all
 137  * interrupts masked at the CPU while an FPGA interrupt handler executes.
 138  *
 139  * Limited testing indicates that this workaround appears to be effective
 140  * for the smc9194 Ethernet driver used on the Innovator.  It should work
 141  * on other FPGA interrupts as well, but any drivers that explicitly mask
 142  * interrupts at the interrupt controller via disable_irq/enable_irq
 143  * could pose a problem.
 144  */
 145 void omap1510_fpga_init_irq(void)
 146 {
 147         int i;
 148
 149         __raw_writeb(0, OMAP1510_FPGA_IMR_LO);
 150         __raw_writeb(0, OMAP1510_FPGA_IMR_HI);
 151         __raw_writeb(0, INNOVATOR_FPGA_IMR2);
 152
 153         for (i = OMAP1510_IH_FPGA_BASE; i < (OMAP1510_IH_FPGA_BASE + NR_FPGA_IRQS); i++) {
 154
 155                 if (i == OMAP1510_INT_FPGA_TS) {
 156                         /*
 157                          * The touchscreen interrupt is level-sensitive, so
 158                          * we'll use the regular mask_ack routine for it.
 159                          */
 160                         set_irq_chip(i, &omap_fpga_irq_ack);
 161                 }
 162                 else {
 163                         /*
 164                          * All FPGA interrupts except the touchscreen are
 165                          * edge-sensitive, so we won't mask them.
 166                          */
 167                         set_irq_chip(i, &omap_fpga_irq);
 168                 }
 169
 170                 set_irq_handler(i, do_edge_IRQ);
 171                 set_irq_flags(i, IRQF_VALID);
 172         }
 173
 174         /*
 175          * The FPGA interrupt line is connected to GPIO13. Claim this pin for
 176          * the ARM.
 177          *
 178          * NOTE: For general GPIO/MPUIO access and interrupts, please see
 179          * gpio.[ch]
 180          */
 181         omap_request_gpio(13);
 182         omap_set_gpio_direction(13, 1);
 183         set_irq_type(OMAP_GPIO_IRQ(13), IRQT_RISING);
 184         set_irq_chained_handler(OMAP1510_INT_FPGA, innovator_fpga_IRQ_demux);
 185 }
 186
 187 EXPORT_SYMBOL(omap1510_fpga_init_irq);