git.oblomov.eu Git - linux-2.6/blob - drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/i2c.h>
  28 #include "drmP.h"
  29 #include "intel_drv.h"
  30 #include "i915_drm.h"
  31 #include "i915_drv.h"
  32
  33 #include "drm_crtc_helper.h"
  34
  35 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  36
  37 typedef struct {
  38     /* given values */
  39     int n;
  40     int m1, m2;
  41     int p1, p2;
  42     /* derived values */
  43     int dot;
  44     int vco;
  45     int m;
  46     int p;
  47 } intel_clock_t;
  48
  49 typedef struct {
  50     int min, max;
  51 } intel_range_t;
  52
  53 typedef struct {
  54     int dot_limit;
  55     int p2_slow, p2_fast;
  56 } intel_p2_t;
  57
  58 #define INTEL_P2_NUM                  2
  59 typedef struct intel_limit intel_limit_t;
  60 struct intel_limit {
  61     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  62     intel_p2_t      p2;
  63     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  64                       int, int, intel_clock_t *);
  65 };
  66
  67 #define I8XX_DOT_MIN              25000
  68 #define I8XX_DOT_MAX             350000
  69 #define I8XX_VCO_MIN             930000
  70 #define I8XX_VCO_MAX            1400000
  71 #define I8XX_N_MIN                    3
  72 #define I8XX_N_MAX                   16
  73 #define I8XX_M_MIN                   96
  74 #define I8XX_M_MAX                  140
  75 #define I8XX_M1_MIN                  18
  76 #define I8XX_M1_MAX                  26
  77 #define I8XX_M2_MIN                   6
  78 #define I8XX_M2_MAX                  16
  79 #define I8XX_P_MIN                    4
  80 #define I8XX_P_MAX                  128
  81 #define I8XX_P1_MIN                   2
  82 #define I8XX_P1_MAX                  33
  83 #define I8XX_P1_LVDS_MIN              1
  84 #define I8XX_P1_LVDS_MAX              6
  85 #define I8XX_P2_SLOW                  4
  86 #define I8XX_P2_FAST                  2
  87 #define I8XX_P2_LVDS_SLOW             14
  88 #define I8XX_P2_LVDS_FAST             14 /* No fast option */
  89 #define I8XX_P2_SLOW_LIMIT       165000
  90
  91 #define I9XX_DOT_MIN              20000
  92 #define I9XX_DOT_MAX             400000
  93 #define I9XX_VCO_MIN            1400000
  94 #define I9XX_VCO_MAX            2800000
  95 #define IGD_VCO_MIN             1700000
  96 #define IGD_VCO_MAX             3500000
  97 #define I9XX_N_MIN                    1
  98 #define I9XX_N_MAX                    6
  99 /* IGD's Ncounter is a ring counter */
 100 #define IGD_N_MIN                     3
 101 #define IGD_N_MAX                     6
 102 #define I9XX_M_MIN                   70
 103 #define I9XX_M_MAX                  120
 104 #define IGD_M_MIN                     2
 105 #define IGD_M_MAX                   256
 106 #define I9XX_M1_MIN                  10
 107 #define I9XX_M1_MAX                  22
 108 #define I9XX_M2_MIN                   5
 109 #define I9XX_M2_MAX                   9
 110 /* IGD M1 is reserved, and must be 0 */
 111 #define IGD_M1_MIN                    0
 112 #define IGD_M1_MAX                    0
 113 #define IGD_M2_MIN                    0
 114 #define IGD_M2_MAX                    254
 115 #define I9XX_P_SDVO_DAC_MIN           5
 116 #define I9XX_P_SDVO_DAC_MAX          80
 117 #define I9XX_P_LVDS_MIN               7
 118 #define I9XX_P_LVDS_MAX              98
 119 #define IGD_P_LVDS_MIN                7
 120 #define IGD_P_LVDS_MAX               112
 121 #define I9XX_P1_MIN                   1
 122 #define I9XX_P1_MAX                   8
 123 #define I9XX_P2_SDVO_DAC_SLOW                10
 124 #define I9XX_P2_SDVO_DAC_FAST                 5
 125 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
 126 #define I9XX_P2_LVDS_SLOW                    14
 127 #define I9XX_P2_LVDS_FAST                     7
 128 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
 129
 130 #define INTEL_LIMIT_I8XX_DVO_DAC    0
 131 #define INTEL_LIMIT_I8XX_LVDS       1
 132 #define INTEL_LIMIT_I9XX_SDVO_DAC   2
 133 #define INTEL_LIMIT_I9XX_LVDS       3
 134 #define INTEL_LIMIT_G4X_SDVO        4
 135 #define INTEL_LIMIT_G4X_HDMI_DAC   5
 136 #define INTEL_LIMIT_G4X_SINGLE_CHANNEL_LVDS   6
 137 #define INTEL_LIMIT_G4X_DUAL_CHANNEL_LVDS   7
 138 #define INTEL_LIMIT_IGD_SDVO_DAC    8
 139 #define INTEL_LIMIT_IGD_LVDS        9
 140
 141 /*The parameter is for SDVO on G4x platform*/
 142 #define G4X_DOT_SDVO_MIN           25000
 143 #define G4X_DOT_SDVO_MAX           270000
 144 #define G4X_VCO_MIN                1750000
 145 #define G4X_VCO_MAX                3500000
 146 #define G4X_N_SDVO_MIN             1
 147 #define G4X_N_SDVO_MAX             4
 148 #define G4X_M_SDVO_MIN             104
 149 #define G4X_M_SDVO_MAX             138
 150 #define G4X_M1_SDVO_MIN            17
 151 #define G4X_M1_SDVO_MAX            23
 152 #define G4X_M2_SDVO_MIN            5
 153 #define G4X_M2_SDVO_MAX            11
 154 #define G4X_P_SDVO_MIN             10
 155 #define G4X_P_SDVO_MAX             30
 156 #define G4X_P1_SDVO_MIN            1
 157 #define G4X_P1_SDVO_MAX            3
 158 #define G4X_P2_SDVO_SLOW           10
 159 #define G4X_P2_SDVO_FAST           10
 160 #define G4X_P2_SDVO_LIMIT          270000
 161
 162 /*The parameter is for HDMI_DAC on G4x platform*/
 163 #define G4X_DOT_HDMI_DAC_MIN           22000
 164 #define G4X_DOT_HDMI_DAC_MAX           400000
 165 #define G4X_N_HDMI_DAC_MIN             1
 166 #define G4X_N_HDMI_DAC_MAX             4
 167 #define G4X_M_HDMI_DAC_MIN             104
 168 #define G4X_M_HDMI_DAC_MAX             138
 169 #define G4X_M1_HDMI_DAC_MIN            16
 170 #define G4X_M1_HDMI_DAC_MAX            23
 171 #define G4X_M2_HDMI_DAC_MIN            5
 172 #define G4X_M2_HDMI_DAC_MAX            11
 173 #define G4X_P_HDMI_DAC_MIN             5
 174 #define G4X_P_HDMI_DAC_MAX             80
 175 #define G4X_P1_HDMI_DAC_MIN            1
 176 #define G4X_P1_HDMI_DAC_MAX            8
 177 #define G4X_P2_HDMI_DAC_SLOW           10
 178 #define G4X_P2_HDMI_DAC_FAST           5
 179 #define G4X_P2_HDMI_DAC_LIMIT          165000
 180
 181 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
 182 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
 183 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
 184 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
 185 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
 186 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
 187 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
 188 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
 189 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
 190 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
 191 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
 192 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
 193 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
 194 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
 195 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
 196 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
 197 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
 198 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
 199
 200 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
 201 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
 202 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
 203 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
 204 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
 205 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
 206 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
 207 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
 208 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
 209 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
 210 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
 211 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
 212 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
 213 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
 214 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
 215 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
 216 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
 217 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
 218
 219 static bool
 220 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 221                     int target, int refclk, intel_clock_t *best_clock);
 222 static bool
 223 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 224                         int target, int refclk, intel_clock_t *best_clock);
 225
 226 static const intel_limit_t intel_limits[] = {
 227     { /* INTEL_LIMIT_I8XX_DVO_DAC */
 228         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 229         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 230         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 231         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 232         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 233         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 234         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 235         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
 236         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 237                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
 238         .find_pll = intel_find_best_PLL,
 239     },
 240     { /* INTEL_LIMIT_I8XX_LVDS */
 241         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 242         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 243         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 244         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 245         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 246         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 247         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 248         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
 249         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 250                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
 251         .find_pll = intel_find_best_PLL,
 252     },
 253     { /* INTEL_LIMIT_I9XX_SDVO_DAC */
 254         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 255         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 256         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 257         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 258         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 259         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 260         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 261         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 262         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 263                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 264         .find_pll = intel_find_best_PLL,
 265     },
 266     { /* INTEL_LIMIT_I9XX_LVDS */
 267         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 268         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 269         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 270         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 271         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 272         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 273         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
 274         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 275         /* The single-channel range is 25-112Mhz, and dual-channel
 276          * is 80-224Mhz.  Prefer single channel as much as possible.
 277          */
 278         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 279                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
 280         .find_pll = intel_find_best_PLL,
 281     },
 282     /* below parameter and function is for G4X Chipset Family*/
 283     { /* INTEL_LIMIT_G4X_SDVO */
 284         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
 285         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 286         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
 287         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
 288         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
 289         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
 290         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
 291         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
 292         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
 293                  .p2_slow = G4X_P2_SDVO_SLOW,
 294                  .p2_fast = G4X_P2_SDVO_FAST
 295         },
 296         .find_pll = intel_g4x_find_best_PLL,
 297     },
 298     { /* INTEL_LIMIT_G4X_HDMI_DAC */
 299         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
 300         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 301         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
 302         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
 303         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
 304         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
 305         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
 306         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
 307         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
 308                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
 309                  .p2_fast = G4X_P2_HDMI_DAC_FAST
 310         },
 311         .find_pll = intel_g4x_find_best_PLL,
 312     },
 313     { /* INTEL_LIMIT_G4X_SINGLE_CHANNEL_LVDS */
 314         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
 315                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
 316         .vco = { .min = G4X_VCO_MIN,
 317                  .max = G4X_VCO_MAX },
 318         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
 319                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
 320         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
 321                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
 322         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
 323                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
 324         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
 325                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
 326         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
 327                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
 328         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
 329                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
 330         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
 331                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
 332                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
 333         },
 334         .find_pll = intel_g4x_find_best_PLL,
 335     },
 336     { /* INTEL_LIMIT_G4X_DUAL_CHANNEL_LVDS */
 337         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
 338                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
 339         .vco = { .min = G4X_VCO_MIN,
 340                  .max = G4X_VCO_MAX },
 341         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
 342                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
 343         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
 344                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
 345         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
 346                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
 347         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
 348                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
 349         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
 350                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
 351         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
 352                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
 353         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
 354                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
 355                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
 356         },
 357         .find_pll = intel_g4x_find_best_PLL,
 358     },
 359     { /* INTEL_LIMIT_IGD_SDVO */
 360         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
 361         .vco = { .min = IGD_VCO_MIN,            .max = IGD_VCO_MAX },
 362         .n   = { .min = IGD_N_MIN,              .max = IGD_N_MAX },
 363         .m   = { .min = IGD_M_MIN,              .max = IGD_M_MAX },
 364         .m1  = { .min = IGD_M1_MIN,             .max = IGD_M1_MAX },
 365         .m2  = { .min = IGD_M2_MIN,             .max = IGD_M2_MAX },
 366         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 367         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 368         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 369                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 370     },
 371     { /* INTEL_LIMIT_IGD_LVDS */
 372         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 373         .vco = { .min = IGD_VCO_MIN,            .max = IGD_VCO_MAX },
 374         .n   = { .min = IGD_N_MIN,              .max = IGD_N_MAX },
 375         .m   = { .min = IGD_M_MIN,              .max = IGD_M_MAX },
 376         .m1  = { .min = IGD_M1_MIN,             .max = IGD_M1_MAX },
 377         .m2  = { .min = IGD_M2_MIN,             .max = IGD_M2_MAX },
 378         .p   = { .min = IGD_P_LVDS_MIN, .max = IGD_P_LVDS_MAX },
 379         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 380         /* IGD only supports single-channel mode. */
 381         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 382                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
 383     },
 384
 385 };
 386
 387 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 388 {
 389         struct drm_device *dev = crtc->dev;
 390         struct drm_i915_private *dev_priv = dev->dev_private;
 391         const intel_limit_t *limit;
 392
 393         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 394                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 395                     LVDS_CLKB_POWER_UP)
 396                         /* LVDS with dual channel */
 397                         limit = &intel_limits
 398                                         [INTEL_LIMIT_G4X_DUAL_CHANNEL_LVDS];
 399                 else
 400                         /* LVDS with dual channel */
 401                         limit = &intel_limits
 402                                         [INTEL_LIMIT_G4X_SINGLE_CHANNEL_LVDS];
 403         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 404                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 405                 limit = &intel_limits[INTEL_LIMIT_G4X_HDMI_DAC];
 406         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 407                 limit = &intel_limits[INTEL_LIMIT_G4X_SDVO];
 408         } else /* The option is for other outputs */
 409                 limit = &intel_limits[INTEL_LIMIT_I9XX_SDVO_DAC];
 410
 411         return limit;
 412 }
 413
 414 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
 415 {
 416         struct drm_device *dev = crtc->dev;
 417         const intel_limit_t *limit;
 418
 419         if (IS_G4X(dev)) {
 420                 limit = intel_g4x_limit(crtc);
 421         } else if (IS_I9XX(dev) && !IS_IGD(dev)) {
 422                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 423                         limit = &intel_limits[INTEL_LIMIT_I9XX_LVDS];
 424                 else
 425                         limit = &intel_limits[INTEL_LIMIT_I9XX_SDVO_DAC];
 426         } else if (IS_IGD(dev)) {
 427                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 428                         limit = &intel_limits[INTEL_LIMIT_IGD_LVDS];
 429                 else
 430                         limit = &intel_limits[INTEL_LIMIT_IGD_SDVO_DAC];
 431         } else {
 432                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 433                         limit = &intel_limits[INTEL_LIMIT_I8XX_LVDS];
 434                 else
 435                         limit = &intel_limits[INTEL_LIMIT_I8XX_DVO_DAC];
 436         }
 437         return limit;
 438 }
 439
 440 /* m1 is reserved as 0 in IGD, n is a ring counter */
 441 static void igd_clock(int refclk, intel_clock_t *clock)
 442 {
 443         clock->m = clock->m2 + 2;
 444         clock->p = clock->p1 * clock->p2;
 445         clock->vco = refclk * clock->m / clock->n;
 446         clock->dot = clock->vco / clock->p;
 447 }
 448
 449 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 450 {
 451         if (IS_IGD(dev)) {
 452                 igd_clock(refclk, clock);
 453                 return;
 454         }
 455         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 456         clock->p = clock->p1 * clock->p2;
 457         clock->vco = refclk * clock->m / (clock->n + 2);
 458         clock->dot = clock->vco / clock->p;
 459 }
 460
 461 /**
 462  * Returns whether any output on the specified pipe is of the specified type
 463  */
 464 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
 465 {
 466     struct drm_device *dev = crtc->dev;
 467     struct drm_mode_config *mode_config = &dev->mode_config;
 468     struct drm_connector *l_entry;
 469
 470     list_for_each_entry(l_entry, &mode_config->connector_list, head) {
 471             if (l_entry->encoder &&
 472                 l_entry->encoder->crtc == crtc) {
 473                     struct intel_output *intel_output = to_intel_output(l_entry);
 474                     if (intel_output->type == type)
 475                             return true;
 476             }
 477     }
 478     return false;
 479 }
 480
 481 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 482 /**
 483  * Returns whether the given set of divisors are valid for a given refclk with
 484  * the given connectors.
 485  */
 486
 487 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
 488 {
 489         const intel_limit_t *limit = intel_limit (crtc);
 490         struct drm_device *dev = crtc->dev;
 491
 492         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 493                 INTELPllInvalid ("p1 out of range\n");
 494         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 495                 INTELPllInvalid ("p out of range\n");
 496         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 497                 INTELPllInvalid ("m2 out of range\n");
 498         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 499                 INTELPllInvalid ("m1 out of range\n");
 500         if (clock->m1 <= clock->m2 && !IS_IGD(dev))
 501                 INTELPllInvalid ("m1 <= m2\n");
 502         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 503                 INTELPllInvalid ("m out of range\n");
 504         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 505                 INTELPllInvalid ("n out of range\n");
 506         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 507                 INTELPllInvalid ("vco out of range\n");
 508         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 509          * connector, etc., rather than just a single range.
 510          */
 511         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 512                 INTELPllInvalid ("dot out of range\n");
 513
 514         return true;
 515 }
 516
 517 static bool
 518 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 519                     int target, int refclk, intel_clock_t *best_clock)
 520
 521 {
 522         struct drm_device *dev = crtc->dev;
 523         struct drm_i915_private *dev_priv = dev->dev_private;
 524         intel_clock_t clock;
 525         int err = target;
 526
 527         if (IS_I9XX(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 528             (I915_READ(LVDS) & LVDS_PORT_EN) != 0) {
 529                 /*
 530                  * For LVDS, if the panel is on, just rely on its current
 531                  * settings for dual-channel.  We haven't figured out how to
 532                  * reliably set up different single/dual channel state, if we
 533                  * even can.
 534                  */
 535                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 536                     LVDS_CLKB_POWER_UP)
 537                         clock.p2 = limit->p2.p2_fast;
 538                 else
 539                         clock.p2 = limit->p2.p2_slow;
 540         } else {
 541                 if (target < limit->p2.dot_limit)
 542                         clock.p2 = limit->p2.p2_slow;
 543                 else
 544                         clock.p2 = limit->p2.p2_fast;
 545         }
 546
 547         memset (best_clock, 0, sizeof (*best_clock));
 548
 549         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 550                 for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max; clock.m2++) {
 551                         /* m1 is always 0 in IGD */
 552                         if (clock.m2 >= clock.m1 && !IS_IGD(dev))
 553                                 break;
 554                         for (clock.n = limit->n.min; clock.n <= limit->n.max;
 555                              clock.n++) {
 556                                 for (clock.p1 = limit->p1.min;
 557                                      clock.p1 <= limit->p1.max; clock.p1++) {
 558                                         int this_err;
 559
 560                                         intel_clock(dev, refclk, &clock);
 561
 562                                         if (!intel_PLL_is_valid(crtc, &clock))
 563                                                 continue;
 564
 565                                         this_err = abs(clock.dot - target);
 566                                         if (this_err < err) {
 567                                                 *best_clock = clock;
 568                                                 err = this_err;
 569                                         }
 570                                 }
 571                         }
 572                 }
 573         }
 574
 575         return (err != target);
 576 }
 577
 578 static bool
 579 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 580                         int target, int refclk, intel_clock_t *best_clock)
 581 {
 582         struct drm_device *dev = crtc->dev;
 583         struct drm_i915_private *dev_priv = dev->dev_private;
 584         intel_clock_t clock;
 585         int max_n;
 586         bool found;
 587         /* approximately equals target * 0.00488 */
 588         int err_most = (target >> 8) + (target >> 10);
 589         found = false;
 590
 591         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 592                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 593                     LVDS_CLKB_POWER_UP)
 594                         clock.p2 = limit->p2.p2_fast;
 595                 else
 596                         clock.p2 = limit->p2.p2_slow;
 597         } else {
 598                 if (target < limit->p2.dot_limit)
 599                         clock.p2 = limit->p2.p2_slow;
 600                 else
 601                         clock.p2 = limit->p2.p2_fast;
 602         }
 603
 604         memset(best_clock, 0, sizeof(*best_clock));
 605         max_n = limit->n.max;
 606         /* based on hardware requriment prefer smaller n to precision */
 607         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 608                 /* based on hardware requirment prefere larger m1,m2, p1 */
 609                 for (clock.m1 = limit->m1.max;
 610                      clock.m1 >= limit->m1.min; clock.m1--) {
 611                         for (clock.m2 = limit->m2.max;
 612                              clock.m2 >= limit->m2.min; clock.m2--) {
 613                                 for (clock.p1 = limit->p1.max;
 614                                      clock.p1 >= limit->p1.min; clock.p1--) {
 615                                         int this_err;
 616
 617                                         intel_clock(dev, refclk, &clock);
 618                                         if (!intel_PLL_is_valid(crtc, &clock))
 619                                                 continue;
 620                                         this_err = abs(clock.dot - target) ;
 621                                         if (this_err < err_most) {
 622                                                 *best_clock = clock;
 623                                                 err_most = this_err;
 624                                                 max_n = clock.n;
 625                                                 found = true;
 626                                         }
 627                                 }
 628                         }
 629                 }
 630         }
 631
 632         return found;
 633 }
 634
 635 void
 636 intel_wait_for_vblank(struct drm_device *dev)
 637 {
 638         /* Wait for 20ms, i.e. one cycle at 50hz. */
 639         udelay(20000);
 640 }
 641
 642 static int
 643 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
 644                     struct drm_framebuffer *old_fb)
 645 {
 646         struct drm_device *dev = crtc->dev;
 647         struct drm_i915_private *dev_priv = dev->dev_private;
 648         struct drm_i915_master_private *master_priv;
 649         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 650         struct intel_framebuffer *intel_fb;
 651         struct drm_i915_gem_object *obj_priv;
 652         struct drm_gem_object *obj;
 653         int pipe = intel_crtc->pipe;
 654         unsigned long Start, Offset;
 655         int dspbase = (pipe == 0 ? DSPAADDR : DSPBADDR);
 656         int dspsurf = (pipe == 0 ? DSPASURF : DSPBSURF);
 657         int dspstride = (pipe == 0) ? DSPASTRIDE : DSPBSTRIDE;
 658         int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
 659         u32 dspcntr, alignment;
 660         int ret;
 661
 662         /* no fb bound */
 663         if (!crtc->fb) {
 664                 DRM_DEBUG("No FB bound\n");
 665                 return 0;
 666         }
 667
 668         switch (pipe) {
 669         case 0:
 670         case 1:
 671                 break;
 672         default:
 673                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
 674                 return -EINVAL;
 675         }
 676
 677         intel_fb = to_intel_framebuffer(crtc->fb);
 678         obj = intel_fb->obj;
 679         obj_priv = obj->driver_private;
 680
 681         switch (obj_priv->tiling_mode) {
 682         case I915_TILING_NONE:
 683                 alignment = 64 * 1024;
 684                 break;
 685         case I915_TILING_X:
 686                 /* pin() will align the object as required by fence */
 687                 alignment = 0;
 688                 break;
 689         case I915_TILING_Y:
 690                 /* FIXME: Is this true? */
 691                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
 692                 return -EINVAL;
 693         default:
 694                 BUG();
 695         }
 696
 697         mutex_lock(&dev->struct_mutex);
 698         ret = i915_gem_object_pin(intel_fb->obj, alignment);
 699         if (ret != 0) {
 700                 mutex_unlock(&dev->struct_mutex);
 701                 return ret;
 702         }
 703
 704         ret = i915_gem_object_set_to_gtt_domain(intel_fb->obj, 1);
 705         if (ret != 0) {
 706                 i915_gem_object_unpin(intel_fb->obj);
 707                 mutex_unlock(&dev->struct_mutex);
 708                 return ret;
 709         }
 710
 711         dspcntr = I915_READ(dspcntr_reg);
 712         /* Mask out pixel format bits in case we change it */
 713         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
 714         switch (crtc->fb->bits_per_pixel) {
 715         case 8:
 716                 dspcntr |= DISPPLANE_8BPP;
 717                 break;
 718         case 16:
 719                 if (crtc->fb->depth == 15)
 720                         dspcntr |= DISPPLANE_15_16BPP;
 721                 else
 722                         dspcntr |= DISPPLANE_16BPP;
 723                 break;
 724         case 24:
 725         case 32:
 726                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
 727                 break;
 728         default:
 729                 DRM_ERROR("Unknown color depth\n");
 730                 i915_gem_object_unpin(intel_fb->obj);
 731                 mutex_unlock(&dev->struct_mutex);
 732                 return -EINVAL;
 733         }
 734         I915_WRITE(dspcntr_reg, dspcntr);
 735
 736         Start = obj_priv->gtt_offset;
 737         Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
 738
 739         DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
 740         I915_WRITE(dspstride, crtc->fb->pitch);
 741         if (IS_I965G(dev)) {
 742                 I915_WRITE(dspbase, Offset);
 743                 I915_READ(dspbase);
 744                 I915_WRITE(dspsurf, Start);
 745                 I915_READ(dspsurf);
 746         } else {
 747                 I915_WRITE(dspbase, Start + Offset);
 748                 I915_READ(dspbase);
 749         }
 750
 751         intel_wait_for_vblank(dev);
 752
 753         if (old_fb) {
 754                 intel_fb = to_intel_framebuffer(old_fb);
 755                 i915_gem_object_unpin(intel_fb->obj);
 756         }
 757         mutex_unlock(&dev->struct_mutex);
 758
 759         if (!dev->primary->master)
 760                 return 0;
 761
 762         master_priv = dev->primary->master->driver_priv;
 763         if (!master_priv->sarea_priv)
 764                 return 0;
 765
 766         if (pipe) {
 767                 master_priv->sarea_priv->pipeB_x = x;
 768                 master_priv->sarea_priv->pipeB_y = y;
 769         } else {
 770                 master_priv->sarea_priv->pipeA_x = x;
 771                 master_priv->sarea_priv->pipeA_y = y;
 772         }
 773
 774         return 0;
 775 }
 776
 777
 778
 779 /**
 780  * Sets the power management mode of the pipe and plane.
 781  *
 782  * This code should probably grow support for turning the cursor off and back
 783  * on appropriately at the same time as we're turning the pipe off/on.
 784  */
 785 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
 786 {
 787         struct drm_device *dev = crtc->dev;
 788         struct drm_i915_master_private *master_priv;
 789         struct drm_i915_private *dev_priv = dev->dev_private;
 790         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 791         int pipe = intel_crtc->pipe;
 792         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
 793         int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
 794         int dspbase_reg = (pipe == 0) ? DSPAADDR : DSPBADDR;
 795         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
 796         u32 temp;
 797         bool enabled;
 798
 799         /* XXX: When our outputs are all unaware of DPMS modes other than off
 800          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
 801          */
 802         switch (mode) {
 803         case DRM_MODE_DPMS_ON:
 804         case DRM_MODE_DPMS_STANDBY:
 805         case DRM_MODE_DPMS_SUSPEND:
 806                 /* Enable the DPLL */
 807                 temp = I915_READ(dpll_reg);
 808                 if ((temp & DPLL_VCO_ENABLE) == 0) {
 809                         I915_WRITE(dpll_reg, temp);
 810                         I915_READ(dpll_reg);
 811                         /* Wait for the clocks to stabilize. */
 812                         udelay(150);
 813                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
 814                         I915_READ(dpll_reg);
 815                         /* Wait for the clocks to stabilize. */
 816                         udelay(150);
 817                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
 818                         I915_READ(dpll_reg);
 819                         /* Wait for the clocks to stabilize. */
 820                         udelay(150);
 821                 }
 822
 823                 /* Enable the pipe */
 824                 temp = I915_READ(pipeconf_reg);
 825                 if ((temp & PIPEACONF_ENABLE) == 0)
 826                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
 827
 828                 /* Enable the plane */
 829                 temp = I915_READ(dspcntr_reg);
 830                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
 831                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
 832                         /* Flush the plane changes */
 833                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
 834                 }
 835
 836                 intel_crtc_load_lut(crtc);
 837
 838                 /* Give the overlay scaler a chance to enable if it's on this pipe */
 839                 //intel_crtc_dpms_video(crtc, true); TODO
 840         break;
 841         case DRM_MODE_DPMS_OFF:
 842                 /* Give the overlay scaler a chance to disable if it's on this pipe */
 843                 //intel_crtc_dpms_video(crtc, FALSE); TODO
 844
 845                 /* Disable the VGA plane that we never use */
 846                 I915_WRITE(VGACNTRL, VGA_DISP_DISABLE);
 847
 848                 /* Disable display plane */
 849                 temp = I915_READ(dspcntr_reg);
 850                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
 851                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
 852                         /* Flush the plane changes */
 853                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
 854                         I915_READ(dspbase_reg);
 855                 }
 856
 857                 if (!IS_I9XX(dev)) {
 858                         /* Wait for vblank for the disable to take effect */
 859                         intel_wait_for_vblank(dev);
 860                 }
 861
 862                 /* Next, disable display pipes */
 863                 temp = I915_READ(pipeconf_reg);
 864                 if ((temp & PIPEACONF_ENABLE) != 0) {
 865                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
 866                         I915_READ(pipeconf_reg);
 867                 }
 868
 869                 /* Wait for vblank for the disable to take effect. */
 870                 intel_wait_for_vblank(dev);
 871
 872                 temp = I915_READ(dpll_reg);
 873                 if ((temp & DPLL_VCO_ENABLE) != 0) {
 874                         I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
 875                         I915_READ(dpll_reg);
 876                 }
 877
 878                 /* Wait for the clocks to turn off. */
 879                 udelay(150);
 880                 break;
 881         }
 882
 883         if (!dev->primary->master)
 884                 return;
 885
 886         master_priv = dev->primary->master->driver_priv;
 887         if (!master_priv->sarea_priv)
 888                 return;
 889
 890         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
 891
 892         switch (pipe) {
 893         case 0:
 894                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
 895                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
 896                 break;
 897         case 1:
 898                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
 899                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
 900                 break;
 901         default:
 902                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
 903                 break;
 904         }
 905
 906         intel_crtc->dpms_mode = mode;
 907 }
 908
 909 static void intel_crtc_prepare (struct drm_crtc *crtc)
 910 {
 911         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
 912         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
 913 }
 914
 915 static void intel_crtc_commit (struct drm_crtc *crtc)
 916 {
 917         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
 918         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
 919 }
 920
 921 void intel_encoder_prepare (struct drm_encoder *encoder)
 922 {
 923         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
 924         /* lvds has its own version of prepare see intel_lvds_prepare */
 925         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
 926 }
 927
 928 void intel_encoder_commit (struct drm_encoder *encoder)
 929 {
 930         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
 931         /* lvds has its own version of commit see intel_lvds_commit */
 932         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
 933 }
 934
 935 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
 936                                   struct drm_display_mode *mode,
 937                                   struct drm_display_mode *adjusted_mode)
 938 {
 939         return true;
 940 }
 941
 942
 943 /** Returns the core display clock speed for i830 - i945 */
 944 static int intel_get_core_clock_speed(struct drm_device *dev)
 945 {
 946
 947         /* Core clock values taken from the published datasheets.
 948          * The 830 may go up to 166 Mhz, which we should check.
 949          */
 950         if (IS_I945G(dev))
 951                 return 400000;
 952         else if (IS_I915G(dev))
 953                 return 333000;
 954         else if (IS_I945GM(dev) || IS_845G(dev) || IS_IGDGM(dev))
 955                 return 200000;
 956         else if (IS_I915GM(dev)) {
 957                 u16 gcfgc = 0;
 958
 959                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
 960
 961                 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
 962                         return 133000;
 963                 else {
 964                         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
 965                         case GC_DISPLAY_CLOCK_333_MHZ:
 966                                 return 333000;
 967                         default:
 968                         case GC_DISPLAY_CLOCK_190_200_MHZ:
 969                                 return 190000;
 970                         }
 971                 }
 972         } else if (IS_I865G(dev))
 973                 return 266000;
 974         else if (IS_I855(dev)) {
 975                 u16 hpllcc = 0;
 976                 /* Assume that the hardware is in the high speed state.  This
 977                  * should be the default.
 978                  */
 979                 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
 980                 case GC_CLOCK_133_200:
 981                 case GC_CLOCK_100_200:
 982                         return 200000;
 983                 case GC_CLOCK_166_250:
 984                         return 250000;
 985                 case GC_CLOCK_100_133:
 986                         return 133000;
 987                 }
 988         } else /* 852, 830 */
 989                 return 133000;
 990
 991         return 0; /* Silence gcc warning */
 992 }
 993
 994
 995 /**
 996  * Return the pipe currently connected to the panel fitter,
 997  * or -1 if the panel fitter is not present or not in use
 998  */
 999 static int intel_panel_fitter_pipe (struct drm_device *dev)
1000 {
1001         struct drm_i915_private *dev_priv = dev->dev_private;
1002         u32  pfit_control;
1003
1004         /* i830 doesn't have a panel fitter */
1005         if (IS_I830(dev))
1006                 return -1;
1007
1008         pfit_control = I915_READ(PFIT_CONTROL);
1009
1010         /* See if the panel fitter is in use */
1011         if ((pfit_control & PFIT_ENABLE) == 0)
1012                 return -1;
1013
1014         /* 965 can place panel fitter on either pipe */
1015         if (IS_I965G(dev))
1016                 return (pfit_control >> 29) & 0x3;
1017
1018         /* older chips can only use pipe 1 */
1019         return 1;
1020 }
1021
1022 static int intel_crtc_mode_set(struct drm_crtc *crtc,
1023                                struct drm_display_mode *mode,
1024                                struct drm_display_mode *adjusted_mode,
1025                                int x, int y,
1026                                struct drm_framebuffer *old_fb)
1027 {
1028         struct drm_device *dev = crtc->dev;
1029         struct drm_i915_private *dev_priv = dev->dev_private;
1030         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1031         int pipe = intel_crtc->pipe;
1032         int fp_reg = (pipe == 0) ? FPA0 : FPB0;
1033         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
1034         int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
1035         int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
1036         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1037         int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1038         int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1039         int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1040         int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1041         int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1042         int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1043         int dspsize_reg = (pipe == 0) ? DSPASIZE : DSPBSIZE;
1044         int dsppos_reg = (pipe == 0) ? DSPAPOS : DSPBPOS;
1045         int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
1046         int refclk, num_outputs = 0;
1047         intel_clock_t clock;
1048         u32 dpll = 0, fp = 0, dspcntr, pipeconf;
1049         bool ok, is_sdvo = false, is_dvo = false;
1050         bool is_crt = false, is_lvds = false, is_tv = false;
1051         struct drm_mode_config *mode_config = &dev->mode_config;
1052         struct drm_connector *connector;
1053         const intel_limit_t *limit;
1054         int ret;
1055
1056         drm_vblank_pre_modeset(dev, pipe);
1057
1058         list_for_each_entry(connector, &mode_config->connector_list, head) {
1059                 struct intel_output *intel_output = to_intel_output(connector);
1060
1061                 if (!connector->encoder || connector->encoder->crtc != crtc)
1062                         continue;
1063
1064                 switch (intel_output->type) {
1065                 case INTEL_OUTPUT_LVDS:
1066                         is_lvds = true;
1067                         break;
1068                 case INTEL_OUTPUT_SDVO:
1069                 case INTEL_OUTPUT_HDMI:
1070                         is_sdvo = true;
1071                         if (intel_output->needs_tv_clock)
1072                                 is_tv = true;
1073                         break;
1074                 case INTEL_OUTPUT_DVO:
1075                         is_dvo = true;
1076                         break;
1077                 case INTEL_OUTPUT_TVOUT:
1078                         is_tv = true;
1079                         break;
1080                 case INTEL_OUTPUT_ANALOG:
1081                         is_crt = true;
1082                         break;
1083                 }
1084
1085                 num_outputs++;
1086         }
1087
1088         if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2) {
1089                 refclk = dev_priv->lvds_ssc_freq * 1000;
1090                 DRM_DEBUG("using SSC reference clock of %d MHz\n", refclk / 1000);
1091         } else if (IS_I9XX(dev)) {
1092                 refclk = 96000;
1093         } else {
1094                 refclk = 48000;
1095         }
1096
1097         /*
1098          * Returns a set of divisors for the desired target clock with the given
1099          * refclk, or FALSE.  The returned values represent the clock equation:
1100          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
1101          */
1102         limit = intel_limit(crtc);
1103         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
1104         if (!ok) {
1105                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
1106                 return -EINVAL;
1107         }
1108
1109         if (IS_IGD(dev))
1110                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
1111         else
1112                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
1113
1114         dpll = DPLL_VGA_MODE_DIS;
1115         if (IS_I9XX(dev)) {
1116                 if (is_lvds)
1117                         dpll |= DPLLB_MODE_LVDS;
1118                 else
1119                         dpll |= DPLLB_MODE_DAC_SERIAL;
1120                 if (is_sdvo) {
1121                         dpll |= DPLL_DVO_HIGH_SPEED;
1122                         if (IS_I945G(dev) || IS_I945GM(dev)) {
1123                                 int sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
1124                                 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
1125                         }
1126                 }
1127
1128                 /* compute bitmask from p1 value */
1129                 if (IS_IGD(dev))
1130                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_IGD;
1131                 else
1132                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
1133                 switch (clock.p2) {
1134                 case 5:
1135                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
1136                         break;
1137                 case 7:
1138                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
1139                         break;
1140                 case 10:
1141                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
1142                         break;
1143                 case 14:
1144                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
1145                         break;
1146                 }
1147                 if (IS_I965G(dev))
1148                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
1149         } else {
1150                 if (is_lvds) {
1151                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
1152                 } else {
1153                         if (clock.p1 == 2)
1154                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
1155                         else
1156                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
1157                         if (clock.p2 == 4)
1158                                 dpll |= PLL_P2_DIVIDE_BY_4;
1159                 }
1160         }
1161
1162         if (is_sdvo && is_tv)
1163                 dpll |= PLL_REF_INPUT_TVCLKINBC;
1164         else if (is_tv)
1165                 /* XXX: just matching BIOS for now */
1166                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
1167                 dpll |= 3;
1168         else if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2)
1169                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
1170         else
1171                 dpll |= PLL_REF_INPUT_DREFCLK;
1172
1173         /* setup pipeconf */
1174         pipeconf = I915_READ(pipeconf_reg);
1175
1176         /* Set up the display plane register */
1177         dspcntr = DISPPLANE_GAMMA_ENABLE;
1178
1179         if (pipe == 0)
1180                 dspcntr |= DISPPLANE_SEL_PIPE_A;
1181         else
1182                 dspcntr |= DISPPLANE_SEL_PIPE_B;
1183
1184         if (pipe == 0 && !IS_I965G(dev)) {
1185                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
1186                  * core speed.
1187                  *
1188                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
1189                  * pipe == 0 check?
1190                  */
1191                 if (mode->clock > intel_get_core_clock_speed(dev) * 9 / 10)
1192                         pipeconf |= PIPEACONF_DOUBLE_WIDE;
1193                 else
1194                         pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
1195         }
1196
1197         dspcntr |= DISPLAY_PLANE_ENABLE;
1198         pipeconf |= PIPEACONF_ENABLE;
1199         dpll |= DPLL_VCO_ENABLE;
1200
1201
1202         /* Disable the panel fitter if it was on our pipe */
1203         if (intel_panel_fitter_pipe(dev) == pipe)
1204                 I915_WRITE(PFIT_CONTROL, 0);
1205
1206         DRM_DEBUG("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
1207         drm_mode_debug_printmodeline(mode);
1208
1209
1210         if (dpll & DPLL_VCO_ENABLE) {
1211                 I915_WRITE(fp_reg, fp);
1212                 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
1213                 I915_READ(dpll_reg);
1214                 udelay(150);
1215         }
1216
1217         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
1218          * This is an exception to the general rule that mode_set doesn't turn
1219          * things on.
1220          */
1221         if (is_lvds) {
1222                 u32 lvds = I915_READ(LVDS);
1223
1224                 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT;
1225                 /* Set the B0-B3 data pairs corresponding to whether we're going to
1226                  * set the DPLLs for dual-channel mode or not.
1227                  */
1228                 if (clock.p2 == 7)
1229                         lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
1230                 else
1231                         lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
1232
1233                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
1234                  * appropriately here, but we need to look more thoroughly into how
1235                  * panels behave in the two modes.
1236                  */
1237
1238                 I915_WRITE(LVDS, lvds);
1239                 I915_READ(LVDS);
1240         }
1241
1242         I915_WRITE(fp_reg, fp);
1243         I915_WRITE(dpll_reg, dpll);
1244         I915_READ(dpll_reg);
1245         /* Wait for the clocks to stabilize. */
1246         udelay(150);
1247
1248         if (IS_I965G(dev)) {
1249                 int sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
1250                 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
1251                            ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
1252         } else {
1253                 /* write it again -- the BIOS does, after all */
1254                 I915_WRITE(dpll_reg, dpll);
1255         }
1256         I915_READ(dpll_reg);
1257         /* Wait for the clocks to stabilize. */
1258         udelay(150);
1259
1260         I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
1261                    ((adjusted_mode->crtc_htotal - 1) << 16));
1262         I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
1263                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
1264         I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
1265                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
1266         I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
1267                    ((adjusted_mode->crtc_vtotal - 1) << 16));
1268         I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
1269                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
1270         I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
1271                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
1272         /* pipesrc and dspsize control the size that is scaled from, which should
1273          * always be the user's requested size.
1274          */
1275         I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1));
1276         I915_WRITE(dsppos_reg, 0);
1277         I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
1278         I915_WRITE(pipeconf_reg, pipeconf);
1279         I915_READ(pipeconf_reg);
1280
1281         intel_wait_for_vblank(dev);
1282
1283         I915_WRITE(dspcntr_reg, dspcntr);
1284
1285         /* Flush the plane changes */
1286         ret = intel_pipe_set_base(crtc, x, y, old_fb);
1287         if (ret != 0)
1288             return ret;
1289
1290         drm_vblank_post_modeset(dev, pipe);
1291
1292         return 0;
1293 }
1294
1295 /** Loads the palette/gamma unit for the CRTC with the prepared values */
1296 void intel_crtc_load_lut(struct drm_crtc *crtc)
1297 {
1298         struct drm_device *dev = crtc->dev;
1299         struct drm_i915_private *dev_priv = dev->dev_private;
1300         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1301         int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
1302         int i;
1303
1304         /* The clocks have to be on to load the palette. */
1305         if (!crtc->enabled)
1306                 return;
1307
1308         for (i = 0; i < 256; i++) {
1309                 I915_WRITE(palreg + 4 * i,
1310                            (intel_crtc->lut_r[i] << 16) |
1311                            (intel_crtc->lut_g[i] << 8) |
1312                            intel_crtc->lut_b[i]);
1313         }
1314 }
1315
1316 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
1317                                  struct drm_file *file_priv,
1318                                  uint32_t handle,
1319                                  uint32_t width, uint32_t height)
1320 {
1321         struct drm_device *dev = crtc->dev;
1322         struct drm_i915_private *dev_priv = dev->dev_private;
1323         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1324         struct drm_gem_object *bo;
1325         struct drm_i915_gem_object *obj_priv;
1326         int pipe = intel_crtc->pipe;
1327         uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
1328         uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
1329         uint32_t temp;
1330         size_t addr;
1331         int ret;
1332
1333         DRM_DEBUG("\n");
1334
1335         /* if we want to turn off the cursor ignore width and height */
1336         if (!handle) {
1337                 DRM_DEBUG("cursor off\n");
1338                 temp = CURSOR_MODE_DISABLE;
1339                 addr = 0;
1340                 bo = NULL;
1341                 mutex_lock(&dev->struct_mutex);
1342                 goto finish;
1343         }
1344
1345         /* Currently we only support 64x64 cursors */
1346         if (width != 64 || height != 64) {
1347                 DRM_ERROR("we currently only support 64x64 cursors\n");
1348                 return -EINVAL;
1349         }
1350
1351         bo = drm_gem_object_lookup(dev, file_priv, handle);
1352         if (!bo)
1353                 return -ENOENT;
1354
1355         obj_priv = bo->driver_private;
1356
1357         if (bo->size < width * height * 4) {
1358                 DRM_ERROR("buffer is to small\n");
1359                 ret = -ENOMEM;
1360                 goto fail;
1361         }
1362
1363         /* we only need to pin inside GTT if cursor is non-phy */
1364         mutex_lock(&dev->struct_mutex);
1365         if (!dev_priv->cursor_needs_physical) {
1366                 ret = i915_gem_object_pin(bo, PAGE_SIZE);
1367                 if (ret) {
1368                         DRM_ERROR("failed to pin cursor bo\n");
1369                         goto fail_locked;
1370                 }
1371                 addr = obj_priv->gtt_offset;
1372         } else {
1373                 ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
1374                 if (ret) {
1375                         DRM_ERROR("failed to attach phys object\n");
1376                         goto fail_locked;
1377                 }
1378                 addr = obj_priv->phys_obj->handle->busaddr;
1379         }
1380
1381         temp = 0;
1382         /* set the pipe for the cursor */
1383         temp |= (pipe << 28);
1384         temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
1385
1386  finish:
1387         I915_WRITE(control, temp);
1388         I915_WRITE(base, addr);
1389
1390         if (intel_crtc->cursor_bo) {
1391                 if (dev_priv->cursor_needs_physical) {
1392                         if (intel_crtc->cursor_bo != bo)
1393                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
1394                 } else
1395                         i915_gem_object_unpin(intel_crtc->cursor_bo);
1396                 drm_gem_object_unreference(intel_crtc->cursor_bo);
1397         }
1398         mutex_unlock(&dev->struct_mutex);
1399
1400         intel_crtc->cursor_addr = addr;
1401         intel_crtc->cursor_bo = bo;
1402
1403         return 0;
1404 fail:
1405         mutex_lock(&dev->struct_mutex);
1406 fail_locked:
1407         drm_gem_object_unreference(bo);
1408         mutex_unlock(&dev->struct_mutex);
1409         return ret;
1410 }
1411
1412 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
1413 {
1414         struct drm_device *dev = crtc->dev;
1415         struct drm_i915_private *dev_priv = dev->dev_private;
1416         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1417         int pipe = intel_crtc->pipe;
1418         uint32_t temp = 0;
1419         uint32_t adder;
1420
1421         if (x < 0) {
1422                 temp |= (CURSOR_POS_SIGN << CURSOR_X_SHIFT);
1423                 x = -x;
1424         }
1425         if (y < 0) {
1426                 temp |= (CURSOR_POS_SIGN << CURSOR_Y_SHIFT);
1427                 y = -y;
1428         }
1429
1430         temp |= ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT);
1431         temp |= ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT);
1432
1433         adder = intel_crtc->cursor_addr;
1434         I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
1435         I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
1436
1437         return 0;
1438 }
1439
1440 /** Sets the color ramps on behalf of RandR */
1441 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
1442                                  u16 blue, int regno)
1443 {
1444         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1445
1446         intel_crtc->lut_r[regno] = red >> 8;
1447         intel_crtc->lut_g[regno] = green >> 8;
1448         intel_crtc->lut_b[regno] = blue >> 8;
1449 }
1450
1451 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
1452                                  u16 *blue, uint32_t size)
1453 {
1454         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1455         int i;
1456
1457         if (size != 256)
1458                 return;
1459
1460         for (i = 0; i < 256; i++) {
1461                 intel_crtc->lut_r[i] = red[i] >> 8;
1462                 intel_crtc->lut_g[i] = green[i] >> 8;
1463                 intel_crtc->lut_b[i] = blue[i] >> 8;
1464         }
1465
1466         intel_crtc_load_lut(crtc);
1467 }
1468
1469 /**
1470  * Get a pipe with a simple mode set on it for doing load-based monitor
1471  * detection.
1472  *
1473  * It will be up to the load-detect code to adjust the pipe as appropriate for
1474  * its requirements.  The pipe will be connected to no other outputs.
1475  *
1476  * Currently this code will only succeed if there is a pipe with no outputs
1477  * configured for it.  In the future, it could choose to temporarily disable
1478  * some outputs to free up a pipe for its use.
1479  *
1480  * \return crtc, or NULL if no pipes are available.
1481  */
1482
1483 /* VESA 640x480x72Hz mode to set on the pipe */
1484 static struct drm_display_mode load_detect_mode = {
1485         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
1486                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1487 };
1488
1489 struct drm_crtc *intel_get_load_detect_pipe(struct intel_output *intel_output,
1490                                             struct drm_display_mode *mode,
1491                                             int *dpms_mode)
1492 {
1493         struct intel_crtc *intel_crtc;
1494         struct drm_crtc *possible_crtc;
1495         struct drm_crtc *supported_crtc =NULL;
1496         struct drm_encoder *encoder = &intel_output->enc;
1497         struct drm_crtc *crtc = NULL;
1498         struct drm_device *dev = encoder->dev;
1499         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1500         struct drm_crtc_helper_funcs *crtc_funcs;
1501         int i = -1;
1502
1503         /*
1504          * Algorithm gets a little messy:
1505          *   - if the connector already has an assigned crtc, use it (but make
1506          *     sure it's on first)
1507          *   - try to find the first unused crtc that can drive this connector,
1508          *     and use that if we find one
1509          *   - if there are no unused crtcs available, try to use the first
1510          *     one we found that supports the connector
1511          */
1512
1513         /* See if we already have a CRTC for this connector */
1514         if (encoder->crtc) {
1515                 crtc = encoder->crtc;
1516                 /* Make sure the crtc and connector are running */
1517                 intel_crtc = to_intel_crtc(crtc);
1518                 *dpms_mode = intel_crtc->dpms_mode;
1519                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
1520                         crtc_funcs = crtc->helper_private;
1521                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
1522                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
1523                 }
1524                 return crtc;
1525         }
1526
1527         /* Find an unused one (if possible) */
1528         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
1529                 i++;
1530                 if (!(encoder->possible_crtcs & (1 << i)))
1531                         continue;
1532                 if (!possible_crtc->enabled) {
1533                         crtc = possible_crtc;
1534                         break;
1535                 }
1536                 if (!supported_crtc)
1537                         supported_crtc = possible_crtc;
1538         }
1539
1540         /*
1541          * If we didn't find an unused CRTC, don't use any.
1542          */
1543         if (!crtc) {
1544                 return NULL;
1545         }
1546
1547         encoder->crtc = crtc;
1548         intel_output->load_detect_temp = true;
1549
1550         intel_crtc = to_intel_crtc(crtc);
1551         *dpms_mode = intel_crtc->dpms_mode;
1552
1553         if (!crtc->enabled) {
1554                 if (!mode)
1555                         mode = &load_detect_mode;
1556                 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
1557         } else {
1558                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
1559                         crtc_funcs = crtc->helper_private;
1560                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
1561                 }
1562
1563                 /* Add this connector to the crtc */
1564                 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
1565                 encoder_funcs->commit(encoder);
1566         }
1567         /* let the connector get through one full cycle before testing */
1568         intel_wait_for_vblank(dev);
1569
1570         return crtc;
1571 }
1572
1573 void intel_release_load_detect_pipe(struct intel_output *intel_output, int dpms_mode)
1574 {
1575         struct drm_encoder *encoder = &intel_output->enc;
1576         struct drm_device *dev = encoder->dev;
1577         struct drm_crtc *crtc = encoder->crtc;
1578         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1579         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1580
1581         if (intel_output->load_detect_temp) {
1582                 encoder->crtc = NULL;
1583                 intel_output->load_detect_temp = false;
1584                 crtc->enabled = drm_helper_crtc_in_use(crtc);
1585                 drm_helper_disable_unused_functions(dev);
1586         }
1587
1588         /* Switch crtc and output back off if necessary */
1589         if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
1590                 if (encoder->crtc == crtc)
1591                         encoder_funcs->dpms(encoder, dpms_mode);
1592                 crtc_funcs->dpms(crtc, dpms_mode);
1593         }
1594 }
1595
1596 /* Returns the clock of the currently programmed mode of the given pipe. */
1597 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
1598 {
1599         struct drm_i915_private *dev_priv = dev->dev_private;
1600         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1601         int pipe = intel_crtc->pipe;
1602         u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
1603         u32 fp;
1604         intel_clock_t clock;
1605
1606         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
1607                 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
1608         else
1609                 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
1610
1611         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
1612         if (IS_IGD(dev)) {
1613                 clock.n = ffs((fp & FP_N_IGD_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
1614                 clock.m2 = (fp & FP_M2_IGD_DIV_MASK) >> FP_M2_DIV_SHIFT;
1615         } else {
1616                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
1617                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
1618         }
1619
1620         if (IS_I9XX(dev)) {
1621                 if (IS_IGD(dev))
1622                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_IGD) >>
1623                                 DPLL_FPA01_P1_POST_DIV_SHIFT_IGD);
1624                 else
1625                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
1626                                DPLL_FPA01_P1_POST_DIV_SHIFT);
1627
1628                 switch (dpll & DPLL_MODE_MASK) {
1629                 case DPLLB_MODE_DAC_SERIAL:
1630                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
1631                                 5 : 10;
1632                         break;
1633                 case DPLLB_MODE_LVDS:
1634                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
1635                                 7 : 14;
1636                         break;
1637                 default:
1638                         DRM_DEBUG("Unknown DPLL mode %08x in programmed "
1639                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
1640                         return 0;
1641                 }
1642
1643                 /* XXX: Handle the 100Mhz refclk */
1644                 intel_clock(dev, 96000, &clock);
1645         } else {
1646                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
1647
1648                 if (is_lvds) {
1649                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
1650                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
1651                         clock.p2 = 14;
1652
1653                         if ((dpll & PLL_REF_INPUT_MASK) ==
1654                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
1655                                 /* XXX: might not be 66MHz */
1656                                 intel_clock(dev, 66000, &clock);
1657                         } else
1658                                 intel_clock(dev, 48000, &clock);
1659                 } else {
1660                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
1661                                 clock.p1 = 2;
1662                         else {
1663                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
1664                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
1665                         }
1666                         if (dpll & PLL_P2_DIVIDE_BY_4)
1667                                 clock.p2 = 4;
1668                         else
1669                                 clock.p2 = 2;
1670
1671                         intel_clock(dev, 48000, &clock);
1672                 }
1673         }
1674
1675         /* XXX: It would be nice to validate the clocks, but we can't reuse
1676          * i830PllIsValid() because it relies on the xf86_config connector
1677          * configuration being accurate, which it isn't necessarily.
1678          */
1679
1680         return clock.dot;
1681 }
1682
1683 /** Returns the currently programmed mode of the given pipe. */
1684 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
1685                                              struct drm_crtc *crtc)
1686 {
1687         struct drm_i915_private *dev_priv = dev->dev_private;
1688         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1689         int pipe = intel_crtc->pipe;
1690         struct drm_display_mode *mode;
1691         int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
1692         int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
1693         int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
1694         int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
1695
1696         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
1697         if (!mode)
1698                 return NULL;
1699
1700         mode->clock = intel_crtc_clock_get(dev, crtc);
1701         mode->hdisplay = (htot & 0xffff) + 1;
1702         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
1703         mode->hsync_start = (hsync & 0xffff) + 1;
1704         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
1705         mode->vdisplay = (vtot & 0xffff) + 1;
1706         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
1707         mode->vsync_start = (vsync & 0xffff) + 1;
1708         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
1709
1710         drm_mode_set_name(mode);
1711         drm_mode_set_crtcinfo(mode, 0);
1712
1713         return mode;
1714 }
1715
1716 static void intel_crtc_destroy(struct drm_crtc *crtc)
1717 {
1718         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1719
1720         drm_crtc_cleanup(crtc);
1721         kfree(intel_crtc);
1722 }
1723
1724 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
1725         .dpms = intel_crtc_dpms,
1726         .mode_fixup = intel_crtc_mode_fixup,
1727         .mode_set = intel_crtc_mode_set,
1728         .mode_set_base = intel_pipe_set_base,
1729         .prepare = intel_crtc_prepare,
1730         .commit = intel_crtc_commit,
1731 };
1732
1733 static const struct drm_crtc_funcs intel_crtc_funcs = {
1734         .cursor_set = intel_crtc_cursor_set,
1735         .cursor_move = intel_crtc_cursor_move,
1736         .gamma_set = intel_crtc_gamma_set,
1737         .set_config = drm_crtc_helper_set_config,
1738         .destroy = intel_crtc_destroy,
1739 };
1740
1741
1742 static void intel_crtc_init(struct drm_device *dev, int pipe)
1743 {
1744         struct intel_crtc *intel_crtc;
1745         int i;
1746
1747         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
1748         if (intel_crtc == NULL)
1749                 return;
1750
1751         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
1752
1753         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
1754         intel_crtc->pipe = pipe;
1755         for (i = 0; i < 256; i++) {
1756                 intel_crtc->lut_r[i] = i;
1757                 intel_crtc->lut_g[i] = i;
1758                 intel_crtc->lut_b[i] = i;
1759         }
1760
1761         intel_crtc->cursor_addr = 0;
1762         intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
1763         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
1764
1765         intel_crtc->mode_set.crtc = &intel_crtc->base;
1766         intel_crtc->mode_set.connectors = (struct drm_connector **)(intel_crtc + 1);
1767         intel_crtc->mode_set.num_connectors = 0;
1768
1769         if (i915_fbpercrtc) {
1770
1771
1772
1773         }
1774 }
1775
1776 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
1777 {
1778         struct drm_crtc *crtc = NULL;
1779
1780         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1781                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1782                 if (intel_crtc->pipe == pipe)
1783                         break;
1784         }
1785         return crtc;
1786 }
1787
1788 static int intel_connector_clones(struct drm_device *dev, int type_mask)
1789 {
1790         int index_mask = 0;
1791         struct drm_connector *connector;
1792         int entry = 0;
1793
1794         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1795                 struct intel_output *intel_output = to_intel_output(connector);
1796                 if (type_mask & (1 << intel_output->type))
1797                         index_mask |= (1 << entry);
1798                 entry++;
1799         }
1800         return index_mask;
1801 }
1802
1803
1804 static void intel_setup_outputs(struct drm_device *dev)
1805 {
1806         struct drm_i915_private *dev_priv = dev->dev_private;
1807         struct drm_connector *connector;
1808
1809         intel_crt_init(dev);
1810
1811         /* Set up integrated LVDS */
1812         if (IS_MOBILE(dev) && !IS_I830(dev))
1813                 intel_lvds_init(dev);
1814
1815         if (IS_I9XX(dev)) {
1816                 int found;
1817                 u32 reg;
1818
1819                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
1820                         found = intel_sdvo_init(dev, SDVOB);
1821                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev))
1822                                 intel_hdmi_init(dev, SDVOB);
1823                 }
1824
1825                 /* Before G4X SDVOC doesn't have its own detect register */
1826                 if (IS_G4X(dev))
1827                         reg = SDVOC;
1828                 else
1829                         reg = SDVOB;
1830
1831                 if (I915_READ(reg) & SDVO_DETECTED) {
1832                         found = intel_sdvo_init(dev, SDVOC);
1833                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev))
1834                                 intel_hdmi_init(dev, SDVOC);
1835                 }
1836         } else
1837                 intel_dvo_init(dev);
1838
1839         if (IS_I9XX(dev) && IS_MOBILE(dev))
1840                 intel_tv_init(dev);
1841
1842         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1843                 struct intel_output *intel_output = to_intel_output(connector);
1844                 struct drm_encoder *encoder = &intel_output->enc;
1845                 int crtc_mask = 0, clone_mask = 0;
1846
1847                 /* valid crtcs */
1848                 switch(intel_output->type) {
1849                 case INTEL_OUTPUT_HDMI:
1850                         crtc_mask = ((1 << 0)|
1851                                      (1 << 1));
1852                         clone_mask = ((1 << INTEL_OUTPUT_HDMI));
1853                         break;
1854                 case INTEL_OUTPUT_DVO:
1855                 case INTEL_OUTPUT_SDVO:
1856                         crtc_mask = ((1 << 0)|
1857                                      (1 << 1));
1858                         clone_mask = ((1 << INTEL_OUTPUT_ANALOG) |
1859                                       (1 << INTEL_OUTPUT_DVO) |
1860                                       (1 << INTEL_OUTPUT_SDVO));
1861                         break;
1862                 case INTEL_OUTPUT_ANALOG:
1863                         crtc_mask = ((1 << 0)|
1864                                      (1 << 1));
1865                         clone_mask = ((1 << INTEL_OUTPUT_ANALOG) |
1866                                       (1 << INTEL_OUTPUT_DVO) |
1867                                       (1 << INTEL_OUTPUT_SDVO));
1868                         break;
1869                 case INTEL_OUTPUT_LVDS:
1870                         crtc_mask = (1 << 1);
1871                         clone_mask = (1 << INTEL_OUTPUT_LVDS);
1872                         break;
1873                 case INTEL_OUTPUT_TVOUT:
1874                         crtc_mask = ((1 << 0) |
1875                                      (1 << 1));
1876                         clone_mask = (1 << INTEL_OUTPUT_TVOUT);
1877                         break;
1878                 }
1879                 encoder->possible_crtcs = crtc_mask;
1880                 encoder->possible_clones = intel_connector_clones(dev, clone_mask);
1881         }
1882 }
1883
1884 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
1885 {
1886         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1887         struct drm_device *dev = fb->dev;
1888
1889         if (fb->fbdev)
1890                 intelfb_remove(dev, fb);
1891
1892         drm_framebuffer_cleanup(fb);
1893         mutex_lock(&dev->struct_mutex);
1894         drm_gem_object_unreference(intel_fb->obj);
1895         mutex_unlock(&dev->struct_mutex);
1896
1897         kfree(intel_fb);
1898 }
1899
1900 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
1901                                                 struct drm_file *file_priv,
1902                                                 unsigned int *handle)
1903 {
1904         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1905         struct drm_gem_object *object = intel_fb->obj;
1906
1907         return drm_gem_handle_create(file_priv, object, handle);
1908 }
1909
1910 static const struct drm_framebuffer_funcs intel_fb_funcs = {
1911         .destroy = intel_user_framebuffer_destroy,
1912         .create_handle = intel_user_framebuffer_create_handle,
1913 };
1914
1915 int intel_framebuffer_create(struct drm_device *dev,
1916                              struct drm_mode_fb_cmd *mode_cmd,
1917                              struct drm_framebuffer **fb,
1918                              struct drm_gem_object *obj)
1919 {
1920         struct intel_framebuffer *intel_fb;
1921         int ret;
1922
1923         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1924         if (!intel_fb)
1925                 return -ENOMEM;
1926
1927         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
1928         if (ret) {
1929                 DRM_ERROR("framebuffer init failed %d\n", ret);
1930                 return ret;
1931         }
1932
1933         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
1934
1935         intel_fb->obj = obj;
1936
1937         *fb = &intel_fb->base;
1938
1939         return 0;
1940 }
1941
1942
1943 static struct drm_framebuffer *
1944 intel_user_framebuffer_create(struct drm_device *dev,
1945                               struct drm_file *filp,
1946                               struct drm_mode_fb_cmd *mode_cmd)
1947 {
1948         struct drm_gem_object *obj;
1949         struct drm_framebuffer *fb;
1950         int ret;
1951
1952         obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
1953         if (!obj)
1954                 return NULL;
1955
1956         ret = intel_framebuffer_create(dev, mode_cmd, &fb, obj);
1957         if (ret) {
1958                 mutex_lock(&dev->struct_mutex);
1959                 drm_gem_object_unreference(obj);
1960                 mutex_unlock(&dev->struct_mutex);
1961                 return NULL;
1962         }
1963
1964         return fb;
1965 }
1966
1967 static const struct drm_mode_config_funcs intel_mode_funcs = {
1968         .fb_create = intel_user_framebuffer_create,
1969         .fb_changed = intelfb_probe,
1970 };
1971
1972 void intel_modeset_init(struct drm_device *dev)
1973 {
1974         int num_pipe;
1975         int i;
1976
1977         drm_mode_config_init(dev);
1978
1979         dev->mode_config.min_width = 0;
1980         dev->mode_config.min_height = 0;
1981
1982         dev->mode_config.funcs = (void *)&intel_mode_funcs;
1983
1984         if (IS_I965G(dev)) {
1985                 dev->mode_config.max_width = 8192;
1986                 dev->mode_config.max_height = 8192;
1987         } else {
1988                 dev->mode_config.max_width = 2048;
1989                 dev->mode_config.max_height = 2048;
1990         }
1991
1992         /* set memory base */
1993         if (IS_I9XX(dev))
1994                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
1995         else
1996                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
1997
1998         if (IS_MOBILE(dev) || IS_I9XX(dev))
1999                 num_pipe = 2;
2000         else
2001                 num_pipe = 1;
2002         DRM_DEBUG("%d display pipe%s available.\n",
2003                   num_pipe, num_pipe > 1 ? "s" : "");
2004
2005         for (i = 0; i < num_pipe; i++) {
2006                 intel_crtc_init(dev, i);
2007         }
2008
2009         intel_setup_outputs(dev);
2010 }
2011
2012 void intel_modeset_cleanup(struct drm_device *dev)
2013 {
2014         drm_mode_config_cleanup(dev);
2015 }
2016
2017
2018 /* current intel driver doesn't take advantage of encoders
2019    always give back the encoder for the connector
2020 */
2021 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
2022 {
2023         struct intel_output *intel_output = to_intel_output(connector);
2024
2025         return &intel_output->enc;
2026 }