git.oblomov.eu Git - linux-2.6/blob - include/asm-mips/mipsregs.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
   7  * Copyright (C) 2000 Silicon Graphics, Inc.
   8  * Modified for further R[236]000 support by Paul M. Antoine, 1996.
   9  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
  10  * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
  11  * Copyright (C) 2003  Maciej W. Rozycki
  12  */
  13 #ifndef _ASM_MIPSREGS_H
  14 #define _ASM_MIPSREGS_H
  15
  16 #include <linux/config.h>
  17 #include <linux/linkage.h>
  18 #include <asm/hazards.h>
  19
  20 /*
  21  * The following macros are especially useful for __asm__
  22  * inline assembler.
  23  */
  24 #ifndef __STR
  25 #define __STR(x) #x
  26 #endif
  27 #ifndef STR
  28 #define STR(x) __STR(x)
  29 #endif
  30
  31 /*
  32  *  Configure language
  33  */
  34 #ifdef __ASSEMBLY__
  35 #define _ULCAST_
  36 #else
  37 #define _ULCAST_ (unsigned long)
  38 #endif
  39
  40 /*
  41  * Coprocessor 0 register names
  42  */
  43 #define CP0_INDEX $0
  44 #define CP0_RANDOM $1
  45 #define CP0_ENTRYLO0 $2
  46 #define CP0_ENTRYLO1 $3
  47 #define CP0_CONF $3
  48 #define CP0_CONTEXT $4
  49 #define CP0_PAGEMASK $5
  50 #define CP0_WIRED $6
  51 #define CP0_INFO $7
  52 #define CP0_BADVADDR $8
  53 #define CP0_COUNT $9
  54 #define CP0_ENTRYHI $10
  55 #define CP0_COMPARE $11
  56 #define CP0_STATUS $12
  57 #define CP0_CAUSE $13
  58 #define CP0_EPC $14
  59 #define CP0_PRID $15
  60 #define CP0_CONFIG $16
  61 #define CP0_LLADDR $17
  62 #define CP0_WATCHLO $18
  63 #define CP0_WATCHHI $19
  64 #define CP0_XCONTEXT $20
  65 #define CP0_FRAMEMASK $21
  66 #define CP0_DIAGNOSTIC $22
  67 #define CP0_DEBUG $23
  68 #define CP0_DEPC $24
  69 #define CP0_PERFORMANCE $25
  70 #define CP0_ECC $26
  71 #define CP0_CACHEERR $27
  72 #define CP0_TAGLO $28
  73 #define CP0_TAGHI $29
  74 #define CP0_ERROREPC $30
  75 #define CP0_DESAVE $31
  76
  77 /*
  78  * R4640/R4650 cp0 register names.  These registers are listed
  79  * here only for completeness; without MMU these CPUs are not useable
  80  * by Linux.  A future ELKS port might take make Linux run on them
  81  * though ...
  82  */
  83 #define CP0_IBASE $0
  84 #define CP0_IBOUND $1
  85 #define CP0_DBASE $2
  86 #define CP0_DBOUND $3
  87 #define CP0_CALG $17
  88 #define CP0_IWATCH $18
  89 #define CP0_DWATCH $19
  90
  91 /*
  92  * Coprocessor 0 Set 1 register names
  93  */
  94 #define CP0_S1_DERRADDR0  $26
  95 #define CP0_S1_DERRADDR1  $27
  96 #define CP0_S1_INTCONTROL $20
  97
  98 /*
  99  *  TX39 Series
 100  */
 101 #define CP0_TX39_CACHE  $7
 102
 103 /*
 104  * Coprocessor 1 (FPU) register names
 105  */
 106 #define CP1_REVISION   $0
 107 #define CP1_STATUS     $31
 108
 109 /*
 110  * FPU Status Register Values
 111  */
 112 /*
 113  * Status Register Values
 114  */
 115
 116 #define FPU_CSR_FLUSH   0x01000000      /* flush denormalised results to 0 */
 117 #define FPU_CSR_COND    0x00800000      /* $fcc0 */
 118 #define FPU_CSR_COND0   0x00800000      /* $fcc0 */
 119 #define FPU_CSR_COND1   0x02000000      /* $fcc1 */
 120 #define FPU_CSR_COND2   0x04000000      /* $fcc2 */
 121 #define FPU_CSR_COND3   0x08000000      /* $fcc3 */
 122 #define FPU_CSR_COND4   0x10000000      /* $fcc4 */
 123 #define FPU_CSR_COND5   0x20000000      /* $fcc5 */
 124 #define FPU_CSR_COND6   0x40000000      /* $fcc6 */
 125 #define FPU_CSR_COND7   0x80000000      /* $fcc7 */
 126
 127 /*
 128  * X the exception cause indicator
 129  * E the exception enable
 130  * S the sticky/flag bit
 131 */
 132 #define FPU_CSR_ALL_X   0x0003f000
 133 #define FPU_CSR_UNI_X   0x00020000
 134 #define FPU_CSR_INV_X   0x00010000
 135 #define FPU_CSR_DIV_X   0x00008000
 136 #define FPU_CSR_OVF_X   0x00004000
 137 #define FPU_CSR_UDF_X   0x00002000
 138 #define FPU_CSR_INE_X   0x00001000
 139
 140 #define FPU_CSR_ALL_E   0x00000f80
 141 #define FPU_CSR_INV_E   0x00000800
 142 #define FPU_CSR_DIV_E   0x00000400
 143 #define FPU_CSR_OVF_E   0x00000200
 144 #define FPU_CSR_UDF_E   0x00000100
 145 #define FPU_CSR_INE_E   0x00000080
 146
 147 #define FPU_CSR_ALL_S   0x0000007c
 148 #define FPU_CSR_INV_S   0x00000040
 149 #define FPU_CSR_DIV_S   0x00000020
 150 #define FPU_CSR_OVF_S   0x00000010
 151 #define FPU_CSR_UDF_S   0x00000008
 152 #define FPU_CSR_INE_S   0x00000004
 153
 154 /* rounding mode */
 155 #define FPU_CSR_RN      0x0     /* nearest */
 156 #define FPU_CSR_RZ      0x1     /* towards zero */
 157 #define FPU_CSR_RU      0x2     /* towards +Infinity */
 158 #define FPU_CSR_RD      0x3     /* towards -Infinity */
 159
 160
 161 /*
 162  * Values for PageMask register
 163  */
 164 #ifdef CONFIG_CPU_VR41XX
 165
 166 /* Why doesn't stupidity hurt ... */
 167
 168 #define PM_1K           0x00000000
 169 #define PM_4K           0x00001800
 170 #define PM_16K          0x00007800
 171 #define PM_64K          0x0001f800
 172 #define PM_256K         0x0007f800
 173
 174 #else
 175
 176 #define PM_4K           0x00000000
 177 #define PM_16K          0x00006000
 178 #define PM_64K          0x0001e000
 179 #define PM_256K         0x0007e000
 180 #define PM_1M           0x001fe000
 181 #define PM_4M           0x007fe000
 182 #define PM_16M          0x01ffe000
 183 #define PM_64M          0x07ffe000
 184 #define PM_256M         0x1fffe000
 185
 186 #endif
 187
 188 /*
 189  * Default page size for a given kernel configuration
 190  */
 191 #ifdef CONFIG_PAGE_SIZE_4KB
 192 #define PM_DEFAULT_MASK PM_4K
 193 #elif defined(CONFIG_PAGE_SIZE_16KB)
 194 #define PM_DEFAULT_MASK PM_16K
 195 #elif defined(CONFIG_PAGE_SIZE_64KB)
 196 #define PM_DEFAULT_MASK PM_64K
 197 #else
 198 #error Bad page size configuration!
 199 #endif
 200
 201
 202 /*
 203  * Values used for computation of new tlb entries
 204  */
 205 #define PL_4K           12
 206 #define PL_16K          14
 207 #define PL_64K          16
 208 #define PL_256K         18
 209 #define PL_1M           20
 210 #define PL_4M           22
 211 #define PL_16M          24
 212 #define PL_64M          26
 213 #define PL_256M         28
 214
 215 /*
 216  * R4x00 interrupt enable / cause bits
 217  */
 218 #define IE_SW0          (_ULCAST_(1) <<  8)
 219 #define IE_SW1          (_ULCAST_(1) <<  9)
 220 #define IE_IRQ0         (_ULCAST_(1) << 10)
 221 #define IE_IRQ1         (_ULCAST_(1) << 11)
 222 #define IE_IRQ2         (_ULCAST_(1) << 12)
 223 #define IE_IRQ3         (_ULCAST_(1) << 13)
 224 #define IE_IRQ4         (_ULCAST_(1) << 14)
 225 #define IE_IRQ5         (_ULCAST_(1) << 15)
 226
 227 /*
 228  * R4x00 interrupt cause bits
 229  */
 230 #define C_SW0           (_ULCAST_(1) <<  8)
 231 #define C_SW1           (_ULCAST_(1) <<  9)
 232 #define C_IRQ0          (_ULCAST_(1) << 10)
 233 #define C_IRQ1          (_ULCAST_(1) << 11)
 234 #define C_IRQ2          (_ULCAST_(1) << 12)
 235 #define C_IRQ3          (_ULCAST_(1) << 13)
 236 #define C_IRQ4          (_ULCAST_(1) << 14)
 237 #define C_IRQ5          (_ULCAST_(1) << 15)
 238
 239 /*
 240  * Bitfields in the R4xx0 cp0 status register
 241  */
 242 #define ST0_IE                  0x00000001
 243 #define ST0_EXL                 0x00000002
 244 #define ST0_ERL                 0x00000004
 245 #define ST0_KSU                 0x00000018
 246 #  define KSU_USER              0x00000010
 247 #  define KSU_SUPERVISOR        0x00000008
 248 #  define KSU_KERNEL            0x00000000
 249 #define ST0_UX                  0x00000020
 250 #define ST0_SX                  0x00000040
 251 #define ST0_KX                  0x00000080
 252 #define ST0_DE                  0x00010000
 253 #define ST0_CE                  0x00020000
 254
 255 /*
 256  * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
 257  * cacheops in userspace.  This bit exists only on RM7000 and RM9000
 258  * processors.
 259  */
 260 #define ST0_CO                  0x08000000
 261
 262 /*
 263  * Bitfields in the R[23]000 cp0 status register.
 264  */
 265 #define ST0_IEC                 0x00000001
 266 #define ST0_KUC                 0x00000002
 267 #define ST0_IEP                 0x00000004
 268 #define ST0_KUP                 0x00000008
 269 #define ST0_IEO                 0x00000010
 270 #define ST0_KUO                 0x00000020
 271 /* bits 6 & 7 are reserved on R[23]000 */
 272 #define ST0_ISC                 0x00010000
 273 #define ST0_SWC                 0x00020000
 274 #define ST0_CM                  0x00080000
 275
 276 /*
 277  * Bits specific to the R4640/R4650
 278  */
 279 #define ST0_UM                  (_ULCAST_(1) <<  4)
 280 #define ST0_IL                  (_ULCAST_(1) << 23)
 281 #define ST0_DL                  (_ULCAST_(1) << 24)
 282
 283 /*
 284  * Bitfields in the TX39 family CP0 Configuration Register 3
 285  */
 286 #define TX39_CONF_ICS_SHIFT     19
 287 #define TX39_CONF_ICS_MASK      0x00380000
 288 #define TX39_CONF_ICS_1KB       0x00000000
 289 #define TX39_CONF_ICS_2KB       0x00080000
 290 #define TX39_CONF_ICS_4KB       0x00100000
 291 #define TX39_CONF_ICS_8KB       0x00180000
 292 #define TX39_CONF_ICS_16KB      0x00200000
 293
 294 #define TX39_CONF_DCS_SHIFT     16
 295 #define TX39_CONF_DCS_MASK      0x00070000
 296 #define TX39_CONF_DCS_1KB       0x00000000
 297 #define TX39_CONF_DCS_2KB       0x00010000
 298 #define TX39_CONF_DCS_4KB       0x00020000
 299 #define TX39_CONF_DCS_8KB       0x00030000
 300 #define TX39_CONF_DCS_16KB      0x00040000
 301
 302 #define TX39_CONF_CWFON         0x00004000
 303 #define TX39_CONF_WBON          0x00002000
 304 #define TX39_CONF_RF_SHIFT      10
 305 #define TX39_CONF_RF_MASK       0x00000c00
 306 #define TX39_CONF_DOZE          0x00000200
 307 #define TX39_CONF_HALT          0x00000100
 308 #define TX39_CONF_LOCK          0x00000080
 309 #define TX39_CONF_ICE           0x00000020
 310 #define TX39_CONF_DCE           0x00000010
 311 #define TX39_CONF_IRSIZE_SHIFT  2
 312 #define TX39_CONF_IRSIZE_MASK   0x0000000c
 313 #define TX39_CONF_DRSIZE_SHIFT  0
 314 #define TX39_CONF_DRSIZE_MASK   0x00000003
 315
 316 /*
 317  * Status register bits available in all MIPS CPUs.
 318  */
 319 #define ST0_IM                  0x0000ff00
 320 #define  STATUSB_IP0            8
 321 #define  STATUSF_IP0            (_ULCAST_(1) <<  8)
 322 #define  STATUSB_IP1            9
 323 #define  STATUSF_IP1            (_ULCAST_(1) <<  9)
 324 #define  STATUSB_IP2            10
 325 #define  STATUSF_IP2            (_ULCAST_(1) << 10)
 326 #define  STATUSB_IP3            11
 327 #define  STATUSF_IP3            (_ULCAST_(1) << 11)
 328 #define  STATUSB_IP4            12
 329 #define  STATUSF_IP4            (_ULCAST_(1) << 12)
 330 #define  STATUSB_IP5            13
 331 #define  STATUSF_IP5            (_ULCAST_(1) << 13)
 332 #define  STATUSB_IP6            14
 333 #define  STATUSF_IP6            (_ULCAST_(1) << 14)
 334 #define  STATUSB_IP7            15
 335 #define  STATUSF_IP7            (_ULCAST_(1) << 15)
 336 #define  STATUSB_IP8            0
 337 #define  STATUSF_IP8            (_ULCAST_(1) <<  0)
 338 #define  STATUSB_IP9            1
 339 #define  STATUSF_IP9            (_ULCAST_(1) <<  1)
 340 #define  STATUSB_IP10           2
 341 #define  STATUSF_IP10           (_ULCAST_(1) <<  2)
 342 #define  STATUSB_IP11           3
 343 #define  STATUSF_IP11           (_ULCAST_(1) <<  3)
 344 #define  STATUSB_IP12           4
 345 #define  STATUSF_IP12           (_ULCAST_(1) <<  4)
 346 #define  STATUSB_IP13           5
 347 #define  STATUSF_IP13           (_ULCAST_(1) <<  5)
 348 #define  STATUSB_IP14           6
 349 #define  STATUSF_IP14           (_ULCAST_(1) <<  6)
 350 #define  STATUSB_IP15           7
 351 #define  STATUSF_IP15           (_ULCAST_(1) <<  7)
 352 #define ST0_CH                  0x00040000
 353 #define ST0_SR                  0x00100000
 354 #define ST0_TS                  0x00200000
 355 #define ST0_BEV                 0x00400000
 356 #define ST0_RE                  0x02000000
 357 #define ST0_FR                  0x04000000
 358 #define ST0_CU                  0xf0000000
 359 #define ST0_CU0                 0x10000000
 360 #define ST0_CU1                 0x20000000
 361 #define ST0_CU2                 0x40000000
 362 #define ST0_CU3                 0x80000000
 363 #define ST0_XX                  0x80000000      /* MIPS IV naming */
 364
 365 /*
 366  * Bitfields and bit numbers in the coprocessor 0 cause register.
 367  *
 368  * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
 369  */
 370 #define  CAUSEB_EXCCODE         2
 371 #define  CAUSEF_EXCCODE         (_ULCAST_(31)  <<  2)
 372 #define  CAUSEB_IP              8
 373 #define  CAUSEF_IP              (_ULCAST_(255) <<  8)
 374 #define  CAUSEB_IP0             8
 375 #define  CAUSEF_IP0             (_ULCAST_(1)   <<  8)
 376 #define  CAUSEB_IP1             9
 377 #define  CAUSEF_IP1             (_ULCAST_(1)   <<  9)
 378 #define  CAUSEB_IP2             10
 379 #define  CAUSEF_IP2             (_ULCAST_(1)   << 10)
 380 #define  CAUSEB_IP3             11
 381 #define  CAUSEF_IP3             (_ULCAST_(1)   << 11)
 382 #define  CAUSEB_IP4             12
 383 #define  CAUSEF_IP4             (_ULCAST_(1)   << 12)
 384 #define  CAUSEB_IP5             13
 385 #define  CAUSEF_IP5             (_ULCAST_(1)   << 13)
 386 #define  CAUSEB_IP6             14
 387 #define  CAUSEF_IP6             (_ULCAST_(1)   << 14)
 388 #define  CAUSEB_IP7             15
 389 #define  CAUSEF_IP7             (_ULCAST_(1)   << 15)
 390 #define  CAUSEB_IV              23
 391 #define  CAUSEF_IV              (_ULCAST_(1)   << 23)
 392 #define  CAUSEB_CE              28
 393 #define  CAUSEF_CE              (_ULCAST_(3)   << 28)
 394 #define  CAUSEB_BD              31
 395 #define  CAUSEF_BD              (_ULCAST_(1)   << 31)
 396
 397 /*
 398  * Bits in the coprocessor 0 config register.
 399  */
 400 /* Generic bits.  */
 401 #define CONF_CM_CACHABLE_NO_WA          0
 402 #define CONF_CM_CACHABLE_WA             1
 403 #define CONF_CM_UNCACHED                2
 404 #define CONF_CM_CACHABLE_NONCOHERENT    3
 405 #define CONF_CM_CACHABLE_CE             4
 406 #define CONF_CM_CACHABLE_COW            5
 407 #define CONF_CM_CACHABLE_CUW            6
 408 #define CONF_CM_CACHABLE_ACCELERATED    7
 409 #define CONF_CM_CMASK                   7
 410 #define CONF_BE                 (_ULCAST_(1) << 15)
 411
 412 /* Bits common to various processors.  */
 413 #define CONF_CU                 (_ULCAST_(1) <<  3)
 414 #define CONF_DB                 (_ULCAST_(1) <<  4)
 415 #define CONF_IB                 (_ULCAST_(1) <<  5)
 416 #define CONF_DC                 (_ULCAST_(7) <<  6)
 417 #define CONF_IC                 (_ULCAST_(7) <<  9)
 418 #define CONF_EB                 (_ULCAST_(1) << 13)
 419 #define CONF_EM                 (_ULCAST_(1) << 14)
 420 #define CONF_SM                 (_ULCAST_(1) << 16)
 421 #define CONF_SC                 (_ULCAST_(1) << 17)
 422 #define CONF_EW                 (_ULCAST_(3) << 18)
 423 #define CONF_EP                 (_ULCAST_(15)<< 24)
 424 #define CONF_EC                 (_ULCAST_(7) << 28)
 425 #define CONF_CM                 (_ULCAST_(1) << 31)
 426
 427 /* Bits specific to the R4xx0.  */
 428 #define R4K_CONF_SW             (_ULCAST_(1) << 20)
 429 #define R4K_CONF_SS             (_ULCAST_(1) << 21)
 430 #define R4K_CONF_SB             (_ULCAST_(3) << 22)
 431
 432 /* Bits specific to the R5000.  */
 433 #define R5K_CONF_SE             (_ULCAST_(1) << 12)
 434 #define R5K_CONF_SS             (_ULCAST_(3) << 20)
 435
 436 /* Bits specific to the R10000.  */
 437 #define R10K_CONF_DN            (_ULCAST_(3) <<  3)
 438 #define R10K_CONF_CT            (_ULCAST_(1) <<  5)
 439 #define R10K_CONF_PE            (_ULCAST_(1) <<  6)
 440 #define R10K_CONF_PM            (_ULCAST_(3) <<  7)
 441 #define R10K_CONF_EC            (_ULCAST_(15)<<  9)
 442 #define R10K_CONF_SB            (_ULCAST_(1) << 13)
 443 #define R10K_CONF_SK            (_ULCAST_(1) << 14)
 444 #define R10K_CONF_SS            (_ULCAST_(7) << 16)
 445 #define R10K_CONF_SC            (_ULCAST_(7) << 19)
 446 #define R10K_CONF_DC            (_ULCAST_(7) << 26)
 447 #define R10K_CONF_IC            (_ULCAST_(7) << 29)
 448
 449 /* Bits specific to the VR41xx.  */
 450 #define VR41_CONF_CS            (_ULCAST_(1) << 12)
 451 #define VR41_CONF_M16           (_ULCAST_(1) << 20)
 452 #define VR41_CONF_AD            (_ULCAST_(1) << 23)
 453
 454 /* Bits specific to the R30xx.  */
 455 #define R30XX_CONF_FDM          (_ULCAST_(1) << 19)
 456 #define R30XX_CONF_REV          (_ULCAST_(1) << 22)
 457 #define R30XX_CONF_AC           (_ULCAST_(1) << 23)
 458 #define R30XX_CONF_RF           (_ULCAST_(1) << 24)
 459 #define R30XX_CONF_HALT         (_ULCAST_(1) << 25)
 460 #define R30XX_CONF_FPINT        (_ULCAST_(7) << 26)
 461 #define R30XX_CONF_DBR          (_ULCAST_(1) << 29)
 462 #define R30XX_CONF_SB           (_ULCAST_(1) << 30)
 463 #define R30XX_CONF_LOCK         (_ULCAST_(1) << 31)
 464
 465 /* Bits specific to the TX49.  */
 466 #define TX49_CONF_DC            (_ULCAST_(1) << 16)
 467 #define TX49_CONF_IC            (_ULCAST_(1) << 17)  /* conflict with CONF_SC */
 468 #define TX49_CONF_HALT          (_ULCAST_(1) << 18)
 469 #define TX49_CONF_CWFON         (_ULCAST_(1) << 27)
 470
 471 /* Bits specific to the MIPS32/64 PRA.  */
 472 #define MIPS_CONF_MT            (_ULCAST_(7) <<  7)
 473 #define MIPS_CONF_AR            (_ULCAST_(7) << 10)
 474 #define MIPS_CONF_AT            (_ULCAST_(3) << 13)
 475 #define MIPS_CONF_M             (_ULCAST_(1) << 31)
 476
 477 /*
 478  * R10000 performance counter definitions.
 479  *
 480  * FIXME: The R10000 performance counter opens a nice way to implement CPU
 481  *        time accounting with a precission of one cycle.  I don't have
 482  *        R10000 silicon but just a manual, so ...
 483  */
 484
 485 /*
 486  * Events counted by counter #0
 487  */
 488 #define CE0_CYCLES                      0
 489 #define CE0_INSN_ISSUED                 1
 490 #define CE0_LPSC_ISSUED                 2
 491 #define CE0_S_ISSUED                    3
 492 #define CE0_SC_ISSUED                   4
 493 #define CE0_SC_FAILED                   5
 494 #define CE0_BRANCH_DECODED              6
 495 #define CE0_QW_WB_SECONDARY             7
 496 #define CE0_CORRECTED_ECC_ERRORS        8
 497 #define CE0_ICACHE_MISSES               9
 498 #define CE0_SCACHE_I_MISSES             10
 499 #define CE0_SCACHE_I_WAY_MISSPREDICTED  11
 500 #define CE0_EXT_INTERVENTIONS_REQ       12
 501 #define CE0_EXT_INVALIDATE_REQ          13
 502 #define CE0_VIRTUAL_COHERENCY_COND      14
 503 #define CE0_INSN_GRADUATED              15
 504
 505 /*
 506  * Events counted by counter #1
 507  */
 508 #define CE1_CYCLES                      0
 509 #define CE1_INSN_GRADUATED              1
 510 #define CE1_LPSC_GRADUATED              2
 511 #define CE1_S_GRADUATED                 3
 512 #define CE1_SC_GRADUATED                4
 513 #define CE1_FP_INSN_GRADUATED           5
 514 #define CE1_QW_WB_PRIMARY               6
 515 #define CE1_TLB_REFILL                  7
 516 #define CE1_BRANCH_MISSPREDICTED        8
 517 #define CE1_DCACHE_MISS                 9
 518 #define CE1_SCACHE_D_MISSES             10
 519 #define CE1_SCACHE_D_WAY_MISSPREDICTED  11
 520 #define CE1_EXT_INTERVENTION_HITS       12
 521 #define CE1_EXT_INVALIDATE_REQ          13
 522 #define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS  14
 523 #define CE1_SP_HINT_TO_SHARED_SC_BLOCKS 15
 524
 525 /*
 526  * These flags define in which privilege mode the counters count events
 527  */
 528 #define CEB_USER        8       /* Count events in user mode, EXL = ERL = 0 */
 529 #define CEB_SUPERVISOR  4       /* Count events in supvervisor mode EXL = ERL = 0 */
 530 #define CEB_KERNEL      2       /* Count events in kernel mode EXL = ERL = 0 */
 531 #define CEB_EXL         1       /* Count events with EXL = 1, ERL = 0 */
 532
 533 #ifndef __ASSEMBLY__
 534
 535 /*
 536  * Functions to access the R10000 performance counters.  These are basically
 537  * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
 538  * performance counter number encoded into bits 1 ... 5 of the instruction.
 539  * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
 540  * disassembler these will look like an access to sel 0 or 1.
 541  */
 542 #define read_r10k_perf_cntr(counter)                            \
 543 ({                                                              \
 544         unsigned int __res;                                     \
 545         __asm__ __volatile__(                                   \
 546         "mfpc\t%0, %1"                                          \
 547         : "=r" (__res)                                          \
 548         : "i" (counter));                                       \
 549                                                                 \
 550         __res;                                                  \
 551 })
 552
 553 #define write_r10k_perf_cntr(counter,val)                       \
 554 do {                                                            \
 555         __asm__ __volatile__(                                   \
 556         "mtpc\t%0, %1"                                          \
 557         :                                                       \
 558         : "r" (val), "i" (counter));                            \
 559 } while (0)
 560
 561 #define read_r10k_perf_event(counter)                           \
 562 ({                                                              \
 563         unsigned int __res;                                     \
 564         __asm__ __volatile__(                                   \
 565         "mfps\t%0, %1"                                          \
 566         : "=r" (__res)                                          \
 567         : "i" (counter));                                       \
 568                                                                 \
 569         __res;                                                  \
 570 })
 571
 572 #define write_r10k_perf_cntl(counter,val)                       \
 573 do {                                                            \
 574         __asm__ __volatile__(                                   \
 575         "mtps\t%0, %1"                                          \
 576         :                                                       \
 577         : "r" (val), "i" (counter));                            \
 578 } while (0)
 579
 580
 581 /*
 582  * Macros to access the system control coprocessor
 583  */
 584
 585 #define __read_32bit_c0_register(source, sel)                           \
 586 ({ int __res;                                                           \
 587         if (sel == 0)                                                   \
 588                 __asm__ __volatile__(                                   \
 589                         "mfc0\t%0, " #source "\n\t"                     \
 590                         : "=r" (__res));                                \
 591         else                                                            \
 592                 __asm__ __volatile__(                                   \
 593                         ".set\tmips32\n\t"                              \
 594                         "mfc0\t%0, " #source ", " #sel "\n\t"           \
 595                         ".set\tmips0\n\t"                               \
 596                         : "=r" (__res));                                \
 597         __res;                                                          \
 598 })
 599
 600 #define __read_64bit_c0_register(source, sel)                           \
 601 ({ unsigned long long __res;                                            \
 602         if (sizeof(unsigned long) == 4)                                 \
 603                 __res = __read_64bit_c0_split(source, sel);             \
 604         else if (sel == 0)                                              \
 605                 __asm__ __volatile__(                                   \
 606                         ".set\tmips3\n\t"                               \
 607                         "dmfc0\t%0, " #source "\n\t"                    \
 608                         ".set\tmips0"                                   \
 609                         : "=r" (__res));                                \
 610         else                                                            \
 611                 __asm__ __volatile__(                                   \
 612                         ".set\tmips64\n\t"                              \
 613                         "dmfc0\t%0, " #source ", " #sel "\n\t"          \
 614                         ".set\tmips0"                                   \
 615                         : "=r" (__res));                                \
 616         __res;                                                          \
 617 })
 618
 619 #define __write_32bit_c0_register(register, sel, value)                 \
 620 do {                                                                    \
 621         if (sel == 0)                                                   \
 622                 __asm__ __volatile__(                                   \
 623                         "mtc0\t%z0, " #register "\n\t"                  \
 624                         : : "Jr" ((unsigned int)value));                \
 625         else                                                            \
 626                 __asm__ __volatile__(                                   \
 627                         ".set\tmips32\n\t"                              \
 628                         "mtc0\t%z0, " #register ", " #sel "\n\t"        \
 629                         ".set\tmips0"                                   \
 630                         : : "Jr" ((unsigned int)value));                \
 631 } while (0)
 632
 633 #define __write_64bit_c0_register(register, sel, value)                 \
 634 do {                                                                    \
 635         if (sizeof(unsigned long) == 4)                                 \
 636                 __write_64bit_c0_split(register, sel, value);           \
 637         else if (sel == 0)                                              \
 638                 __asm__ __volatile__(                                   \
 639                         ".set\tmips3\n\t"                               \
 640                         "dmtc0\t%z0, " #register "\n\t"                 \
 641                         ".set\tmips0"                                   \
 642                         : : "Jr" (value));                              \
 643         else                                                            \
 644                 __asm__ __volatile__(                                   \
 645                         ".set\tmips64\n\t"                              \
 646                         "dmtc0\t%z0, " #register ", " #sel "\n\t"       \
 647                         ".set\tmips0"                                   \
 648                         : : "Jr" (value));                              \
 649 } while (0)
 650
 651 #define __read_ulong_c0_register(reg, sel)                              \
 652         ((sizeof(unsigned long) == 4) ?                                 \
 653         (unsigned long) __read_32bit_c0_register(reg, sel) :            \
 654         (unsigned long) __read_64bit_c0_register(reg, sel))
 655
 656 #define __write_ulong_c0_register(reg, sel, val)                        \
 657 do {                                                                    \
 658         if (sizeof(unsigned long) == 4)                                 \
 659                 __write_32bit_c0_register(reg, sel, val);               \
 660         else                                                            \
 661                 __write_64bit_c0_register(reg, sel, val);               \
 662 } while (0)
 663
 664 /*
 665  * On RM7000/RM9000 these are uses to access cop0 set 1 registers
 666  */
 667 #define __read_32bit_c0_ctrl_register(source)                           \
 668 ({ int __res;                                                           \
 669         __asm__ __volatile__(                                           \
 670                 "cfc0\t%0, " #source "\n\t"                             \
 671                 : "=r" (__res));                                        \
 672         __res;                                                          \
 673 })
 674
 675 #define __write_32bit_c0_ctrl_register(register, value)                 \
 676 do {                                                                    \
 677         __asm__ __volatile__(                                           \
 678                 "ctc0\t%z0, " #register "\n\t"                          \
 679                 : : "Jr" ((unsigned int)value));                        \
 680 } while (0)
 681
 682 /*
 683  * These versions are only needed for systems with more than 38 bits of
 684  * physical address space running the 32-bit kernel.  That's none atm :-)
 685  */
 686 #define __read_64bit_c0_split(source, sel)                              \
 687 ({                                                                      \
 688         unsigned long long val;                                         \
 689         unsigned long flags;                                            \
 690                                                                         \
 691         local_irq_save(flags);                                          \
 692         if (sel == 0)                                                   \
 693                 __asm__ __volatile__(                                   \
 694                         ".set\tmips64\n\t"                              \
 695                         "dmfc0\t%M0, " #source "\n\t"                   \
 696                         "dsll\t%L0, %M0, 32\n\t"                        \
 697                         "dsrl\t%M0, %M0, 32\n\t"                        \
 698                         "dsrl\t%L0, %L0, 32\n\t"                        \
 699                         ".set\tmips0"                                   \
 700                         : "=r" (val));                                  \
 701         else                                                            \
 702                 __asm__ __volatile__(                                   \
 703                         ".set\tmips64\n\t"                              \
 704                         "dmfc0\t%M0, " #source ", " #sel "\n\t"         \
 705                         "dsll\t%L0, %M0, 32\n\t"                        \
 706                         "dsrl\t%M0, %M0, 32\n\t"                        \
 707                         "dsrl\t%L0, %L0, 32\n\t"                        \
 708                         ".set\tmips0"                                   \
 709                         : "=r" (val));                                  \
 710         local_irq_restore(flags);                                       \
 711                                                                         \
 712         val;                                                            \
 713 })
 714
 715 #define __write_64bit_c0_split(source, sel, val)                        \
 716 do {                                                                    \
 717         unsigned long flags;                                            \
 718                                                                         \
 719         local_irq_save(flags);                                          \
 720         if (sel == 0)                                                   \
 721                 __asm__ __volatile__(                                   \
 722                         ".set\tmips64\n\t"                              \
 723                         "dsll\t%L0, %L0, 32\n\t"                        \
 724                         "dsrl\t%L0, %L0, 32\n\t"                        \
 725                         "dsll\t%M0, %M0, 32\n\t"                        \
 726                         "or\t%L0, %L0, %M0\n\t"                         \
 727                         "dmtc0\t%L0, " #source "\n\t"                   \
 728                         ".set\tmips0"                                   \
 729                         : : "r" (val));                                 \
 730         else                                                            \
 731                 __asm__ __volatile__(                                   \
 732                         ".set\tmips64\n\t"                              \
 733                         "dsll\t%L0, %L0, 32\n\t"                        \
 734                         "dsrl\t%L0, %L0, 32\n\t"                        \
 735                         "dsll\t%M0, %M0, 32\n\t"                        \
 736                         "or\t%L0, %L0, %M0\n\t"                         \
 737                         "dmtc0\t%L0, " #source ", " #sel "\n\t"         \
 738                         ".set\tmips0"                                   \
 739                         : : "r" (val));                                 \
 740         local_irq_restore(flags);                                       \
 741 } while (0)
 742
 743 #define read_c0_index()         __read_32bit_c0_register($0, 0)
 744 #define write_c0_index(val)     __write_32bit_c0_register($0, 0, val)
 745
 746 #define read_c0_entrylo0()      __read_ulong_c0_register($2, 0)
 747 #define write_c0_entrylo0(val)  __write_ulong_c0_register($2, 0, val)
 748
 749 #define read_c0_entrylo1()      __read_ulong_c0_register($3, 0)
 750 #define write_c0_entrylo1(val)  __write_ulong_c0_register($3, 0, val)
 751
 752 #define read_c0_conf()          __read_32bit_c0_register($3, 0)
 753 #define write_c0_conf(val)      __write_32bit_c0_register($3, 0, val)
 754
 755 #define read_c0_context()       __read_ulong_c0_register($4, 0)
 756 #define write_c0_context(val)   __write_ulong_c0_register($4, 0, val)
 757
 758 #define read_c0_pagemask()      __read_32bit_c0_register($5, 0)
 759 #define write_c0_pagemask(val)  __write_32bit_c0_register($5, 0, val)
 760
 761 #define read_c0_wired()         __read_32bit_c0_register($6, 0)
 762 #define write_c0_wired(val)     __write_32bit_c0_register($6, 0, val)
 763
 764 #define read_c0_info()          __read_32bit_c0_register($7, 0)
 765
 766 #define read_c0_cache()         __read_32bit_c0_register($7, 0) /* TX39xx */
 767 #define write_c0_cache(val)     __write_32bit_c0_register($7, 0, val)
 768
 769 #define read_c0_count()         __read_32bit_c0_register($9, 0)
 770 #define write_c0_count(val)     __write_32bit_c0_register($9, 0, val)
 771
 772 #define read_c0_entryhi()       __read_ulong_c0_register($10, 0)
 773 #define write_c0_entryhi(val)   __write_ulong_c0_register($10, 0, val)
 774
 775 #define read_c0_compare()       __read_32bit_c0_register($11, 0)
 776 #define write_c0_compare(val)   __write_32bit_c0_register($11, 0, val)
 777
 778 #define read_c0_status()        __read_32bit_c0_register($12, 0)
 779 #define write_c0_status(val)    __write_32bit_c0_register($12, 0, val)
 780
 781 #define read_c0_cause()         __read_32bit_c0_register($13, 0)
 782 #define write_c0_cause(val)     __write_32bit_c0_register($13, 0, val)
 783
 784 #define read_c0_epc()           __read_ulong_c0_register($14, 0)
 785 #define write_c0_epc(val)       __write_ulong_c0_register($14, 0, val)
 786
 787 #define read_c0_prid()          __read_32bit_c0_register($15, 0)
 788
 789 #define read_c0_config()        __read_32bit_c0_register($16, 0)
 790 #define read_c0_config1()       __read_32bit_c0_register($16, 1)
 791 #define read_c0_config2()       __read_32bit_c0_register($16, 2)
 792 #define read_c0_config3()       __read_32bit_c0_register($16, 3)
 793 #define write_c0_config(val)    __write_32bit_c0_register($16, 0, val)
 794 #define write_c0_config1(val)   __write_32bit_c0_register($16, 1, val)
 795 #define write_c0_config2(val)   __write_32bit_c0_register($16, 2, val)
 796 #define write_c0_config3(val)   __write_32bit_c0_register($16, 3, val)
 797
 798 /*
 799  * The WatchLo register.  There may be upto 8 of them.
 800  */
 801 #define read_c0_watchlo0()      __read_ulong_c0_register($18, 0)
 802 #define read_c0_watchlo1()      __read_ulong_c0_register($18, 1)
 803 #define read_c0_watchlo2()      __read_ulong_c0_register($18, 2)
 804 #define read_c0_watchlo3()      __read_ulong_c0_register($18, 3)
 805 #define read_c0_watchlo4()      __read_ulong_c0_register($18, 4)
 806 #define read_c0_watchlo5()      __read_ulong_c0_register($18, 5)
 807 #define read_c0_watchlo6()      __read_ulong_c0_register($18, 6)
 808 #define read_c0_watchlo7()      __read_ulong_c0_register($18, 7)
 809 #define write_c0_watchlo0(val)  __write_ulong_c0_register($18, 0, val)
 810 #define write_c0_watchlo1(val)  __write_ulong_c0_register($18, 1, val)
 811 #define write_c0_watchlo2(val)  __write_ulong_c0_register($18, 2, val)
 812 #define write_c0_watchlo3(val)  __write_ulong_c0_register($18, 3, val)
 813 #define write_c0_watchlo4(val)  __write_ulong_c0_register($18, 4, val)
 814 #define write_c0_watchlo5(val)  __write_ulong_c0_register($18, 5, val)
 815 #define write_c0_watchlo6(val)  __write_ulong_c0_register($18, 6, val)
 816 #define write_c0_watchlo7(val)  __write_ulong_c0_register($18, 7, val)
 817
 818 /*
 819  * The WatchHi register.  There may be upto 8 of them.
 820  */
 821 #define read_c0_watchhi0()      __read_32bit_c0_register($19, 0)
 822 #define read_c0_watchhi1()      __read_32bit_c0_register($19, 1)
 823 #define read_c0_watchhi2()      __read_32bit_c0_register($19, 2)
 824 #define read_c0_watchhi3()      __read_32bit_c0_register($19, 3)
 825 #define read_c0_watchhi4()      __read_32bit_c0_register($19, 4)
 826 #define read_c0_watchhi5()      __read_32bit_c0_register($19, 5)
 827 #define read_c0_watchhi6()      __read_32bit_c0_register($19, 6)
 828 #define read_c0_watchhi7()      __read_32bit_c0_register($19, 7)
 829
 830 #define write_c0_watchhi0(val)  __write_32bit_c0_register($19, 0, val)
 831 #define write_c0_watchhi1(val)  __write_32bit_c0_register($19, 1, val)
 832 #define write_c0_watchhi2(val)  __write_32bit_c0_register($19, 2, val)
 833 #define write_c0_watchhi3(val)  __write_32bit_c0_register($19, 3, val)
 834 #define write_c0_watchhi4(val)  __write_32bit_c0_register($19, 4, val)
 835 #define write_c0_watchhi5(val)  __write_32bit_c0_register($19, 5, val)
 836 #define write_c0_watchhi6(val)  __write_32bit_c0_register($19, 6, val)
 837 #define write_c0_watchhi7(val)  __write_32bit_c0_register($19, 7, val)
 838
 839 #define read_c0_xcontext()      __read_ulong_c0_register($20, 0)
 840 #define write_c0_xcontext(val)  __write_ulong_c0_register($20, 0, val)
 841
 842 #define read_c0_intcontrol()    __read_32bit_c0_ctrl_register($20)
 843 #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
 844
 845 #define read_c0_framemask()     __read_32bit_c0_register($21, 0)
 846 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
 847
 848 /* RM9000 PerfControl performance counter control register */
 849 #define read_c0_perfcontrol()   __read_32bit_c0_register($22, 0)
 850 #define write_c0_perfcontrol(val) __write_32bit_c0_register($22, 0, val)
 851
 852 #define read_c0_diag()          __read_32bit_c0_register($22, 0)
 853 #define write_c0_diag(val)      __write_32bit_c0_register($22, 0, val)
 854
 855 #define read_c0_diag1()         __read_32bit_c0_register($22, 1)
 856 #define write_c0_diag1(val)     __write_32bit_c0_register($22, 1, val)
 857
 858 #define read_c0_diag2()         __read_32bit_c0_register($22, 2)
 859 #define write_c0_diag2(val)     __write_32bit_c0_register($22, 2, val)
 860
 861 #define read_c0_diag3()         __read_32bit_c0_register($22, 3)
 862 #define write_c0_diag3(val)     __write_32bit_c0_register($22, 3, val)
 863
 864 #define read_c0_diag4()         __read_32bit_c0_register($22, 4)
 865 #define write_c0_diag4(val)     __write_32bit_c0_register($22, 4, val)
 866
 867 #define read_c0_diag5()         __read_32bit_c0_register($22, 5)
 868 #define write_c0_diag5(val)     __write_32bit_c0_register($22, 5, val)
 869
 870 #define read_c0_debug()         __read_32bit_c0_register($23, 0)
 871 #define write_c0_debug(val)     __write_32bit_c0_register($23, 0, val)
 872
 873 #define read_c0_depc()          __read_ulong_c0_register($24, 0)
 874 #define write_c0_depc(val)      __write_ulong_c0_register($24, 0, val)
 875
 876 /*
 877  * MIPS32 / MIPS64 performance counters
 878  */
 879 #define read_c0_perfctrl0()     __read_32bit_c0_register($25, 0)
 880 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
 881 #define read_c0_perfcntr0()     __read_32bit_c0_register($25, 1)
 882 #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
 883 #define read_c0_perfctrl1()     __read_32bit_c0_register($25, 2)
 884 #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
 885 #define read_c0_perfcntr1()     __read_32bit_c0_register($25, 3)
 886 #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
 887 #define read_c0_perfctrl2()     __read_32bit_c0_register($25, 4)
 888 #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
 889 #define read_c0_perfcntr2()     __read_32bit_c0_register($25, 5)
 890 #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
 891 #define read_c0_perfctrl3()     __read_32bit_c0_register($25, 6)
 892 #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
 893 #define read_c0_perfcntr3()     __read_32bit_c0_register($25, 7)
 894 #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
 895
 896 /* RM9000 PerfCount performance counter register */
 897 #define read_c0_perfcount()     __read_64bit_c0_register($25, 0)
 898 #define write_c0_perfcount(val) __write_64bit_c0_register($25, 0, val)
 899
 900 #define read_c0_ecc()           __read_32bit_c0_register($26, 0)
 901 #define write_c0_ecc(val)       __write_32bit_c0_register($26, 0, val)
 902
 903 #define read_c0_derraddr0()     __read_ulong_c0_register($26, 1)
 904 #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
 905
 906 #define read_c0_cacheerr()      __read_32bit_c0_register($27, 0)
 907
 908 #define read_c0_derraddr1()     __read_ulong_c0_register($27, 1)
 909 #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
 910
 911 #define read_c0_taglo()         __read_32bit_c0_register($28, 0)
 912 #define write_c0_taglo(val)     __write_32bit_c0_register($28, 0, val)
 913
 914 #define read_c0_taghi()         __read_32bit_c0_register($29, 0)
 915 #define write_c0_taghi(val)     __write_32bit_c0_register($29, 0, val)
 916
 917 #define read_c0_errorepc()      __read_ulong_c0_register($30, 0)
 918 #define write_c0_errorepc(val)  __write_ulong_c0_register($30, 0, val)
 919
 920 /*
 921  * Macros to access the floating point coprocessor control registers
 922  */
 923 #define read_32bit_cp1_register(source)                         \
 924 ({ int __res;                                                   \
 925         __asm__ __volatile__(                                   \
 926         ".set\tpush\n\t"                                        \
 927         ".set\treorder\n\t"                                     \
 928         "cfc1\t%0,"STR(source)"\n\t"                            \
 929         ".set\tpop"                                             \
 930         : "=r" (__res));                                        \
 931         __res;})
 932
 933 /*
 934  * TLB operations.
 935  *
 936  * It is responsibility of the caller to take care of any TLB hazards.
 937  */
 938 static inline void tlb_probe(void)
 939 {
 940         __asm__ __volatile__(
 941                 ".set noreorder\n\t"
 942                 "tlbp\n\t"
 943                 ".set reorder");
 944 }
 945
 946 static inline void tlb_read(void)
 947 {
 948         __asm__ __volatile__(
 949                 ".set noreorder\n\t"
 950                 "tlbr\n\t"
 951                 ".set reorder");
 952 }
 953
 954 static inline void tlb_write_indexed(void)
 955 {
 956         __asm__ __volatile__(
 957                 ".set noreorder\n\t"
 958                 "tlbwi\n\t"
 959                 ".set reorder");
 960 }
 961
 962 static inline void tlb_write_random(void)
 963 {
 964         __asm__ __volatile__(
 965                 ".set noreorder\n\t"
 966                 "tlbwr\n\t"
 967                 ".set reorder");
 968 }
 969
 970 /*
 971  * Manipulate bits in a c0 register.
 972  */
 973 #define __BUILD_SET_C0(name)                                    \
 974 static inline unsigned int                                      \
 975 set_c0_##name(unsigned int set)                                 \
 976 {                                                               \
 977         unsigned int res;                                       \
 978                                                                 \
 979         res = read_c0_##name();                                 \
 980         res |= set;                                             \
 981         write_c0_##name(res);                                   \
 982                                                                 \
 983         return res;                                             \
 984 }                                                               \
 985                                                                 \
 986 static inline unsigned int                                      \
 987 clear_c0_##name(unsigned int clear)                             \
 988 {                                                               \
 989         unsigned int res;                                       \
 990                                                                 \
 991         res = read_c0_##name();                                 \
 992         res &= ~clear;                                          \
 993         write_c0_##name(res);                                   \
 994                                                                 \
 995         return res;                                             \
 996 }                                                               \
 997                                                                 \
 998 static inline unsigned int                                      \
 999 change_c0_##name(unsigned int change, unsigned int new)         \
1000 {                                                               \
1001         unsigned int res;                                       \
1002                                                                 \
1003         res = read_c0_##name();                                 \
1004         res &= ~change;                                         \
1005         res |= (new & change);                                  \
1006         write_c0_##name(res);                                   \
1007                                                                 \
1008         return res;                                             \
1009 }
1010
1011 __BUILD_SET_C0(status)
1012 __BUILD_SET_C0(cause)
1013 __BUILD_SET_C0(config)
1014 __BUILD_SET_C0(intcontrol)
1015
1016 #endif /* !__ASSEMBLY__ */
1017
1018 #endif /* _ASM_MIPSREGS_H */