Merge git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6
[linux-2.6] / arch / powerpc / boot / dts / mpc8541cds.dts
1 /*
2  * MPC8541 CDS Device Tree Source
3  *
4  * Copyright 2006, 2008 Freescale Semiconductor Inc.
5  *
6  * This program is free software; you can redistribute  it and/or modify it
7  * under  the terms of  the GNU General  Public License as published by the
8  * Free Software Foundation;  either version 2 of the  License, or (at your
9  * option) any later version.
10  */
11
12 /dts-v1/;
13
14 / {
15         model = "MPC8541CDS";
16         compatible = "MPC8541CDS", "MPC85xxCDS";
17         #address-cells = <1>;
18         #size-cells = <1>;
19
20         aliases {
21                 ethernet0 = &enet0;
22                 ethernet1 = &enet1;
23                 serial0 = &serial0;
24                 serial1 = &serial1;
25                 pci0 = &pci0;
26                 pci1 = &pci1;
27         };
28
29         cpus {
30                 #address-cells = <1>;
31                 #size-cells = <0>;
32
33                 PowerPC,8541@0 {
34                         device_type = "cpu";
35                         reg = <0x0>;
36                         d-cache-line-size = <32>;       // 32 bytes
37                         i-cache-line-size = <32>;       // 32 bytes
38                         d-cache-size = <0x8000>;                // L1, 32K
39                         i-cache-size = <0x8000>;                // L1, 32K
40                         timebase-frequency = <0>;       //  33 MHz, from uboot
41                         bus-frequency = <0>;    // 166 MHz
42                         clock-frequency = <0>;  // 825 MHz, from uboot
43                         next-level-cache = <&L2>;
44                 };
45         };
46
47         memory {
48                 device_type = "memory";
49                 reg = <0x0 0x8000000>;  // 128M at 0x0
50         };
51
52         soc8541@e0000000 {
53                 #address-cells = <1>;
54                 #size-cells = <1>;
55                 device_type = "soc";
56                 compatible = "simple-bus";
57                 ranges = <0x0 0xe0000000 0x100000>;
58                 reg = <0xe0000000 0x1000>;      // CCSRBAR 1M
59                 bus-frequency = <0>;
60
61                 memory-controller@2000 {
62                         compatible = "fsl,8541-memory-controller";
63                         reg = <0x2000 0x1000>;
64                         interrupt-parent = <&mpic>;
65                         interrupts = <18 2>;
66                 };
67
68                 L2: l2-cache-controller@20000 {
69                         compatible = "fsl,8541-l2-cache-controller";
70                         reg = <0x20000 0x1000>;
71                         cache-line-size = <32>; // 32 bytes
72                         cache-size = <0x40000>; // L2, 256K
73                         interrupt-parent = <&mpic>;
74                         interrupts = <16 2>;
75                 };
76
77                 i2c@3000 {
78                         #address-cells = <1>;
79                         #size-cells = <0>;
80                         cell-index = <0>;
81                         compatible = "fsl-i2c";
82                         reg = <0x3000 0x100>;
83                         interrupts = <43 2>;
84                         interrupt-parent = <&mpic>;
85                         dfsrr;
86                 };
87
88                 dma@21300 {
89                         #address-cells = <1>;
90                         #size-cells = <1>;
91                         compatible = "fsl,mpc8541-dma", "fsl,eloplus-dma";
92                         reg = <0x21300 0x4>;
93                         ranges = <0x0 0x21100 0x200>;
94                         cell-index = <0>;
95                         dma-channel@0 {
96                                 compatible = "fsl,mpc8541-dma-channel",
97                                                 "fsl,eloplus-dma-channel";
98                                 reg = <0x0 0x80>;
99                                 cell-index = <0>;
100                                 interrupt-parent = <&mpic>;
101                                 interrupts = <20 2>;
102                         };
103                         dma-channel@80 {
104                                 compatible = "fsl,mpc8541-dma-channel",
105                                                 "fsl,eloplus-dma-channel";
106                                 reg = <0x80 0x80>;
107                                 cell-index = <1>;
108                                 interrupt-parent = <&mpic>;
109                                 interrupts = <21 2>;
110                         };
111                         dma-channel@100 {
112                                 compatible = "fsl,mpc8541-dma-channel",
113                                                 "fsl,eloplus-dma-channel";
114                                 reg = <0x100 0x80>;
115                                 cell-index = <2>;
116                                 interrupt-parent = <&mpic>;
117                                 interrupts = <22 2>;
118                         };
119                         dma-channel@180 {
120                                 compatible = "fsl,mpc8541-dma-channel",
121                                                 "fsl,eloplus-dma-channel";
122                                 reg = <0x180 0x80>;
123                                 cell-index = <3>;
124                                 interrupt-parent = <&mpic>;
125                                 interrupts = <23 2>;
126                         };
127                 };
128
129                 enet0: ethernet@24000 {
130                         #address-cells = <1>;
131                         #size-cells = <1>;
132                         cell-index = <0>;
133                         device_type = "network";
134                         model = "TSEC";
135                         compatible = "gianfar";
136                         reg = <0x24000 0x1000>;
137                         ranges = <0x0 0x24000 0x1000>;
138                         local-mac-address = [ 00 00 00 00 00 00 ];
139                         interrupts = <29 2 30 2 34 2>;
140                         interrupt-parent = <&mpic>;
141                         tbi-handle = <&tbi0>;
142                         phy-handle = <&phy0>;
143
144                         mdio@520 {
145                                 #address-cells = <1>;
146                                 #size-cells = <0>;
147                                 compatible = "fsl,gianfar-mdio";
148                                 reg = <0x520 0x20>;
149
150                                 phy0: ethernet-phy@0 {
151                                         interrupt-parent = <&mpic>;
152                                         interrupts = <5 1>;
153                                         reg = <0x0>;
154                                         device_type = "ethernet-phy";
155                                 };
156                                 phy1: ethernet-phy@1 {
157                                         interrupt-parent = <&mpic>;
158                                         interrupts = <5 1>;
159                                         reg = <0x1>;
160                                         device_type = "ethernet-phy";
161                                 };
162                                 tbi0: tbi-phy@11 {
163                                         reg = <0x11>;
164                                         device_type = "tbi-phy";
165                                 };
166                         };
167                 };
168
169                 enet1: ethernet@25000 {
170                         #address-cells = <1>;
171                         #size-cells = <1>;
172                         cell-index = <1>;
173                         device_type = "network";
174                         model = "TSEC";
175                         compatible = "gianfar";
176                         reg = <0x25000 0x1000>;
177                         ranges = <0x0 0x25000 0x1000>;
178                         local-mac-address = [ 00 00 00 00 00 00 ];
179                         interrupts = <35 2 36 2 40 2>;
180                         interrupt-parent = <&mpic>;
181                         tbi-handle = <&tbi1>;
182                         phy-handle = <&phy1>;
183
184                         mdio@520 {
185                                 #address-cells = <1>;
186                                 #size-cells = <0>;
187                                 compatible = "fsl,gianfar-tbi";
188                                 reg = <0x520 0x20>;
189
190                                 tbi1: tbi-phy@11 {
191                                         reg = <0x11>;
192                                         device_type = "tbi-phy";
193                                 };
194                         };
195                 };
196
197                 serial0: serial@4500 {
198                         cell-index = <0>;
199                         device_type = "serial";
200                         compatible = "ns16550";
201                         reg = <0x4500 0x100>;   // reg base, size
202                         clock-frequency = <0>;  // should we fill in in uboot?
203                         interrupts = <42 2>;
204                         interrupt-parent = <&mpic>;
205                 };
206
207                 serial1: serial@4600 {
208                         cell-index = <1>;
209                         device_type = "serial";
210                         compatible = "ns16550";
211                         reg = <0x4600 0x100>;   // reg base, size
212                         clock-frequency = <0>;  // should we fill in in uboot?
213                         interrupts = <42 2>;
214                         interrupt-parent = <&mpic>;
215                 };
216
217                 crypto@30000 {
218                         compatible = "fsl,sec2.0";
219                         reg = <0x30000 0x10000>;
220                         interrupts = <45 2>;
221                         interrupt-parent = <&mpic>;
222                         fsl,num-channels = <4>;
223                         fsl,channel-fifo-len = <24>;
224                         fsl,exec-units-mask = <0x7e>;
225                         fsl,descriptor-types-mask = <0x01010ebf>;
226                 };
227
228                 mpic: pic@40000 {
229                         interrupt-controller;
230                         #address-cells = <0>;
231                         #interrupt-cells = <2>;
232                         reg = <0x40000 0x40000>;
233                         compatible = "chrp,open-pic";
234                         device_type = "open-pic";
235                 };
236
237                 cpm@919c0 {
238                         #address-cells = <1>;
239                         #size-cells = <1>;
240                         compatible = "fsl,mpc8541-cpm", "fsl,cpm2";
241                         reg = <0x919c0 0x30>;
242                         ranges;
243
244                         muram@80000 {
245                                 #address-cells = <1>;
246                                 #size-cells = <1>;
247                                 ranges = <0x0 0x80000 0x10000>;
248
249                                 data@0 {
250                                         compatible = "fsl,cpm-muram-data";
251                                         reg = <0x0 0x2000 0x9000 0x1000>;
252                                 };
253                         };
254
255                         brg@919f0 {
256                                 compatible = "fsl,mpc8541-brg",
257                                              "fsl,cpm2-brg",
258                                              "fsl,cpm-brg";
259                                 reg = <0x919f0 0x10 0x915f0 0x10>;
260                         };
261
262                         cpmpic: pic@90c00 {
263                                 interrupt-controller;
264                                 #address-cells = <0>;
265                                 #interrupt-cells = <2>;
266                                 interrupts = <46 2>;
267                                 interrupt-parent = <&mpic>;
268                                 reg = <0x90c00 0x80>;
269                                 compatible = "fsl,mpc8541-cpm-pic", "fsl,cpm2-pic";
270                         };
271                 };
272         };
273
274         pci0: pci@e0008000 {
275                 cell-index = <0>;
276                 interrupt-map-mask = <0x1f800 0x0 0x0 0x7>;
277                 interrupt-map = <
278
279                         /* IDSEL 0x10 */
280                         0x8000 0x0 0x0 0x1 &mpic 0x0 0x1
281                         0x8000 0x0 0x0 0x2 &mpic 0x1 0x1
282                         0x8000 0x0 0x0 0x3 &mpic 0x2 0x1
283                         0x8000 0x0 0x0 0x4 &mpic 0x3 0x1
284
285                         /* IDSEL 0x11 */
286                         0x8800 0x0 0x0 0x1 &mpic 0x0 0x1
287                         0x8800 0x0 0x0 0x2 &mpic 0x1 0x1
288                         0x8800 0x0 0x0 0x3 &mpic 0x2 0x1
289                         0x8800 0x0 0x0 0x4 &mpic 0x3 0x1
290
291                         /* IDSEL 0x12 (Slot 1) */
292                         0x9000 0x0 0x0 0x1 &mpic 0x0 0x1
293                         0x9000 0x0 0x0 0x2 &mpic 0x1 0x1
294                         0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
295                         0x9000 0x0 0x0 0x4 &mpic 0x3 0x1
296
297                         /* IDSEL 0x13 (Slot 2) */
298                         0x9800 0x0 0x0 0x1 &mpic 0x1 0x1
299                         0x9800 0x0 0x0 0x2 &mpic 0x2 0x1
300                         0x9800 0x0 0x0 0x3 &mpic 0x3 0x1
301                         0x9800 0x0 0x0 0x4 &mpic 0x0 0x1
302
303                         /* IDSEL 0x14 (Slot 3) */
304                         0xa000 0x0 0x0 0x1 &mpic 0x2 0x1
305                         0xa000 0x0 0x0 0x2 &mpic 0x3 0x1
306                         0xa000 0x0 0x0 0x3 &mpic 0x0 0x1
307                         0xa000 0x0 0x0 0x4 &mpic 0x1 0x1
308
309                         /* IDSEL 0x15 (Slot 4) */
310                         0xa800 0x0 0x0 0x1 &mpic 0x3 0x1
311                         0xa800 0x0 0x0 0x2 &mpic 0x0 0x1
312                         0xa800 0x0 0x0 0x3 &mpic 0x1 0x1
313                         0xa800 0x0 0x0 0x4 &mpic 0x2 0x1
314
315                         /* Bus 1 (Tundra Bridge) */
316                         /* IDSEL 0x12 (ISA bridge) */
317                         0x19000 0x0 0x0 0x1 &mpic 0x0 0x1
318                         0x19000 0x0 0x0 0x2 &mpic 0x1 0x1
319                         0x19000 0x0 0x0 0x3 &mpic 0x2 0x1
320                         0x19000 0x0 0x0 0x4 &mpic 0x3 0x1>;
321                 interrupt-parent = <&mpic>;
322                 interrupts = <24 2>;
323                 bus-range = <0 0>;
324                 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
325                           0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
326                 clock-frequency = <66666666>;
327                 #interrupt-cells = <1>;
328                 #size-cells = <2>;
329                 #address-cells = <3>;
330                 reg = <0xe0008000 0x1000>;
331                 compatible = "fsl,mpc8540-pci";
332                 device_type = "pci";
333
334                 i8259@19000 {
335                         interrupt-controller;
336                         device_type = "interrupt-controller";
337                         reg = <0x19000 0x0 0x0 0x0 0x1>;
338                         #address-cells = <0>;
339                         #interrupt-cells = <2>;
340                         compatible = "chrp,iic";
341                         interrupts = <1>;
342                         interrupt-parent = <&pci0>;
343                 };
344         };
345
346         pci1: pci@e0009000 {
347                 cell-index = <1>;
348                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
349                 interrupt-map = <
350
351                         /* IDSEL 0x15 */
352                         0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
353                         0xa800 0x0 0x0 0x2 &mpic 0xb 0x1
354                         0xa800 0x0 0x0 0x3 &mpic 0xb 0x1
355                         0xa800 0x0 0x0 0x4 &mpic 0xb 0x1>;
356                 interrupt-parent = <&mpic>;
357                 interrupts = <25 2>;
358                 bus-range = <0 0>;
359                 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
360                           0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
361                 clock-frequency = <66666666>;
362                 #interrupt-cells = <1>;
363                 #size-cells = <2>;
364                 #address-cells = <3>;
365                 reg = <0xe0009000 0x1000>;
366                 compatible = "fsl,mpc8540-pci";
367                 device_type = "pci";
368         };
369 };