2 * MPC8641 HPCN Device Tree Source
4 * Copyright 2006 Freescale Semiconductor Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
15 model = "MPC8641HPCN";
16 compatible = "fsl,mpc8641hpcn";
30 * Only one of Rapid IO or PCI can be present due to HW limitations and
31 * due to the fact that the 2 now share address space in the new memory
32 * map. The most likely case is that we have PCI, so comment out the
33 * rapidio node. Leave it here for reference.
35 /* rapidio0 = &rapidio0; */
45 d-cache-line-size = <32>;
46 i-cache-line-size = <32>;
47 d-cache-size = <32768>; // L1
48 i-cache-size = <32768>; // L1
49 timebase-frequency = <0>; // From uboot
50 bus-frequency = <0>; // From uboot
51 clock-frequency = <0>; // From uboot
56 d-cache-line-size = <32>;
57 i-cache-line-size = <32>;
58 d-cache-size = <32768>;
59 i-cache-size = <32768>;
60 timebase-frequency = <0>; // From uboot
61 bus-frequency = <0>; // From uboot
62 clock-frequency = <0>; // From uboot
67 device_type = "memory";
68 reg = <0x00000000 0x40000000>; // 1G at 0x0
74 compatible = "fsl,mpc8641-localbus", "simple-bus";
75 reg = <0xffe05000 0x1000>;
77 interrupt-parent = <&mpic>;
79 ranges = <0 0 0xef800000 0x00800000
80 2 0 0xffdf8000 0x00008000
81 3 0 0xffdf0000 0x00008000>;
84 compatible = "cfi-flash";
85 reg = <0 0 0x00800000>;
92 reg = <0x00000000 0x00300000>;
96 reg = <0x00300000 0x00100000>;
101 reg = <0x00400000 0x00300000>;
104 label = "firmware a";
105 reg = <0x00700000 0x00100000>;
112 #address-cells = <1>;
115 compatible = "simple-bus";
116 ranges = <0x00000000 0xffe00000 0x00100000>;
117 reg = <0xffe00000 0x00001000>; // CCSRBAR
121 #address-cells = <1>;
124 compatible = "fsl-i2c";
125 reg = <0x3000 0x100>;
127 interrupt-parent = <&mpic>;
132 #address-cells = <1>;
135 compatible = "fsl-i2c";
136 reg = <0x3100 0x100>;
138 interrupt-parent = <&mpic>;
143 #address-cells = <1>;
145 compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
147 ranges = <0x0 0x21100 0x200>;
150 compatible = "fsl,mpc8641-dma-channel",
151 "fsl,eloplus-dma-channel";
154 interrupt-parent = <&mpic>;
158 compatible = "fsl,mpc8641-dma-channel",
159 "fsl,eloplus-dma-channel";
162 interrupt-parent = <&mpic>;
166 compatible = "fsl,mpc8641-dma-channel",
167 "fsl,eloplus-dma-channel";
170 interrupt-parent = <&mpic>;
174 compatible = "fsl,mpc8641-dma-channel",
175 "fsl,eloplus-dma-channel";
178 interrupt-parent = <&mpic>;
183 enet0: ethernet@24000 {
184 #address-cells = <1>;
187 device_type = "network";
189 compatible = "gianfar";
190 reg = <0x24000 0x1000>;
191 ranges = <0x0 0x24000 0x1000>;
192 local-mac-address = [ 00 00 00 00 00 00 ];
193 interrupts = <29 2 30 2 34 2>;
194 interrupt-parent = <&mpic>;
195 tbi-handle = <&tbi0>;
196 phy-handle = <&phy0>;
197 phy-connection-type = "rgmii-id";
200 #address-cells = <1>;
202 compatible = "fsl,gianfar-mdio";
205 phy0: ethernet-phy@0 {
206 interrupt-parent = <&mpic>;
209 device_type = "ethernet-phy";
211 phy1: ethernet-phy@1 {
212 interrupt-parent = <&mpic>;
215 device_type = "ethernet-phy";
217 phy2: ethernet-phy@2 {
218 interrupt-parent = <&mpic>;
221 device_type = "ethernet-phy";
223 phy3: ethernet-phy@3 {
224 interrupt-parent = <&mpic>;
227 device_type = "ethernet-phy";
231 device_type = "tbi-phy";
236 enet1: ethernet@25000 {
237 #address-cells = <1>;
240 device_type = "network";
242 compatible = "gianfar";
243 reg = <0x25000 0x1000>;
244 ranges = <0x0 0x25000 0x1000>;
245 local-mac-address = [ 00 00 00 00 00 00 ];
246 interrupts = <35 2 36 2 40 2>;
247 interrupt-parent = <&mpic>;
248 tbi-handle = <&tbi1>;
249 phy-handle = <&phy1>;
250 phy-connection-type = "rgmii-id";
253 #address-cells = <1>;
255 compatible = "fsl,gianfar-tbi";
260 device_type = "tbi-phy";
265 enet2: ethernet@26000 {
266 #address-cells = <1>;
269 device_type = "network";
271 compatible = "gianfar";
272 reg = <0x26000 0x1000>;
273 ranges = <0x0 0x26000 0x1000>;
274 local-mac-address = [ 00 00 00 00 00 00 ];
275 interrupts = <31 2 32 2 33 2>;
276 interrupt-parent = <&mpic>;
277 tbi-handle = <&tbi2>;
278 phy-handle = <&phy2>;
279 phy-connection-type = "rgmii-id";
282 #address-cells = <1>;
284 compatible = "fsl,gianfar-tbi";
289 device_type = "tbi-phy";
294 enet3: ethernet@27000 {
295 #address-cells = <1>;
298 device_type = "network";
300 compatible = "gianfar";
301 reg = <0x27000 0x1000>;
302 ranges = <0x0 0x27000 0x1000>;
303 local-mac-address = [ 00 00 00 00 00 00 ];
304 interrupts = <37 2 38 2 39 2>;
305 interrupt-parent = <&mpic>;
306 tbi-handle = <&tbi3>;
307 phy-handle = <&phy3>;
308 phy-connection-type = "rgmii-id";
311 #address-cells = <1>;
313 compatible = "fsl,gianfar-tbi";
318 device_type = "tbi-phy";
323 serial0: serial@4500 {
325 device_type = "serial";
326 compatible = "ns16550";
327 reg = <0x4500 0x100>;
328 clock-frequency = <0>;
330 interrupt-parent = <&mpic>;
333 serial1: serial@4600 {
335 device_type = "serial";
336 compatible = "ns16550";
337 reg = <0x4600 0x100>;
338 clock-frequency = <0>;
340 interrupt-parent = <&mpic>;
344 interrupt-controller;
345 #address-cells = <0>;
346 #interrupt-cells = <2>;
347 reg = <0x40000 0x40000>;
348 compatible = "chrp,open-pic";
349 device_type = "open-pic";
352 global-utilities@e0000 {
353 compatible = "fsl,mpc8641-guts";
354 reg = <0xe0000 0x1000>;
359 pci0: pcie@ffe08000 {
361 compatible = "fsl,mpc8641-pcie";
363 #interrupt-cells = <1>;
365 #address-cells = <3>;
366 reg = <0xffe08000 0x1000>;
367 bus-range = <0x0 0xff>;
368 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
369 0x01000000 0x0 0x00000000 0xffc00000 0x0 0x00010000>;
370 clock-frequency = <33333333>;
371 interrupt-parent = <&mpic>;
373 interrupt-map-mask = <0xff00 0 0 7>;
375 /* IDSEL 0x11 func 0 - PCI slot 1 */
376 0x8800 0 0 1 &mpic 2 1
377 0x8800 0 0 2 &mpic 3 1
378 0x8800 0 0 3 &mpic 4 1
379 0x8800 0 0 4 &mpic 1 1
381 /* IDSEL 0x11 func 1 - PCI slot 1 */
382 0x8900 0 0 1 &mpic 2 1
383 0x8900 0 0 2 &mpic 3 1
384 0x8900 0 0 3 &mpic 4 1
385 0x8900 0 0 4 &mpic 1 1
387 /* IDSEL 0x11 func 2 - PCI slot 1 */
388 0x8a00 0 0 1 &mpic 2 1
389 0x8a00 0 0 2 &mpic 3 1
390 0x8a00 0 0 3 &mpic 4 1
391 0x8a00 0 0 4 &mpic 1 1
393 /* IDSEL 0x11 func 3 - PCI slot 1 */
394 0x8b00 0 0 1 &mpic 2 1
395 0x8b00 0 0 2 &mpic 3 1
396 0x8b00 0 0 3 &mpic 4 1
397 0x8b00 0 0 4 &mpic 1 1
399 /* IDSEL 0x11 func 4 - PCI slot 1 */
400 0x8c00 0 0 1 &mpic 2 1
401 0x8c00 0 0 2 &mpic 3 1
402 0x8c00 0 0 3 &mpic 4 1
403 0x8c00 0 0 4 &mpic 1 1
405 /* IDSEL 0x11 func 5 - PCI slot 1 */
406 0x8d00 0 0 1 &mpic 2 1
407 0x8d00 0 0 2 &mpic 3 1
408 0x8d00 0 0 3 &mpic 4 1
409 0x8d00 0 0 4 &mpic 1 1
411 /* IDSEL 0x11 func 6 - PCI slot 1 */
412 0x8e00 0 0 1 &mpic 2 1
413 0x8e00 0 0 2 &mpic 3 1
414 0x8e00 0 0 3 &mpic 4 1
415 0x8e00 0 0 4 &mpic 1 1
417 /* IDSEL 0x11 func 7 - PCI slot 1 */
418 0x8f00 0 0 1 &mpic 2 1
419 0x8f00 0 0 2 &mpic 3 1
420 0x8f00 0 0 3 &mpic 4 1
421 0x8f00 0 0 4 &mpic 1 1
423 /* IDSEL 0x12 func 0 - PCI slot 2 */
424 0x9000 0 0 1 &mpic 3 1
425 0x9000 0 0 2 &mpic 4 1
426 0x9000 0 0 3 &mpic 1 1
427 0x9000 0 0 4 &mpic 2 1
429 /* IDSEL 0x12 func 1 - PCI slot 2 */
430 0x9100 0 0 1 &mpic 3 1
431 0x9100 0 0 2 &mpic 4 1
432 0x9100 0 0 3 &mpic 1 1
433 0x9100 0 0 4 &mpic 2 1
435 /* IDSEL 0x12 func 2 - PCI slot 2 */
436 0x9200 0 0 1 &mpic 3 1
437 0x9200 0 0 2 &mpic 4 1
438 0x9200 0 0 3 &mpic 1 1
439 0x9200 0 0 4 &mpic 2 1
441 /* IDSEL 0x12 func 3 - PCI slot 2 */
442 0x9300 0 0 1 &mpic 3 1
443 0x9300 0 0 2 &mpic 4 1
444 0x9300 0 0 3 &mpic 1 1
445 0x9300 0 0 4 &mpic 2 1
447 /* IDSEL 0x12 func 4 - PCI slot 2 */
448 0x9400 0 0 1 &mpic 3 1
449 0x9400 0 0 2 &mpic 4 1
450 0x9400 0 0 3 &mpic 1 1
451 0x9400 0 0 4 &mpic 2 1
453 /* IDSEL 0x12 func 5 - PCI slot 2 */
454 0x9500 0 0 1 &mpic 3 1
455 0x9500 0 0 2 &mpic 4 1
456 0x9500 0 0 3 &mpic 1 1
457 0x9500 0 0 4 &mpic 2 1
459 /* IDSEL 0x12 func 6 - PCI slot 2 */
460 0x9600 0 0 1 &mpic 3 1
461 0x9600 0 0 2 &mpic 4 1
462 0x9600 0 0 3 &mpic 1 1
463 0x9600 0 0 4 &mpic 2 1
465 /* IDSEL 0x12 func 7 - PCI slot 2 */
466 0x9700 0 0 1 &mpic 3 1
467 0x9700 0 0 2 &mpic 4 1
468 0x9700 0 0 3 &mpic 1 1
469 0x9700 0 0 4 &mpic 2 1
472 0xe000 0 0 1 &i8259 12 2
473 0xe100 0 0 2 &i8259 9 2
474 0xe200 0 0 3 &i8259 10 2
475 0xe300 0 0 4 &i8259 11 2
478 0xe800 0 0 1 &i8259 6 2
481 0xf000 0 0 1 &i8259 7 2
482 0xf100 0 0 1 &i8259 7 2
484 // IDSEL 0x1f IDE/SATA
485 0xf800 0 0 1 &i8259 14 2
486 0xf900 0 0 1 &i8259 5 2
492 #address-cells = <3>;
494 ranges = <0x02000000 0x0 0x80000000
495 0x02000000 0x0 0x80000000
498 0x01000000 0x0 0x00000000
499 0x01000000 0x0 0x00000000
504 #address-cells = <3>;
505 ranges = <0x02000000 0x0 0x80000000
506 0x02000000 0x0 0x80000000
508 0x01000000 0x0 0x00000000
509 0x01000000 0x0 0x00000000
513 #interrupt-cells = <2>;
515 #address-cells = <2>;
516 reg = <0xf000 0 0 0 0>;
517 ranges = <1 0 0x01000000 0 0
519 interrupt-parent = <&i8259>;
521 i8259: interrupt-controller@20 {
525 interrupt-controller;
526 device_type = "interrupt-controller";
527 #address-cells = <0>;
528 #interrupt-cells = <2>;
529 compatible = "chrp,iic";
531 interrupt-parent = <&mpic>;
536 #address-cells = <1>;
537 reg = <1 0x60 1 1 0x64 1>;
538 interrupts = <1 3 12 3>;
544 compatible = "pnpPNP,303";
549 compatible = "pnpPNP,f03";
560 reg = <1 0x400 0x80>;
568 pci1: pcie@ffe09000 {
570 compatible = "fsl,mpc8641-pcie";
572 #interrupt-cells = <1>;
574 #address-cells = <3>;
575 reg = <0xffe09000 0x1000>;
576 bus-range = <0 0xff>;
577 ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
578 0x01000000 0x0 0x00000000 0xffc10000 0x0 0x00010000>;
579 clock-frequency = <33333333>;
580 interrupt-parent = <&mpic>;
582 interrupt-map-mask = <0xf800 0 0 7>;
585 0x0000 0 0 1 &mpic 4 1
586 0x0000 0 0 2 &mpic 5 1
587 0x0000 0 0 3 &mpic 6 1
588 0x0000 0 0 4 &mpic 7 1
593 #address-cells = <3>;
595 ranges = <0x02000000 0x0 0xa0000000
596 0x02000000 0x0 0xa0000000
599 0x01000000 0x0 0x00000000
600 0x01000000 0x0 0x00000000
605 rapidio0: rapidio@ffec0000 {
606 #address-cells = <2>;
608 compatible = "fsl,rapidio-delta";
609 reg = <0xffec0000 0x20000>;
610 ranges = <0 0 0x80000000 0 0x20000000>;
611 interrupt-parent = <&mpic>;
612 // err_irq bell_outb_irq bell_inb_irq
613 // msg1_tx_irq msg1_rx_irq msg2_tx_irq msg2_rx_irq
614 interrupts = <48 2 49 2 50 2 53 2 54 2 55 2 56 2>;