2 * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
4 #ifndef _ASM_POWERPC_PPC_ASM_H
5 #define _ASM_POWERPC_PPC_ASM_H
7 #include <linux/stringify.h>
8 #include <asm/asm-compat.h>
9 #include <asm/processor.h>
10 #include <asm/ppc-opcode.h>
13 #error __FILE__ should only be used in assembler files
16 #define SZL (BITS_PER_LONG/8)
19 * Stuff for accurate CPU time accounting.
20 * These macros handle transitions between user and system state
21 * in exception entry and exit and accumulate time to the
22 * user_time and system_time fields in the paca.
25 #ifndef CONFIG_VIRT_CPU_ACCOUNTING
26 #define ACCOUNT_CPU_USER_ENTRY(ra, rb)
27 #define ACCOUNT_CPU_USER_EXIT(ra, rb)
29 #define ACCOUNT_CPU_USER_ENTRY(ra, rb) \
30 beq 2f; /* if from kernel mode */ \
32 mfspr ra,SPRN_PURR; /* get processor util. reg */ \
33 END_FTR_SECTION_IFSET(CPU_FTR_PURR); \
35 MFTB(ra); /* or get TB if no PURR */ \
36 END_FTR_SECTION_IFCLR(CPU_FTR_PURR); \
37 ld rb,PACA_STARTPURR(r13); \
38 std ra,PACA_STARTPURR(r13); \
39 subf rb,rb,ra; /* subtract start value */ \
40 ld ra,PACA_USER_TIME(r13); \
41 add ra,ra,rb; /* add on to user time */ \
42 std ra,PACA_USER_TIME(r13); \
45 #define ACCOUNT_CPU_USER_EXIT(ra, rb) \
47 mfspr ra,SPRN_PURR; /* get processor util. reg */ \
48 END_FTR_SECTION_IFSET(CPU_FTR_PURR); \
50 MFTB(ra); /* or get TB if no PURR */ \
51 END_FTR_SECTION_IFCLR(CPU_FTR_PURR); \
52 ld rb,PACA_STARTPURR(r13); \
53 std ra,PACA_STARTPURR(r13); \
54 subf rb,rb,ra; /* subtract start value */ \
55 ld ra,PACA_SYSTEM_TIME(r13); \
56 add ra,ra,rb; /* add on to user time */ \
57 std ra,PACA_SYSTEM_TIME(r13);
61 * Macros for storing registers into and loading registers from
65 #define SAVE_GPR(n, base) std n,GPR0+8*(n)(base)
66 #define REST_GPR(n, base) ld n,GPR0+8*(n)(base)
67 #define SAVE_NVGPRS(base) SAVE_8GPRS(14, base); SAVE_10GPRS(22, base)
68 #define REST_NVGPRS(base) REST_8GPRS(14, base); REST_10GPRS(22, base)
70 #define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base)
71 #define REST_GPR(n, base) lwz n,GPR0+4*(n)(base)
72 #define SAVE_NVGPRS(base) SAVE_GPR(13, base); SAVE_8GPRS(14, base); \
74 #define REST_NVGPRS(base) REST_GPR(13, base); REST_8GPRS(14, base); \
79 * Define what the VSX XX1 form instructions will look like, then add
80 * the 128 bit load store instructions based on that.
82 #define VSX_XX1(xs, ra, rb) (((xs) & 0x1f) << 21 | ((ra) << 16) | \
83 ((rb) << 11) | (((xs) >> 5)))
85 #define STXVD2X(xs, ra, rb) .long (0x7c000798 | VSX_XX1((xs), (ra), (rb)))
86 #define LXVD2X(xs, ra, rb) .long (0x7c000698 | VSX_XX1((xs), (ra), (rb)))
88 #define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base)
89 #define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
90 #define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
91 #define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
92 #define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base)
93 #define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base)
94 #define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base)
95 #define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base)
97 #define SAVE_FPR(n, base) stfd n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base)
98 #define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base)
99 #define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base)
100 #define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base)
101 #define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base)
102 #define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base)
103 #define REST_FPR(n, base) lfd n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base)
104 #define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base)
105 #define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base)
106 #define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base)
107 #define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base)
108 #define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base)
110 #define SAVE_VR(n,b,base) li b,THREAD_VR0+(16*(n)); stvx n,b,base
111 #define SAVE_2VRS(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)
112 #define SAVE_4VRS(n,b,base) SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base)
113 #define SAVE_8VRS(n,b,base) SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base)
114 #define SAVE_16VRS(n,b,base) SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base)
115 #define SAVE_32VRS(n,b,base) SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base)
116 #define REST_VR(n,b,base) li b,THREAD_VR0+(16*(n)); lvx n,b,base
117 #define REST_2VRS(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base)
118 #define REST_4VRS(n,b,base) REST_2VRS(n,b,base); REST_2VRS(n+2,b,base)
119 #define REST_8VRS(n,b,base) REST_4VRS(n,b,base); REST_4VRS(n+4,b,base)
120 #define REST_16VRS(n,b,base) REST_8VRS(n,b,base); REST_8VRS(n+8,b,base)
121 #define REST_32VRS(n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base)
123 /* Save the lower 32 VSRs in the thread VSR region */
124 #define SAVE_VSR(n,b,base) li b,THREAD_VSR0+(16*(n)); STXVD2X(n,b,base)
125 #define SAVE_2VSRS(n,b,base) SAVE_VSR(n,b,base); SAVE_VSR(n+1,b,base)
126 #define SAVE_4VSRS(n,b,base) SAVE_2VSRS(n,b,base); SAVE_2VSRS(n+2,b,base)
127 #define SAVE_8VSRS(n,b,base) SAVE_4VSRS(n,b,base); SAVE_4VSRS(n+4,b,base)
128 #define SAVE_16VSRS(n,b,base) SAVE_8VSRS(n,b,base); SAVE_8VSRS(n+8,b,base)
129 #define SAVE_32VSRS(n,b,base) SAVE_16VSRS(n,b,base); SAVE_16VSRS(n+16,b,base)
130 #define REST_VSR(n,b,base) li b,THREAD_VSR0+(16*(n)); LXVD2X(n,b,base)
131 #define REST_2VSRS(n,b,base) REST_VSR(n,b,base); REST_VSR(n+1,b,base)
132 #define REST_4VSRS(n,b,base) REST_2VSRS(n,b,base); REST_2VSRS(n+2,b,base)
133 #define REST_8VSRS(n,b,base) REST_4VSRS(n,b,base); REST_4VSRS(n+4,b,base)
134 #define REST_16VSRS(n,b,base) REST_8VSRS(n,b,base); REST_8VSRS(n+8,b,base)
135 #define REST_32VSRS(n,b,base) REST_16VSRS(n,b,base); REST_16VSRS(n+16,b,base)
136 /* Save the upper 32 VSRs (32-63) in the thread VSX region (0-31) */
137 #define SAVE_VSRU(n,b,base) li b,THREAD_VR0+(16*(n)); STXVD2X(n+32,b,base)
138 #define SAVE_2VSRSU(n,b,base) SAVE_VSRU(n,b,base); SAVE_VSRU(n+1,b,base)
139 #define SAVE_4VSRSU(n,b,base) SAVE_2VSRSU(n,b,base); SAVE_2VSRSU(n+2,b,base)
140 #define SAVE_8VSRSU(n,b,base) SAVE_4VSRSU(n,b,base); SAVE_4VSRSU(n+4,b,base)
141 #define SAVE_16VSRSU(n,b,base) SAVE_8VSRSU(n,b,base); SAVE_8VSRSU(n+8,b,base)
142 #define SAVE_32VSRSU(n,b,base) SAVE_16VSRSU(n,b,base); SAVE_16VSRSU(n+16,b,base)
143 #define REST_VSRU(n,b,base) li b,THREAD_VR0+(16*(n)); LXVD2X(n+32,b,base)
144 #define REST_2VSRSU(n,b,base) REST_VSRU(n,b,base); REST_VSRU(n+1,b,base)
145 #define REST_4VSRSU(n,b,base) REST_2VSRSU(n,b,base); REST_2VSRSU(n+2,b,base)
146 #define REST_8VSRSU(n,b,base) REST_4VSRSU(n,b,base); REST_4VSRSU(n+4,b,base)
147 #define REST_16VSRSU(n,b,base) REST_8VSRSU(n,b,base); REST_8VSRSU(n+8,b,base)
148 #define REST_32VSRSU(n,b,base) REST_16VSRSU(n,b,base); REST_16VSRSU(n+16,b,base)
150 #define SAVE_EVR(n,s,base) evmergehi s,s,n; stw s,THREAD_EVR0+4*(n)(base)
151 #define SAVE_2EVRS(n,s,base) SAVE_EVR(n,s,base); SAVE_EVR(n+1,s,base)
152 #define SAVE_4EVRS(n,s,base) SAVE_2EVRS(n,s,base); SAVE_2EVRS(n+2,s,base)
153 #define SAVE_8EVRS(n,s,base) SAVE_4EVRS(n,s,base); SAVE_4EVRS(n+4,s,base)
154 #define SAVE_16EVRS(n,s,base) SAVE_8EVRS(n,s,base); SAVE_8EVRS(n+8,s,base)
155 #define SAVE_32EVRS(n,s,base) SAVE_16EVRS(n,s,base); SAVE_16EVRS(n+16,s,base)
156 #define REST_EVR(n,s,base) lwz s,THREAD_EVR0+4*(n)(base); evmergelo n,s,n
157 #define REST_2EVRS(n,s,base) REST_EVR(n,s,base); REST_EVR(n+1,s,base)
158 #define REST_4EVRS(n,s,base) REST_2EVRS(n,s,base); REST_2EVRS(n+2,s,base)
159 #define REST_8EVRS(n,s,base) REST_4EVRS(n,s,base); REST_4EVRS(n+4,s,base)
160 #define REST_16EVRS(n,s,base) REST_8EVRS(n,s,base); REST_8EVRS(n+8,s,base)
161 #define REST_32EVRS(n,s,base) REST_16EVRS(n,s,base); REST_16EVRS(n+16,s,base)
163 /* Macros to adjust thread priority for hardware multithreading */
164 #define HMT_VERY_LOW or 31,31,31 # very low priority
165 #define HMT_LOW or 1,1,1
166 #define HMT_MEDIUM_LOW or 6,6,6 # medium low priority
167 #define HMT_MEDIUM or 2,2,2
168 #define HMT_MEDIUM_HIGH or 5,5,5 # medium high priority
169 #define HMT_HIGH or 3,3,3
174 #define XGLUE(a,b) a##b
175 #define GLUE(a,b) XGLUE(a,b)
177 #define _GLOBAL(name) \
181 .globl GLUE(.,name); \
182 .section ".opd","aw"; \
184 .quad GLUE(.,name); \
185 .quad .TOC.@tocbase; \
188 .type GLUE(.,name),@function; \
191 #define _INIT_GLOBAL(name) \
192 .section ".text.init.refok"; \
195 .globl GLUE(.,name); \
196 .section ".opd","aw"; \
198 .quad GLUE(.,name); \
199 .quad .TOC.@tocbase; \
202 .type GLUE(.,name),@function; \
205 #define _KPROBE(name) \
206 .section ".kprobes.text","a"; \
209 .globl GLUE(.,name); \
210 .section ".opd","aw"; \
212 .quad GLUE(.,name); \
213 .quad .TOC.@tocbase; \
216 .type GLUE(.,name),@function; \
219 #define _STATIC(name) \
222 .section ".opd","aw"; \
224 .quad GLUE(.,name); \
225 .quad .TOC.@tocbase; \
228 .type GLUE(.,name),@function; \
231 #define _INIT_STATIC(name) \
232 .section ".text.init.refok"; \
234 .section ".opd","aw"; \
236 .quad GLUE(.,name); \
237 .quad .TOC.@tocbase; \
240 .type GLUE(.,name),@function; \
251 .stabs __stringify(n:F-1),N_FUN,0,0,n;\
256 .section ".kprobes.text","a"; \
263 * LOAD_REG_IMMEDIATE(rn, expr)
264 * Loads the value of the constant expression 'expr' into register 'rn'
265 * using immediate instructions only. Use this when it's important not
266 * to reference other data (i.e. on ppc64 when the TOC pointer is not
267 * valid) and when 'expr' is a constant or absolute address.
269 * LOAD_REG_ADDR(rn, name)
270 * Loads the address of label 'name' into register 'rn'. Use this when
271 * you don't particularly need immediate instructions only, but you need
272 * the whole address in one register (e.g. it's a structure address and
273 * you want to access various offsets within it). On ppc32 this is
274 * identical to LOAD_REG_IMMEDIATE.
276 * LOAD_REG_ADDRBASE(rn, name)
278 * LOAD_REG_ADDRBASE loads part of the address of label 'name' into
279 * register 'rn'. ADDROFF(name) returns the remainder of the address as
280 * a constant expression. ADDROFF(name) is a signed expression < 16 bits
281 * in size, so is suitable for use directly as an offset in load and store
282 * instructions. Use this when loading/storing a single word or less as:
283 * LOAD_REG_ADDRBASE(rX, name)
284 * ld rY,ADDROFF(name)(rX)
287 #define LOAD_REG_IMMEDIATE(reg,expr) \
288 lis (reg),(expr)@highest; \
289 ori (reg),(reg),(expr)@higher; \
290 rldicr (reg),(reg),32,31; \
291 oris (reg),(reg),(expr)@h; \
292 ori (reg),(reg),(expr)@l;
294 #define LOAD_REG_ADDR(reg,name) \
295 ld (reg),name@got(r2)
297 #define LOAD_REG_ADDRBASE(reg,name) LOAD_REG_ADDR(reg,name)
298 #define ADDROFF(name) 0
300 /* offsets for stack frame layout */
305 #define LOAD_REG_IMMEDIATE(reg,expr) \
306 lis (reg),(expr)@ha; \
307 addi (reg),(reg),(expr)@l;
309 #define LOAD_REG_ADDR(reg,name) LOAD_REG_IMMEDIATE(reg, name)
311 #define LOAD_REG_ADDRBASE(reg, name) lis (reg),name@ha
312 #define ADDROFF(name) name@l
314 /* offsets for stack frame layout */
319 /* various errata or part fixups */
320 #ifdef CONFIG_PPC601_SYNC_FIX
325 END_FTR_SECTION_IFSET(CPU_FTR_601)
329 END_FTR_SECTION_IFSET(CPU_FTR_601)
333 END_FTR_SECTION_IFSET(CPU_FTR_601)
340 #ifdef CONFIG_PPC_CELL
343 BEGIN_FTR_SECTION_NESTED(96); \
346 END_FTR_SECTION_NESTED(CPU_FTR_CELL_TB_BUG, CPU_FTR_CELL_TB_BUG, 96)
348 #define MFTB(dest) mftb dest
353 #else /* CONFIG_SMP */
354 /* tlbsync is not implemented on 601 */
359 END_FTR_SECTION_IFCLR(CPU_FTR_601)
364 * This instruction is not implemented on the PPC 603 or 601; however, on
365 * the 403GCX and 405GP tlbia IS defined and tlbie is not.
366 * All of these instructions exist in the 8xx, they have magical powers,
367 * and they must be used.
370 #if !defined(CONFIG_4xx) && !defined(CONFIG_8xx)
374 lis r4,KERNELBASE@h; \
381 #ifdef CONFIG_IBM440EP_ERR42
382 #define PPC440EP_ERR42 isync
384 #define PPC440EP_ERR42
388 #if defined(CONFIG_BOOKE)
393 * We use addis to ensure compatibility with the "classic" ppc versions of
394 * these macros, which use rs = 0 to get the tophys offset in rd, rather than
395 * converting the address in r0, and so this version has to do that too
396 * (i.e. set register rd to 0 when rs == 0).
398 #define tophys(rd,rs) \
401 #define tovirt(rd,rs) \
404 #elif defined(CONFIG_PPC64)
405 #define toreal(rd) /* we can access c000... in real mode */
408 #define tophys(rd,rs) \
411 #define tovirt(rd,rs) \
413 ori rd,rd,((KERNELBASE>>48)&0xFFFF);\
417 * On APUS (Amiga PowerPC cpu upgrade board), we don't know the
418 * physical base address of RAM at compile time.
420 #define toreal(rd) tophys(rd,rd)
421 #define fromreal(rd) tovirt(rd,rd)
423 #define tophys(rd,rs) \
424 0: addis rd,rs,-PAGE_OFFSET@h; \
425 .section ".vtop_fixup","aw"; \
430 #define tovirt(rd,rs) \
431 0: addis rd,rs,PAGE_OFFSET@h; \
432 .section ".ptov_fixup","aw"; \
440 #define MTMSRD(r) mtmsrd r
443 #define FIX_SRR1(ra, rb)
447 #define RFI rfi; b . /* Prevent prefetch past rfi */
449 #define MTMSRD(r) mtmsr r
453 #endif /* __KERNEL__ */
455 /* The boring bits... */
457 /* Condition Register Bit Fields */
469 /* General Purpose Registers (GPRs) */
505 /* Floating Point Registers (FPRs) */
540 /* AltiVec Registers (VPRs) */
575 /* VSX Registers (VSRs) */
642 /* SPE Registers (EVPRs) */
677 /* some stab codes */
683 #endif /* __ASSEMBLY__ */
685 #endif /* _ASM_POWERPC_PPC_ASM_H */