2 * INET An implementation of the TCP/IP protocol suite for the LINUX
3 * operating system. INET is implemented using the BSD Socket
4 * interface as the means of communication with the user level.
6 * IP/TCP/UDP checksumming routines
8 * Xtensa version: Copyright (C) 2001 Tensilica, Inc. by Kevin Chea
9 * Optimized by Joe Taylor
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
17 #include <asm/errno.h>
18 #include <linux/linkage.h>
19 #include <asm/variant/core.h>
22 * computes a partial checksum, e.g. for TCP/UDP fragments
26 * unsigned int csum_partial(const unsigned char *buf, int len,
32 * This function assumes 2- or 4-byte alignment. Other alignments will fail!
35 /* ONES_ADD converts twos-complement math to ones-complement. */
36 #define ONES_ADD(sum, val) \
38 bgeu sum, val, 99f ; \
45 * Experiments with Ethernet and SLIP connections show that buf
46 * is aligned on either a 2-byte or 4-byte boundary.
50 bnez a5, 8f /* branch if 2-byte aligned */
51 /* Fall-through on common case, 4-byte alignment */
53 srli a5, a3, 5 /* 32-byte chunks */
59 add a5, a5, a2 /* a5 = end of last 32-byte chunk */
83 extui a5, a3, 2, 3 /* remaining 4-byte chunks */
89 add a5, a5, a2 /* a5 = end of last 4-byte chunk */
99 _bbci.l a3, 1, 5f /* remaining 2-byte chunk */
104 _bbci.l a3, 0, 7f /* remaining 1-byte chunk */
107 slli a6, a6, 8 /* load byte into bits 8..15 */
114 /* uncommon case, buf is 2-byte aligned */
116 beqz a3, 7b /* branch if len == 0 */
117 beqi a3, 1, 6b /* branch if len == 1 */
120 bnez a5, 8f /* branch if 1-byte aligned */
122 l16ui a6, a2, 0 /* common case, len >= 2 */
124 addi a2, a2, 2 /* adjust buf */
125 addi a3, a3, -2 /* adjust len */
126 j 1b /* now buf is 4-byte aligned */
128 /* case: odd-byte aligned, len > 1
129 * This case is dog slow, so don't give us an odd address.
130 * (I don't think this ever happens, but just in case.)
133 srli a5, a3, 2 /* 4-byte chunks */
139 add a5, a5, a2 /* a5 = end of last 4-byte chunk */
142 l8ui a6, a2, 0 /* bits 24..31 */
143 l16ui a7, a2, 1 /* bits 8..23 */
144 l8ui a8, a2, 3 /* bits 0.. 8 */
155 #if !XCHAL_HAVE_LOOPS
159 _bbci.l a3, 1, 3f /* remaining 2-byte chunk, still odd addr */
171 j 5b /* branch to handle the remaining byte */
176 * Copy from ds while checksumming, otherwise like csum_partial
178 * The macros SRC and DST specify the type of access for the instruction.
179 * thus we can call a custom exception handler for each access type.
184 .section __ex_table, "a"; \
185 .long 9999b, 6001f ; \
190 .section __ex_table, "a"; \
191 .long 9999b, 6002f ; \
195 unsigned int csum_partial_copy_generic (const char *src, char *dst, int len,
196 int sum, int *src_err_ptr, int *dst_err_ptr)
206 a11 = original len for exception handling
207 a12 = original dst for exception handling
209 This function is optimized for 4-byte aligned addresses. Other
210 alignments work, but not nearly as efficiently.
213 ENTRY(csum_partial_copy_generic)
219 /* We optimize the following alignment tests for the 4-byte
220 aligned case. Two bbsi.l instructions might seem more optimal
221 (commented out below). However, both labels 5: and 3: are out
222 of the imm8 range, so the assembler relaxes them into
223 equivalent bbci.l, j combinations, which is actually
227 beqz a9, 1f /* branch if both are 4-byte aligned */
228 bbsi.l a10, 0, 5f /* branch if one address is odd */
229 j 3f /* one address is 2-byte aligned */
231 /* _bbsi.l a10, 0, 5f */ /* branch if odd address */
232 /* _bbsi.l a10, 1, 3f */ /* branch if 2-byte-aligned address */
235 /* src and dst are both 4-byte aligned */
236 srli a10, a4, 5 /* 32-byte chunks */
242 add a10, a10, a2 /* a10 = end of last 32-byte src chunk */
245 SRC( l32i a9, a2, 0 )
246 SRC( l32i a8, a2, 4 )
247 DST( s32i a9, a3, 0 )
248 DST( s32i a8, a3, 4 )
251 SRC( l32i a9, a2, 8 )
252 SRC( l32i a8, a2, 12 )
253 DST( s32i a9, a3, 8 )
254 DST( s32i a8, a3, 12 )
257 SRC( l32i a9, a2, 16 )
258 SRC( l32i a8, a2, 20 )
259 DST( s32i a9, a3, 16 )
260 DST( s32i a8, a3, 20 )
263 SRC( l32i a9, a2, 24 )
264 SRC( l32i a8, a2, 28 )
265 DST( s32i a9, a3, 24 )
266 DST( s32i a8, a3, 28 )
271 #if !XCHAL_HAVE_LOOPS
275 extui a10, a4, 2, 3 /* remaining 4-byte chunks */
276 extui a4, a4, 0, 2 /* reset len for general-case, 2-byte chunks */
282 add a10, a10, a2 /* a10 = end of last 4-byte src chunk */
285 SRC( l32i a9, a2, 0 )
286 DST( s32i a9, a3, 0 )
290 #if !XCHAL_HAVE_LOOPS
295 Control comes to here in two cases: (1) It may fall through
296 to here from the 4-byte alignment case to process, at most,
297 one 2-byte chunk. (2) It branches to here from above if
298 either src or dst is 2-byte aligned, and we process all bytes
299 here, except for perhaps a trailing odd byte. It's
300 inefficient, so align your addresses to 4-byte boundaries.
307 srli a10, a4, 1 /* 2-byte chunks */
313 add a10, a10, a2 /* a10 = end of last 2-byte src chunk */
316 SRC( l16ui a9, a2, 0 )
317 DST( s16i a9, a3, 0 )
321 #if !XCHAL_HAVE_LOOPS
325 /* This section processes a possible trailing odd byte. */
326 _bbci.l a4, 0, 8f /* 1-byte chunk */
327 SRC( l8ui a9, a2, 0 )
330 slli a9, a9, 8 /* shift byte to bits 8..15 */
338 /* Control branch to here when either src or dst is odd. We
339 process all bytes using 8-bit accesses. Grossly inefficient,
340 so don't feed us an odd address. */
342 srli a10, a4, 1 /* handle in pairs for 16-bit csum */
348 add a10, a10, a2 /* a10 = end of last odd-aligned, 2-byte src chunk */
351 SRC( l8ui a9, a2, 0 )
352 SRC( l8ui a8, a2, 1 )
356 slli a9, a9, 8 /* combine into a single 16-bit value */
357 #else /* for checksum computation */
364 #if !XCHAL_HAVE_LOOPS
368 j 4b /* process the possible trailing odd byte */
372 .section .fixup, "ax"
376 a11 = original len for exception handling
377 a12 = original dst for exception handling
382 s32i a2, a6, 0 /* src_err_ptr */
384 # clear the complete destination - computing the rest
391 add a11, a11, a12 /* a11 = ending address */
396 #if !XCHAL_HAVE_LOOPS
397 blt a12, a11, .Leloop
404 s32i a2, a7, 0 /* dst_err_ptr */