git.oblomov.eu Git - linux-2.6/blob - arch/powerpc/platforms/83xx/mpc836x_mds.c

   1 /*
   2  * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved.
   3  *
   4  * Author: Li Yang <LeoLi@freescale.com>
   5  *         Yin Olivia <Hong-hua.Yin@freescale.com>
   6  *
   7  * Description:
   8  * MPC8360E MDS board specific routines.
   9  *
  10  * Changelog:
  11  * Jun 21, 2006 Initial version
  12  *
  13  * This program is free software; you can redistribute it and/or modify it
  14  * under  the terms of  the GNU General  Public License as published by the
  15  * Free Software Foundation;  either version 2 of the  License, or (at your
  16  * option) any later version.
  17  */
  18
  19 #include <linux/stddef.h>
  20 #include <linux/kernel.h>
  21 #include <linux/init.h>
  22 #include <linux/errno.h>
  23 #include <linux/reboot.h>
  24 #include <linux/pci.h>
  25 #include <linux/kdev_t.h>
  26 #include <linux/major.h>
  27 #include <linux/console.h>
  28 #include <linux/delay.h>
  29 #include <linux/seq_file.h>
  30 #include <linux/root_dev.h>
  31 #include <linux/initrd.h>
  32 #include <linux/of_platform.h>
  33 #include <linux/of_device.h>
  34
  35 #include <asm/system.h>
  36 #include <asm/atomic.h>
  37 #include <asm/time.h>
  38 #include <asm/io.h>
  39 #include <asm/machdep.h>
  40 #include <asm/ipic.h>
  41 #include <asm/irq.h>
  42 #include <asm/prom.h>
  43 #include <asm/udbg.h>
  44 #include <sysdev/fsl_soc.h>
  45 #include <asm/qe.h>
  46 #include <asm/qe_ic.h>
  47
  48 #include "mpc83xx.h"
  49
  50 #undef DEBUG
  51 #ifdef DEBUG
  52 #define DBG(fmt...) udbg_printf(fmt)
  53 #else
  54 #define DBG(fmt...)
  55 #endif
  56
  57 static u8 *bcsr_regs = NULL;
  58
  59 /* ************************************************************************
  60  *
  61  * Setup the architecture
  62  *
  63  */
  64 static void __init mpc836x_mds_setup_arch(void)
  65 {
  66         struct device_node *np;
  67
  68         if (ppc_md.progress)
  69                 ppc_md.progress("mpc836x_mds_setup_arch()", 0);
  70
  71         /* Map BCSR area */
  72         np = of_find_node_by_name(NULL, "bcsr");
  73         if (np != 0) {
  74                 struct resource res;
  75
  76                 of_address_to_resource(np, 0, &res);
  77                 bcsr_regs = ioremap(res.start, res.end - res.start +1);
  78                 of_node_put(np);
  79         }
  80
  81 #ifdef CONFIG_PCI
  82         for_each_compatible_node(np, "pci", "fsl,mpc8349-pci")
  83                 mpc83xx_add_bridge(np);
  84 #endif
  85
  86 #ifdef CONFIG_QUICC_ENGINE
  87         qe_reset();
  88
  89         if ((np = of_find_node_by_name(NULL, "par_io")) != NULL) {
  90                 par_io_init(np);
  91                 of_node_put(np);
  92
  93                 for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;)
  94                         par_io_of_config(np);
  95         }
  96
  97         if ((np = of_find_compatible_node(NULL, "network", "ucc_geth"))
  98                         != NULL){
  99                 uint svid;
 100
 101                 /* Reset the Ethernet PHY */
 102 #define BCSR9_GETHRST 0x20
 103                 clrbits8(&bcsr_regs[9], BCSR9_GETHRST);
 104                 udelay(1000);
 105                 setbits8(&bcsr_regs[9], BCSR9_GETHRST);
 106
 107                 /* handle mpc8360ea rev.2.1 erratum 2: RGMII Timing */
 108                 svid = mfspr(SPRN_SVR);
 109                 if (svid == 0x80480021) {
 110                         void __iomem *immap;
 111
 112                         immap = ioremap(get_immrbase() + 0x14a8, 8);
 113
 114                         /*
 115                          * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)
 116                          * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)
 117                          */
 118                         setbits32(immap, 0x0c003000);
 119
 120                         /*
 121                          * IMMR + 0x14AC[20:27] = 10101010
 122                          * (data delay for both UCC's)
 123                          */
 124                         clrsetbits_be32(immap + 4, 0xff0, 0xaa0);
 125
 126                         iounmap(immap);
 127                 }
 128
 129                 iounmap(bcsr_regs);
 130                 of_node_put(np);
 131         }
 132 #endif                          /* CONFIG_QUICC_ENGINE */
 133 }
 134
 135 static struct of_device_id mpc836x_ids[] = {
 136         { .type = "soc", },
 137         { .compatible = "soc", },
 138         { .type = "qe", },
 139         { .compatible = "fsl,qe", },
 140         {},
 141 };
 142
 143 static int __init mpc836x_declare_of_platform_devices(void)
 144 {
 145         /* Publish the QE devices */
 146         of_platform_bus_probe(NULL, mpc836x_ids, NULL);
 147
 148         return 0;
 149 }
 150 machine_device_initcall(mpc836x_mds, mpc836x_declare_of_platform_devices);
 151
 152 static void __init mpc836x_mds_init_IRQ(void)
 153 {
 154         struct device_node *np;
 155
 156         np = of_find_node_by_type(NULL, "ipic");
 157         if (!np)
 158                 return;
 159
 160         ipic_init(np, 0);
 161
 162         /* Initialize the default interrupt mapping priorities,
 163          * in case the boot rom changed something on us.
 164          */
 165         ipic_set_default_priority();
 166         of_node_put(np);
 167
 168 #ifdef CONFIG_QUICC_ENGINE
 169         np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
 170         if (!np) {
 171                 np = of_find_node_by_type(NULL, "qeic");
 172                 if (!np)
 173                         return;
 174         }
 175         qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic);
 176         of_node_put(np);
 177 #endif                          /* CONFIG_QUICC_ENGINE */
 178 }
 179
 180 /*
 181  * Called very early, MMU is off, device-tree isn't unflattened
 182  */
 183 static int __init mpc836x_mds_probe(void)
 184 {
 185         unsigned long root = of_get_flat_dt_root();
 186
 187         return of_flat_dt_is_compatible(root, "MPC836xMDS");
 188 }
 189
 190 define_machine(mpc836x_mds) {
 191         .name           = "MPC836x MDS",
 192         .probe          = mpc836x_mds_probe,
 193         .setup_arch     = mpc836x_mds_setup_arch,
 194         .init_IRQ       = mpc836x_mds_init_IRQ,
 195         .get_irq        = ipic_get_irq,
 196         .restart        = mpc83xx_restart,
 197         .time_init      = mpc83xx_time_init,
 198         .calibrate_decr = generic_calibrate_decr,
 199         .progress       = udbg_progress,
 200 };