2 * Copyright (C) 2008 Christian Lamparter <chunkeey@web.de>
4 * This driver is a port from stlc45xx:
5 * Copyright (C) 2008 Nokia Corporation and/or its subsidiary(-ies).
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 2 as published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
25 #include <linux/mutex.h>
26 #include <linux/list.h>
27 #include <net/mac80211.h>
28 #include <mach/board.h>
32 /* Bit 15 is read/write bit; ON = READ, OFF = WRITE */
33 #define SPI_ADRS_READ_BIT_15 0x8000
35 #define SPI_ADRS_ARM_INTERRUPTS 0x00
36 #define SPI_ADRS_ARM_INT_EN 0x04
38 #define SPI_ADRS_HOST_INTERRUPTS 0x08
39 #define SPI_ADRS_HOST_INT_EN 0x0c
40 #define SPI_ADRS_HOST_INT_ACK 0x10
42 #define SPI_ADRS_GEN_PURP_1 0x14
43 #define SPI_ADRS_GEN_PURP_2 0x18
45 #define SPI_ADRS_DEV_CTRL_STAT 0x26 /* high word */
47 #define SPI_ADRS_DMA_DATA 0x28
49 #define SPI_ADRS_DMA_WRITE_CTRL 0x2c
50 #define SPI_ADRS_DMA_WRITE_LEN 0x2e
51 #define SPI_ADRS_DMA_WRITE_BASE 0x30
53 #define SPI_ADRS_DMA_READ_CTRL 0x34
54 #define SPI_ADRS_DMA_READ_LEN 0x36
55 #define SPI_ADRS_DMA_READ_BASE 0x38
57 #define SPI_CTRL_STAT_HOST_OVERRIDE 0x8000
58 #define SPI_CTRL_STAT_START_HALTED 0x4000
59 #define SPI_CTRL_STAT_RAM_BOOT 0x2000
60 #define SPI_CTRL_STAT_HOST_RESET 0x1000
61 #define SPI_CTRL_STAT_HOST_CPU_EN 0x0800
63 #define SPI_DMA_WRITE_CTRL_ENABLE 0x0001
64 #define SPI_DMA_READ_CTRL_ENABLE 0x0001
65 #define HOST_ALLOWED (1 << 7)
67 #define SPI_TIMEOUT 100 /* msec */
69 #define SPI_MAX_TX_PACKETS 32
71 #define SPI_MAX_PACKET_SIZE 32767
73 #define SPI_TARGET_INT_WAKEUP 0x00000001
74 #define SPI_TARGET_INT_SLEEP 0x00000002
75 #define SPI_TARGET_INT_RDDONE 0x00000004
77 #define SPI_TARGET_INT_CTS 0x00004000
78 #define SPI_TARGET_INT_DR 0x00008000
80 #define SPI_HOST_INT_READY 0x00000001
81 #define SPI_HOST_INT_WR_READY 0x00000002
82 #define SPI_HOST_INT_SW_UPDATE 0x00000004
83 #define SPI_HOST_INT_UPDATE 0x10000000
86 #define SPI_HOST_INT_CR 0x00004000
89 #define SPI_HOST_INT_DR 0x00008000
91 #define SPI_HOST_INTS_DEFAULT \
92 (SPI_HOST_INT_READY | SPI_HOST_INT_UPDATE | SPI_HOST_INT_SW_UPDATE)
94 #define TARGET_BOOT_SLEEP 50
96 struct p54s_dma_regs {
100 } __attribute__ ((packed));
102 struct p54s_tx_info {
103 struct list_head tx_list;
107 /* p54_common has to be the first entry */
108 struct p54_common common;
109 struct ieee80211_hw *hw;
110 struct spi_device *spi;
111 const struct omap_wlan_cx3110x_config *config;
113 struct work_struct work;
116 struct completion fw_comp;
120 /* protected by tx_lock */
121 struct list_head tx_pending;
123 enum fw_state fw_state;
124 const struct firmware *firmware;
127 #endif /* P54SPI_H */