Merge branch 'x86/fpu' into x86/cleanups
[linux-2.6] / arch / arm / mm / abort-macro.S
1 /*
2  * The ARM LDRD and Thumb LDRSB instructions use bit 20/11 (ARM/Thumb)
3  * differently than every other instruction, so it is set to 0 (write)
4  * even though the instructions are read instructions. This means that
5  * during an abort the instructions will be treated as a write and the
6  * handler will raise a signal from unwriteable locations if they
7  * fault. We have to specifically check for these instructions
8  * from the abort handlers to treat them properly.
9  *
10  */
11
12         .macro  do_thumb_abort
13         tst     r3, #PSR_T_BIT
14         beq     not_thumb
15         ldrh    r3, [r2]                        @ Read aborted Thumb instruction
16         and     r3, r3, # 0xfe00                @ Mask opcode field
17         cmp     r3, # 0x5600                    @ Is it ldrsb?
18         orreq   r3, r3, #1 << 11                @ Set L-bit if yes
19         tst     r3, #1 << 11                    @ L = 0 -> write
20         orreq   r1, r1, #1 << 11                @ yes.
21         mov     pc, lr
22 not_thumb:
23         .endm
24
25 /*
26  * We check for the following insturction encoding for LDRD.
27  *
28  * [27:25] == 0
29  *   [7:4] == 1101
30  *    [20] == 0
31  */
32         .macro  do_ldrd_abort
33         tst     r3, #0x0e000000                 @ [27:25] == 0
34         bne     not_ldrd
35         and     r2, r3, #0x000000f0             @ [7:4] == 1101
36         cmp     r2, #0x000000d0
37         bne     not_ldrd
38         tst     r3, #1 << 20                    @ [20] == 0
39         moveq   pc, lr
40 not_ldrd:
41         .endm
42