2 * sata_mv.c - Marvell SATA support
4 * Copyright 2005: EMC Corporation, all rights reserved.
5 * Copyright 2005 Red Hat, Inc. All rights reserved.
7 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/pci.h>
27 #include <linux/init.h>
28 #include <linux/blkdev.h>
29 #include <linux/delay.h>
30 #include <linux/interrupt.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/device.h>
33 #include <scsi/scsi_host.h>
34 #include <scsi/scsi_cmnd.h>
35 #include <linux/libata.h>
37 #define DRV_NAME "sata_mv"
38 #define DRV_VERSION "0.8"
41 /* BAR's are enumerated in terms of pci_resource_start() terms */
42 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
43 MV_IO_BAR = 2, /* offset 0x18: IO space */
44 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
46 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
47 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
50 MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */
51 MV_IRQ_COAL_CAUSE = (MV_IRQ_COAL_REG_BASE + 0x08),
52 MV_IRQ_COAL_CAUSE_LO = (MV_IRQ_COAL_REG_BASE + 0x88),
53 MV_IRQ_COAL_CAUSE_HI = (MV_IRQ_COAL_REG_BASE + 0x8c),
54 MV_IRQ_COAL_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xcc),
55 MV_IRQ_COAL_TIME_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xd0),
57 MV_SATAHC0_REG_BASE = 0x20000,
58 MV_FLASH_CTL = 0x1046c,
59 MV_GPIO_PORT_CTL = 0x104f0,
60 MV_RESET_CFG = 0x180d8,
62 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
63 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
64 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
65 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
67 MV_USE_Q_DEPTH = ATA_DEF_QUEUE,
70 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
72 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
73 * CRPB needs alignment on a 256B boundary. Size == 256B
74 * SG count of 176 leads to MV_PORT_PRIV_DMA_SZ == 4KB
75 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
77 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
78 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
80 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
81 MV_PORT_PRIV_DMA_SZ = (MV_CRQB_Q_SZ + MV_CRPB_Q_SZ + MV_SG_TBL_SZ),
84 /* == (port / MV_PORTS_PER_HC) to determine HC from 0-7 port */
86 /* == (port % MV_PORTS_PER_HC) to determine hard port from 0-7 port */
90 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
91 MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */
92 MV_COMMON_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
93 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO |
94 ATA_FLAG_NO_ATAPI | ATA_FLAG_PIO_POLLING),
95 MV_6XXX_FLAGS = MV_FLAG_IRQ_COALESCE,
97 CRQB_FLAG_READ = (1 << 0),
99 CRQB_CMD_ADDR_SHIFT = 8,
100 CRQB_CMD_CS = (0x2 << 11),
101 CRQB_CMD_LAST = (1 << 15),
103 CRPB_FLAG_STATUS_SHIFT = 8,
105 EPRD_FLAG_END_OF_TBL = (1 << 31),
107 /* PCI interface registers */
109 PCI_COMMAND_OFS = 0xc00,
111 PCI_MAIN_CMD_STS_OFS = 0xd30,
112 STOP_PCI_MASTER = (1 << 2),
113 PCI_MASTER_EMPTY = (1 << 3),
114 GLOB_SFT_RST = (1 << 4),
117 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
118 MV_PCI_DISC_TIMER = 0xd04,
119 MV_PCI_MSI_TRIGGER = 0xc38,
120 MV_PCI_SERR_MASK = 0xc28,
121 MV_PCI_XBAR_TMOUT = 0x1d04,
122 MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
123 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
124 MV_PCI_ERR_ATTRIBUTE = 0x1d48,
125 MV_PCI_ERR_COMMAND = 0x1d50,
127 PCI_IRQ_CAUSE_OFS = 0x1d58,
128 PCI_IRQ_MASK_OFS = 0x1d5c,
129 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
131 HC_MAIN_IRQ_CAUSE_OFS = 0x1d60,
132 HC_MAIN_IRQ_MASK_OFS = 0x1d64,
133 PORT0_ERR = (1 << 0), /* shift by port # */
134 PORT0_DONE = (1 << 1), /* shift by port # */
135 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
136 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
138 TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */
139 TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */
140 PORTS_0_3_COAL_DONE = (1 << 8),
141 PORTS_4_7_COAL_DONE = (1 << 17),
142 PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */
143 GPIO_INT = (1 << 22),
144 SELF_INT = (1 << 23),
145 TWSI_INT = (1 << 24),
146 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
147 HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */
148 HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE |
149 PORTS_0_7_COAL_DONE | GPIO_INT | TWSI_INT |
151 HC_MAIN_MASKED_IRQS_5 = (PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE |
154 /* SATAHC registers */
157 HC_IRQ_CAUSE_OFS = 0x14,
158 CRPB_DMA_DONE = (1 << 0), /* shift by port # */
159 HC_IRQ_COAL = (1 << 4), /* IRQ coalescing */
160 DEV_IRQ = (1 << 8), /* shift by port # */
162 /* Shadow block registers */
164 SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */
167 SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */
168 SATA_ACTIVE_OFS = 0x350,
175 SATA_INTERFACE_CTL = 0x050,
177 MV_M2_PREAMP_MASK = 0x7e0,
181 EDMA_CFG_Q_DEPTH = 0, /* queueing disabled */
182 EDMA_CFG_NCQ = (1 << 5),
183 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
184 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
185 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
187 EDMA_ERR_IRQ_CAUSE_OFS = 0x8,
188 EDMA_ERR_IRQ_MASK_OFS = 0xc,
189 EDMA_ERR_D_PAR = (1 << 0),
190 EDMA_ERR_PRD_PAR = (1 << 1),
191 EDMA_ERR_DEV = (1 << 2),
192 EDMA_ERR_DEV_DCON = (1 << 3),
193 EDMA_ERR_DEV_CON = (1 << 4),
194 EDMA_ERR_SERR = (1 << 5),
195 EDMA_ERR_SELF_DIS = (1 << 7),
196 EDMA_ERR_BIST_ASYNC = (1 << 8),
197 EDMA_ERR_CRBQ_PAR = (1 << 9),
198 EDMA_ERR_CRPB_PAR = (1 << 10),
199 EDMA_ERR_INTRL_PAR = (1 << 11),
200 EDMA_ERR_IORDY = (1 << 12),
201 EDMA_ERR_LNK_CTRL_RX = (0xf << 13),
202 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15),
203 EDMA_ERR_LNK_DATA_RX = (0xf << 17),
204 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21),
205 EDMA_ERR_LNK_DATA_TX = (0x1f << 26),
206 EDMA_ERR_TRANS_PROTO = (1 << 31),
207 EDMA_ERR_FATAL = (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
208 EDMA_ERR_DEV_DCON | EDMA_ERR_CRBQ_PAR |
209 EDMA_ERR_CRPB_PAR | EDMA_ERR_INTRL_PAR |
210 EDMA_ERR_IORDY | EDMA_ERR_LNK_CTRL_RX_2 |
211 EDMA_ERR_LNK_DATA_RX |
212 EDMA_ERR_LNK_DATA_TX |
213 EDMA_ERR_TRANS_PROTO),
215 EDMA_REQ_Q_BASE_HI_OFS = 0x10,
216 EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */
218 EDMA_REQ_Q_OUT_PTR_OFS = 0x18,
219 EDMA_REQ_Q_PTR_SHIFT = 5,
221 EDMA_RSP_Q_BASE_HI_OFS = 0x1c,
222 EDMA_RSP_Q_IN_PTR_OFS = 0x20,
223 EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */
224 EDMA_RSP_Q_PTR_SHIFT = 3,
231 EDMA_IORDY_TMOUT = 0x34,
234 /* Host private flags (hp_flags) */
235 MV_HP_FLAG_MSI = (1 << 0),
236 MV_HP_ERRATA_50XXB0 = (1 << 1),
237 MV_HP_ERRATA_50XXB2 = (1 << 2),
238 MV_HP_ERRATA_60X1B2 = (1 << 3),
239 MV_HP_ERRATA_60X1C0 = (1 << 4),
240 MV_HP_ERRATA_XX42A0 = (1 << 5),
241 MV_HP_50XX = (1 << 6),
242 MV_HP_GEN_IIE = (1 << 7),
244 /* Port private flags (pp_flags) */
245 MV_PP_FLAG_EDMA_EN = (1 << 0),
246 MV_PP_FLAG_EDMA_DS_ACT = (1 << 1),
249 #define IS_50XX(hpriv) ((hpriv)->hp_flags & MV_HP_50XX)
250 #define IS_60XX(hpriv) (((hpriv)->hp_flags & MV_HP_50XX) == 0)
251 #define IS_GEN_I(hpriv) IS_50XX(hpriv)
252 #define IS_GEN_II(hpriv) IS_60XX(hpriv)
253 #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
256 MV_DMA_BOUNDARY = 0xffffffffU,
258 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
260 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
273 /* Command ReQuest Block: 32B */
289 /* Command ResPonse Block: 8B */
296 /* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
304 struct mv_port_priv {
305 struct mv_crqb *crqb;
307 struct mv_crpb *crpb;
309 struct mv_sg *sg_tbl;
310 dma_addr_t sg_tbl_dma;
314 struct mv_port_signal {
321 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
323 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
324 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
326 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
328 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
329 void (*reset_bus)(struct pci_dev *pdev, void __iomem *mmio);
332 struct mv_host_priv {
334 struct mv_port_signal signal[8];
335 const struct mv_hw_ops *ops;
338 static void mv_irq_clear(struct ata_port *ap);
339 static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in);
340 static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
341 static u32 mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in);
342 static void mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
343 static void mv_phy_reset(struct ata_port *ap);
344 static void __mv_phy_reset(struct ata_port *ap, int can_sleep);
345 static int mv_port_start(struct ata_port *ap);
346 static void mv_port_stop(struct ata_port *ap);
347 static void mv_qc_prep(struct ata_queued_cmd *qc);
348 static void mv_qc_prep_iie(struct ata_queued_cmd *qc);
349 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
350 static irqreturn_t mv_interrupt(int irq, void *dev_instance);
351 static void mv_eng_timeout(struct ata_port *ap);
352 static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
354 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
356 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
357 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
359 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
361 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
362 static void mv5_reset_bus(struct pci_dev *pdev, void __iomem *mmio);
364 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
366 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
367 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
369 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
371 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
372 static void mv_reset_pci_bus(struct pci_dev *pdev, void __iomem *mmio);
373 static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio,
374 unsigned int port_no);
375 static void mv_stop_and_reset(struct ata_port *ap);
377 static struct scsi_host_template mv_sht = {
378 .module = THIS_MODULE,
380 .ioctl = ata_scsi_ioctl,
381 .queuecommand = ata_scsi_queuecmd,
382 .can_queue = MV_USE_Q_DEPTH,
383 .this_id = ATA_SHT_THIS_ID,
384 .sg_tablesize = MV_MAX_SG_CT,
385 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
386 .emulated = ATA_SHT_EMULATED,
388 .proc_name = DRV_NAME,
389 .dma_boundary = MV_DMA_BOUNDARY,
390 .slave_configure = ata_scsi_slave_config,
391 .slave_destroy = ata_scsi_slave_destroy,
392 .bios_param = ata_std_bios_param,
395 static const struct ata_port_operations mv5_ops = {
396 .port_disable = ata_port_disable,
398 .tf_load = ata_tf_load,
399 .tf_read = ata_tf_read,
400 .check_status = ata_check_status,
401 .exec_command = ata_exec_command,
402 .dev_select = ata_std_dev_select,
404 .phy_reset = mv_phy_reset,
405 .cable_detect = ata_cable_sata,
407 .qc_prep = mv_qc_prep,
408 .qc_issue = mv_qc_issue,
409 .data_xfer = ata_data_xfer,
411 .eng_timeout = mv_eng_timeout,
413 .irq_handler = mv_interrupt,
414 .irq_clear = mv_irq_clear,
415 .irq_on = ata_irq_on,
416 .irq_ack = ata_irq_ack,
418 .scr_read = mv5_scr_read,
419 .scr_write = mv5_scr_write,
421 .port_start = mv_port_start,
422 .port_stop = mv_port_stop,
425 static const struct ata_port_operations mv6_ops = {
426 .port_disable = ata_port_disable,
428 .tf_load = ata_tf_load,
429 .tf_read = ata_tf_read,
430 .check_status = ata_check_status,
431 .exec_command = ata_exec_command,
432 .dev_select = ata_std_dev_select,
434 .phy_reset = mv_phy_reset,
435 .cable_detect = ata_cable_sata,
437 .qc_prep = mv_qc_prep,
438 .qc_issue = mv_qc_issue,
439 .data_xfer = ata_data_xfer,
441 .eng_timeout = mv_eng_timeout,
443 .irq_handler = mv_interrupt,
444 .irq_clear = mv_irq_clear,
445 .irq_on = ata_irq_on,
446 .irq_ack = ata_irq_ack,
448 .scr_read = mv_scr_read,
449 .scr_write = mv_scr_write,
451 .port_start = mv_port_start,
452 .port_stop = mv_port_stop,
455 static const struct ata_port_operations mv_iie_ops = {
456 .port_disable = ata_port_disable,
458 .tf_load = ata_tf_load,
459 .tf_read = ata_tf_read,
460 .check_status = ata_check_status,
461 .exec_command = ata_exec_command,
462 .dev_select = ata_std_dev_select,
464 .phy_reset = mv_phy_reset,
465 .cable_detect = ata_cable_sata,
467 .qc_prep = mv_qc_prep_iie,
468 .qc_issue = mv_qc_issue,
469 .data_xfer = ata_data_xfer,
471 .eng_timeout = mv_eng_timeout,
473 .irq_handler = mv_interrupt,
474 .irq_clear = mv_irq_clear,
475 .irq_on = ata_irq_on,
476 .irq_ack = ata_irq_ack,
478 .scr_read = mv_scr_read,
479 .scr_write = mv_scr_write,
481 .port_start = mv_port_start,
482 .port_stop = mv_port_stop,
485 static const struct ata_port_info mv_port_info[] = {
488 .flags = MV_COMMON_FLAGS,
489 .pio_mask = 0x1f, /* pio0-4 */
490 .udma_mask = 0x7f, /* udma0-6 */
491 .port_ops = &mv5_ops,
495 .flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC),
496 .pio_mask = 0x1f, /* pio0-4 */
497 .udma_mask = 0x7f, /* udma0-6 */
498 .port_ops = &mv5_ops,
502 .flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC),
503 .pio_mask = 0x1f, /* pio0-4 */
504 .udma_mask = 0x7f, /* udma0-6 */
505 .port_ops = &mv5_ops,
509 .flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS),
510 .pio_mask = 0x1f, /* pio0-4 */
511 .udma_mask = 0x7f, /* udma0-6 */
512 .port_ops = &mv6_ops,
516 .flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS |
518 .pio_mask = 0x1f, /* pio0-4 */
519 .udma_mask = 0x7f, /* udma0-6 */
520 .port_ops = &mv6_ops,
524 .flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS),
525 .pio_mask = 0x1f, /* pio0-4 */
526 .udma_mask = 0x7f, /* udma0-6 */
527 .port_ops = &mv_iie_ops,
531 .flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS),
532 .pio_mask = 0x1f, /* pio0-4 */
533 .udma_mask = 0x7f, /* udma0-6 */
534 .port_ops = &mv_iie_ops,
538 static const struct pci_device_id mv_pci_tbl[] = {
539 { PCI_VDEVICE(MARVELL, 0x5040), chip_504x },
540 { PCI_VDEVICE(MARVELL, 0x5041), chip_504x },
541 { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 },
542 { PCI_VDEVICE(MARVELL, 0x5081), chip_508x },
544 { PCI_VDEVICE(MARVELL, 0x6040), chip_604x },
545 { PCI_VDEVICE(MARVELL, 0x6041), chip_604x },
546 { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 },
547 { PCI_VDEVICE(MARVELL, 0x6080), chip_608x },
548 { PCI_VDEVICE(MARVELL, 0x6081), chip_608x },
550 { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x },
552 { PCI_VDEVICE(TTI, 0x2310), chip_7042 },
554 /* add Marvell 7042 support */
555 { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 },
557 { } /* terminate list */
560 static struct pci_driver mv_pci_driver = {
562 .id_table = mv_pci_tbl,
563 .probe = mv_init_one,
564 .remove = ata_pci_remove_one,
567 static const struct mv_hw_ops mv5xxx_ops = {
568 .phy_errata = mv5_phy_errata,
569 .enable_leds = mv5_enable_leds,
570 .read_preamp = mv5_read_preamp,
571 .reset_hc = mv5_reset_hc,
572 .reset_flash = mv5_reset_flash,
573 .reset_bus = mv5_reset_bus,
576 static const struct mv_hw_ops mv6xxx_ops = {
577 .phy_errata = mv6_phy_errata,
578 .enable_leds = mv6_enable_leds,
579 .read_preamp = mv6_read_preamp,
580 .reset_hc = mv6_reset_hc,
581 .reset_flash = mv6_reset_flash,
582 .reset_bus = mv_reset_pci_bus,
588 static int msi; /* Use PCI msi; either zero (off, default) or non-zero */
591 /* move to PCI layer or libata core? */
592 static int pci_go_64(struct pci_dev *pdev)
596 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
597 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
599 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
601 dev_printk(KERN_ERR, &pdev->dev,
602 "64-bit DMA enable failed\n");
607 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
609 dev_printk(KERN_ERR, &pdev->dev,
610 "32-bit DMA enable failed\n");
613 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
615 dev_printk(KERN_ERR, &pdev->dev,
616 "32-bit consistent DMA enable failed\n");
628 static inline void writelfl(unsigned long data, void __iomem *addr)
631 (void) readl(addr); /* flush to avoid PCI posted write */
634 static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
636 return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
639 static inline unsigned int mv_hc_from_port(unsigned int port)
641 return port >> MV_PORT_HC_SHIFT;
644 static inline unsigned int mv_hardport_from_port(unsigned int port)
646 return port & MV_PORT_MASK;
649 static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
652 return mv_hc_base(base, mv_hc_from_port(port));
655 static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
657 return mv_hc_base_from_port(base, port) +
658 MV_SATAHC_ARBTR_REG_SZ +
659 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
662 static inline void __iomem *mv_ap_base(struct ata_port *ap)
664 return mv_port_base(ap->host->iomap[MV_PRIMARY_BAR], ap->port_no);
667 static inline int mv_get_hc_count(unsigned long port_flags)
669 return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
672 static void mv_irq_clear(struct ata_port *ap)
677 * mv_start_dma - Enable eDMA engine
678 * @base: port base address
679 * @pp: port private data
681 * Verify the local cache of the eDMA state is accurate with a
685 * Inherited from caller.
687 static void mv_start_dma(void __iomem *base, struct mv_port_priv *pp)
689 if (!(MV_PP_FLAG_EDMA_EN & pp->pp_flags)) {
690 writelfl(EDMA_EN, base + EDMA_CMD_OFS);
691 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
693 WARN_ON(!(EDMA_EN & readl(base + EDMA_CMD_OFS)));
697 * mv_stop_dma - Disable eDMA engine
698 * @ap: ATA channel to manipulate
700 * Verify the local cache of the eDMA state is accurate with a
704 * Inherited from caller.
706 static void mv_stop_dma(struct ata_port *ap)
708 void __iomem *port_mmio = mv_ap_base(ap);
709 struct mv_port_priv *pp = ap->private_data;
713 if (MV_PP_FLAG_EDMA_EN & pp->pp_flags) {
714 /* Disable EDMA if active. The disable bit auto clears.
716 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
717 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
719 WARN_ON(EDMA_EN & readl(port_mmio + EDMA_CMD_OFS));
722 /* now properly wait for the eDMA to stop */
723 for (i = 1000; i > 0; i--) {
724 reg = readl(port_mmio + EDMA_CMD_OFS);
725 if (!(EDMA_EN & reg)) {
732 ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n");
733 /* FIXME: Consider doing a reset here to recover */
738 static void mv_dump_mem(void __iomem *start, unsigned bytes)
741 for (b = 0; b < bytes; ) {
742 DPRINTK("%p: ", start + b);
743 for (w = 0; b < bytes && w < 4; w++) {
744 printk("%08x ",readl(start + b));
752 static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
757 for (b = 0; b < bytes; ) {
758 DPRINTK("%02x: ", b);
759 for (w = 0; b < bytes && w < 4; w++) {
760 (void) pci_read_config_dword(pdev,b,&dw);
768 static void mv_dump_all_regs(void __iomem *mmio_base, int port,
769 struct pci_dev *pdev)
772 void __iomem *hc_base = mv_hc_base(mmio_base,
773 port >> MV_PORT_HC_SHIFT);
774 void __iomem *port_base;
775 int start_port, num_ports, p, start_hc, num_hcs, hc;
778 start_hc = start_port = 0;
779 num_ports = 8; /* shld be benign for 4 port devs */
782 start_hc = port >> MV_PORT_HC_SHIFT;
784 num_ports = num_hcs = 1;
786 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
787 num_ports > 1 ? num_ports - 1 : start_port);
790 DPRINTK("PCI config space regs:\n");
791 mv_dump_pci_cfg(pdev, 0x68);
793 DPRINTK("PCI regs:\n");
794 mv_dump_mem(mmio_base+0xc00, 0x3c);
795 mv_dump_mem(mmio_base+0xd00, 0x34);
796 mv_dump_mem(mmio_base+0xf00, 0x4);
797 mv_dump_mem(mmio_base+0x1d00, 0x6c);
798 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
799 hc_base = mv_hc_base(mmio_base, hc);
800 DPRINTK("HC regs (HC %i):\n", hc);
801 mv_dump_mem(hc_base, 0x1c);
803 for (p = start_port; p < start_port + num_ports; p++) {
804 port_base = mv_port_base(mmio_base, p);
805 DPRINTK("EDMA regs (port %i):\n",p);
806 mv_dump_mem(port_base, 0x54);
807 DPRINTK("SATA regs (port %i):\n",p);
808 mv_dump_mem(port_base+0x300, 0x60);
813 static unsigned int mv_scr_offset(unsigned int sc_reg_in)
821 ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32));
824 ofs = SATA_ACTIVE_OFS; /* active is not with the others */
833 static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in)
835 unsigned int ofs = mv_scr_offset(sc_reg_in);
837 if (0xffffffffU != ofs)
838 return readl(mv_ap_base(ap) + ofs);
843 static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
845 unsigned int ofs = mv_scr_offset(sc_reg_in);
847 if (0xffffffffU != ofs)
848 writelfl(val, mv_ap_base(ap) + ofs);
851 static void mv_edma_cfg(struct mv_host_priv *hpriv, void __iomem *port_mmio)
853 u32 cfg = readl(port_mmio + EDMA_CFG_OFS);
855 /* set up non-NCQ EDMA configuration */
856 cfg &= ~(1 << 9); /* disable equeue */
858 if (IS_GEN_I(hpriv)) {
859 cfg &= ~0x1f; /* clear queue depth */
860 cfg |= (1 << 8); /* enab config burst size mask */
863 else if (IS_GEN_II(hpriv)) {
864 cfg &= ~0x1f; /* clear queue depth */
865 cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN;
866 cfg &= ~(EDMA_CFG_NCQ | EDMA_CFG_NCQ_GO_ON_ERR); /* clear NCQ */
869 else if (IS_GEN_IIE(hpriv)) {
870 cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */
871 cfg |= (1 << 22); /* enab 4-entry host queue cache */
872 cfg &= ~(1 << 19); /* dis 128-entry queue (for now?) */
873 cfg |= (1 << 18); /* enab early completion */
874 cfg |= (1 << 17); /* enab cut-through (dis stor&forwrd) */
875 cfg &= ~(1 << 16); /* dis FIS-based switching (for now) */
876 cfg &= ~(EDMA_CFG_NCQ | EDMA_CFG_NCQ_GO_ON_ERR); /* clear NCQ */
879 writelfl(cfg, port_mmio + EDMA_CFG_OFS);
883 * mv_port_start - Port specific init/start routine.
884 * @ap: ATA channel to manipulate
886 * Allocate and point to DMA memory, init port private memory,
890 * Inherited from caller.
892 static int mv_port_start(struct ata_port *ap)
894 struct device *dev = ap->host->dev;
895 struct mv_host_priv *hpriv = ap->host->private_data;
896 struct mv_port_priv *pp;
897 void __iomem *port_mmio = mv_ap_base(ap);
902 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
906 mem = dmam_alloc_coherent(dev, MV_PORT_PRIV_DMA_SZ, &mem_dma,
910 memset(mem, 0, MV_PORT_PRIV_DMA_SZ);
912 rc = ata_pad_alloc(ap, dev);
916 /* First item in chunk of DMA memory:
917 * 32-slot command request table (CRQB), 32 bytes each in size
920 pp->crqb_dma = mem_dma;
922 mem_dma += MV_CRQB_Q_SZ;
925 * 32-slot command response table (CRPB), 8 bytes each in size
928 pp->crpb_dma = mem_dma;
930 mem_dma += MV_CRPB_Q_SZ;
933 * Table of scatter-gather descriptors (ePRD), 16 bytes each
936 pp->sg_tbl_dma = mem_dma;
938 mv_edma_cfg(hpriv, port_mmio);
940 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS);
941 writelfl(pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK,
942 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
944 if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
945 writelfl(pp->crqb_dma & 0xffffffff,
946 port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
948 writelfl(0, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
950 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS);
952 if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
953 writelfl(pp->crpb_dma & 0xffffffff,
954 port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
956 writelfl(0, port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
958 writelfl(pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK,
959 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
961 /* Don't turn on EDMA here...do it before DMA commands only. Else
962 * we'll be unable to send non-data, PIO, etc due to restricted access
965 ap->private_data = pp;
970 * mv_port_stop - Port specific cleanup/stop routine.
971 * @ap: ATA channel to manipulate
973 * Stop DMA, cleanup port memory.
976 * This routine uses the host lock to protect the DMA stop.
978 static void mv_port_stop(struct ata_port *ap)
982 spin_lock_irqsave(&ap->host->lock, flags);
984 spin_unlock_irqrestore(&ap->host->lock, flags);
988 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
989 * @qc: queued command whose SG list to source from
991 * Populate the SG list and mark the last entry.
994 * Inherited from caller.
996 static unsigned int mv_fill_sg(struct ata_queued_cmd *qc)
998 struct mv_port_priv *pp = qc->ap->private_data;
999 unsigned int n_sg = 0;
1000 struct scatterlist *sg;
1001 struct mv_sg *mv_sg;
1004 ata_for_each_sg(sg, qc) {
1005 dma_addr_t addr = sg_dma_address(sg);
1006 u32 sg_len = sg_dma_len(sg);
1008 mv_sg->addr = cpu_to_le32(addr & 0xffffffff);
1009 mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
1010 mv_sg->flags_size = cpu_to_le32(sg_len & 0xffff);
1012 if (ata_sg_is_last(sg, qc))
1013 mv_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
1022 static inline unsigned mv_inc_q_index(unsigned index)
1024 return (index + 1) & MV_MAX_Q_DEPTH_MASK;
1027 static inline void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last)
1029 u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
1030 (last ? CRQB_CMD_LAST : 0);
1031 *cmdw = cpu_to_le16(tmp);
1035 * mv_qc_prep - Host specific command preparation.
1036 * @qc: queued command to prepare
1038 * This routine simply redirects to the general purpose routine
1039 * if command is not DMA. Else, it handles prep of the CRQB
1040 * (command request block), does some sanity checking, and calls
1041 * the SG load routine.
1044 * Inherited from caller.
1046 static void mv_qc_prep(struct ata_queued_cmd *qc)
1048 struct ata_port *ap = qc->ap;
1049 struct mv_port_priv *pp = ap->private_data;
1051 struct ata_taskfile *tf;
1055 if (ATA_PROT_DMA != qc->tf.protocol)
1058 /* Fill in command request block
1060 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
1061 flags |= CRQB_FLAG_READ;
1062 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
1063 flags |= qc->tag << CRQB_TAG_SHIFT;
1065 /* get current queue index from hardware */
1066 in_index = (readl(mv_ap_base(ap) + EDMA_REQ_Q_IN_PTR_OFS)
1067 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1069 pp->crqb[in_index].sg_addr =
1070 cpu_to_le32(pp->sg_tbl_dma & 0xffffffff);
1071 pp->crqb[in_index].sg_addr_hi =
1072 cpu_to_le32((pp->sg_tbl_dma >> 16) >> 16);
1073 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags);
1075 cw = &pp->crqb[in_index].ata_cmd[0];
1078 /* Sadly, the CRQB cannot accomodate all registers--there are
1079 * only 11 bytes...so we must pick and choose required
1080 * registers based on the command. So, we drop feature and
1081 * hob_feature for [RW] DMA commands, but they are needed for
1082 * NCQ. NCQ will drop hob_nsect.
1084 switch (tf->command) {
1086 case ATA_CMD_READ_EXT:
1088 case ATA_CMD_WRITE_EXT:
1089 case ATA_CMD_WRITE_FUA_EXT:
1090 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
1092 #ifdef LIBATA_NCQ /* FIXME: remove this line when NCQ added */
1093 case ATA_CMD_FPDMA_READ:
1094 case ATA_CMD_FPDMA_WRITE:
1095 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
1096 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
1098 #endif /* FIXME: remove this line when NCQ added */
1100 /* The only other commands EDMA supports in non-queued and
1101 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
1102 * of which are defined/used by Linux. If we get here, this
1103 * driver needs work.
1105 * FIXME: modify libata to give qc_prep a return value and
1106 * return error here.
1108 BUG_ON(tf->command);
1111 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
1112 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
1113 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
1114 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
1115 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
1116 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
1117 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
1118 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
1119 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
1121 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
1127 * mv_qc_prep_iie - Host specific command preparation.
1128 * @qc: queued command to prepare
1130 * This routine simply redirects to the general purpose routine
1131 * if command is not DMA. Else, it handles prep of the CRQB
1132 * (command request block), does some sanity checking, and calls
1133 * the SG load routine.
1136 * Inherited from caller.
1138 static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
1140 struct ata_port *ap = qc->ap;
1141 struct mv_port_priv *pp = ap->private_data;
1142 struct mv_crqb_iie *crqb;
1143 struct ata_taskfile *tf;
1147 if (ATA_PROT_DMA != qc->tf.protocol)
1150 /* Fill in Gen IIE command request block
1152 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
1153 flags |= CRQB_FLAG_READ;
1155 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
1156 flags |= qc->tag << CRQB_TAG_SHIFT;
1158 /* get current queue index from hardware */
1159 in_index = (readl(mv_ap_base(ap) + EDMA_REQ_Q_IN_PTR_OFS)
1160 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1162 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];
1163 crqb->addr = cpu_to_le32(pp->sg_tbl_dma & 0xffffffff);
1164 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma >> 16) >> 16);
1165 crqb->flags = cpu_to_le32(flags);
1168 crqb->ata_cmd[0] = cpu_to_le32(
1169 (tf->command << 16) |
1172 crqb->ata_cmd[1] = cpu_to_le32(
1178 crqb->ata_cmd[2] = cpu_to_le32(
1179 (tf->hob_lbal << 0) |
1180 (tf->hob_lbam << 8) |
1181 (tf->hob_lbah << 16) |
1182 (tf->hob_feature << 24)
1184 crqb->ata_cmd[3] = cpu_to_le32(
1186 (tf->hob_nsect << 8)
1189 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
1195 * mv_qc_issue - Initiate a command to the host
1196 * @qc: queued command to start
1198 * This routine simply redirects to the general purpose routine
1199 * if command is not DMA. Else, it sanity checks our local
1200 * caches of the request producer/consumer indices then enables
1201 * DMA and bumps the request producer index.
1204 * Inherited from caller.
1206 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
1208 void __iomem *port_mmio = mv_ap_base(qc->ap);
1209 struct mv_port_priv *pp = qc->ap->private_data;
1213 if (ATA_PROT_DMA != qc->tf.protocol) {
1214 /* We're about to send a non-EDMA capable command to the
1215 * port. Turn off EDMA so there won't be problems accessing
1216 * shadow block, etc registers.
1218 mv_stop_dma(qc->ap);
1219 return ata_qc_issue_prot(qc);
1222 in_ptr = readl(port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
1223 in_index = (in_ptr >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1225 /* until we do queuing, the queue should be empty at this point */
1226 WARN_ON(in_index != ((readl(port_mmio + EDMA_REQ_Q_OUT_PTR_OFS)
1227 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK));
1229 in_index = mv_inc_q_index(in_index); /* now incr producer index */
1231 mv_start_dma(port_mmio, pp);
1233 /* and write the request in pointer to kick the EDMA to life */
1234 in_ptr &= EDMA_REQ_Q_BASE_LO_MASK;
1235 in_ptr |= in_index << EDMA_REQ_Q_PTR_SHIFT;
1236 writelfl(in_ptr, port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
1242 * mv_get_crpb_status - get status from most recently completed cmd
1243 * @ap: ATA channel to manipulate
1245 * This routine is for use when the port is in DMA mode, when it
1246 * will be using the CRPB (command response block) method of
1247 * returning command completion information. We check indices
1248 * are good, grab status, and bump the response consumer index to
1249 * prove that we're up to date.
1252 * Inherited from caller.
1254 static u8 mv_get_crpb_status(struct ata_port *ap)
1256 void __iomem *port_mmio = mv_ap_base(ap);
1257 struct mv_port_priv *pp = ap->private_data;
1262 out_ptr = readl(port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
1263 out_index = (out_ptr >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1265 ata_status = le16_to_cpu(pp->crpb[out_index].flags)
1266 >> CRPB_FLAG_STATUS_SHIFT;
1268 /* increment our consumer index... */
1269 out_index = mv_inc_q_index(out_index);
1271 /* and, until we do NCQ, there should only be 1 CRPB waiting */
1272 WARN_ON(out_index != ((readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS)
1273 >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK));
1275 /* write out our inc'd consumer index so EDMA knows we're caught up */
1276 out_ptr &= EDMA_RSP_Q_BASE_LO_MASK;
1277 out_ptr |= out_index << EDMA_RSP_Q_PTR_SHIFT;
1278 writelfl(out_ptr, port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
1280 /* Return ATA status register for completed CRPB */
1285 * mv_err_intr - Handle error interrupts on the port
1286 * @ap: ATA channel to manipulate
1287 * @reset_allowed: bool: 0 == don't trigger from reset here
1289 * In most cases, just clear the interrupt and move on. However,
1290 * some cases require an eDMA reset, which is done right before
1291 * the COMRESET in mv_phy_reset(). The SERR case requires a
1292 * clear of pending errors in the SATA SERROR register. Finally,
1293 * if the port disabled DMA, update our cached copy to match.
1296 * Inherited from caller.
1298 static void mv_err_intr(struct ata_port *ap, int reset_allowed)
1300 void __iomem *port_mmio = mv_ap_base(ap);
1301 u32 edma_err_cause, serr = 0;
1303 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1305 if (EDMA_ERR_SERR & edma_err_cause) {
1306 sata_scr_read(ap, SCR_ERROR, &serr);
1307 sata_scr_write_flush(ap, SCR_ERROR, serr);
1309 if (EDMA_ERR_SELF_DIS & edma_err_cause) {
1310 struct mv_port_priv *pp = ap->private_data;
1311 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1313 DPRINTK(KERN_ERR "ata%u: port error; EDMA err cause: 0x%08x "
1314 "SERR: 0x%08x\n", ap->print_id, edma_err_cause, serr);
1316 /* Clear EDMA now that SERR cleanup done */
1317 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1319 /* check for fatal here and recover if needed */
1320 if (reset_allowed && (EDMA_ERR_FATAL & edma_err_cause))
1321 mv_stop_and_reset(ap);
1325 * mv_host_intr - Handle all interrupts on the given host controller
1326 * @host: host specific structure
1327 * @relevant: port error bits relevant to this host controller
1328 * @hc: which host controller we're to look at
1330 * Read then write clear the HC interrupt status then walk each
1331 * port connected to the HC and see if it needs servicing. Port
1332 * success ints are reported in the HC interrupt status reg, the
1333 * port error ints are reported in the higher level main
1334 * interrupt status register and thus are passed in via the
1335 * 'relevant' argument.
1338 * Inherited from caller.
1340 static void mv_host_intr(struct ata_host *host, u32 relevant, unsigned int hc)
1342 void __iomem *mmio = host->iomap[MV_PRIMARY_BAR];
1343 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
1344 struct ata_queued_cmd *qc;
1346 int shift, port, port0, hard_port, handled;
1347 unsigned int err_mask;
1352 port0 = MV_PORTS_PER_HC;
1354 /* we'll need the HC success int register in most cases */
1355 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
1357 writelfl(~hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
1359 VPRINTK("ENTER, hc%u relevant=0x%08x HC IRQ cause=0x%08x\n",
1360 hc,relevant,hc_irq_cause);
1362 for (port = port0; port < port0 + MV_PORTS_PER_HC; port++) {
1364 struct ata_port *ap = host->ports[port];
1365 struct mv_port_priv *pp = ap->private_data;
1367 hard_port = mv_hardport_from_port(port); /* range 0..3 */
1368 handled = 0; /* ensure ata_status is set if handled++ */
1370 /* Note that DEV_IRQ might happen spuriously during EDMA,
1371 * and should be ignored in such cases.
1372 * The cause of this is still under investigation.
1374 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
1375 /* EDMA: check for response queue interrupt */
1376 if ((CRPB_DMA_DONE << hard_port) & hc_irq_cause) {
1377 ata_status = mv_get_crpb_status(ap);
1381 /* PIO: check for device (drive) interrupt */
1382 if ((DEV_IRQ << hard_port) & hc_irq_cause) {
1383 ata_status = readb(ap->ioaddr.status_addr);
1385 /* ignore spurious intr if drive still BUSY */
1386 if (ata_status & ATA_BUSY) {
1393 if (ap && (ap->flags & ATA_FLAG_DISABLED))
1396 err_mask = ac_err_mask(ata_status);
1398 shift = port << 1; /* (port * 2) */
1399 if (port >= MV_PORTS_PER_HC) {
1400 shift++; /* skip bit 8 in the HC Main IRQ reg */
1402 if ((PORT0_ERR << shift) & relevant) {
1404 err_mask |= AC_ERR_OTHER;
1409 qc = ata_qc_from_tag(ap, ap->active_tag);
1410 if (qc && (qc->flags & ATA_QCFLAG_ACTIVE)) {
1411 VPRINTK("port %u IRQ found for qc, "
1412 "ata_status 0x%x\n", port,ata_status);
1413 /* mark qc status appropriately */
1414 if (!(qc->tf.flags & ATA_TFLAG_POLLING)) {
1415 qc->err_mask |= err_mask;
1416 ata_qc_complete(qc);
1427 * @dev_instance: private data; in this case the host structure
1430 * Read the read only register to determine if any host
1431 * controllers have pending interrupts. If so, call lower level
1432 * routine to handle. Also check for PCI errors which are only
1436 * This routine holds the host lock while processing pending
1439 static irqreturn_t mv_interrupt(int irq, void *dev_instance)
1441 struct ata_host *host = dev_instance;
1442 unsigned int hc, handled = 0, n_hcs;
1443 void __iomem *mmio = host->iomap[MV_PRIMARY_BAR];
1444 struct mv_host_priv *hpriv;
1447 irq_stat = readl(mmio + HC_MAIN_IRQ_CAUSE_OFS);
1449 /* check the cases where we either have nothing pending or have read
1450 * a bogus register value which can indicate HW removal or PCI fault
1452 if (!irq_stat || (0xffffffffU == irq_stat))
1455 n_hcs = mv_get_hc_count(host->ports[0]->flags);
1456 spin_lock(&host->lock);
1458 for (hc = 0; hc < n_hcs; hc++) {
1459 u32 relevant = irq_stat & (HC0_IRQ_PEND << (hc * HC_SHIFT));
1461 mv_host_intr(host, relevant, hc);
1466 hpriv = host->private_data;
1467 if (IS_60XX(hpriv)) {
1468 /* deal with the interrupt coalescing bits */
1469 if (irq_stat & (TRAN_LO_DONE | TRAN_HI_DONE | PORTS_0_7_COAL_DONE)) {
1470 writelfl(0, mmio + MV_IRQ_COAL_CAUSE_LO);
1471 writelfl(0, mmio + MV_IRQ_COAL_CAUSE_HI);
1472 writelfl(0, mmio + MV_IRQ_COAL_CAUSE);
1476 if (PCI_ERR & irq_stat) {
1477 printk(KERN_ERR DRV_NAME ": PCI ERROR; PCI IRQ cause=0x%08x\n",
1478 readl(mmio + PCI_IRQ_CAUSE_OFS));
1480 DPRINTK("All regs @ PCI error\n");
1481 mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev));
1483 writelfl(0, mmio + PCI_IRQ_CAUSE_OFS);
1486 spin_unlock(&host->lock);
1488 return IRQ_RETVAL(handled);
1491 static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
1493 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
1494 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
1496 return hc_mmio + ofs;
1499 static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
1503 switch (sc_reg_in) {
1507 ofs = sc_reg_in * sizeof(u32);
1516 static u32 mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in)
1518 void __iomem *mmio = ap->host->iomap[MV_PRIMARY_BAR];
1519 void __iomem *addr = mv5_phy_base(mmio, ap->port_no);
1520 unsigned int ofs = mv5_scr_offset(sc_reg_in);
1522 if (ofs != 0xffffffffU)
1523 return readl(addr + ofs);
1528 static void mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
1530 void __iomem *mmio = ap->host->iomap[MV_PRIMARY_BAR];
1531 void __iomem *addr = mv5_phy_base(mmio, ap->port_no);
1532 unsigned int ofs = mv5_scr_offset(sc_reg_in);
1534 if (ofs != 0xffffffffU)
1535 writelfl(val, addr + ofs);
1538 static void mv5_reset_bus(struct pci_dev *pdev, void __iomem *mmio)
1543 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
1545 early_5080 = (pdev->device == 0x5080) && (rev_id == 0);
1548 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
1550 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
1553 mv_reset_pci_bus(pdev, mmio);
1556 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
1558 writel(0x0fcfffff, mmio + MV_FLASH_CTL);
1561 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
1564 void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
1567 tmp = readl(phy_mmio + MV5_PHY_MODE);
1569 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
1570 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
1573 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
1577 writel(0, mmio + MV_GPIO_PORT_CTL);
1579 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
1581 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
1583 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
1586 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
1589 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
1590 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
1592 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
1595 tmp = readl(phy_mmio + MV5_LT_MODE);
1597 writel(tmp, phy_mmio + MV5_LT_MODE);
1599 tmp = readl(phy_mmio + MV5_PHY_CTL);
1602 writel(tmp, phy_mmio + MV5_PHY_CTL);
1605 tmp = readl(phy_mmio + MV5_PHY_MODE);
1607 tmp |= hpriv->signal[port].pre;
1608 tmp |= hpriv->signal[port].amps;
1609 writel(tmp, phy_mmio + MV5_PHY_MODE);
1614 #define ZERO(reg) writel(0, port_mmio + (reg))
1615 static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
1618 void __iomem *port_mmio = mv_port_base(mmio, port);
1620 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
1622 mv_channel_reset(hpriv, mmio, port);
1624 ZERO(0x028); /* command */
1625 writel(0x11f, port_mmio + EDMA_CFG_OFS);
1626 ZERO(0x004); /* timer */
1627 ZERO(0x008); /* irq err cause */
1628 ZERO(0x00c); /* irq err mask */
1629 ZERO(0x010); /* rq bah */
1630 ZERO(0x014); /* rq inp */
1631 ZERO(0x018); /* rq outp */
1632 ZERO(0x01c); /* respq bah */
1633 ZERO(0x024); /* respq outp */
1634 ZERO(0x020); /* respq inp */
1635 ZERO(0x02c); /* test control */
1636 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT);
1640 #define ZERO(reg) writel(0, hc_mmio + (reg))
1641 static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1644 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
1652 tmp = readl(hc_mmio + 0x20);
1655 writel(tmp, hc_mmio + 0x20);
1659 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1662 unsigned int hc, port;
1664 for (hc = 0; hc < n_hc; hc++) {
1665 for (port = 0; port < MV_PORTS_PER_HC; port++)
1666 mv5_reset_hc_port(hpriv, mmio,
1667 (hc * MV_PORTS_PER_HC) + port);
1669 mv5_reset_one_hc(hpriv, mmio, hc);
1676 #define ZERO(reg) writel(0, mmio + (reg))
1677 static void mv_reset_pci_bus(struct pci_dev *pdev, void __iomem *mmio)
1681 tmp = readl(mmio + MV_PCI_MODE);
1683 writel(tmp, mmio + MV_PCI_MODE);
1685 ZERO(MV_PCI_DISC_TIMER);
1686 ZERO(MV_PCI_MSI_TRIGGER);
1687 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT);
1688 ZERO(HC_MAIN_IRQ_MASK_OFS);
1689 ZERO(MV_PCI_SERR_MASK);
1690 ZERO(PCI_IRQ_CAUSE_OFS);
1691 ZERO(PCI_IRQ_MASK_OFS);
1692 ZERO(MV_PCI_ERR_LOW_ADDRESS);
1693 ZERO(MV_PCI_ERR_HIGH_ADDRESS);
1694 ZERO(MV_PCI_ERR_ATTRIBUTE);
1695 ZERO(MV_PCI_ERR_COMMAND);
1699 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
1703 mv5_reset_flash(hpriv, mmio);
1705 tmp = readl(mmio + MV_GPIO_PORT_CTL);
1707 tmp |= (1 << 5) | (1 << 6);
1708 writel(tmp, mmio + MV_GPIO_PORT_CTL);
1712 * mv6_reset_hc - Perform the 6xxx global soft reset
1713 * @mmio: base address of the HBA
1715 * This routine only applies to 6xxx parts.
1718 * Inherited from caller.
1720 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1723 void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS;
1727 /* Following procedure defined in PCI "main command and status
1731 writel(t | STOP_PCI_MASTER, reg);
1733 for (i = 0; i < 1000; i++) {
1736 if (PCI_MASTER_EMPTY & t) {
1740 if (!(PCI_MASTER_EMPTY & t)) {
1741 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
1749 writel(t | GLOB_SFT_RST, reg);
1752 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
1754 if (!(GLOB_SFT_RST & t)) {
1755 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
1760 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
1763 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
1766 } while ((GLOB_SFT_RST & t) && (i-- > 0));
1768 if (GLOB_SFT_RST & t) {
1769 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
1776 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
1779 void __iomem *port_mmio;
1782 tmp = readl(mmio + MV_RESET_CFG);
1783 if ((tmp & (1 << 0)) == 0) {
1784 hpriv->signal[idx].amps = 0x7 << 8;
1785 hpriv->signal[idx].pre = 0x1 << 5;
1789 port_mmio = mv_port_base(mmio, idx);
1790 tmp = readl(port_mmio + PHY_MODE2);
1792 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
1793 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
1796 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
1798 writel(0x00000060, mmio + MV_GPIO_PORT_CTL);
1801 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
1804 void __iomem *port_mmio = mv_port_base(mmio, port);
1806 u32 hp_flags = hpriv->hp_flags;
1808 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
1810 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
1813 if (fix_phy_mode2) {
1814 m2 = readl(port_mmio + PHY_MODE2);
1817 writel(m2, port_mmio + PHY_MODE2);
1821 m2 = readl(port_mmio + PHY_MODE2);
1822 m2 &= ~((1 << 16) | (1 << 31));
1823 writel(m2, port_mmio + PHY_MODE2);
1828 /* who knows what this magic does */
1829 tmp = readl(port_mmio + PHY_MODE3);
1832 writel(tmp, port_mmio + PHY_MODE3);
1834 if (fix_phy_mode4) {
1837 m4 = readl(port_mmio + PHY_MODE4);
1839 if (hp_flags & MV_HP_ERRATA_60X1B2)
1840 tmp = readl(port_mmio + 0x310);
1842 m4 = (m4 & ~(1 << 1)) | (1 << 0);
1844 writel(m4, port_mmio + PHY_MODE4);
1846 if (hp_flags & MV_HP_ERRATA_60X1B2)
1847 writel(tmp, port_mmio + 0x310);
1850 /* Revert values of pre-emphasis and signal amps to the saved ones */
1851 m2 = readl(port_mmio + PHY_MODE2);
1853 m2 &= ~MV_M2_PREAMP_MASK;
1854 m2 |= hpriv->signal[port].amps;
1855 m2 |= hpriv->signal[port].pre;
1858 /* according to mvSata 3.6.1, some IIE values are fixed */
1859 if (IS_GEN_IIE(hpriv)) {
1864 writel(m2, port_mmio + PHY_MODE2);
1867 static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio,
1868 unsigned int port_no)
1870 void __iomem *port_mmio = mv_port_base(mmio, port_no);
1872 writelfl(ATA_RST, port_mmio + EDMA_CMD_OFS);
1874 if (IS_60XX(hpriv)) {
1875 u32 ifctl = readl(port_mmio + SATA_INTERFACE_CTL);
1876 ifctl |= (1 << 7); /* enable gen2i speed */
1877 ifctl = (ifctl & 0xfff) | 0x9b1000; /* from chip spec */
1878 writelfl(ifctl, port_mmio + SATA_INTERFACE_CTL);
1881 udelay(25); /* allow reset propagation */
1883 /* Spec never mentions clearing the bit. Marvell's driver does
1884 * clear the bit, however.
1886 writelfl(0, port_mmio + EDMA_CMD_OFS);
1888 hpriv->ops->phy_errata(hpriv, mmio, port_no);
1894 static void mv_stop_and_reset(struct ata_port *ap)
1896 struct mv_host_priv *hpriv = ap->host->private_data;
1897 void __iomem *mmio = ap->host->iomap[MV_PRIMARY_BAR];
1901 mv_channel_reset(hpriv, mmio, ap->port_no);
1903 __mv_phy_reset(ap, 0);
1906 static inline void __msleep(unsigned int msec, int can_sleep)
1915 * __mv_phy_reset - Perform eDMA reset followed by COMRESET
1916 * @ap: ATA channel to manipulate
1918 * Part of this is taken from __sata_phy_reset and modified to
1919 * not sleep since this routine gets called from interrupt level.
1922 * Inherited from caller. This is coded to safe to call at
1923 * interrupt level, i.e. it does not sleep.
1925 static void __mv_phy_reset(struct ata_port *ap, int can_sleep)
1927 struct mv_port_priv *pp = ap->private_data;
1928 struct mv_host_priv *hpriv = ap->host->private_data;
1929 void __iomem *port_mmio = mv_ap_base(ap);
1930 struct ata_taskfile tf;
1931 struct ata_device *dev = &ap->device[0];
1932 unsigned long timeout;
1936 VPRINTK("ENTER, port %u, mmio 0x%p\n", ap->port_no, port_mmio);
1938 DPRINTK("S-regs after ATA_RST: SStat 0x%08x SErr 0x%08x "
1939 "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS),
1940 mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL));
1942 /* Issue COMRESET via SControl */
1944 sata_scr_write_flush(ap, SCR_CONTROL, 0x301);
1945 __msleep(1, can_sleep);
1947 sata_scr_write_flush(ap, SCR_CONTROL, 0x300);
1948 __msleep(20, can_sleep);
1950 timeout = jiffies + msecs_to_jiffies(200);
1952 sata_scr_read(ap, SCR_STATUS, &sstatus);
1953 if (((sstatus & 0x3) == 3) || ((sstatus & 0x3) == 0))
1956 __msleep(1, can_sleep);
1957 } while (time_before(jiffies, timeout));
1959 /* work around errata */
1960 if (IS_60XX(hpriv) &&
1961 (sstatus != 0x0) && (sstatus != 0x113) && (sstatus != 0x123) &&
1963 goto comreset_retry;
1965 DPRINTK("S-regs after PHY wake: SStat 0x%08x SErr 0x%08x "
1966 "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS),
1967 mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL));
1969 if (ata_port_online(ap)) {
1972 sata_scr_read(ap, SCR_STATUS, &sstatus);
1973 ata_port_printk(ap, KERN_INFO,
1974 "no device found (phy stat %08x)\n", sstatus);
1975 ata_port_disable(ap);
1979 /* even after SStatus reflects that device is ready,
1980 * it seems to take a while for link to be fully
1981 * established (and thus Status no longer 0x80/0x7F),
1982 * so we poll a bit for that, here.
1986 u8 drv_stat = ata_check_status(ap);
1987 if ((drv_stat != 0x80) && (drv_stat != 0x7f))
1989 __msleep(500, can_sleep);
1994 tf.lbah = readb(ap->ioaddr.lbah_addr);
1995 tf.lbam = readb(ap->ioaddr.lbam_addr);
1996 tf.lbal = readb(ap->ioaddr.lbal_addr);
1997 tf.nsect = readb(ap->ioaddr.nsect_addr);
1999 dev->class = ata_dev_classify(&tf);
2000 if (!ata_dev_enabled(dev)) {
2001 VPRINTK("Port disabled post-sig: No device present.\n");
2002 ata_port_disable(ap);
2005 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2007 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
2012 static void mv_phy_reset(struct ata_port *ap)
2014 __mv_phy_reset(ap, 1);
2018 * mv_eng_timeout - Routine called by libata when SCSI times out I/O
2019 * @ap: ATA channel to manipulate
2021 * Intent is to clear all pending error conditions, reset the
2022 * chip/bus, fail the command, and move on.
2025 * This routine holds the host lock while failing the command.
2027 static void mv_eng_timeout(struct ata_port *ap)
2029 void __iomem *mmio = ap->host->iomap[MV_PRIMARY_BAR];
2030 struct ata_queued_cmd *qc;
2031 unsigned long flags;
2033 ata_port_printk(ap, KERN_ERR, "Entering mv_eng_timeout\n");
2034 DPRINTK("All regs @ start of eng_timeout\n");
2035 mv_dump_all_regs(mmio, ap->port_no, to_pci_dev(ap->host->dev));
2037 qc = ata_qc_from_tag(ap, ap->active_tag);
2038 printk(KERN_ERR "mmio_base %p ap %p qc %p scsi_cmnd %p &cmnd %p\n",
2039 mmio, ap, qc, qc->scsicmd, &qc->scsicmd->cmnd);
2041 spin_lock_irqsave(&ap->host->lock, flags);
2043 mv_stop_and_reset(ap);
2044 spin_unlock_irqrestore(&ap->host->lock, flags);
2046 WARN_ON(!(qc->flags & ATA_QCFLAG_ACTIVE));
2047 if (qc->flags & ATA_QCFLAG_ACTIVE) {
2048 qc->err_mask |= AC_ERR_TIMEOUT;
2049 ata_eh_qc_complete(qc);
2054 * mv_port_init - Perform some early initialization on a single port.
2055 * @port: libata data structure storing shadow register addresses
2056 * @port_mmio: base address of the port
2058 * Initialize shadow register mmio addresses, clear outstanding
2059 * interrupts on the port, and unmask interrupts for the future
2060 * start of the port.
2063 * Inherited from caller.
2065 static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
2067 void __iomem *shd_base = port_mmio + SHD_BLK_OFS;
2070 /* PIO related setup
2072 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
2074 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
2075 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
2076 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
2077 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
2078 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
2079 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
2081 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
2082 /* special case: control/altstatus doesn't have ATA_REG_ address */
2083 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS;
2086 port->cmd_addr = port->bmdma_addr = port->scr_addr = NULL;
2088 /* Clear any currently outstanding port interrupt conditions */
2089 serr_ofs = mv_scr_offset(SCR_ERROR);
2090 writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs);
2091 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2093 /* unmask all EDMA error interrupts */
2094 writelfl(~0, port_mmio + EDMA_ERR_IRQ_MASK_OFS);
2096 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
2097 readl(port_mmio + EDMA_CFG_OFS),
2098 readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS),
2099 readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS));
2102 static int mv_chip_id(struct pci_dev *pdev, struct mv_host_priv *hpriv,
2103 unsigned int board_idx)
2106 u32 hp_flags = hpriv->hp_flags;
2108 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
2112 hpriv->ops = &mv5xxx_ops;
2113 hp_flags |= MV_HP_50XX;
2117 hp_flags |= MV_HP_ERRATA_50XXB0;
2120 hp_flags |= MV_HP_ERRATA_50XXB2;
2123 dev_printk(KERN_WARNING, &pdev->dev,
2124 "Applying 50XXB2 workarounds to unknown rev\n");
2125 hp_flags |= MV_HP_ERRATA_50XXB2;
2132 hpriv->ops = &mv5xxx_ops;
2133 hp_flags |= MV_HP_50XX;
2137 hp_flags |= MV_HP_ERRATA_50XXB0;
2140 hp_flags |= MV_HP_ERRATA_50XXB2;
2143 dev_printk(KERN_WARNING, &pdev->dev,
2144 "Applying B2 workarounds to unknown rev\n");
2145 hp_flags |= MV_HP_ERRATA_50XXB2;
2152 hpriv->ops = &mv6xxx_ops;
2156 hp_flags |= MV_HP_ERRATA_60X1B2;
2159 hp_flags |= MV_HP_ERRATA_60X1C0;
2162 dev_printk(KERN_WARNING, &pdev->dev,
2163 "Applying B2 workarounds to unknown rev\n");
2164 hp_flags |= MV_HP_ERRATA_60X1B2;
2171 hpriv->ops = &mv6xxx_ops;
2173 hp_flags |= MV_HP_GEN_IIE;
2177 hp_flags |= MV_HP_ERRATA_XX42A0;
2180 hp_flags |= MV_HP_ERRATA_60X1C0;
2183 dev_printk(KERN_WARNING, &pdev->dev,
2184 "Applying 60X1C0 workarounds to unknown rev\n");
2185 hp_flags |= MV_HP_ERRATA_60X1C0;
2191 printk(KERN_ERR DRV_NAME ": BUG: invalid board index %u\n", board_idx);
2195 hpriv->hp_flags = hp_flags;
2201 * mv_init_host - Perform some early initialization of the host.
2202 * @pdev: host PCI device
2203 * @probe_ent: early data struct representing the host
2205 * If possible, do an early global reset of the host. Then do
2206 * our port init and clear/unmask all/relevant host interrupts.
2209 * Inherited from caller.
2211 static int mv_init_host(struct pci_dev *pdev, struct ata_probe_ent *probe_ent,
2212 unsigned int board_idx)
2214 int rc = 0, n_hc, port, hc;
2215 void __iomem *mmio = probe_ent->iomap[MV_PRIMARY_BAR];
2216 struct mv_host_priv *hpriv = probe_ent->private_data;
2218 /* global interrupt mask */
2219 writel(0, mmio + HC_MAIN_IRQ_MASK_OFS);
2221 rc = mv_chip_id(pdev, hpriv, board_idx);
2225 n_hc = mv_get_hc_count(probe_ent->port_flags);
2226 probe_ent->n_ports = MV_PORTS_PER_HC * n_hc;
2228 for (port = 0; port < probe_ent->n_ports; port++)
2229 hpriv->ops->read_preamp(hpriv, port, mmio);
2231 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
2235 hpriv->ops->reset_flash(hpriv, mmio);
2236 hpriv->ops->reset_bus(pdev, mmio);
2237 hpriv->ops->enable_leds(hpriv, mmio);
2239 for (port = 0; port < probe_ent->n_ports; port++) {
2240 if (IS_60XX(hpriv)) {
2241 void __iomem *port_mmio = mv_port_base(mmio, port);
2243 u32 ifctl = readl(port_mmio + SATA_INTERFACE_CTL);
2244 ifctl |= (1 << 7); /* enable gen2i speed */
2245 ifctl = (ifctl & 0xfff) | 0x9b1000; /* from chip spec */
2246 writelfl(ifctl, port_mmio + SATA_INTERFACE_CTL);
2249 hpriv->ops->phy_errata(hpriv, mmio, port);
2252 for (port = 0; port < probe_ent->n_ports; port++) {
2253 void __iomem *port_mmio = mv_port_base(mmio, port);
2254 mv_port_init(&probe_ent->port[port], port_mmio);
2257 for (hc = 0; hc < n_hc; hc++) {
2258 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
2260 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
2261 "(before clear)=0x%08x\n", hc,
2262 readl(hc_mmio + HC_CFG_OFS),
2263 readl(hc_mmio + HC_IRQ_CAUSE_OFS));
2265 /* Clear any currently outstanding hc interrupt conditions */
2266 writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS);
2269 /* Clear any currently outstanding host interrupt conditions */
2270 writelfl(0, mmio + PCI_IRQ_CAUSE_OFS);
2272 /* and unmask interrupt generation for host regs */
2273 writelfl(PCI_UNMASK_ALL_IRQS, mmio + PCI_IRQ_MASK_OFS);
2276 writelfl(~HC_MAIN_MASKED_IRQS_5, mmio + HC_MAIN_IRQ_MASK_OFS);
2278 writelfl(~HC_MAIN_MASKED_IRQS, mmio + HC_MAIN_IRQ_MASK_OFS);
2280 VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x "
2281 "PCI int cause/mask=0x%08x/0x%08x\n",
2282 readl(mmio + HC_MAIN_IRQ_CAUSE_OFS),
2283 readl(mmio + HC_MAIN_IRQ_MASK_OFS),
2284 readl(mmio + PCI_IRQ_CAUSE_OFS),
2285 readl(mmio + PCI_IRQ_MASK_OFS));
2292 * mv_print_info - Dump key info to kernel log for perusal.
2293 * @probe_ent: early data struct representing the host
2295 * FIXME: complete this.
2298 * Inherited from caller.
2300 static void mv_print_info(struct ata_probe_ent *probe_ent)
2302 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
2303 struct mv_host_priv *hpriv = probe_ent->private_data;
2307 /* Use this to determine the HW stepping of the chip so we know
2308 * what errata to workaround
2310 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
2312 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
2315 else if (scc == 0x01)
2320 dev_printk(KERN_INFO, &pdev->dev,
2321 "%u slots %u ports %s mode IRQ via %s\n",
2322 (unsigned)MV_MAX_Q_DEPTH, probe_ent->n_ports,
2323 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
2327 * mv_init_one - handle a positive probe of a Marvell host
2328 * @pdev: PCI device found
2329 * @ent: PCI device ID entry for the matched host
2332 * Inherited from caller.
2334 static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2336 static int printed_version = 0;
2337 struct device *dev = &pdev->dev;
2338 struct ata_probe_ent *probe_ent;
2339 struct mv_host_priv *hpriv;
2340 unsigned int board_idx = (unsigned int)ent->driver_data;
2343 if (!printed_version++)
2344 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
2346 rc = pcim_enable_device(pdev);
2349 pci_set_master(pdev);
2351 rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME);
2353 pcim_pin_device(pdev);
2357 rc = pci_go_64(pdev);
2361 probe_ent = devm_kzalloc(dev, sizeof(*probe_ent), GFP_KERNEL);
2362 if (probe_ent == NULL)
2365 probe_ent->dev = pci_dev_to_dev(pdev);
2366 INIT_LIST_HEAD(&probe_ent->node);
2368 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
2372 probe_ent->sht = mv_port_info[board_idx].sht;
2373 probe_ent->port_flags = mv_port_info[board_idx].flags;
2374 probe_ent->pio_mask = mv_port_info[board_idx].pio_mask;
2375 probe_ent->udma_mask = mv_port_info[board_idx].udma_mask;
2376 probe_ent->port_ops = mv_port_info[board_idx].port_ops;
2378 probe_ent->irq = pdev->irq;
2379 probe_ent->irq_flags = IRQF_SHARED;
2380 probe_ent->iomap = pcim_iomap_table(pdev);
2381 probe_ent->private_data = hpriv;
2383 /* initialize adapter */
2384 rc = mv_init_host(pdev, probe_ent, board_idx);
2388 /* Enable interrupts */
2389 if (msi && pci_enable_msi(pdev))
2392 mv_dump_pci_cfg(pdev, 0x68);
2393 mv_print_info(probe_ent);
2395 if (ata_device_add(probe_ent) == 0)
2398 devm_kfree(dev, probe_ent);
2402 static int __init mv_init(void)
2404 return pci_register_driver(&mv_pci_driver);
2407 static void __exit mv_exit(void)
2409 pci_unregister_driver(&mv_pci_driver);
2412 MODULE_AUTHOR("Brett Russ");
2413 MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
2414 MODULE_LICENSE("GPL");
2415 MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
2416 MODULE_VERSION(DRV_VERSION);
2418 module_param(msi, int, 0444);
2419 MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
2421 module_init(mv_init);
2422 module_exit(mv_exit);