2 * pata_it8213.c - iTE Tech. Inc. IT8213 PATA driver
4 * The IT8213 is a very Intel ICH like device for timing purposes, having
5 * a similar register layout and the same split clock arrangement. Cable
6 * detection is different, and it does not have slave channels or all the
7 * clutter of later ICH/SATA setups.
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/pci.h>
13 #include <linux/init.h>
14 #include <linux/blkdev.h>
15 #include <linux/delay.h>
16 #include <linux/device.h>
17 #include <scsi/scsi_host.h>
18 #include <linux/libata.h>
19 #include <linux/ata.h>
21 #define DRV_NAME "pata_it8213"
22 #define DRV_VERSION "0.0.2"
25 * it8213_pre_reset - check for 40/80 pin
28 * Filter out ports by the enable bits before doing the normal reset
32 static int it8213_pre_reset(struct ata_port *ap)
34 static const struct pci_bits it8213_enable_bits[] = {
35 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
37 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
38 if (!pci_test_config_bits(pdev, &it8213_enable_bits[ap->port_no]))
40 return ata_std_prereset(ap);
44 * it8213_error_handler - Probe specified port on PATA host controller
48 * None (inherited from caller).
51 static void it8213_error_handler(struct ata_port *ap)
53 ata_bmdma_drive_eh(ap, it8213_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
57 * it8213_cable_detect - check for 40/80 pin
60 * Perform cable detection for the 8213 ATA interface. This is
61 * different to the PIIX arrangement
64 static int it8213_cable_detect(struct ata_port *ap)
66 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
68 pci_read_config_byte(pdev, 0x42, &tmp);
69 if (tmp & 2) /* The initial docs are incorrect */
70 return ATA_CBL_PATA40;
71 return ATA_CBL_PATA80;
75 * it8213_set_piomode - Initialize host controller PATA PIO timings
76 * @ap: Port whose timings we are configuring
77 * @adev: Device whose timings we are configuring
79 * Set PIO mode for device, in host controller PCI config space.
82 * None (inherited from caller).
85 static void it8213_set_piomode (struct ata_port *ap, struct ata_device *adev)
87 unsigned int pio = adev->pio_mode - XFER_PIO_0;
88 struct pci_dev *dev = to_pci_dev(ap->host->dev);
89 unsigned int idetm_port= ap->port_no ? 0x42 : 0x40;
94 * See Intel Document 298600-004 for the timing programing rules
95 * for PIIX/ICH. The 8213 is a clone so very similar
98 static const /* ISP RTC */
99 u8 timings[][2] = { { 0, 0 },
106 control |= 1; /* TIME1 enable */
107 if (ata_pio_need_iordy(adev)) /* PIO 3/4 require IORDY */
108 control |= 2; /* IORDY enable */
109 /* Bit 2 is set for ATAPI on the IT8213 - reverse of ICH/PIIX */
110 if (adev->class != ATA_DEV_ATA)
113 pci_read_config_word(dev, idetm_port, &idetm_data);
115 /* Enable PPE, IE and TIME as appropriate */
117 if (adev->devno == 0) {
118 idetm_data &= 0xCCF0;
119 idetm_data |= control;
120 idetm_data |= (timings[pio][0] << 12) |
121 (timings[pio][1] << 8);
125 idetm_data &= 0xCC0F;
126 idetm_data |= (control << 4);
128 /* Slave timing in seperate register */
129 pci_read_config_byte(dev, 0x44, &slave_data);
131 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << 4;
132 pci_write_config_byte(dev, 0x44, slave_data);
135 idetm_data |= 0x4000; /* Ensure SITRE is enabled */
136 pci_write_config_word(dev, idetm_port, idetm_data);
140 * it8213_set_dmamode - Initialize host controller PATA DMA timings
141 * @ap: Port whose timings we are configuring
142 * @adev: Device to program
144 * Set UDMA/MWDMA mode for device, in host controller PCI config space.
145 * This device is basically an ICH alike.
148 * None (inherited from caller).
151 static void it8213_set_dmamode (struct ata_port *ap, struct ata_device *adev)
153 struct pci_dev *dev = to_pci_dev(ap->host->dev);
155 u8 speed = adev->dma_mode;
156 int devid = adev->devno;
159 static const /* ISP RTC */
160 u8 timings[][2] = { { 0, 0 },
166 pci_read_config_word(dev, 0x40, &master_data);
167 pci_read_config_byte(dev, 0x48, &udma_enable);
169 if (speed >= XFER_UDMA_0) {
170 unsigned int udma = adev->dma_mode - XFER_UDMA_0;
173 int u_clock, u_speed;
175 /* Clocks follow the PIIX style */
176 u_speed = min(2 - (udma & 1), udma);
178 u_clock = 0x1000; /* 100Mhz */
180 u_clock = 1; /* 66Mhz */
182 u_clock = 0; /* 33Mhz */
184 udma_enable |= (1 << devid);
186 /* Load the UDMA mode number */
187 pci_read_config_word(dev, 0x4A, &udma_timing);
188 udma_timing &= ~(3 << (4 * devid));
189 udma_timing |= (udma & 3) << (4 * devid);
190 pci_write_config_word(dev, 0x4A, udma_timing);
192 /* Load the clock selection */
193 pci_read_config_word(dev, 0x54, &ideconf);
194 ideconf &= ~(0x1001 << devid);
195 ideconf |= u_clock << devid;
196 pci_write_config_word(dev, 0x54, ideconf);
199 * MWDMA is driven by the PIO timings. We must also enable
200 * IORDY unconditionally along with TIME1. PPE has already
201 * been set when the PIO timing was set.
203 unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;
204 unsigned int control;
206 static const unsigned int needed_pio[3] = {
207 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
209 int pio = needed_pio[mwdma] - XFER_PIO_0;
211 control = 3; /* IORDY|TIME1 */
213 /* If the drive MWDMA is faster than it can do PIO then
214 we must force PIO into PIO0 */
216 if (adev->pio_mode < needed_pio[mwdma])
217 /* Enable DMA timing only */
218 control |= 8; /* PIO cycles in PIO0 */
220 if (devid) { /* Slave */
221 master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */
222 master_data |= control << 4;
223 pci_read_config_byte(dev, 0x44, &slave_data);
224 slave_data &= (0x0F + 0xE1 * ap->port_no);
225 /* Load the matching timing */
226 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
227 pci_write_config_byte(dev, 0x44, slave_data);
228 } else { /* Master */
229 master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY
230 and master timing bits */
231 master_data |= control;
233 (timings[pio][0] << 12) |
234 (timings[pio][1] << 8);
236 udma_enable &= ~(1 << devid);
237 pci_write_config_word(dev, 0x40, master_data);
239 pci_write_config_byte(dev, 0x48, udma_enable);
242 static struct scsi_host_template it8213_sht = {
243 .module = THIS_MODULE,
245 .ioctl = ata_scsi_ioctl,
246 .queuecommand = ata_scsi_queuecmd,
247 .can_queue = ATA_DEF_QUEUE,
248 .this_id = ATA_SHT_THIS_ID,
249 .sg_tablesize = LIBATA_MAX_PRD,
250 .max_sectors = ATA_MAX_SECTORS,
251 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
252 .emulated = ATA_SHT_EMULATED,
253 .use_clustering = ATA_SHT_USE_CLUSTERING,
254 .proc_name = DRV_NAME,
255 .dma_boundary = ATA_DMA_BOUNDARY,
256 .slave_configure = ata_scsi_slave_config,
257 .bios_param = ata_std_bios_param,
259 .resume = ata_scsi_device_resume,
260 .suspend = ata_scsi_device_suspend,
264 static const struct ata_port_operations it8213_ops = {
265 .port_disable = ata_port_disable,
266 .set_piomode = it8213_set_piomode,
267 .set_dmamode = it8213_set_dmamode,
268 .mode_filter = ata_pci_default_filter,
270 .tf_load = ata_tf_load,
271 .tf_read = ata_tf_read,
272 .check_status = ata_check_status,
273 .exec_command = ata_exec_command,
274 .dev_select = ata_std_dev_select,
276 .freeze = ata_bmdma_freeze,
277 .thaw = ata_bmdma_thaw,
278 .error_handler = it8213_error_handler,
279 .post_internal_cmd = ata_bmdma_post_internal_cmd,
280 .cable_detect = it8213_cable_detect,
282 .bmdma_setup = ata_bmdma_setup,
283 .bmdma_start = ata_bmdma_start,
284 .bmdma_stop = ata_bmdma_stop,
285 .bmdma_status = ata_bmdma_status,
286 .qc_prep = ata_qc_prep,
287 .qc_issue = ata_qc_issue_prot,
288 .data_xfer = ata_data_xfer,
290 .irq_handler = ata_interrupt,
291 .irq_clear = ata_bmdma_irq_clear,
292 .irq_on = ata_irq_on,
293 .irq_ack = ata_irq_ack,
295 .port_start = ata_port_start,
300 * it8213_init_one - Register 8213 ATA PCI device with kernel services
301 * @pdev: PCI device to register
302 * @ent: Entry in it8213_pci_tbl matching with @pdev
304 * Called from kernel PCI layer.
307 * Inherited from PCI layer (may sleep).
310 * Zero on success, or -ERRNO value.
313 static int it8213_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
315 static int printed_version;
316 static struct ata_port_info info = {
318 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
319 .pio_mask = 0x1f, /* pio0-4 */
320 .mwdma_mask = 0x07, /* mwdma0-2 */
321 .udma_mask = 0x1f, /* UDMA 100 */
322 .port_ops = &it8213_ops,
324 static struct ata_port_info *port_info[2] = { &info, &info };
326 if (!printed_version++)
327 dev_printk(KERN_DEBUG, &pdev->dev,
328 "version " DRV_VERSION "\n");
330 /* Current IT8213 stuff is single port */
331 return ata_pci_init_one(pdev, port_info, 1);
334 static const struct pci_device_id it8213_pci_tbl[] = {
335 { PCI_VDEVICE(ITE, PCI_DEVICE_ID_ITE_8213), },
337 { } /* terminate list */
340 static struct pci_driver it8213_pci_driver = {
342 .id_table = it8213_pci_tbl,
343 .probe = it8213_init_one,
344 .remove = ata_pci_remove_one,
346 .suspend = ata_pci_device_suspend,
347 .resume = ata_pci_device_resume,
351 static int __init it8213_init(void)
353 return pci_register_driver(&it8213_pci_driver);
356 static void __exit it8213_exit(void)
358 pci_unregister_driver(&it8213_pci_driver);
361 module_init(it8213_init);
362 module_exit(it8213_exit);
364 MODULE_AUTHOR("Alan Cox");
365 MODULE_DESCRIPTION("SCSI low-level driver for the ITE 8213");
366 MODULE_LICENSE("GPL");
367 MODULE_DEVICE_TABLE(pci, it8213_pci_tbl);
368 MODULE_VERSION(DRV_VERSION);