git.oblomov.eu Git - linux-2.6/blob - drivers/media/common/tuners/mxl5005s.c

   1 /*
   2     MaxLinear MXL5005S VSB/QAM/DVBT tuner driver
   3
   4     Copyright (C) 2008 MaxLinear
   5     Copyright (C) 2006 Steven Toth <stoth@hauppauge.com>
   6       Functions:
   7         mxl5005s_reset()
   8         mxl5005s_writereg()
   9         mxl5005s_writeregs()
  10         mxl5005s_init()
  11         mxl5005s_reconfigure()
  12         mxl5005s_AssignTunerMode()
  13         mxl5005s_set_params()
  14         mxl5005s_get_frequency()
  15         mxl5005s_get_bandwidth()
  16         mxl5005s_release()
  17         mxl5005s_attach()
  18
  19     Copyright (c) 2008 Realtek
  20     Copyright (c) 2008 Jan Hoogenraad, Barnaby Shearer, Andy Hasper
  21       Functions:
  22         mxl5005s_SetRfFreqHz()
  23
  24     This program is free software; you can redistribute it and/or modify
  25     it under the terms of the GNU General Public License as published by
  26     the Free Software Foundation; either version 2 of the License, or
  27     (at your option) any later version.
  28
  29     This program is distributed in the hope that it will be useful,
  30     but WITHOUT ANY WARRANTY; without even the implied warranty of
  31     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  32     GNU General Public License for more details.
  33
  34     You should have received a copy of the GNU General Public License
  35     along with this program; if not, write to the Free Software
  36     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  37
  38 */
  39
  40 /*
  41     History of this driver (Steven Toth):
  42       I was given a public release of a linux driver that included
  43       support for the MaxLinear MXL5005S silicon tuner. Analysis of
  44       the tuner driver showed clearly three things.
  45
  46       1. The tuner driver didn't support the LinuxTV tuner API
  47          so the code Realtek added had to be removed.
  48
  49       2. A significant amount of the driver is reference driver code
  50          from MaxLinear, I felt it was important to identify and
  51          preserve this.
  52
  53       3. New code has to be added to interface correctly with the
  54          LinuxTV API, as a regular kernel module.
  55
  56       Other than the reference driver enum's, I've clearly marked
  57       sections of the code and retained the copyright of the
  58       respective owners.
  59 */
  60 #include <linux/kernel.h>
  61 #include <linux/init.h>
  62 #include <linux/module.h>
  63 #include <linux/string.h>
  64 #include <linux/slab.h>
  65 #include <linux/delay.h>
  66 #include "dvb_frontend.h"
  67 #include "mxl5005s.h"
  68
  69 static int debug = 2;
  70
  71 #define dprintk(level, arg...) do {    \
  72         if (level <= debug)            \
  73                 printk(arg);    \
  74         } while (0)
  75
  76 #define TUNER_REGS_NUM          104
  77 #define INITCTRL_NUM            40
  78
  79 #ifdef _MXL_PRODUCTION
  80 #define CHCTRL_NUM              39
  81 #else
  82 #define CHCTRL_NUM              36
  83 #endif
  84
  85 #define MXLCTRL_NUM             189
  86 #define MASTER_CONTROL_ADDR     9
  87
  88 /* Enumeration of Master Control Register State */
  89 enum master_control_state {
  90         MC_LOAD_START = 1,
  91         MC_POWER_DOWN,
  92         MC_SYNTH_RESET,
  93         MC_SEQ_OFF
  94 };
  95
  96 /* Enumeration of MXL5005 Tuner Modulation Type */
  97 enum {
  98         MXL_DEFAULT_MODULATION = 0,
  99         MXL_DVBT,
 100         MXL_ATSC,
 101         MXL_QAM,
 102         MXL_ANALOG_CABLE,
 103         MXL_ANALOG_OTA
 104 } tuner_modu_type;
 105
 106 /* MXL5005 Tuner Register Struct */
 107 struct TunerReg {
 108         u16 Reg_Num;    /* Tuner Register Address */
 109         u16 Reg_Val;    /* Current sw programmed value waiting to be writen */
 110 };
 111
 112 enum {
 113         /* Initialization Control Names */
 114         DN_IQTN_AMP_CUT = 1,       /* 1 */
 115         BB_MODE,                   /* 2 */
 116         BB_BUF,                    /* 3 */
 117         BB_BUF_OA,                 /* 4 */
 118         BB_ALPF_BANDSELECT,        /* 5 */
 119         BB_IQSWAP,                 /* 6 */
 120         BB_DLPF_BANDSEL,           /* 7 */
 121         RFSYN_CHP_GAIN,            /* 8 */
 122         RFSYN_EN_CHP_HIGAIN,       /* 9 */
 123         AGC_IF,                    /* 10 */
 124         AGC_RF,                    /* 11 */
 125         IF_DIVVAL,                 /* 12 */
 126         IF_VCO_BIAS,               /* 13 */
 127         CHCAL_INT_MOD_IF,          /* 14 */
 128         CHCAL_FRAC_MOD_IF,         /* 15 */
 129         DRV_RES_SEL,               /* 16 */
 130         I_DRIVER,                  /* 17 */
 131         EN_AAF,                    /* 18 */
 132         EN_3P,                     /* 19 */
 133         EN_AUX_3P,                 /* 20 */
 134         SEL_AAF_BAND,              /* 21 */
 135         SEQ_ENCLK16_CLK_OUT,       /* 22 */
 136         SEQ_SEL4_16B,              /* 23 */
 137         XTAL_CAPSELECT,            /* 24 */
 138         IF_SEL_DBL,                /* 25 */
 139         RFSYN_R_DIV,               /* 26 */
 140         SEQ_EXTSYNTHCALIF,         /* 27 */
 141         SEQ_EXTDCCAL,              /* 28 */
 142         AGC_EN_RSSI,               /* 29 */
 143         RFA_ENCLKRFAGC,            /* 30 */
 144         RFA_RSSI_REFH,             /* 31 */
 145         RFA_RSSI_REF,              /* 32 */
 146         RFA_RSSI_REFL,             /* 33 */
 147         RFA_FLR,                   /* 34 */
 148         RFA_CEIL,                  /* 35 */
 149         SEQ_EXTIQFSMPULSE,         /* 36 */
 150         OVERRIDE_1,                /* 37 */
 151         BB_INITSTATE_DLPF_TUNE,    /* 38 */
 152         TG_R_DIV,                  /* 39 */
 153         EN_CHP_LIN_B,              /* 40 */
 154
 155         /* Channel Change Control Names */
 156         DN_POLY = 51,              /* 51 */
 157         DN_RFGAIN,                 /* 52 */
 158         DN_CAP_RFLPF,              /* 53 */
 159         DN_EN_VHFUHFBAR,           /* 54 */
 160         DN_GAIN_ADJUST,            /* 55 */
 161         DN_IQTNBUF_AMP,            /* 56 */
 162         DN_IQTNGNBFBIAS_BST,       /* 57 */
 163         RFSYN_EN_OUTMUX,           /* 58 */
 164         RFSYN_SEL_VCO_OUT,         /* 59 */
 165         RFSYN_SEL_VCO_HI,          /* 60 */
 166         RFSYN_SEL_DIVM,            /* 61 */
 167         RFSYN_RF_DIV_BIAS,         /* 62 */
 168         DN_SEL_FREQ,               /* 63 */
 169         RFSYN_VCO_BIAS,            /* 64 */
 170         CHCAL_INT_MOD_RF,          /* 65 */
 171         CHCAL_FRAC_MOD_RF,         /* 66 */
 172         RFSYN_LPF_R,               /* 67 */
 173         CHCAL_EN_INT_RF,           /* 68 */
 174         TG_LO_DIVVAL,              /* 69 */
 175         TG_LO_SELVAL,              /* 70 */
 176         TG_DIV_VAL,                /* 71 */
 177         TG_VCO_BIAS,               /* 72 */
 178         SEQ_EXTPOWERUP,            /* 73 */
 179         OVERRIDE_2,                /* 74 */
 180         OVERRIDE_3,                /* 75 */
 181         OVERRIDE_4,                /* 76 */
 182         SEQ_FSM_PULSE,             /* 77 */
 183         GPIO_4B,                   /* 78 */
 184         GPIO_3B,                   /* 79 */
 185         GPIO_4,                    /* 80 */
 186         GPIO_3,                    /* 81 */
 187         GPIO_1B,                   /* 82 */
 188         DAC_A_ENABLE,              /* 83 */
 189         DAC_B_ENABLE,              /* 84 */
 190         DAC_DIN_A,                 /* 85 */
 191         DAC_DIN_B,                 /* 86 */
 192 #ifdef _MXL_PRODUCTION
 193         RFSYN_EN_DIV,              /* 87 */
 194         RFSYN_DIVM,                /* 88 */
 195         DN_BYPASS_AGC_I2C          /* 89 */
 196 #endif
 197 } MXL5005_ControlName;
 198
 199 /*
 200  * The following context is source code provided by MaxLinear.
 201  * MaxLinear source code - Common_MXL.h (?)
 202  */
 203
 204 /* Constants */
 205 #define MXL5005S_REG_WRITING_TABLE_LEN_MAX      104
 206 #define MXL5005S_LATCH_BYTE                     0xfe
 207
 208 /* Register address, MSB, and LSB */
 209 #define MXL5005S_BB_IQSWAP_ADDR                 59
 210 #define MXL5005S_BB_IQSWAP_MSB                  0
 211 #define MXL5005S_BB_IQSWAP_LSB                  0
 212
 213 #define MXL5005S_BB_DLPF_BANDSEL_ADDR           53
 214 #define MXL5005S_BB_DLPF_BANDSEL_MSB            4
 215 #define MXL5005S_BB_DLPF_BANDSEL_LSB            3
 216
 217 /* Standard modes */
 218 enum {
 219         MXL5005S_STANDARD_DVBT,
 220         MXL5005S_STANDARD_ATSC,
 221 };
 222 #define MXL5005S_STANDARD_MODE_NUM              2
 223
 224 /* Bandwidth modes */
 225 enum {
 226         MXL5005S_BANDWIDTH_6MHZ = 6000000,
 227         MXL5005S_BANDWIDTH_7MHZ = 7000000,
 228         MXL5005S_BANDWIDTH_8MHZ = 8000000,
 229 };
 230 #define MXL5005S_BANDWIDTH_MODE_NUM             3
 231
 232 /* MXL5005 Tuner Control Struct */
 233 struct TunerControl {
 234         u16 Ctrl_Num;   /* Control Number */
 235         u16 size;       /* Number of bits to represent Value */
 236         u16 addr[25];   /* Array of Tuner Register Address for each bit pos */
 237         u16 bit[25];    /* Array of bit pos in Reg Addr for each bit pos */
 238         u16 val[25];    /* Binary representation of Value */
 239 };
 240
 241 /* MXL5005 Tuner Struct */
 242 struct mxl5005s_state {
 243         u8      Mode;           /* 0: Analog Mode ; 1: Digital Mode */
 244         u8      IF_Mode;        /* for Analog Mode, 0: zero IF; 1: low IF */
 245         u32     Chan_Bandwidth; /* filter  channel bandwidth (6, 7, 8) */
 246         u32     IF_OUT;         /* Desired IF Out Frequency */
 247         u16     IF_OUT_LOAD;    /* IF Out Load Resistor (200/300 Ohms) */
 248         u32     RF_IN;          /* RF Input Frequency */
 249         u32     Fxtal;          /* XTAL Frequency */
 250         u8      AGC_Mode;       /* AGC Mode 0: Dual AGC; 1: Single AGC */
 251         u16     TOP;            /* Value: take over point */
 252         u8      CLOCK_OUT;      /* 0: turn off clk out; 1: turn on clock out */
 253         u8      DIV_OUT;        /* 4MHz or 16MHz */
 254         u8      CAPSELECT;      /* 0: disable On-Chip pulling cap; 1: enable */
 255         u8      EN_RSSI;        /* 0: disable RSSI; 1: enable RSSI */
 256
 257         /* Modulation Type; */
 258         /* 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable */
 259         u8      Mod_Type;
 260
 261         /* Tracking Filter Type */
 262         /* 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H */
 263         u8      TF_Type;
 264
 265         /* Calculated Settings */
 266         u32     RF_LO;          /* Synth RF LO Frequency */
 267         u32     IF_LO;          /* Synth IF LO Frequency */
 268         u32     TG_LO;          /* Synth TG_LO Frequency */
 269
 270         /* Pointers to ControlName Arrays */
 271         u16     Init_Ctrl_Num;          /* Number of INIT Control Names */
 272         struct TunerControl
 273                 Init_Ctrl[INITCTRL_NUM]; /* INIT Control Names Array Pointer */
 274
 275         u16     CH_Ctrl_Num;            /* Number of CH Control Names */
 276         struct TunerControl
 277                 CH_Ctrl[CHCTRL_NUM];    /* CH Control Name Array Pointer */
 278
 279         u16     MXL_Ctrl_Num;           /* Number of MXL Control Names */
 280         struct TunerControl
 281                 MXL_Ctrl[MXLCTRL_NUM];  /* MXL Control Name Array Pointer */
 282
 283         /* Pointer to Tuner Register Array */
 284         u16     TunerRegs_Num;          /* Number of Tuner Registers */
 285         struct TunerReg
 286                 TunerRegs[TUNER_REGS_NUM]; /* Tuner Register Array Pointer */
 287
 288         /* Linux driver framework specific */
 289         struct mxl5005s_config *config;
 290         struct dvb_frontend *frontend;
 291         struct i2c_adapter *i2c;
 292
 293         /* Cache values */
 294         u32 current_mode;
 295
 296 };
 297
 298 static u16 MXL_GetMasterControl(u8 *MasterReg, int state);
 299 static u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value);
 300 static u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value);
 301 static void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit,
 302         u8 bitVal);
 303 static u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 *RegNum,
 304         u8 *RegVal, int *count);
 305 static u32 MXL_Ceiling(u32 value, u32 resolution);
 306 static u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal);
 307 static u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal);
 308 static u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum,
 309         u32 value, u16 controlGroup);
 310 static u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val);
 311 static u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 *RegNum,
 312         u8 *RegVal, int *count);
 313 static u32 MXL_GetXtalInt(u32 Xtal_Freq);
 314 static u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq);
 315 static void MXL_SynthIFLO_Calc(struct dvb_frontend *fe);
 316 static void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe);
 317 static u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum,
 318         u8 *RegVal, int *count);
 319 static int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable,
 320         u8 *datatable, u8 len);
 321 static u16 MXL_IFSynthInit(struct dvb_frontend *fe);
 322 static int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type,
 323         u32 bandwidth);
 324 static int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type,
 325         u32 bandwidth);
 326
 327 /* ----------------------------------------------------------------
 328  * Begin: Custom code salvaged from the Realtek driver.
 329  * Copyright (c) 2008 Realtek
 330  * Copyright (c) 2008 Jan Hoogenraad, Barnaby Shearer, Andy Hasper
 331  * This code is placed under the terms of the GNU General Public License
 332  *
 333  * Released by Realtek under GPLv2.
 334  * Thanks to Realtek for a lot of support we received !
 335  *
 336  *  Revision: 080314 - original version
 337  */
 338
 339 static int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz)
 340 {
 341         struct mxl5005s_state *state = fe->tuner_priv;
 342         unsigned char AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX];
 343         unsigned char ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX];
 344         int TableLen;
 345
 346         u32 IfDivval = 0;
 347         unsigned char MasterControlByte;
 348
 349         dprintk(1, "%s() freq=%ld\n", __func__, RfFreqHz);
 350
 351         /* Set MxL5005S tuner RF frequency according to example code. */
 352
 353         /* Tuner RF frequency setting stage 0 */
 354         MXL_GetMasterControl(ByteTable, MC_SYNTH_RESET);
 355         AddrTable[0] = MASTER_CONTROL_ADDR;
 356         ByteTable[0] |= state->config->AgcMasterByte;
 357
 358         mxl5005s_writeregs(fe, AddrTable, ByteTable, 1);
 359
 360         /* Tuner RF frequency setting stage 1 */
 361         MXL_TuneRF(fe, RfFreqHz);
 362
 363         MXL_ControlRead(fe, IF_DIVVAL, &IfDivval);
 364
 365         MXL_ControlWrite(fe, SEQ_FSM_PULSE, 0);
 366         MXL_ControlWrite(fe, SEQ_EXTPOWERUP, 1);
 367         MXL_ControlWrite(fe, IF_DIVVAL, 8);
 368         MXL_GetCHRegister(fe, AddrTable, ByteTable, &TableLen);
 369
 370         MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START);
 371         AddrTable[TableLen] = MASTER_CONTROL_ADDR ;
 372         ByteTable[TableLen] = MasterControlByte |
 373                 state->config->AgcMasterByte;
 374         TableLen += 1;
 375
 376         mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen);
 377
 378         /* Wait 30 ms. */
 379         msleep(150);
 380
 381         /* Tuner RF frequency setting stage 2 */
 382         MXL_ControlWrite(fe, SEQ_FSM_PULSE, 1);
 383         MXL_ControlWrite(fe, IF_DIVVAL, IfDivval);
 384         MXL_GetCHRegister_ZeroIF(fe, AddrTable, ByteTable, &TableLen);
 385
 386         MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START);
 387         AddrTable[TableLen] = MASTER_CONTROL_ADDR ;
 388         ByteTable[TableLen] = MasterControlByte |
 389                 state->config->AgcMasterByte ;
 390         TableLen += 1;
 391
 392         mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen);
 393
 394         msleep(100);
 395
 396         return 0;
 397 }
 398 /* End: Custom code taken from the Realtek driver */
 399
 400 /* ----------------------------------------------------------------
 401  * Begin: Reference driver code found in the Realtek driver.
 402  * Copyright (c) 2008 MaxLinear
 403  */
 404 static u16 MXL5005_RegisterInit(struct dvb_frontend *fe)
 405 {
 406         struct mxl5005s_state *state = fe->tuner_priv;
 407         state->TunerRegs_Num = TUNER_REGS_NUM ;
 408
 409         state->TunerRegs[0].Reg_Num = 9 ;
 410         state->TunerRegs[0].Reg_Val = 0x40 ;
 411
 412         state->TunerRegs[1].Reg_Num = 11 ;
 413         state->TunerRegs[1].Reg_Val = 0x19 ;
 414
 415         state->TunerRegs[2].Reg_Num = 12 ;
 416         state->TunerRegs[2].Reg_Val = 0x60 ;
 417
 418         state->TunerRegs[3].Reg_Num = 13 ;
 419         state->TunerRegs[3].Reg_Val = 0x00 ;
 420
 421         state->TunerRegs[4].Reg_Num = 14 ;
 422         state->TunerRegs[4].Reg_Val = 0x00 ;
 423
 424         state->TunerRegs[5].Reg_Num = 15 ;
 425         state->TunerRegs[5].Reg_Val = 0xC0 ;
 426
 427         state->TunerRegs[6].Reg_Num = 16 ;
 428         state->TunerRegs[6].Reg_Val = 0x00 ;
 429
 430         state->TunerRegs[7].Reg_Num = 17 ;
 431         state->TunerRegs[7].Reg_Val = 0x00 ;
 432
 433         state->TunerRegs[8].Reg_Num = 18 ;
 434         state->TunerRegs[8].Reg_Val = 0x00 ;
 435
 436         state->TunerRegs[9].Reg_Num = 19 ;
 437         state->TunerRegs[9].Reg_Val = 0x34 ;
 438
 439         state->TunerRegs[10].Reg_Num = 21 ;
 440         state->TunerRegs[10].Reg_Val = 0x00 ;
 441
 442         state->TunerRegs[11].Reg_Num = 22 ;
 443         state->TunerRegs[11].Reg_Val = 0x6B ;
 444
 445         state->TunerRegs[12].Reg_Num = 23 ;
 446         state->TunerRegs[12].Reg_Val = 0x35 ;
 447
 448         state->TunerRegs[13].Reg_Num = 24 ;
 449         state->TunerRegs[13].Reg_Val = 0x70 ;
 450
 451         state->TunerRegs[14].Reg_Num = 25 ;
 452         state->TunerRegs[14].Reg_Val = 0x3E ;
 453
 454         state->TunerRegs[15].Reg_Num = 26 ;
 455         state->TunerRegs[15].Reg_Val = 0x82 ;
 456
 457         state->TunerRegs[16].Reg_Num = 31 ;
 458         state->TunerRegs[16].Reg_Val = 0x00 ;
 459
 460         state->TunerRegs[17].Reg_Num = 32 ;
 461         state->TunerRegs[17].Reg_Val = 0x40 ;
 462
 463         state->TunerRegs[18].Reg_Num = 33 ;
 464         state->TunerRegs[18].Reg_Val = 0x53 ;
 465
 466         state->TunerRegs[19].Reg_Num = 34 ;
 467         state->TunerRegs[19].Reg_Val = 0x81 ;
 468
 469         state->TunerRegs[20].Reg_Num = 35 ;
 470         state->TunerRegs[20].Reg_Val = 0xC9 ;
 471
 472         state->TunerRegs[21].Reg_Num = 36 ;
 473         state->TunerRegs[21].Reg_Val = 0x01 ;
 474
 475         state->TunerRegs[22].Reg_Num = 37 ;
 476         state->TunerRegs[22].Reg_Val = 0x00 ;
 477
 478         state->TunerRegs[23].Reg_Num = 41 ;
 479         state->TunerRegs[23].Reg_Val = 0x00 ;
 480
 481         state->TunerRegs[24].Reg_Num = 42 ;
 482         state->TunerRegs[24].Reg_Val = 0xF8 ;
 483
 484         state->TunerRegs[25].Reg_Num = 43 ;
 485         state->TunerRegs[25].Reg_Val = 0x43 ;
 486
 487         state->TunerRegs[26].Reg_Num = 44 ;
 488         state->TunerRegs[26].Reg_Val = 0x20 ;
 489
 490         state->TunerRegs[27].Reg_Num = 45 ;
 491         state->TunerRegs[27].Reg_Val = 0x80 ;
 492
 493         state->TunerRegs[28].Reg_Num = 46 ;
 494         state->TunerRegs[28].Reg_Val = 0x88 ;
 495
 496         state->TunerRegs[29].Reg_Num = 47 ;
 497         state->TunerRegs[29].Reg_Val = 0x86 ;
 498
 499         state->TunerRegs[30].Reg_Num = 48 ;
 500         state->TunerRegs[30].Reg_Val = 0x00 ;
 501
 502         state->TunerRegs[31].Reg_Num = 49 ;
 503         state->TunerRegs[31].Reg_Val = 0x00 ;
 504
 505         state->TunerRegs[32].Reg_Num = 53 ;
 506         state->TunerRegs[32].Reg_Val = 0x94 ;
 507
 508         state->TunerRegs[33].Reg_Num = 54 ;
 509         state->TunerRegs[33].Reg_Val = 0xFA ;
 510
 511         state->TunerRegs[34].Reg_Num = 55 ;
 512         state->TunerRegs[34].Reg_Val = 0x92 ;
 513
 514         state->TunerRegs[35].Reg_Num = 56 ;
 515         state->TunerRegs[35].Reg_Val = 0x80 ;
 516
 517         state->TunerRegs[36].Reg_Num = 57 ;
 518         state->TunerRegs[36].Reg_Val = 0x41 ;
 519
 520         state->TunerRegs[37].Reg_Num = 58 ;
 521         state->TunerRegs[37].Reg_Val = 0xDB ;
 522
 523         state->TunerRegs[38].Reg_Num = 59 ;
 524         state->TunerRegs[38].Reg_Val = 0x00 ;
 525
 526         state->TunerRegs[39].Reg_Num = 60 ;
 527         state->TunerRegs[39].Reg_Val = 0x00 ;
 528
 529         state->TunerRegs[40].Reg_Num = 61 ;
 530         state->TunerRegs[40].Reg_Val = 0x00 ;
 531
 532         state->TunerRegs[41].Reg_Num = 62 ;
 533         state->TunerRegs[41].Reg_Val = 0x00 ;
 534
 535         state->TunerRegs[42].Reg_Num = 65 ;
 536         state->TunerRegs[42].Reg_Val = 0xF8 ;
 537
 538         state->TunerRegs[43].Reg_Num = 66 ;
 539         state->TunerRegs[43].Reg_Val = 0xE4 ;
 540
 541         state->TunerRegs[44].Reg_Num = 67 ;
 542         state->TunerRegs[44].Reg_Val = 0x90 ;
 543
 544         state->TunerRegs[45].Reg_Num = 68 ;
 545         state->TunerRegs[45].Reg_Val = 0xC0 ;
 546
 547         state->TunerRegs[46].Reg_Num = 69 ;
 548         state->TunerRegs[46].Reg_Val = 0x01 ;
 549
 550         state->TunerRegs[47].Reg_Num = 70 ;
 551         state->TunerRegs[47].Reg_Val = 0x50 ;
 552
 553         state->TunerRegs[48].Reg_Num = 71 ;
 554         state->TunerRegs[48].Reg_Val = 0x06 ;
 555
 556         state->TunerRegs[49].Reg_Num = 72 ;
 557         state->TunerRegs[49].Reg_Val = 0x00 ;
 558
 559         state->TunerRegs[50].Reg_Num = 73 ;
 560         state->TunerRegs[50].Reg_Val = 0x20 ;
 561
 562         state->TunerRegs[51].Reg_Num = 76 ;
 563         state->TunerRegs[51].Reg_Val = 0xBB ;
 564
 565         state->TunerRegs[52].Reg_Num = 77 ;
 566         state->TunerRegs[52].Reg_Val = 0x13 ;
 567
 568         state->TunerRegs[53].Reg_Num = 81 ;
 569         state->TunerRegs[53].Reg_Val = 0x04 ;
 570
 571         state->TunerRegs[54].Reg_Num = 82 ;
 572         state->TunerRegs[54].Reg_Val = 0x75 ;
 573
 574         state->TunerRegs[55].Reg_Num = 83 ;
 575         state->TunerRegs[55].Reg_Val = 0x00 ;
 576
 577         state->TunerRegs[56].Reg_Num = 84 ;
 578         state->TunerRegs[56].Reg_Val = 0x00 ;
 579
 580         state->TunerRegs[57].Reg_Num = 85 ;
 581         state->TunerRegs[57].Reg_Val = 0x00 ;
 582
 583         state->TunerRegs[58].Reg_Num = 91 ;
 584         state->TunerRegs[58].Reg_Val = 0x70 ;
 585
 586         state->TunerRegs[59].Reg_Num = 92 ;
 587         state->TunerRegs[59].Reg_Val = 0x00 ;
 588
 589         state->TunerRegs[60].Reg_Num = 93 ;
 590         state->TunerRegs[60].Reg_Val = 0x00 ;
 591
 592         state->TunerRegs[61].Reg_Num = 94 ;
 593         state->TunerRegs[61].Reg_Val = 0x00 ;
 594
 595         state->TunerRegs[62].Reg_Num = 95 ;
 596         state->TunerRegs[62].Reg_Val = 0x0C ;
 597
 598         state->TunerRegs[63].Reg_Num = 96 ;
 599         state->TunerRegs[63].Reg_Val = 0x00 ;
 600
 601         state->TunerRegs[64].Reg_Num = 97 ;
 602         state->TunerRegs[64].Reg_Val = 0x00 ;
 603
 604         state->TunerRegs[65].Reg_Num = 98 ;
 605         state->TunerRegs[65].Reg_Val = 0xE2 ;
 606
 607         state->TunerRegs[66].Reg_Num = 99 ;
 608         state->TunerRegs[66].Reg_Val = 0x00 ;
 609
 610         state->TunerRegs[67].Reg_Num = 100 ;
 611         state->TunerRegs[67].Reg_Val = 0x00 ;
 612
 613         state->TunerRegs[68].Reg_Num = 101 ;
 614         state->TunerRegs[68].Reg_Val = 0x12 ;
 615
 616         state->TunerRegs[69].Reg_Num = 102 ;
 617         state->TunerRegs[69].Reg_Val = 0x80 ;
 618
 619         state->TunerRegs[70].Reg_Num = 103 ;
 620         state->TunerRegs[70].Reg_Val = 0x32 ;
 621
 622         state->TunerRegs[71].Reg_Num = 104 ;
 623         state->TunerRegs[71].Reg_Val = 0xB4 ;
 624
 625         state->TunerRegs[72].Reg_Num = 105 ;
 626         state->TunerRegs[72].Reg_Val = 0x60 ;
 627
 628         state->TunerRegs[73].Reg_Num = 106 ;
 629         state->TunerRegs[73].Reg_Val = 0x83 ;
 630
 631         state->TunerRegs[74].Reg_Num = 107 ;
 632         state->TunerRegs[74].Reg_Val = 0x84 ;
 633
 634         state->TunerRegs[75].Reg_Num = 108 ;
 635         state->TunerRegs[75].Reg_Val = 0x9C ;
 636
 637         state->TunerRegs[76].Reg_Num = 109 ;
 638         state->TunerRegs[76].Reg_Val = 0x02 ;
 639
 640         state->TunerRegs[77].Reg_Num = 110 ;
 641         state->TunerRegs[77].Reg_Val = 0x81 ;
 642
 643         state->TunerRegs[78].Reg_Num = 111 ;
 644         state->TunerRegs[78].Reg_Val = 0xC0 ;
 645
 646         state->TunerRegs[79].Reg_Num = 112 ;
 647         state->TunerRegs[79].Reg_Val = 0x10 ;
 648
 649         state->TunerRegs[80].Reg_Num = 131 ;
 650         state->TunerRegs[80].Reg_Val = 0x8A ;
 651
 652         state->TunerRegs[81].Reg_Num = 132 ;
 653         state->TunerRegs[81].Reg_Val = 0x10 ;
 654
 655         state->TunerRegs[82].Reg_Num = 133 ;
 656         state->TunerRegs[82].Reg_Val = 0x24 ;
 657
 658         state->TunerRegs[83].Reg_Num = 134 ;
 659         state->TunerRegs[83].Reg_Val = 0x00 ;
 660
 661         state->TunerRegs[84].Reg_Num = 135 ;
 662         state->TunerRegs[84].Reg_Val = 0x00 ;
 663
 664         state->TunerRegs[85].Reg_Num = 136 ;
 665         state->TunerRegs[85].Reg_Val = 0x7E ;
 666
 667         state->TunerRegs[86].Reg_Num = 137 ;
 668         state->TunerRegs[86].Reg_Val = 0x40 ;
 669
 670         state->TunerRegs[87].Reg_Num = 138 ;
 671         state->TunerRegs[87].Reg_Val = 0x38 ;
 672
 673         state->TunerRegs[88].Reg_Num = 146 ;
 674         state->TunerRegs[88].Reg_Val = 0xF6 ;
 675
 676         state->TunerRegs[89].Reg_Num = 147 ;
 677         state->TunerRegs[89].Reg_Val = 0x1A ;
 678
 679         state->TunerRegs[90].Reg_Num = 148 ;
 680         state->TunerRegs[90].Reg_Val = 0x62 ;
 681
 682         state->TunerRegs[91].Reg_Num = 149 ;
 683         state->TunerRegs[91].Reg_Val = 0x33 ;
 684
 685         state->TunerRegs[92].Reg_Num = 150 ;
 686         state->TunerRegs[92].Reg_Val = 0x80 ;
 687
 688         state->TunerRegs[93].Reg_Num = 156 ;
 689         state->TunerRegs[93].Reg_Val = 0x56 ;
 690
 691         state->TunerRegs[94].Reg_Num = 157 ;
 692         state->TunerRegs[94].Reg_Val = 0x17 ;
 693
 694         state->TunerRegs[95].Reg_Num = 158 ;
 695         state->TunerRegs[95].Reg_Val = 0xA9 ;
 696
 697         state->TunerRegs[96].Reg_Num = 159 ;
 698         state->TunerRegs[96].Reg_Val = 0x00 ;
 699
 700         state->TunerRegs[97].Reg_Num = 160 ;
 701         state->TunerRegs[97].Reg_Val = 0x00 ;
 702
 703         state->TunerRegs[98].Reg_Num = 161 ;
 704         state->TunerRegs[98].Reg_Val = 0x00 ;
 705
 706         state->TunerRegs[99].Reg_Num = 162 ;
 707         state->TunerRegs[99].Reg_Val = 0x40 ;
 708
 709         state->TunerRegs[100].Reg_Num = 166 ;
 710         state->TunerRegs[100].Reg_Val = 0xAE ;
 711
 712         state->TunerRegs[101].Reg_Num = 167 ;
 713         state->TunerRegs[101].Reg_Val = 0x1B ;
 714
 715         state->TunerRegs[102].Reg_Num = 168 ;
 716         state->TunerRegs[102].Reg_Val = 0xF2 ;
 717
 718         state->TunerRegs[103].Reg_Num = 195 ;
 719         state->TunerRegs[103].Reg_Val = 0x00 ;
 720
 721         return 0 ;
 722 }
 723
 724 static u16 MXL5005_ControlInit(struct dvb_frontend *fe)
 725 {
 726         struct mxl5005s_state *state = fe->tuner_priv;
 727         state->Init_Ctrl_Num = INITCTRL_NUM;
 728
 729         state->Init_Ctrl[0].Ctrl_Num = DN_IQTN_AMP_CUT ;
 730         state->Init_Ctrl[0].size = 1 ;
 731         state->Init_Ctrl[0].addr[0] = 73;
 732         state->Init_Ctrl[0].bit[0] = 7;
 733         state->Init_Ctrl[0].val[0] = 0;
 734
 735         state->Init_Ctrl[1].Ctrl_Num = BB_MODE ;
 736         state->Init_Ctrl[1].size = 1 ;
 737         state->Init_Ctrl[1].addr[0] = 53;
 738         state->Init_Ctrl[1].bit[0] = 2;
 739         state->Init_Ctrl[1].val[0] = 1;
 740
 741         state->Init_Ctrl[2].Ctrl_Num = BB_BUF ;
 742         state->Init_Ctrl[2].size = 2 ;
 743         state->Init_Ctrl[2].addr[0] = 53;
 744         state->Init_Ctrl[2].bit[0] = 1;
 745         state->Init_Ctrl[2].val[0] = 0;
 746         state->Init_Ctrl[2].addr[1] = 57;
 747         state->Init_Ctrl[2].bit[1] = 0;
 748         state->Init_Ctrl[2].val[1] = 1;
 749
 750         state->Init_Ctrl[3].Ctrl_Num = BB_BUF_OA ;
 751         state->Init_Ctrl[3].size = 1 ;
 752         state->Init_Ctrl[3].addr[0] = 53;
 753         state->Init_Ctrl[3].bit[0] = 0;
 754         state->Init_Ctrl[3].val[0] = 0;
 755
 756         state->Init_Ctrl[4].Ctrl_Num = BB_ALPF_BANDSELECT ;
 757         state->Init_Ctrl[4].size = 3 ;
 758         state->Init_Ctrl[4].addr[0] = 53;
 759         state->Init_Ctrl[4].bit[0] = 5;
 760         state->Init_Ctrl[4].val[0] = 0;
 761         state->Init_Ctrl[4].addr[1] = 53;
 762         state->Init_Ctrl[4].bit[1] = 6;
 763         state->Init_Ctrl[4].val[1] = 0;
 764         state->Init_Ctrl[4].addr[2] = 53;
 765         state->Init_Ctrl[4].bit[2] = 7;
 766         state->Init_Ctrl[4].val[2] = 1;
 767
 768         state->Init_Ctrl[5].Ctrl_Num = BB_IQSWAP ;
 769         state->Init_Ctrl[5].size = 1 ;
 770         state->Init_Ctrl[5].addr[0] = 59;
 771         state->Init_Ctrl[5].bit[0] = 0;
 772         state->Init_Ctrl[5].val[0] = 0;
 773
 774         state->Init_Ctrl[6].Ctrl_Num = BB_DLPF_BANDSEL ;
 775         state->Init_Ctrl[6].size = 2 ;
 776         state->Init_Ctrl[6].addr[0] = 53;
 777         state->Init_Ctrl[6].bit[0] = 3;
 778         state->Init_Ctrl[6].val[0] = 0;
 779         state->Init_Ctrl[6].addr[1] = 53;
 780         state->Init_Ctrl[6].bit[1] = 4;
 781         state->Init_Ctrl[6].val[1] = 1;
 782
 783         state->Init_Ctrl[7].Ctrl_Num = RFSYN_CHP_GAIN ;
 784         state->Init_Ctrl[7].size = 4 ;
 785         state->Init_Ctrl[7].addr[0] = 22;
 786         state->Init_Ctrl[7].bit[0] = 4;
 787         state->Init_Ctrl[7].val[0] = 0;
 788         state->Init_Ctrl[7].addr[1] = 22;
 789         state->Init_Ctrl[7].bit[1] = 5;
 790         state->Init_Ctrl[7].val[1] = 1;
 791         state->Init_Ctrl[7].addr[2] = 22;
 792         state->Init_Ctrl[7].bit[2] = 6;
 793         state->Init_Ctrl[7].val[2] = 1;
 794         state->Init_Ctrl[7].addr[3] = 22;
 795         state->Init_Ctrl[7].bit[3] = 7;
 796         state->Init_Ctrl[7].val[3] = 0;
 797
 798         state->Init_Ctrl[8].Ctrl_Num = RFSYN_EN_CHP_HIGAIN ;
 799         state->Init_Ctrl[8].size = 1 ;
 800         state->Init_Ctrl[8].addr[0] = 22;
 801         state->Init_Ctrl[8].bit[0] = 2;
 802         state->Init_Ctrl[8].val[0] = 0;
 803
 804         state->Init_Ctrl[9].Ctrl_Num = AGC_IF ;
 805         state->Init_Ctrl[9].size = 4 ;
 806         state->Init_Ctrl[9].addr[0] = 76;
 807         state->Init_Ctrl[9].bit[0] = 0;
 808         state->Init_Ctrl[9].val[0] = 1;
 809         state->Init_Ctrl[9].addr[1] = 76;
 810         state->Init_Ctrl[9].bit[1] = 1;
 811         state->Init_Ctrl[9].val[1] = 1;
 812         state->Init_Ctrl[9].addr[2] = 76;
 813         state->Init_Ctrl[9].bit[2] = 2;
 814         state->Init_Ctrl[9].val[2] = 0;
 815         state->Init_Ctrl[9].addr[3] = 76;
 816         state->Init_Ctrl[9].bit[3] = 3;
 817         state->Init_Ctrl[9].val[3] = 1;
 818
 819         state->Init_Ctrl[10].Ctrl_Num = AGC_RF ;
 820         state->Init_Ctrl[10].size = 4 ;
 821         state->Init_Ctrl[10].addr[0] = 76;
 822         state->Init_Ctrl[10].bit[0] = 4;
 823         state->Init_Ctrl[10].val[0] = 1;
 824         state->Init_Ctrl[10].addr[1] = 76;
 825         state->Init_Ctrl[10].bit[1] = 5;
 826         state->Init_Ctrl[10].val[1] = 1;
 827         state->Init_Ctrl[10].addr[2] = 76;
 828         state->Init_Ctrl[10].bit[2] = 6;
 829         state->Init_Ctrl[10].val[2] = 0;
 830         state->Init_Ctrl[10].addr[3] = 76;
 831         state->Init_Ctrl[10].bit[3] = 7;
 832         state->Init_Ctrl[10].val[3] = 1;
 833
 834         state->Init_Ctrl[11].Ctrl_Num = IF_DIVVAL ;
 835         state->Init_Ctrl[11].size = 5 ;
 836         state->Init_Ctrl[11].addr[0] = 43;
 837         state->Init_Ctrl[11].bit[0] = 3;
 838         state->Init_Ctrl[11].val[0] = 0;
 839         state->Init_Ctrl[11].addr[1] = 43;
 840         state->Init_Ctrl[11].bit[1] = 4;
 841         state->Init_Ctrl[11].val[1] = 0;
 842         state->Init_Ctrl[11].addr[2] = 43;
 843         state->Init_Ctrl[11].bit[2] = 5;
 844         state->Init_Ctrl[11].val[2] = 0;
 845         state->Init_Ctrl[11].addr[3] = 43;
 846         state->Init_Ctrl[11].bit[3] = 6;
 847         state->Init_Ctrl[11].val[3] = 1;
 848         state->Init_Ctrl[11].addr[4] = 43;
 849         state->Init_Ctrl[11].bit[4] = 7;
 850         state->Init_Ctrl[11].val[4] = 0;
 851
 852         state->Init_Ctrl[12].Ctrl_Num = IF_VCO_BIAS ;
 853         state->Init_Ctrl[12].size = 6 ;
 854         state->Init_Ctrl[12].addr[0] = 44;
 855         state->Init_Ctrl[12].bit[0] = 2;
 856         state->Init_Ctrl[12].val[0] = 0;
 857         state->Init_Ctrl[12].addr[1] = 44;
 858         state->Init_Ctrl[12].bit[1] = 3;
 859         state->Init_Ctrl[12].val[1] = 0;
 860         state->Init_Ctrl[12].addr[2] = 44;
 861         state->Init_Ctrl[12].bit[2] = 4;
 862         state->Init_Ctrl[12].val[2] = 0;
 863         state->Init_Ctrl[12].addr[3] = 44;
 864         state->Init_Ctrl[12].bit[3] = 5;
 865         state->Init_Ctrl[12].val[3] = 1;
 866         state->Init_Ctrl[12].addr[4] = 44;
 867         state->Init_Ctrl[12].bit[4] = 6;
 868         state->Init_Ctrl[12].val[4] = 0;
 869         state->Init_Ctrl[12].addr[5] = 44;
 870         state->Init_Ctrl[12].bit[5] = 7;
 871         state->Init_Ctrl[12].val[5] = 0;
 872
 873         state->Init_Ctrl[13].Ctrl_Num = CHCAL_INT_MOD_IF ;
 874         state->Init_Ctrl[13].size = 7 ;
 875         state->Init_Ctrl[13].addr[0] = 11;
 876         state->Init_Ctrl[13].bit[0] = 0;
 877         state->Init_Ctrl[13].val[0] = 1;
 878         state->Init_Ctrl[13].addr[1] = 11;
 879         state->Init_Ctrl[13].bit[1] = 1;
 880         state->Init_Ctrl[13].val[1] = 0;
 881         state->Init_Ctrl[13].addr[2] = 11;
 882         state->Init_Ctrl[13].bit[2] = 2;
 883         state->Init_Ctrl[13].val[2] = 0;
 884         state->Init_Ctrl[13].addr[3] = 11;
 885         state->Init_Ctrl[13].bit[3] = 3;
 886         state->Init_Ctrl[13].val[3] = 1;
 887         state->Init_Ctrl[13].addr[4] = 11;
 888         state->Init_Ctrl[13].bit[4] = 4;
 889         state->Init_Ctrl[13].val[4] = 1;
 890         state->Init_Ctrl[13].addr[5] = 11;
 891         state->Init_Ctrl[13].bit[5] = 5;
 892         state->Init_Ctrl[13].val[5] = 0;
 893         state->Init_Ctrl[13].addr[6] = 11;
 894         state->Init_Ctrl[13].bit[6] = 6;
 895         state->Init_Ctrl[13].val[6] = 0;
 896
 897         state->Init_Ctrl[14].Ctrl_Num = CHCAL_FRAC_MOD_IF ;
 898         state->Init_Ctrl[14].size = 16 ;
 899         state->Init_Ctrl[14].addr[0] = 13;
 900         state->Init_Ctrl[14].bit[0] = 0;
 901         state->Init_Ctrl[14].val[0] = 0;
 902         state->Init_Ctrl[14].addr[1] = 13;
 903         state->Init_Ctrl[14].bit[1] = 1;
 904         state->Init_Ctrl[14].val[1] = 0;
 905         state->Init_Ctrl[14].addr[2] = 13;
 906         state->Init_Ctrl[14].bit[2] = 2;
 907         state->Init_Ctrl[14].val[2] = 0;
 908         state->Init_Ctrl[14].addr[3] = 13;
 909         state->Init_Ctrl[14].bit[3] = 3;
 910         state->Init_Ctrl[14].val[3] = 0;
 911         state->Init_Ctrl[14].addr[4] = 13;
 912         state->Init_Ctrl[14].bit[4] = 4;
 913         state->Init_Ctrl[14].val[4] = 0;
 914         state->Init_Ctrl[14].addr[5] = 13;
 915         state->Init_Ctrl[14].bit[5] = 5;
 916         state->Init_Ctrl[14].val[5] = 0;
 917         state->Init_Ctrl[14].addr[6] = 13;
 918         state->Init_Ctrl[14].bit[6] = 6;
 919         state->Init_Ctrl[14].val[6] = 0;
 920         state->Init_Ctrl[14].addr[7] = 13;
 921         state->Init_Ctrl[14].bit[7] = 7;
 922         state->Init_Ctrl[14].val[7] = 0;
 923         state->Init_Ctrl[14].addr[8] = 12;
 924         state->Init_Ctrl[14].bit[8] = 0;
 925         state->Init_Ctrl[14].val[8] = 0;
 926         state->Init_Ctrl[14].addr[9] = 12;
 927         state->Init_Ctrl[14].bit[9] = 1;
 928         state->Init_Ctrl[14].val[9] = 0;
 929         state->Init_Ctrl[14].addr[10] = 12;
 930         state->Init_Ctrl[14].bit[10] = 2;
 931         state->Init_Ctrl[14].val[10] = 0;
 932         state->Init_Ctrl[14].addr[11] = 12;
 933         state->Init_Ctrl[14].bit[11] = 3;
 934         state->Init_Ctrl[14].val[11] = 0;
 935         state->Init_Ctrl[14].addr[12] = 12;
 936         state->Init_Ctrl[14].bit[12] = 4;
 937         state->Init_Ctrl[14].val[12] = 0;
 938         state->Init_Ctrl[14].addr[13] = 12;
 939         state->Init_Ctrl[14].bit[13] = 5;
 940         state->Init_Ctrl[14].val[13] = 1;
 941         state->Init_Ctrl[14].addr[14] = 12;
 942         state->Init_Ctrl[14].bit[14] = 6;
 943         state->Init_Ctrl[14].val[14] = 1;
 944         state->Init_Ctrl[14].addr[15] = 12;
 945         state->Init_Ctrl[14].bit[15] = 7;
 946         state->Init_Ctrl[14].val[15] = 0;
 947
 948         state->Init_Ctrl[15].Ctrl_Num = DRV_RES_SEL ;
 949         state->Init_Ctrl[15].size = 3 ;
 950         state->Init_Ctrl[15].addr[0] = 147;
 951         state->Init_Ctrl[15].bit[0] = 2;
 952         state->Init_Ctrl[15].val[0] = 0;
 953         state->Init_Ctrl[15].addr[1] = 147;
 954         state->Init_Ctrl[15].bit[1] = 3;
 955         state->Init_Ctrl[15].val[1] = 1;
 956         state->Init_Ctrl[15].addr[2] = 147;
 957         state->Init_Ctrl[15].bit[2] = 4;
 958         state->Init_Ctrl[15].val[2] = 1;
 959
 960         state->Init_Ctrl[16].Ctrl_Num = I_DRIVER ;
 961         state->Init_Ctrl[16].size = 2 ;
 962         state->Init_Ctrl[16].addr[0] = 147;
 963         state->Init_Ctrl[16].bit[0] = 0;
 964         state->Init_Ctrl[16].val[0] = 0;
 965         state->Init_Ctrl[16].addr[1] = 147;
 966         state->Init_Ctrl[16].bit[1] = 1;
 967         state->Init_Ctrl[16].val[1] = 1;
 968
 969         state->Init_Ctrl[17].Ctrl_Num = EN_AAF ;
 970         state->Init_Ctrl[17].size = 1 ;
 971         state->Init_Ctrl[17].addr[0] = 147;
 972         state->Init_Ctrl[17].bit[0] = 7;
 973         state->Init_Ctrl[17].val[0] = 0;
 974
 975         state->Init_Ctrl[18].Ctrl_Num = EN_3P ;
 976         state->Init_Ctrl[18].size = 1 ;
 977         state->Init_Ctrl[18].addr[0] = 147;
 978         state->Init_Ctrl[18].bit[0] = 6;
 979         state->Init_Ctrl[18].val[0] = 0;
 980
 981         state->Init_Ctrl[19].Ctrl_Num = EN_AUX_3P ;
 982         state->Init_Ctrl[19].size = 1 ;
 983         state->Init_Ctrl[19].addr[0] = 156;
 984         state->Init_Ctrl[19].bit[0] = 0;
 985         state->Init_Ctrl[19].val[0] = 0;
 986
 987         state->Init_Ctrl[20].Ctrl_Num = SEL_AAF_BAND ;
 988         state->Init_Ctrl[20].size = 1 ;
 989         state->Init_Ctrl[20].addr[0] = 147;
 990         state->Init_Ctrl[20].bit[0] = 5;
 991         state->Init_Ctrl[20].val[0] = 0;
 992
 993         state->Init_Ctrl[21].Ctrl_Num = SEQ_ENCLK16_CLK_OUT ;
 994         state->Init_Ctrl[21].size = 1 ;
 995         state->Init_Ctrl[21].addr[0] = 137;
 996         state->Init_Ctrl[21].bit[0] = 4;
 997         state->Init_Ctrl[21].val[0] = 0;
 998
 999         state->Init_Ctrl[22].Ctrl_Num = SEQ_SEL4_16B ;
1000         state->Init_Ctrl[22].size = 1 ;
1001         state->Init_Ctrl[22].addr[0] = 137;
1002         state->Init_Ctrl[22].bit[0] = 7;
1003         state->Init_Ctrl[22].val[0] = 0;
1004
1005         state->Init_Ctrl[23].Ctrl_Num = XTAL_CAPSELECT ;
1006         state->Init_Ctrl[23].size = 1 ;
1007         state->Init_Ctrl[23].addr[0] = 91;
1008         state->Init_Ctrl[23].bit[0] = 5;
1009         state->Init_Ctrl[23].val[0] = 1;
1010
1011         state->Init_Ctrl[24].Ctrl_Num = IF_SEL_DBL ;
1012         state->Init_Ctrl[24].size = 1 ;
1013         state->Init_Ctrl[24].addr[0] = 43;
1014         state->Init_Ctrl[24].bit[0] = 0;
1015         state->Init_Ctrl[24].val[0] = 1;
1016
1017         state->Init_Ctrl[25].Ctrl_Num = RFSYN_R_DIV ;
1018         state->Init_Ctrl[25].size = 2 ;
1019         state->Init_Ctrl[25].addr[0] = 22;
1020         state->Init_Ctrl[25].bit[0] = 0;
1021         state->Init_Ctrl[25].val[0] = 1;
1022         state->Init_Ctrl[25].addr[1] = 22;
1023         state->Init_Ctrl[25].bit[1] = 1;
1024         state->Init_Ctrl[25].val[1] = 1;
1025
1026         state->Init_Ctrl[26].Ctrl_Num = SEQ_EXTSYNTHCALIF ;
1027         state->Init_Ctrl[26].size = 1 ;
1028         state->Init_Ctrl[26].addr[0] = 134;
1029         state->Init_Ctrl[26].bit[0] = 2;
1030         state->Init_Ctrl[26].val[0] = 0;
1031
1032         state->Init_Ctrl[27].Ctrl_Num = SEQ_EXTDCCAL ;
1033         state->Init_Ctrl[27].size = 1 ;
1034         state->Init_Ctrl[27].addr[0] = 137;
1035         state->Init_Ctrl[27].bit[0] = 3;
1036         state->Init_Ctrl[27].val[0] = 0;
1037
1038         state->Init_Ctrl[28].Ctrl_Num = AGC_EN_RSSI ;
1039         state->Init_Ctrl[28].size = 1 ;
1040         state->Init_Ctrl[28].addr[0] = 77;
1041         state->Init_Ctrl[28].bit[0] = 7;
1042         state->Init_Ctrl[28].val[0] = 0;
1043
1044         state->Init_Ctrl[29].Ctrl_Num = RFA_ENCLKRFAGC ;
1045         state->Init_Ctrl[29].size = 1 ;
1046         state->Init_Ctrl[29].addr[0] = 166;
1047         state->Init_Ctrl[29].bit[0] = 7;
1048         state->Init_Ctrl[29].val[0] = 1;
1049
1050         state->Init_Ctrl[30].Ctrl_Num = RFA_RSSI_REFH ;
1051         state->Init_Ctrl[30].size = 3 ;
1052         state->Init_Ctrl[30].addr[0] = 166;
1053         state->Init_Ctrl[30].bit[0] = 0;
1054         state->Init_Ctrl[30].val[0] = 0;
1055         state->Init_Ctrl[30].addr[1] = 166;
1056         state->Init_Ctrl[30].bit[1] = 1;
1057         state->Init_Ctrl[30].val[1] = 1;
1058         state->Init_Ctrl[30].addr[2] = 166;
1059         state->Init_Ctrl[30].bit[2] = 2;
1060         state->Init_Ctrl[30].val[2] = 1;
1061
1062         state->Init_Ctrl[31].Ctrl_Num = RFA_RSSI_REF ;
1063         state->Init_Ctrl[31].size = 3 ;
1064         state->Init_Ctrl[31].addr[0] = 166;
1065         state->Init_Ctrl[31].bit[0] = 3;
1066         state->Init_Ctrl[31].val[0] = 1;
1067         state->Init_Ctrl[31].addr[1] = 166;
1068         state->Init_Ctrl[31].bit[1] = 4;
1069         state->Init_Ctrl[31].val[1] = 0;
1070         state->Init_Ctrl[31].addr[2] = 166;
1071         state->Init_Ctrl[31].bit[2] = 5;
1072         state->Init_Ctrl[31].val[2] = 1;
1073
1074         state->Init_Ctrl[32].Ctrl_Num = RFA_RSSI_REFL ;
1075         state->Init_Ctrl[32].size = 3 ;
1076         state->Init_Ctrl[32].addr[0] = 167;
1077         state->Init_Ctrl[32].bit[0] = 0;
1078         state->Init_Ctrl[32].val[0] = 1;
1079         state->Init_Ctrl[32].addr[1] = 167;
1080         state->Init_Ctrl[32].bit[1] = 1;
1081         state->Init_Ctrl[32].val[1] = 1;
1082         state->Init_Ctrl[32].addr[2] = 167;
1083         state->Init_Ctrl[32].bit[2] = 2;
1084         state->Init_Ctrl[32].val[2] = 0;
1085
1086         state->Init_Ctrl[33].Ctrl_Num = RFA_FLR ;
1087         state->Init_Ctrl[33].size = 4 ;
1088         state->Init_Ctrl[33].addr[0] = 168;
1089         state->Init_Ctrl[33].bit[0] = 0;
1090         state->Init_Ctrl[33].val[0] = 0;
1091         state->Init_Ctrl[33].addr[1] = 168;
1092         state->Init_Ctrl[33].bit[1] = 1;
1093         state->Init_Ctrl[33].val[1] = 1;
1094         state->Init_Ctrl[33].addr[2] = 168;
1095         state->Init_Ctrl[33].bit[2] = 2;
1096         state->Init_Ctrl[33].val[2] = 0;
1097         state->Init_Ctrl[33].addr[3] = 168;
1098         state->Init_Ctrl[33].bit[3] = 3;
1099         state->Init_Ctrl[33].val[3] = 0;
1100
1101         state->Init_Ctrl[34].Ctrl_Num = RFA_CEIL ;
1102         state->Init_Ctrl[34].size = 4 ;
1103         state->Init_Ctrl[34].addr[0] = 168;
1104         state->Init_Ctrl[34].bit[0] = 4;
1105         state->Init_Ctrl[34].val[0] = 1;
1106         state->Init_Ctrl[34].addr[1] = 168;
1107         state->Init_Ctrl[34].bit[1] = 5;
1108         state->Init_Ctrl[34].val[1] = 1;
1109         state->Init_Ctrl[34].addr[2] = 168;
1110         state->Init_Ctrl[34].bit[2] = 6;
1111         state->Init_Ctrl[34].val[2] = 1;
1112         state->Init_Ctrl[34].addr[3] = 168;
1113         state->Init_Ctrl[34].bit[3] = 7;
1114         state->Init_Ctrl[34].val[3] = 1;
1115
1116         state->Init_Ctrl[35].Ctrl_Num = SEQ_EXTIQFSMPULSE ;
1117         state->Init_Ctrl[35].size = 1 ;
1118         state->Init_Ctrl[35].addr[0] = 135;
1119         state->Init_Ctrl[35].bit[0] = 0;
1120         state->Init_Ctrl[35].val[0] = 0;
1121
1122         state->Init_Ctrl[36].Ctrl_Num = OVERRIDE_1 ;
1123         state->Init_Ctrl[36].size = 1 ;
1124         state->Init_Ctrl[36].addr[0] = 56;
1125         state->Init_Ctrl[36].bit[0] = 3;
1126         state->Init_Ctrl[36].val[0] = 0;
1127
1128         state->Init_Ctrl[37].Ctrl_Num = BB_INITSTATE_DLPF_TUNE ;
1129         state->Init_Ctrl[37].size = 7 ;
1130         state->Init_Ctrl[37].addr[0] = 59;
1131         state->Init_Ctrl[37].bit[0] = 1;
1132         state->Init_Ctrl[37].val[0] = 0;
1133         state->Init_Ctrl[37].addr[1] = 59;
1134         state->Init_Ctrl[37].bit[1] = 2;
1135         state->Init_Ctrl[37].val[1] = 0;
1136         state->Init_Ctrl[37].addr[2] = 59;
1137         state->Init_Ctrl[37].bit[2] = 3;
1138         state->Init_Ctrl[37].val[2] = 0;
1139         state->Init_Ctrl[37].addr[3] = 59;
1140         state->Init_Ctrl[37].bit[3] = 4;
1141         state->Init_Ctrl[37].val[3] = 0;
1142         state->Init_Ctrl[37].addr[4] = 59;
1143         state->Init_Ctrl[37].bit[4] = 5;
1144         state->Init_Ctrl[37].val[4] = 0;
1145         state->Init_Ctrl[37].addr[5] = 59;
1146         state->Init_Ctrl[37].bit[5] = 6;
1147         state->Init_Ctrl[37].val[5] = 0;
1148         state->Init_Ctrl[37].addr[6] = 59;
1149         state->Init_Ctrl[37].bit[6] = 7;
1150         state->Init_Ctrl[37].val[6] = 0;
1151
1152         state->Init_Ctrl[38].Ctrl_Num = TG_R_DIV ;
1153         state->Init_Ctrl[38].size = 6 ;
1154         state->Init_Ctrl[38].addr[0] = 32;
1155         state->Init_Ctrl[38].bit[0] = 2;
1156         state->Init_Ctrl[38].val[0] = 0;
1157         state->Init_Ctrl[38].addr[1] = 32;
1158         state->Init_Ctrl[38].bit[1] = 3;
1159         state->Init_Ctrl[38].val[1] = 0;
1160         state->Init_Ctrl[38].addr[2] = 32;
1161         state->Init_Ctrl[38].bit[2] = 4;
1162         state->Init_Ctrl[38].val[2] = 0;
1163         state->Init_Ctrl[38].addr[3] = 32;
1164         state->Init_Ctrl[38].bit[3] = 5;
1165         state->Init_Ctrl[38].val[3] = 0;
1166         state->Init_Ctrl[38].addr[4] = 32;
1167         state->Init_Ctrl[38].bit[4] = 6;
1168         state->Init_Ctrl[38].val[4] = 1;
1169         state->Init_Ctrl[38].addr[5] = 32;
1170         state->Init_Ctrl[38].bit[5] = 7;
1171         state->Init_Ctrl[38].val[5] = 0;
1172
1173         state->Init_Ctrl[39].Ctrl_Num = EN_CHP_LIN_B ;
1174         state->Init_Ctrl[39].size = 1 ;
1175         state->Init_Ctrl[39].addr[0] = 25;
1176         state->Init_Ctrl[39].bit[0] = 3;
1177         state->Init_Ctrl[39].val[0] = 1;
1178
1179
1180         state->CH_Ctrl_Num = CHCTRL_NUM ;
1181
1182         state->CH_Ctrl[0].Ctrl_Num = DN_POLY ;
1183         state->CH_Ctrl[0].size = 2 ;
1184         state->CH_Ctrl[0].addr[0] = 68;
1185         state->CH_Ctrl[0].bit[0] = 6;
1186         state->CH_Ctrl[0].val[0] = 1;
1187         state->CH_Ctrl[0].addr[1] = 68;
1188         state->CH_Ctrl[0].bit[1] = 7;
1189         state->CH_Ctrl[0].val[1] = 1;
1190
1191         state->CH_Ctrl[1].Ctrl_Num = DN_RFGAIN ;
1192         state->CH_Ctrl[1].size = 2 ;
1193         state->CH_Ctrl[1].addr[0] = 70;
1194         state->CH_Ctrl[1].bit[0] = 6;
1195         state->CH_Ctrl[1].val[0] = 1;
1196         state->CH_Ctrl[1].addr[1] = 70;
1197         state->CH_Ctrl[1].bit[1] = 7;
1198         state->CH_Ctrl[1].val[1] = 0;
1199
1200         state->CH_Ctrl[2].Ctrl_Num = DN_CAP_RFLPF ;
1201         state->CH_Ctrl[2].size = 9 ;
1202         state->CH_Ctrl[2].addr[0] = 69;
1203         state->CH_Ctrl[2].bit[0] = 5;
1204         state->CH_Ctrl[2].val[0] = 0;
1205         state->CH_Ctrl[2].addr[1] = 69;
1206         state->CH_Ctrl[2].bit[1] = 6;
1207         state->CH_Ctrl[2].val[1] = 0;
1208         state->CH_Ctrl[2].addr[2] = 69;
1209         state->CH_Ctrl[2].bit[2] = 7;
1210         state->CH_Ctrl[2].val[2] = 0;
1211         state->CH_Ctrl[2].addr[3] = 68;
1212         state->CH_Ctrl[2].bit[3] = 0;
1213         state->CH_Ctrl[2].val[3] = 0;
1214         state->CH_Ctrl[2].addr[4] = 68;
1215         state->CH_Ctrl[2].bit[4] = 1;
1216         state->CH_Ctrl[2].val[4] = 0;
1217         state->CH_Ctrl[2].addr[5] = 68;
1218         state->CH_Ctrl[2].bit[5] = 2;
1219         state->CH_Ctrl[2].val[5] = 0;
1220         state->CH_Ctrl[2].addr[6] = 68;
1221         state->CH_Ctrl[2].bit[6] = 3;
1222         state->CH_Ctrl[2].val[6] = 0;
1223         state->CH_Ctrl[2].addr[7] = 68;
1224         state->CH_Ctrl[2].bit[7] = 4;
1225         state->CH_Ctrl[2].val[7] = 0;
1226         state->CH_Ctrl[2].addr[8] = 68;
1227         state->CH_Ctrl[2].bit[8] = 5;
1228         state->CH_Ctrl[2].val[8] = 0;
1229
1230         state->CH_Ctrl[3].Ctrl_Num = DN_EN_VHFUHFBAR ;
1231         state->CH_Ctrl[3].size = 1 ;
1232         state->CH_Ctrl[3].addr[0] = 70;
1233         state->CH_Ctrl[3].bit[0] = 5;
1234         state->CH_Ctrl[3].val[0] = 0;
1235
1236         state->CH_Ctrl[4].Ctrl_Num = DN_GAIN_ADJUST ;
1237         state->CH_Ctrl[4].size = 3 ;
1238         state->CH_Ctrl[4].addr[0] = 73;
1239         state->CH_Ctrl[4].bit[0] = 4;
1240         state->CH_Ctrl[4].val[0] = 0;
1241         state->CH_Ctrl[4].addr[1] = 73;
1242         state->CH_Ctrl[4].bit[1] = 5;
1243         state->CH_Ctrl[4].val[1] = 1;
1244         state->CH_Ctrl[4].addr[2] = 73;
1245         state->CH_Ctrl[4].bit[2] = 6;
1246         state->CH_Ctrl[4].val[2] = 0;
1247
1248         state->CH_Ctrl[5].Ctrl_Num = DN_IQTNBUF_AMP ;
1249         state->CH_Ctrl[5].size = 4 ;
1250         state->CH_Ctrl[5].addr[0] = 70;
1251         state->CH_Ctrl[5].bit[0] = 0;
1252         state->CH_Ctrl[5].val[0] = 0;
1253         state->CH_Ctrl[5].addr[1] = 70;
1254         state->CH_Ctrl[5].bit[1] = 1;
1255         state->CH_Ctrl[5].val[1] = 0;
1256         state->CH_Ctrl[5].addr[2] = 70;
1257         state->CH_Ctrl[5].bit[2] = 2;
1258         state->CH_Ctrl[5].val[2] = 0;
1259         state->CH_Ctrl[5].addr[3] = 70;
1260         state->CH_Ctrl[5].bit[3] = 3;
1261         state->CH_Ctrl[5].val[3] = 0;
1262
1263         state->CH_Ctrl[6].Ctrl_Num = DN_IQTNGNBFBIAS_BST ;
1264         state->CH_Ctrl[6].size = 1 ;
1265         state->CH_Ctrl[6].addr[0] = 70;
1266         state->CH_Ctrl[6].bit[0] = 4;
1267         state->CH_Ctrl[6].val[0] = 1;
1268
1269         state->CH_Ctrl[7].Ctrl_Num = RFSYN_EN_OUTMUX ;
1270         state->CH_Ctrl[7].size = 1 ;
1271         state->CH_Ctrl[7].addr[0] = 111;
1272         state->CH_Ctrl[7].bit[0] = 4;
1273         state->CH_Ctrl[7].val[0] = 0;
1274
1275         state->CH_Ctrl[8].Ctrl_Num = RFSYN_SEL_VCO_OUT ;
1276         state->CH_Ctrl[8].size = 1 ;
1277         state->CH_Ctrl[8].addr[0] = 111;
1278         state->CH_Ctrl[8].bit[0] = 7;
1279         state->CH_Ctrl[8].val[0] = 1;
1280
1281         state->CH_Ctrl[9].Ctrl_Num = RFSYN_SEL_VCO_HI ;
1282         state->CH_Ctrl[9].size = 1 ;
1283         state->CH_Ctrl[9].addr[0] = 111;
1284         state->CH_Ctrl[9].bit[0] = 6;
1285         state->CH_Ctrl[9].val[0] = 1;
1286
1287         state->CH_Ctrl[10].Ctrl_Num = RFSYN_SEL_DIVM ;
1288         state->CH_Ctrl[10].size = 1 ;
1289         state->CH_Ctrl[10].addr[0] = 111;
1290         state->CH_Ctrl[10].bit[0] = 5;
1291         state->CH_Ctrl[10].val[0] = 0;
1292
1293         state->CH_Ctrl[11].Ctrl_Num = RFSYN_RF_DIV_BIAS ;
1294         state->CH_Ctrl[11].size = 2 ;
1295         state->CH_Ctrl[11].addr[0] = 110;
1296         state->CH_Ctrl[11].bit[0] = 0;
1297         state->CH_Ctrl[11].val[0] = 1;
1298         state->CH_Ctrl[11].addr[1] = 110;
1299         state->CH_Ctrl[11].bit[1] = 1;
1300         state->CH_Ctrl[11].val[1] = 0;
1301
1302         state->CH_Ctrl[12].Ctrl_Num = DN_SEL_FREQ ;
1303         state->CH_Ctrl[12].size = 3 ;
1304         state->CH_Ctrl[12].addr[0] = 69;
1305         state->CH_Ctrl[12].bit[0] = 2;
1306         state->CH_Ctrl[12].val[0] = 0;
1307         state->CH_Ctrl[12].addr[1] = 69;
1308         state->CH_Ctrl[12].bit[1] = 3;
1309         state->CH_Ctrl[12].val[1] = 0;
1310         state->CH_Ctrl[12].addr[2] = 69;
1311         state->CH_Ctrl[12].bit[2] = 4;
1312         state->CH_Ctrl[12].val[2] = 0;
1313
1314         state->CH_Ctrl[13].Ctrl_Num = RFSYN_VCO_BIAS ;
1315         state->CH_Ctrl[13].size = 6 ;
1316         state->CH_Ctrl[13].addr[0] = 110;
1317         state->CH_Ctrl[13].bit[0] = 2;
1318         state->CH_Ctrl[13].val[0] = 0;
1319         state->CH_Ctrl[13].addr[1] = 110;
1320         state->CH_Ctrl[13].bit[1] = 3;
1321         state->CH_Ctrl[13].val[1] = 0;
1322         state->CH_Ctrl[13].addr[2] = 110;
1323         state->CH_Ctrl[13].bit[2] = 4;
1324         state->CH_Ctrl[13].val[2] = 0;
1325         state->CH_Ctrl[13].addr[3] = 110;
1326         state->CH_Ctrl[13].bit[3] = 5;
1327         state->CH_Ctrl[13].val[3] = 0;
1328         state->CH_Ctrl[13].addr[4] = 110;
1329         state->CH_Ctrl[13].bit[4] = 6;
1330         state->CH_Ctrl[13].val[4] = 0;
1331         state->CH_Ctrl[13].addr[5] = 110;
1332         state->CH_Ctrl[13].bit[5] = 7;
1333         state->CH_Ctrl[13].val[5] = 1;
1334
1335         state->CH_Ctrl[14].Ctrl_Num = CHCAL_INT_MOD_RF ;
1336         state->CH_Ctrl[14].size = 7 ;
1337         state->CH_Ctrl[14].addr[0] = 14;
1338         state->CH_Ctrl[14].bit[0] = 0;
1339         state->CH_Ctrl[14].val[0] = 0;
1340         state->CH_Ctrl[14].addr[1] = 14;
1341         state->CH_Ctrl[14].bit[1] = 1;
1342         state->CH_Ctrl[14].val[1] = 0;
1343         state->CH_Ctrl[14].addr[2] = 14;
1344         state->CH_Ctrl[14].bit[2] = 2;
1345         state->CH_Ctrl[14].val[2] = 0;
1346         state->CH_Ctrl[14].addr[3] = 14;
1347         state->CH_Ctrl[14].bit[3] = 3;
1348         state->CH_Ctrl[14].val[3] = 0;
1349         state->CH_Ctrl[14].addr[4] = 14;
1350         state->CH_Ctrl[14].bit[4] = 4;
1351         state->CH_Ctrl[14].val[4] = 0;
1352         state->CH_Ctrl[14].addr[5] = 14;
1353         state->CH_Ctrl[14].bit[5] = 5;
1354         state->CH_Ctrl[14].val[5] = 0;
1355         state->CH_Ctrl[14].addr[6] = 14;
1356         state->CH_Ctrl[14].bit[6] = 6;
1357         state->CH_Ctrl[14].val[6] = 0;
1358
1359         state->CH_Ctrl[15].Ctrl_Num = CHCAL_FRAC_MOD_RF ;
1360         state->CH_Ctrl[15].size = 18 ;
1361         state->CH_Ctrl[15].addr[0] = 17;
1362         state->CH_Ctrl[15].bit[0] = 6;
1363         state->CH_Ctrl[15].val[0] = 0;
1364         state->CH_Ctrl[15].addr[1] = 17;
1365         state->CH_Ctrl[15].bit[1] = 7;
1366         state->CH_Ctrl[15].val[1] = 0;
1367         state->CH_Ctrl[15].addr[2] = 16;
1368         state->CH_Ctrl[15].bit[2] = 0;
1369         state->CH_Ctrl[15].val[2] = 0;
1370         state->CH_Ctrl[15].addr[3] = 16;
1371         state->CH_Ctrl[15].bit[3] = 1;
1372         state->CH_Ctrl[15].val[3] = 0;
1373         state->CH_Ctrl[15].addr[4] = 16;
1374         state->CH_Ctrl[15].bit[4] = 2;
1375         state->CH_Ctrl[15].val[4] = 0;
1376         state->CH_Ctrl[15].addr[5] = 16;
1377         state->CH_Ctrl[15].bit[5] = 3;
1378         state->CH_Ctrl[15].val[5] = 0;
1379         state->CH_Ctrl[15].addr[6] = 16;
1380         state->CH_Ctrl[15].bit[6] = 4;
1381         state->CH_Ctrl[15].val[6] = 0;
1382         state->CH_Ctrl[15].addr[7] = 16;
1383         state->CH_Ctrl[15].bit[7] = 5;
1384         state->CH_Ctrl[15].val[7] = 0;
1385         state->CH_Ctrl[15].addr[8] = 16;
1386         state->CH_Ctrl[15].bit[8] = 6;
1387         state->CH_Ctrl[15].val[8] = 0;
1388         state->CH_Ctrl[15].addr[9] = 16;
1389         state->CH_Ctrl[15].bit[9] = 7;
1390         state->CH_Ctrl[15].val[9] = 0;
1391         state->CH_Ctrl[15].addr[10] = 15;
1392         state->CH_Ctrl[15].bit[10] = 0;
1393         state->CH_Ctrl[15].val[10] = 0;
1394         state->CH_Ctrl[15].addr[11] = 15;
1395         state->CH_Ctrl[15].bit[11] = 1;
1396         state->CH_Ctrl[15].val[11] = 0;
1397         state->CH_Ctrl[15].addr[12] = 15;
1398         state->CH_Ctrl[15].bit[12] = 2;
1399         state->CH_Ctrl[15].val[12] = 0;
1400         state->CH_Ctrl[15].addr[13] = 15;
1401         state->CH_Ctrl[15].bit[13] = 3;
1402         state->CH_Ctrl[15].val[13] = 0;
1403         state->CH_Ctrl[15].addr[14] = 15;
1404         state->CH_Ctrl[15].bit[14] = 4;
1405         state->CH_Ctrl[15].val[14] = 0;
1406         state->CH_Ctrl[15].addr[15] = 15;
1407         state->CH_Ctrl[15].bit[15] = 5;
1408         state->CH_Ctrl[15].val[15] = 0;
1409         state->CH_Ctrl[15].addr[16] = 15;
1410         state->CH_Ctrl[15].bit[16] = 6;
1411         state->CH_Ctrl[15].val[16] = 1;
1412         state->CH_Ctrl[15].addr[17] = 15;
1413         state->CH_Ctrl[15].bit[17] = 7;
1414         state->CH_Ctrl[15].val[17] = 1;
1415
1416         state->CH_Ctrl[16].Ctrl_Num = RFSYN_LPF_R ;
1417         state->CH_Ctrl[16].size = 5 ;
1418         state->CH_Ctrl[16].addr[0] = 112;
1419         state->CH_Ctrl[16].bit[0] = 0;
1420         state->CH_Ctrl[16].val[0] = 0;
1421         state->CH_Ctrl[16].addr[1] = 112;
1422         state->CH_Ctrl[16].bit[1] = 1;
1423         state->CH_Ctrl[16].val[1] = 0;
1424         state->CH_Ctrl[16].addr[2] = 112;
1425         state->CH_Ctrl[16].bit[2] = 2;
1426         state->CH_Ctrl[16].val[2] = 0;
1427         state->CH_Ctrl[16].addr[3] = 112;
1428         state->CH_Ctrl[16].bit[3] = 3;
1429         state->CH_Ctrl[16].val[3] = 0;
1430         state->CH_Ctrl[16].addr[4] = 112;
1431         state->CH_Ctrl[16].bit[4] = 4;
1432         state->CH_Ctrl[16].val[4] = 1;
1433
1434         state->CH_Ctrl[17].Ctrl_Num = CHCAL_EN_INT_RF ;
1435         state->CH_Ctrl[17].size = 1 ;
1436         state->CH_Ctrl[17].addr[0] = 14;
1437         state->CH_Ctrl[17].bit[0] = 7;
1438         state->CH_Ctrl[17].val[0] = 0;
1439
1440         state->CH_Ctrl[18].Ctrl_Num = TG_LO_DIVVAL ;
1441         state->CH_Ctrl[18].size = 4 ;
1442         state->CH_Ctrl[18].addr[0] = 107;
1443         state->CH_Ctrl[18].bit[0] = 3;
1444         state->CH_Ctrl[18].val[0] = 0;
1445         state->CH_Ctrl[18].addr[1] = 107;
1446         state->CH_Ctrl[18].bit[1] = 4;
1447         state->CH_Ctrl[18].val[1] = 0;
1448         state->CH_Ctrl[18].addr[2] = 107;
1449         state->CH_Ctrl[18].bit[2] = 5;
1450         state->CH_Ctrl[18].val[2] = 0;
1451         state->CH_Ctrl[18].addr[3] = 107;
1452         state->CH_Ctrl[18].bit[3] = 6;
1453         state->CH_Ctrl[18].val[3] = 0;
1454
1455         state->CH_Ctrl[19].Ctrl_Num = TG_LO_SELVAL ;
1456         state->CH_Ctrl[19].size = 3 ;
1457         state->CH_Ctrl[19].addr[0] = 107;
1458         state->CH_Ctrl[19].bit[0] = 7;
1459         state->CH_Ctrl[19].val[0] = 1;
1460         state->CH_Ctrl[19].addr[1] = 106;
1461         state->CH_Ctrl[19].bit[1] = 0;
1462         state->CH_Ctrl[19].val[1] = 1;
1463         state->CH_Ctrl[19].addr[2] = 106;
1464         state->CH_Ctrl[19].bit[2] = 1;
1465         state->CH_Ctrl[19].val[2] = 1;
1466
1467         state->CH_Ctrl[20].Ctrl_Num = TG_DIV_VAL ;
1468         state->CH_Ctrl[20].size = 11 ;
1469         state->CH_Ctrl[20].addr[0] = 109;
1470         state->CH_Ctrl[20].bit[0] = 2;
1471         state->CH_Ctrl[20].val[0] = 0;
1472         state->CH_Ctrl[20].addr[1] = 109;
1473         state->CH_Ctrl[20].bit[1] = 3;
1474         state->CH_Ctrl[20].val[1] = 0;
1475         state->CH_Ctrl[20].addr[2] = 109;
1476         state->CH_Ctrl[20].bit[2] = 4;
1477         state->CH_Ctrl[20].val[2] = 0;
1478         state->CH_Ctrl[20].addr[3] = 109;
1479         state->CH_Ctrl[20].bit[3] = 5;
1480         state->CH_Ctrl[20].val[3] = 0;
1481         state->CH_Ctrl[20].addr[4] = 109;
1482         state->CH_Ctrl[20].bit[4] = 6;
1483         state->CH_Ctrl[20].val[4] = 0;
1484         state->CH_Ctrl[20].addr[5] = 109;
1485         state->CH_Ctrl[20].bit[5] = 7;
1486         state->CH_Ctrl[20].val[5] = 0;
1487         state->CH_Ctrl[20].addr[6] = 108;
1488         state->CH_Ctrl[20].bit[6] = 0;
1489         state->CH_Ctrl[20].val[6] = 0;
1490         state->CH_Ctrl[20].addr[7] = 108;
1491         state->CH_Ctrl[20].bit[7] = 1;
1492         state->CH_Ctrl[20].val[7] = 0;
1493         state->CH_Ctrl[20].addr[8] = 108;
1494         state->CH_Ctrl[20].bit[8] = 2;
1495         state->CH_Ctrl[20].val[8] = 1;
1496         state->CH_Ctrl[20].addr[9] = 108;
1497         state->CH_Ctrl[20].bit[9] = 3;
1498         state->CH_Ctrl[20].val[9] = 1;
1499         state->CH_Ctrl[20].addr[10] = 108;
1500         state->CH_Ctrl[20].bit[10] = 4;
1501         state->CH_Ctrl[20].val[10] = 1;
1502
1503         state->CH_Ctrl[21].Ctrl_Num = TG_VCO_BIAS ;
1504         state->CH_Ctrl[21].size = 6 ;
1505         state->CH_Ctrl[21].addr[0] = 106;
1506         state->CH_Ctrl[21].bit[0] = 2;
1507         state->CH_Ctrl[21].val[0] = 0;
1508         state->CH_Ctrl[21].addr[1] = 106;
1509         state->CH_Ctrl[21].bit[1] = 3;
1510         state->CH_Ctrl[21].val[1] = 0;
1511         state->CH_Ctrl[21].addr[2] = 106;
1512         state->CH_Ctrl[21].bit[2] = 4;
1513         state->CH_Ctrl[21].val[2] = 0;
1514         state->CH_Ctrl[21].addr[3] = 106;
1515         state->CH_Ctrl[21].bit[3] = 5;
1516         state->CH_Ctrl[21].val[3] = 0;
1517         state->CH_Ctrl[21].addr[4] = 106;
1518         state->CH_Ctrl[21].bit[4] = 6;
1519         state->CH_Ctrl[21].val[4] = 0;
1520         state->CH_Ctrl[21].addr[5] = 106;
1521         state->CH_Ctrl[21].bit[5] = 7;
1522         state->CH_Ctrl[21].val[5] = 1;
1523
1524         state->CH_Ctrl[22].Ctrl_Num = SEQ_EXTPOWERUP ;
1525         state->CH_Ctrl[22].size = 1 ;
1526         state->CH_Ctrl[22].addr[0] = 138;
1527         state->CH_Ctrl[22].bit[0] = 4;
1528         state->CH_Ctrl[22].val[0] = 1;
1529
1530         state->CH_Ctrl[23].Ctrl_Num = OVERRIDE_2 ;
1531         state->CH_Ctrl[23].size = 1 ;
1532         state->CH_Ctrl[23].addr[0] = 17;
1533         state->CH_Ctrl[23].bit[0] = 5;
1534         state->CH_Ctrl[23].val[0] = 0;
1535
1536         state->CH_Ctrl[24].Ctrl_Num = OVERRIDE_3 ;
1537         state->CH_Ctrl[24].size = 1 ;
1538         state->CH_Ctrl[24].addr[0] = 111;
1539         state->CH_Ctrl[24].bit[0] = 3;
1540         state->CH_Ctrl[24].val[0] = 0;
1541
1542         state->CH_Ctrl[25].Ctrl_Num = OVERRIDE_4 ;
1543         state->CH_Ctrl[25].size = 1 ;
1544         state->CH_Ctrl[25].addr[0] = 112;
1545         state->CH_Ctrl[25].bit[0] = 7;
1546         state->CH_Ctrl[25].val[0] = 0;
1547
1548         state->CH_Ctrl[26].Ctrl_Num = SEQ_FSM_PULSE ;
1549         state->CH_Ctrl[26].size = 1 ;
1550         state->CH_Ctrl[26].addr[0] = 136;
1551         state->CH_Ctrl[26].bit[0] = 7;
1552         state->CH_Ctrl[26].val[0] = 0;
1553
1554         state->CH_Ctrl[27].Ctrl_Num = GPIO_4B ;
1555         state->CH_Ctrl[27].size = 1 ;
1556         state->CH_Ctrl[27].addr[0] = 149;
1557         state->CH_Ctrl[27].bit[0] = 7;
1558         state->CH_Ctrl[27].val[0] = 0;
1559
1560         state->CH_Ctrl[28].Ctrl_Num = GPIO_3B ;
1561         state->CH_Ctrl[28].size = 1 ;
1562         state->CH_Ctrl[28].addr[0] = 149;
1563         state->CH_Ctrl[28].bit[0] = 6;
1564         state->CH_Ctrl[28].val[0] = 0;
1565
1566         state->CH_Ctrl[29].Ctrl_Num = GPIO_4 ;
1567         state->CH_Ctrl[29].size = 1 ;
1568         state->CH_Ctrl[29].addr[0] = 149;
1569         state->CH_Ctrl[29].bit[0] = 5;
1570         state->CH_Ctrl[29].val[0] = 1;
1571
1572         state->CH_Ctrl[30].Ctrl_Num = GPIO_3 ;
1573         state->CH_Ctrl[30].size = 1 ;
1574         state->CH_Ctrl[30].addr[0] = 149;
1575         state->CH_Ctrl[30].bit[0] = 4;
1576         state->CH_Ctrl[30].val[0] = 1;
1577
1578         state->CH_Ctrl[31].Ctrl_Num = GPIO_1B ;
1579         state->CH_Ctrl[31].size = 1 ;
1580         state->CH_Ctrl[31].addr[0] = 149;
1581         state->CH_Ctrl[31].bit[0] = 3;
1582         state->CH_Ctrl[31].val[0] = 0;
1583
1584         state->CH_Ctrl[32].Ctrl_Num = DAC_A_ENABLE ;
1585         state->CH_Ctrl[32].size = 1 ;
1586         state->CH_Ctrl[32].addr[0] = 93;
1587         state->CH_Ctrl[32].bit[0] = 1;
1588         state->CH_Ctrl[32].val[0] = 0;
1589
1590         state->CH_Ctrl[33].Ctrl_Num = DAC_B_ENABLE ;
1591         state->CH_Ctrl[33].size = 1 ;
1592         state->CH_Ctrl[33].addr[0] = 93;
1593         state->CH_Ctrl[33].bit[0] = 0;
1594         state->CH_Ctrl[33].val[0] = 0;
1595
1596         state->CH_Ctrl[34].Ctrl_Num = DAC_DIN_A ;
1597         state->CH_Ctrl[34].size = 6 ;
1598         state->CH_Ctrl[34].addr[0] = 92;
1599         state->CH_Ctrl[34].bit[0] = 2;
1600         state->CH_Ctrl[34].val[0] = 0;
1601         state->CH_Ctrl[34].addr[1] = 92;
1602         state->CH_Ctrl[34].bit[1] = 3;
1603         state->CH_Ctrl[34].val[1] = 0;
1604         state->CH_Ctrl[34].addr[2] = 92;
1605         state->CH_Ctrl[34].bit[2] = 4;
1606         state->CH_Ctrl[34].val[2] = 0;
1607         state->CH_Ctrl[34].addr[3] = 92;
1608         state->CH_Ctrl[34].bit[3] = 5;
1609         state->CH_Ctrl[34].val[3] = 0;
1610         state->CH_Ctrl[34].addr[4] = 92;
1611         state->CH_Ctrl[34].bit[4] = 6;
1612         state->CH_Ctrl[34].val[4] = 0;
1613         state->CH_Ctrl[34].addr[5] = 92;
1614         state->CH_Ctrl[34].bit[5] = 7;
1615         state->CH_Ctrl[34].val[5] = 0;
1616
1617         state->CH_Ctrl[35].Ctrl_Num = DAC_DIN_B ;
1618         state->CH_Ctrl[35].size = 6 ;
1619         state->CH_Ctrl[35].addr[0] = 93;
1620         state->CH_Ctrl[35].bit[0] = 2;
1621         state->CH_Ctrl[35].val[0] = 0;
1622         state->CH_Ctrl[35].addr[1] = 93;
1623         state->CH_Ctrl[35].bit[1] = 3;
1624         state->CH_Ctrl[35].val[1] = 0;
1625         state->CH_Ctrl[35].addr[2] = 93;
1626         state->CH_Ctrl[35].bit[2] = 4;
1627         state->CH_Ctrl[35].val[2] = 0;
1628         state->CH_Ctrl[35].addr[3] = 93;
1629         state->CH_Ctrl[35].bit[3] = 5;
1630         state->CH_Ctrl[35].val[3] = 0;
1631         state->CH_Ctrl[35].addr[4] = 93;
1632         state->CH_Ctrl[35].bit[4] = 6;
1633         state->CH_Ctrl[35].val[4] = 0;
1634         state->CH_Ctrl[35].addr[5] = 93;
1635         state->CH_Ctrl[35].bit[5] = 7;
1636         state->CH_Ctrl[35].val[5] = 0;
1637
1638 #ifdef _MXL_PRODUCTION
1639         state->CH_Ctrl[36].Ctrl_Num = RFSYN_EN_DIV ;
1640         state->CH_Ctrl[36].size = 1 ;
1641         state->CH_Ctrl[36].addr[0] = 109;
1642         state->CH_Ctrl[36].bit[0] = 1;
1643         state->CH_Ctrl[36].val[0] = 1;
1644
1645         state->CH_Ctrl[37].Ctrl_Num = RFSYN_DIVM ;
1646         state->CH_Ctrl[37].size = 2 ;
1647         state->CH_Ctrl[37].addr[0] = 112;
1648         state->CH_Ctrl[37].bit[0] = 5;
1649         state->CH_Ctrl[37].val[0] = 0;
1650         state->CH_Ctrl[37].addr[1] = 112;
1651         state->CH_Ctrl[37].bit[1] = 6;
1652         state->CH_Ctrl[37].val[1] = 0;
1653
1654         state->CH_Ctrl[38].Ctrl_Num = DN_BYPASS_AGC_I2C ;
1655         state->CH_Ctrl[38].size = 1 ;
1656         state->CH_Ctrl[38].addr[0] = 65;
1657         state->CH_Ctrl[38].bit[0] = 1;
1658         state->CH_Ctrl[38].val[0] = 0;
1659 #endif
1660
1661         return 0 ;
1662 }
1663
1664 static void InitTunerControls(struct dvb_frontend *fe)
1665 {
1666         MXL5005_RegisterInit(fe);
1667         MXL5005_ControlInit(fe);
1668 #ifdef _MXL_INTERNAL
1669         MXL5005_MXLControlInit(fe);
1670 #endif
1671 }
1672
1673 static u16 MXL5005_TunerConfig(struct dvb_frontend *fe,
1674         u8      Mode,           /* 0: Analog Mode ; 1: Digital Mode */
1675         u8      IF_mode,        /* for Analog Mode, 0: zero IF; 1: low IF */
1676         u32     Bandwidth,      /* filter  channel bandwidth (6, 7, 8) */
1677         u32     IF_out,         /* Desired IF Out Frequency */
1678         u32     Fxtal,          /* XTAL Frequency */
1679         u8      AGC_Mode,       /* AGC Mode - Dual AGC: 0, Single AGC: 1 */
1680         u16     TOP,            /* 0: Dual AGC; Value: take over point */
1681         u16     IF_OUT_LOAD,    /* IF Out Load Resistor (200 / 300 Ohms) */
1682         u8      CLOCK_OUT,      /* 0: turn off clk out; 1: turn on clock out */
1683         u8      DIV_OUT,        /* 0: Div-1; 1: Div-4 */
1684         u8      CAPSELECT,      /* 0: disable On-Chip pulling cap; 1: enable */
1685         u8      EN_RSSI,        /* 0: disable RSSI; 1: enable RSSI */
1686
1687         /* Modulation Type; */
1688         /* 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable */
1689         u8      Mod_Type,
1690
1691         /* Tracking Filter */
1692         /* 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H */
1693         u8      TF_Type
1694         )
1695 {
1696         struct mxl5005s_state *state = fe->tuner_priv;
1697         u16 status = 0;
1698
1699         state->Mode = Mode;
1700         state->IF_Mode = IF_mode;
1701         state->Chan_Bandwidth = Bandwidth;
1702         state->IF_OUT = IF_out;
1703         state->Fxtal = Fxtal;
1704         state->AGC_Mode = AGC_Mode;
1705         state->TOP = TOP;
1706         state->IF_OUT_LOAD = IF_OUT_LOAD;
1707         state->CLOCK_OUT = CLOCK_OUT;
1708         state->DIV_OUT = DIV_OUT;
1709         state->CAPSELECT = CAPSELECT;
1710         state->EN_RSSI = EN_RSSI;
1711         state->Mod_Type = Mod_Type;
1712         state->TF_Type = TF_Type;
1713
1714         /* Initialize all the controls and registers */
1715         InitTunerControls(fe);
1716
1717         /* Synthesizer LO frequency calculation */
1718         MXL_SynthIFLO_Calc(fe);
1719
1720         return status;
1721 }
1722
1723 static void MXL_SynthIFLO_Calc(struct dvb_frontend *fe)
1724 {
1725         struct mxl5005s_state *state = fe->tuner_priv;
1726         if (state->Mode == 1) /* Digital Mode */
1727                 state->IF_LO = state->IF_OUT;
1728         else /* Analog Mode */ {
1729                 if (state->IF_Mode == 0) /* Analog Zero IF mode */
1730                         state->IF_LO = state->IF_OUT + 400000;
1731                 else /* Analog Low IF mode */
1732                         state->IF_LO = state->IF_OUT + state->Chan_Bandwidth/2;
1733         }
1734 }
1735
1736 static void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe)
1737 {
1738         struct mxl5005s_state *state = fe->tuner_priv;
1739
1740         if (state->Mode == 1) /* Digital Mode */ {
1741                         /* remove 20.48MHz setting for 2.6.10 */
1742                         state->RF_LO = state->RF_IN;
1743                         /* change for 2.6.6 */
1744                         state->TG_LO = state->RF_IN - 750000;
1745         } else /* Analog Mode */ {
1746                 if (state->IF_Mode == 0) /* Analog Zero IF mode */ {
1747                         state->RF_LO = state->RF_IN - 400000;
1748                         state->TG_LO = state->RF_IN - 1750000;
1749                 } else /* Analog Low IF mode */ {
1750                         state->RF_LO = state->RF_IN - state->Chan_Bandwidth/2;
1751                         state->TG_LO = state->RF_IN -
1752                                 state->Chan_Bandwidth + 500000;
1753                 }
1754         }
1755 }
1756
1757 static u16 MXL_OverwriteICDefault(struct dvb_frontend *fe)
1758 {
1759         u16 status = 0;
1760
1761         status += MXL_ControlWrite(fe, OVERRIDE_1, 1);
1762         status += MXL_ControlWrite(fe, OVERRIDE_2, 1);
1763         status += MXL_ControlWrite(fe, OVERRIDE_3, 1);
1764         status += MXL_ControlWrite(fe, OVERRIDE_4, 1);
1765
1766         return status;
1767 }
1768
1769 static u16 MXL_BlockInit(struct dvb_frontend *fe)
1770 {
1771         struct mxl5005s_state *state = fe->tuner_priv;
1772         u16 status = 0;
1773
1774         status += MXL_OverwriteICDefault(fe);
1775
1776         /* Downconverter Control Dig Ana */
1777         status += MXL_ControlWrite(fe, DN_IQTN_AMP_CUT, state->Mode ? 1 : 0);
1778
1779         /* Filter Control  Dig  Ana */
1780         status += MXL_ControlWrite(fe, BB_MODE, state->Mode ? 0 : 1);
1781         status += MXL_ControlWrite(fe, BB_BUF, state->Mode ? 3 : 2);
1782         status += MXL_ControlWrite(fe, BB_BUF_OA, state->Mode ? 1 : 0);
1783         status += MXL_ControlWrite(fe, BB_IQSWAP, state->Mode ? 0 : 1);
1784         status += MXL_ControlWrite(fe, BB_INITSTATE_DLPF_TUNE, 0);
1785
1786         /* Initialize Low-Pass Filter */
1787         if (state->Mode) { /* Digital Mode */
1788                 switch (state->Chan_Bandwidth) {
1789                 case 8000000:
1790                         status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 0);
1791                         break;
1792                 case 7000000:
1793                         status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 2);
1794                         break;
1795                 case 6000000:
1796                         status += MXL_ControlWrite(fe,
1797                                         BB_DLPF_BANDSEL, 3);
1798                         break;
1799                 }
1800         } else { /* Analog Mode */
1801                 switch (state->Chan_Bandwidth) {
1802                 case 8000000:   /* Low Zero */
1803                         status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT,
1804                                         (state->IF_Mode ? 0 : 3));
1805                         break;
1806                 case 7000000:
1807                         status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT,
1808                                         (state->IF_Mode ? 1 : 4));
1809                         break;
1810                 case 6000000:
1811                         status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT,
1812                                         (state->IF_Mode ? 2 : 5));
1813                         break;
1814                 }
1815         }
1816
1817         /* Charge Pump Control Dig  Ana */
1818         status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, state->Mode ? 5 : 8);
1819         status += MXL_ControlWrite(fe,
1820                 RFSYN_EN_CHP_HIGAIN, state->Mode ? 1 : 1);
1821         status += MXL_ControlWrite(fe, EN_CHP_LIN_B, state->Mode ? 0 : 0);
1822
1823         /* AGC TOP Control */
1824         if (state->AGC_Mode == 0) /* Dual AGC */ {
1825                 status += MXL_ControlWrite(fe, AGC_IF, 15);
1826                 status += MXL_ControlWrite(fe, AGC_RF, 15);
1827         } else /*  Single AGC Mode Dig  Ana */
1828                 status += MXL_ControlWrite(fe, AGC_RF, state->Mode ? 15 : 12);
1829
1830         if (state->TOP == 55) /* TOP == 5.5 */
1831                 status += MXL_ControlWrite(fe, AGC_IF, 0x0);
1832
1833         if (state->TOP == 72) /* TOP == 7.2 */
1834                 status += MXL_ControlWrite(fe, AGC_IF, 0x1);
1835
1836         if (state->TOP == 92) /* TOP == 9.2 */
1837                 status += MXL_ControlWrite(fe, AGC_IF, 0x2);
1838
1839         if (state->TOP == 110) /* TOP == 11.0 */
1840                 status += MXL_ControlWrite(fe, AGC_IF, 0x3);
1841
1842         if (state->TOP == 129) /* TOP == 12.9 */
1843                 status += MXL_ControlWrite(fe, AGC_IF, 0x4);
1844
1845         if (state->TOP == 147) /* TOP == 14.7 */
1846                 status += MXL_ControlWrite(fe, AGC_IF, 0x5);
1847
1848         if (state->TOP == 168) /* TOP == 16.8 */
1849                 status += MXL_ControlWrite(fe, AGC_IF, 0x6);
1850
1851         if (state->TOP == 194) /* TOP == 19.4 */
1852                 status += MXL_ControlWrite(fe, AGC_IF, 0x7);
1853
1854         if (state->TOP == 212) /* TOP == 21.2 */
1855                 status += MXL_ControlWrite(fe, AGC_IF, 0x9);
1856
1857         if (state->TOP == 232) /* TOP == 23.2 */
1858                 status += MXL_ControlWrite(fe, AGC_IF, 0xA);
1859
1860         if (state->TOP == 252) /* TOP == 25.2 */
1861                 status += MXL_ControlWrite(fe, AGC_IF, 0xB);
1862
1863         if (state->TOP == 271) /* TOP == 27.1 */
1864                 status += MXL_ControlWrite(fe, AGC_IF, 0xC);
1865
1866         if (state->TOP == 292) /* TOP == 29.2 */
1867                 status += MXL_ControlWrite(fe, AGC_IF, 0xD);
1868
1869         if (state->TOP == 317) /* TOP == 31.7 */
1870                 status += MXL_ControlWrite(fe, AGC_IF, 0xE);
1871
1872         if (state->TOP == 349) /* TOP == 34.9 */
1873                 status += MXL_ControlWrite(fe, AGC_IF, 0xF);
1874
1875         /* IF Synthesizer Control */
1876         status += MXL_IFSynthInit(fe);
1877
1878         /* IF UpConverter Control */
1879         if (state->IF_OUT_LOAD == 200) {
1880                 status += MXL_ControlWrite(fe, DRV_RES_SEL, 6);
1881                 status += MXL_ControlWrite(fe, I_DRIVER, 2);
1882         }
1883         if (state->IF_OUT_LOAD == 300) {
1884                 status += MXL_ControlWrite(fe, DRV_RES_SEL, 4);
1885                 status += MXL_ControlWrite(fe, I_DRIVER, 1);
1886         }
1887
1888         /* Anti-Alias Filtering Control
1889          * initialise Anti-Aliasing Filter
1890          */
1891         if (state->Mode) { /* Digital Mode */
1892                 if (state->IF_OUT >= 4000000UL && state->IF_OUT <= 6280000UL) {
1893                         status += MXL_ControlWrite(fe, EN_AAF, 1);
1894                         status += MXL_ControlWrite(fe, EN_3P, 1);
1895                         status += MXL_ControlWrite(fe, EN_AUX_3P, 1);
1896                         status += MXL_ControlWrite(fe, SEL_AAF_BAND, 0);
1897                 }
1898                 if ((state->IF_OUT == 36125000UL) ||
1899                         (state->IF_OUT == 36150000UL)) {
1900                         status += MXL_ControlWrite(fe, EN_AAF, 1);
1901                         status += MXL_ControlWrite(fe, EN_3P, 1);
1902                         status += MXL_ControlWrite(fe, EN_AUX_3P, 1);
1903                         status += MXL_ControlWrite(fe, SEL_AAF_BAND, 1);
1904                 }
1905                 if (state->IF_OUT > 36150000UL) {
1906                         status += MXL_ControlWrite(fe, EN_AAF, 0);
1907                         status += MXL_ControlWrite(fe, EN_3P, 1);
1908                         status += MXL_ControlWrite(fe, EN_AUX_3P, 1);
1909                         status += MXL_ControlWrite(fe, SEL_AAF_BAND, 1);
1910                 }
1911         } else { /* Analog Mode */
1912                 if (state->IF_OUT >= 4000000UL && state->IF_OUT <= 5000000UL) {
1913                         status += MXL_ControlWrite(fe, EN_AAF, 1);
1914                         status += MXL_ControlWrite(fe, EN_3P, 1);
1915                         status += MXL_ControlWrite(fe, EN_AUX_3P, 1);
1916                         status += MXL_ControlWrite(fe, SEL_AAF_BAND, 0);
1917                 }
1918                 if (state->IF_OUT > 5000000UL) {
1919                         status += MXL_ControlWrite(fe, EN_AAF, 0);
1920                         status += MXL_ControlWrite(fe, EN_3P, 0);
1921                         status += MXL_ControlWrite(fe, EN_AUX_3P, 0);
1922                         status += MXL_ControlWrite(fe, SEL_AAF_BAND, 0);
1923                 }
1924         }
1925
1926         /* Demod Clock Out */
1927         if (state->CLOCK_OUT)
1928                 status += MXL_ControlWrite(fe, SEQ_ENCLK16_CLK_OUT, 1);
1929         else
1930                 status += MXL_ControlWrite(fe, SEQ_ENCLK16_CLK_OUT, 0);
1931
1932         if (state->DIV_OUT == 1)
1933                 status += MXL_ControlWrite(fe, SEQ_SEL4_16B, 1);
1934         if (state->DIV_OUT == 0)
1935                 status += MXL_ControlWrite(fe, SEQ_SEL4_16B, 0);
1936
1937         /* Crystal Control */
1938         if (state->CAPSELECT)
1939                 status += MXL_ControlWrite(fe, XTAL_CAPSELECT, 1);
1940         else
1941                 status += MXL_ControlWrite(fe, XTAL_CAPSELECT, 0);
1942
1943         if (state->Fxtal >= 12000000UL && state->Fxtal <= 16000000UL)
1944                 status += MXL_ControlWrite(fe, IF_SEL_DBL, 1);
1945         if (state->Fxtal > 16000000UL && state->Fxtal <= 32000000UL)
1946                 status += MXL_ControlWrite(fe, IF_SEL_DBL, 0);
1947
1948         if (state->Fxtal >= 12000000UL && state->Fxtal <= 22000000UL)
1949                 status += MXL_ControlWrite(fe, RFSYN_R_DIV, 3);
1950         if (state->Fxtal > 22000000UL && state->Fxtal <= 32000000UL)
1951                 status += MXL_ControlWrite(fe, RFSYN_R_DIV, 0);
1952
1953         /* Misc Controls */
1954         if (state->Mode == 0 && state->IF_Mode == 1) /* Analog LowIF mode */
1955                 status += MXL_ControlWrite(fe, SEQ_EXTIQFSMPULSE, 0);
1956         else
1957                 status += MXL_ControlWrite(fe, SEQ_EXTIQFSMPULSE, 1);
1958
1959         /* status += MXL_ControlRead(fe, IF_DIVVAL, &IF_DIVVAL_Val); */
1960
1961         /* Set TG_R_DIV */
1962         status += MXL_ControlWrite(fe, TG_R_DIV,
1963                 MXL_Ceiling(state->Fxtal, 1000000));
1964
1965         /* Apply Default value to BB_INITSTATE_DLPF_TUNE */
1966
1967         /* RSSI Control */
1968         if (state->EN_RSSI) {
1969                 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
1970                 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
1971                 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1);
1972                 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
1973
1974                 /* RSSI reference point */
1975                 status += MXL_ControlWrite(fe, RFA_RSSI_REF, 2);
1976                 status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 3);
1977                 status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 1);
1978
1979                 /* TOP point */
1980                 status += MXL_ControlWrite(fe, RFA_FLR, 0);
1981                 status += MXL_ControlWrite(fe, RFA_CEIL, 12);
1982         }
1983
1984         /* Modulation type bit settings
1985          * Override the control values preset
1986          */
1987         if (state->Mod_Type == MXL_DVBT) /* DVB-T Mode */ {
1988                 state->AGC_Mode = 1; /* Single AGC Mode */
1989
1990                 /* Enable RSSI */
1991                 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
1992                 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
1993                 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1);
1994                 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
1995
1996                 /* RSSI reference point */
1997                 status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3);
1998                 status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5);
1999                 status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 1);
2000
2001                 /* TOP point */
2002                 status += MXL_ControlWrite(fe, RFA_FLR, 2);
2003                 status += MXL_ControlWrite(fe, RFA_CEIL, 13);
2004                 if (state->IF_OUT <= 6280000UL) /* Low IF */
2005                         status += MXL_ControlWrite(fe, BB_IQSWAP, 0);
2006                 else /* High IF */
2007                         status += MXL_ControlWrite(fe, BB_IQSWAP, 1);
2008
2009         }
2010         if (state->Mod_Type == MXL_ATSC) /* ATSC Mode */ {
2011                 state->AGC_Mode = 1;    /* Single AGC Mode */
2012
2013                 /* Enable RSSI */
2014                 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
2015                 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
2016                 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1);
2017                 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
2018
2019                 /* RSSI reference point */
2020                 status += MXL_ControlWrite(fe, RFA_RSSI_REF, 2);
2021                 status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 4);
2022                 status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 1);
2023
2024                 /* TOP point */
2025                 status += MXL_ControlWrite(fe, RFA_FLR, 2);
2026                 status += MXL_ControlWrite(fe, RFA_CEIL, 13);
2027                 status += MXL_ControlWrite(fe, BB_INITSTATE_DLPF_TUNE, 1);
2028                 /* Low Zero */
2029                 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 5);
2030
2031                 if (state->IF_OUT <= 6280000UL) /* Low IF */
2032                         status += MXL_ControlWrite(fe, BB_IQSWAP, 0);
2033                 else /* High IF */
2034                         status += MXL_ControlWrite(fe, BB_IQSWAP, 1);
2035         }
2036         if (state->Mod_Type == MXL_QAM) /* QAM Mode */ {
2037                 state->Mode = MXL_DIGITAL_MODE;
2038
2039                 /* state->AGC_Mode = 1; */ /* Single AGC Mode */
2040
2041                 /* Disable RSSI */      /* change here for v2.6.5 */
2042                 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
2043                 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
2044                 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0);
2045                 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
2046
2047                 /* RSSI reference point */
2048                 status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5);
2049                 status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3);
2050                 status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 2);
2051                 /* change here for v2.6.5 */
2052                 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3);
2053
2054                 if (state->IF_OUT <= 6280000UL) /* Low IF */
2055                         status += MXL_ControlWrite(fe, BB_IQSWAP, 0);
2056                 else /* High IF */
2057                         status += MXL_ControlWrite(fe, BB_IQSWAP, 1);
2058                 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 2);
2059
2060         }
2061         if (state->Mod_Type == MXL_ANALOG_CABLE) {
2062                 /* Analog Cable Mode */
2063                 /* state->Mode = MXL_DIGITAL_MODE; */
2064
2065                 state->AGC_Mode = 1; /* Single AGC Mode */
2066
2067                 /* Disable RSSI */
2068                 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
2069                 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
2070                 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0);
2071                 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
2072                 /* change for 2.6.3 */
2073                 status += MXL_ControlWrite(fe, AGC_IF, 1);
2074                 status += MXL_ControlWrite(fe, AGC_RF, 15);
2075                 status += MXL_ControlWrite(fe, BB_IQSWAP, 1);
2076         }
2077
2078         if (state->Mod_Type == MXL_ANALOG_OTA) {
2079                 /* Analog OTA Terrestrial mode add for 2.6.7 */
2080                 /* state->Mode = MXL_ANALOG_MODE; */
2081
2082                 /* Enable RSSI */
2083                 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
2084                 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
2085                 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1);
2086                 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
2087
2088                 /* RSSI reference point */
2089                 status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5);
2090                 status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3);
2091                 status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 2);
2092                 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3);
2093                 status += MXL_ControlWrite(fe, BB_IQSWAP, 1);
2094         }
2095
2096         /* RSSI disable */
2097         if (state->EN_RSSI == 0) {
2098                 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
2099                 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
2100                 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0);
2101                 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
2102         }
2103
2104         return status;
2105 }
2106
2107 static u16 MXL_IFSynthInit(struct dvb_frontend *fe)
2108 {
2109         struct mxl5005s_state *state = fe->tuner_priv;
2110         u16 status = 0 ;
2111         u32     Fref = 0 ;
2112         u32     Kdbl, intModVal ;
2113         u32     fracModVal ;
2114         Kdbl = 2 ;
2115
2116         if (state->Fxtal >= 12000000UL && state->Fxtal <= 16000000UL)
2117                 Kdbl = 2 ;
2118         if (state->Fxtal > 16000000UL && state->Fxtal <= 32000000UL)
2119                 Kdbl = 1 ;
2120
2121         /* IF Synthesizer Control */
2122         if (state->Mode == 0 && state->IF_Mode == 1) /* Analog Low IF mode */ {
2123                 if (state->IF_LO == 41000000UL) {
2124                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x08);
2125                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
2126                         Fref = 328000000UL ;
2127                 }
2128                 if (state->IF_LO == 47000000UL) {
2129                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x08);
2130                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2131                         Fref = 376000000UL ;
2132                 }
2133                 if (state->IF_LO == 54000000UL) {
2134                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x10);
2135                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
2136                         Fref = 324000000UL ;
2137                 }
2138                 if (state->IF_LO == 60000000UL) {
2139                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x10);
2140                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2141                         Fref = 360000000UL ;
2142                 }
2143                 if (state->IF_LO == 39250000UL) {
2144                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x08);
2145                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
2146                         Fref = 314000000UL ;
2147                 }
2148                 if (state->IF_LO == 39650000UL) {
2149                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x08);
2150                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
2151                         Fref = 317200000UL ;
2152                 }
2153                 if (state->IF_LO == 40150000UL) {
2154                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x08);
2155                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
2156                         Fref = 321200000UL ;
2157                 }
2158                 if (state->IF_LO == 40650000UL) {
2159                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x08);
2160                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
2161                         Fref = 325200000UL ;
2162                 }
2163         }
2164
2165         if (state->Mode || (state->Mode == 0 && state->IF_Mode == 0)) {
2166                 if (state->IF_LO == 57000000UL) {
2167                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x10);
2168                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2169                         Fref = 342000000UL ;
2170                 }
2171                 if (state->IF_LO == 44000000UL) {
2172                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x08);
2173                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2174                         Fref = 352000000UL ;
2175                 }
2176                 if (state->IF_LO == 43750000UL) {
2177                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x08);
2178                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2179                         Fref = 350000000UL ;
2180                 }
2181                 if (state->IF_LO == 36650000UL) {
2182                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x04);
2183                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2184                         Fref = 366500000UL ;
2185                 }
2186                 if (state->IF_LO == 36150000UL) {
2187                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x04);
2188                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2189                         Fref = 361500000UL ;
2190                 }
2191                 if (state->IF_LO == 36000000UL) {
2192                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x04);
2193                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2194                         Fref = 360000000UL ;
2195                 }
2196                 if (state->IF_LO == 35250000UL) {
2197                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x04);
2198                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2199                         Fref = 352500000UL ;
2200                 }
2201                 if (state->IF_LO == 34750000UL) {
2202                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x04);
2203                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2204                         Fref = 347500000UL ;
2205                 }
2206                 if (state->IF_LO == 6280000UL) {
2207                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x07);
2208                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2209                         Fref = 376800000UL ;
2210                 }
2211                 if (state->IF_LO == 5000000UL) {
2212                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x09);
2213                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2214                         Fref = 360000000UL ;
2215                 }
2216                 if (state->IF_LO == 4500000UL) {
2217                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x06);
2218                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2219                         Fref = 360000000UL ;
2220                 }
2221                 if (state->IF_LO == 4570000UL) {
2222                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x06);
2223                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2224                         Fref = 365600000UL ;
2225                 }
2226                 if (state->IF_LO == 4000000UL) {
2227                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x05);
2228                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2229                         Fref = 360000000UL ;
2230                 }
2231                 if (state->IF_LO == 57400000UL) {
2232                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x10);
2233                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2234                         Fref = 344400000UL ;
2235                 }
2236                 if (state->IF_LO == 44400000UL) {
2237                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x08);
2238                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2239                         Fref = 355200000UL ;
2240                 }
2241                 if (state->IF_LO == 44150000UL) {
2242                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x08);
2243                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2244                         Fref = 353200000UL ;
2245                 }
2246                 if (state->IF_LO == 37050000UL) {
2247                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x04);
2248                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2249                         Fref = 370500000UL ;
2250                 }
2251                 if (state->IF_LO == 36550000UL) {
2252                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x04);
2253                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2254                         Fref = 365500000UL ;
2255                 }
2256                 if (state->IF_LO == 36125000UL) {
2257                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x04);
2258                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2259                         Fref = 361250000UL ;
2260                 }
2261                 if (state->IF_LO == 6000000UL) {
2262                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x07);
2263                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2264                         Fref = 360000000UL ;
2265                 }
2266                 if (state->IF_LO == 5400000UL) {
2267                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x07);
2268                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
2269                         Fref = 324000000UL ;
2270                 }
2271                 if (state->IF_LO == 5380000UL) {
2272                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x07);
2273                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
2274                         Fref = 322800000UL ;
2275                 }
2276                 if (state->IF_LO == 5200000UL) {
2277                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x09);
2278                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2279                         Fref = 374400000UL ;
2280                 }
2281                 if (state->IF_LO == 4900000UL) {
2282                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x09);
2283                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2284                         Fref = 352800000UL ;
2285                 }
2286                 if (state->IF_LO == 4400000UL) {
2287                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x06);
2288                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2289                         Fref = 352000000UL ;
2290                 }
2291                 if (state->IF_LO == 4063000UL)  /* add for 2.6.8 */ {
2292                         status += MXL_ControlWrite(fe, IF_DIVVAL,   0x05);
2293                         status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2294                         Fref = 365670000UL ;
2295                 }
2296         }
2297         /* CHCAL_INT_MOD_IF */
2298         /* CHCAL_FRAC_MOD_IF */
2299         intModVal = Fref / (state->Fxtal * Kdbl/2);
2300         status += MXL_ControlWrite(fe, CHCAL_INT_MOD_IF, intModVal);
2301
2302         fracModVal = (2<<15)*(Fref/1000 - (state->Fxtal/1000 * Kdbl/2) *
2303                 intModVal);
2304
2305         fracModVal = fracModVal / ((state->Fxtal * Kdbl/2)/1000);
2306         status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_IF, fracModVal);
2307
2308         return status ;
2309 }
2310
2311 static u32 MXL_GetXtalInt(u32 Xtal_Freq)
2312 {
2313         if ((Xtal_Freq % 1000000) == 0)
2314                 return (Xtal_Freq / 10000);
2315         else
2316                 return (((Xtal_Freq / 1000000) + 1)*100);
2317 }
2318
2319 static u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq)
2320 {
2321         struct mxl5005s_state *state = fe->tuner_priv;
2322         u16 status = 0;
2323         u32 divider_val, E3, E4, E5, E5A;
2324         u32 Fmax, Fmin, FmaxBin, FminBin;
2325         u32 Kdbl_RF = 2;
2326         u32 tg_divval;
2327         u32 tg_lo;
2328         u32 Xtal_Int;
2329
2330         u32 Fref_TG;
2331         u32 Fvco;
2332
2333         Xtal_Int = MXL_GetXtalInt(state->Fxtal);
2334
2335         state->RF_IN = RF_Freq;
2336
2337         MXL_SynthRFTGLO_Calc(fe);
2338
2339         if (state->Fxtal >= 12000000UL && state->Fxtal <= 22000000UL)
2340                 Kdbl_RF = 2;
2341         if (state->Fxtal > 22000000 && state->Fxtal <= 32000000)
2342                 Kdbl_RF = 1;
2343
2344         /* Downconverter Controls
2345          * Look-Up Table Implementation for:
2346          *      DN_POLY
2347          *      DN_RFGAIN
2348          *      DN_CAP_RFLPF
2349          *      DN_EN_VHFUHFBAR
2350          *      DN_GAIN_ADJUST
2351          *  Change the boundary reference from RF_IN to RF_LO
2352          */
2353         if (state->RF_LO < 40000000UL)
2354                 return -1;
2355
2356         if (state->RF_LO >= 40000000UL && state->RF_LO <= 75000000UL) {
2357                 status += MXL_ControlWrite(fe, DN_POLY,              2);
2358                 status += MXL_ControlWrite(fe, DN_RFGAIN,            3);
2359                 status += MXL_ControlWrite(fe, DN_CAP_RFLPF,         423);
2360                 status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR,      1);
2361                 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST,       1);
2362         }
2363         if (state->RF_LO > 75000000UL && state->RF_LO <= 100000000UL) {
2364                 status += MXL_ControlWrite(fe, DN_POLY,              3);
2365                 status += MXL_ControlWrite(fe, DN_RFGAIN,            3);
2366                 status += MXL_ControlWrite(fe, DN_CAP_RFLPF,         222);
2367                 status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR,      1);
2368                 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST,       1);
2369         }
2370         if (state->RF_LO > 100000000UL && state->RF_LO <= 150000000UL) {
2371                 status += MXL_ControlWrite(fe, DN_POLY,              3);
2372                 status += MXL_ControlWrite(fe, DN_RFGAIN,            3);
2373                 status += MXL_ControlWrite(fe, DN_CAP_RFLPF,         147);
2374                 status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR,      1);
2375                 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST,       2);
2376         }
2377         if (state->RF_LO > 150000000UL && state->RF_LO <= 200000000UL) {
2378                 status += MXL_ControlWrite(fe, DN_POLY,              3);
2379                 status += MXL_ControlWrite(fe, DN_RFGAIN,            3);
2380                 status += MXL_ControlWrite(fe, DN_CAP_RFLPF,         9);
2381                 status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR,      1);
2382                 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST,       2);
2383         }
2384         if (state->RF_LO > 200000000UL && state->RF_LO <= 300000000UL) {
2385                 status += MXL_ControlWrite(fe, DN_POLY,              3);
2386                 status += MXL_ControlWrite(fe, DN_RFGAIN,            3);
2387                 status += MXL_ControlWrite(fe, DN_CAP_RFLPF,         0);
2388                 status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR,      1);
2389                 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST,       3);
2390         }
2391         if (state->RF_LO > 300000000UL && state->RF_LO <= 650000000UL) {
2392                 status += MXL_ControlWrite(fe, DN_POLY,              3);
2393                 status += MXL_ControlWrite(fe, DN_RFGAIN,            1);
2394                 status += MXL_ControlWrite(fe, DN_CAP_RFLPF,         0);
2395                 status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR,      0);
2396                 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST,       3);
2397         }
2398         if (state->RF_LO > 650000000UL && state->RF_LO <= 900000000UL) {
2399                 status += MXL_ControlWrite(fe, DN_POLY,              3);
2400                 status += MXL_ControlWrite(fe, DN_RFGAIN,            2);
2401                 status += MXL_ControlWrite(fe, DN_CAP_RFLPF,         0);
2402                 status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR,      0);
2403                 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST,       3);
2404         }
2405         if (state->RF_LO > 900000000UL)
2406                 return -1;
2407
2408         /*      DN_IQTNBUF_AMP */
2409         /*      DN_IQTNGNBFBIAS_BST */
2410         if (state->RF_LO >= 40000000UL && state->RF_LO <= 75000000UL) {
2411                 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP,       1);
2412                 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST,  0);
2413         }
2414         if (state->RF_LO > 75000000UL && state->RF_LO <= 100000000UL) {
2415                 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP,       1);
2416                 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST,  0);
2417         }
2418         if (state->RF_LO > 100000000UL && state->RF_LO <= 150000000UL) {
2419                 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP,       1);
2420                 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST,  0);
2421         }
2422         if (state->RF_LO > 150000000UL && state->RF_LO <= 200000000UL) {
2423                 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP,       1);
2424                 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST,  0);
2425         }
2426         if (state->RF_LO > 200000000UL && state->RF_LO <= 300000000UL) {
2427                 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP,       1);
2428                 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST,  0);
2429         }
2430         if (state->RF_LO > 300000000UL && state->RF_LO <= 400000000UL) {
2431                 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP,       1);
2432                 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST,  0);
2433         }
2434         if (state->RF_LO > 400000000UL && state->RF_LO <= 450000000UL) {
2435                 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP,       1);
2436                 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST,  0);
2437         }
2438         if (state->RF_LO > 450000000UL && state->RF_LO <= 500000000UL) {
2439                 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP,       1);
2440                 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST,  0);
2441         }
2442         if (state->RF_LO > 500000000UL && state->RF_LO <= 550000000UL) {
2443                 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP,       1);
2444                 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST,  0);
2445         }
2446         if (state->RF_LO > 550000000UL && state->RF_LO <= 600000000UL) {
2447                 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP,       1);
2448                 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST,  0);
2449         }
2450         if (state->RF_LO > 600000000UL && state->RF_LO <= 650000000UL) {
2451                 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP,       1);
2452                 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST,  0);
2453         }
2454         if (state->RF_LO > 650000000UL && state->RF_LO <= 700000000UL) {
2455                 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP,       1);
2456                 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST,  0);
2457         }
2458         if (state->RF_LO > 700000000UL && state->RF_LO <= 750000000UL) {
2459                 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP,       1);
2460                 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST,  0);
2461         }
2462         if (state->RF_LO > 750000000UL && state->RF_LO <= 800000000UL) {
2463                 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP,       1);
2464                 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST,  0);
2465         }
2466         if (state->RF_LO > 800000000UL && state->RF_LO <= 850000000UL) {
2467                 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP,       10);
2468                 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST,  1);
2469         }
2470         if (state->RF_LO > 850000000UL && state->RF_LO <= 900000000UL) {
2471                 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP,       10);
2472                 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST,  1);
2473         }
2474
2475         /*
2476          * Set RF Synth and LO Path Control
2477          *
2478          * Look-Up table implementation for:
2479          *      RFSYN_EN_OUTMUX
2480          *      RFSYN_SEL_VCO_OUT
2481          *      RFSYN_SEL_VCO_HI
2482          *  RFSYN_SEL_DIVM
2483          *      RFSYN_RF_DIV_BIAS
2484          *      DN_SEL_FREQ
2485          *
2486          * Set divider_val, Fmax, Fmix to use in Equations
2487          */
2488         FminBin = 28000000UL ;
2489         FmaxBin = 42500000UL ;
2490         if (state->RF_LO >= 40000000UL && state->RF_LO <= FmaxBin) {
2491                 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX,     1);
2492                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT,   0);
2493                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI,    0);
2494                 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM,      0);
2495                 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS,   1);
2496                 status += MXL_ControlWrite(fe, DN_SEL_FREQ,         1);
2497                 divider_val = 64 ;
2498                 Fmax = FmaxBin ;
2499                 Fmin = FminBin ;
2500         }
2501         FminBin = 42500000UL ;
2502         FmaxBin = 56000000UL ;
2503         if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2504                 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX,     1);
2505                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT,   0);
2506                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI,    1);
2507                 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM,      0);
2508                 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS,   1);
2509                 status += MXL_ControlWrite(fe, DN_SEL_FREQ,         1);
2510                 divider_val = 64 ;
2511                 Fmax = FmaxBin ;
2512                 Fmin = FminBin ;
2513         }
2514         FminBin = 56000000UL ;
2515         FmaxBin = 85000000UL ;
2516         if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2517                 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX,     0);
2518                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT,   1);
2519                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI,    0);
2520                 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM,      0);
2521                 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS,   1);
2522                 status += MXL_ControlWrite(fe, DN_SEL_FREQ,         1);
2523                 divider_val = 32 ;
2524                 Fmax = FmaxBin ;
2525                 Fmin = FminBin ;
2526         }
2527         FminBin = 85000000UL ;
2528         FmaxBin = 112000000UL ;
2529         if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2530                 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX,     0);
2531                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT,   1);
2532                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI,    1);
2533                 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM,      0);
2534                 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS,   1);
2535                 status += MXL_ControlWrite(fe, DN_SEL_FREQ,         1);
2536                 divider_val = 32 ;
2537                 Fmax = FmaxBin ;
2538                 Fmin = FminBin ;
2539         }
2540         FminBin = 112000000UL ;
2541         FmaxBin = 170000000UL ;
2542         if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2543                 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX,     0);
2544                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT,   1);
2545                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI,    0);
2546                 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM,      0);
2547                 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS,   1);
2548                 status += MXL_ControlWrite(fe, DN_SEL_FREQ,         2);
2549                 divider_val = 16 ;
2550                 Fmax = FmaxBin ;
2551                 Fmin = FminBin ;
2552         }
2553         FminBin = 170000000UL ;
2554         FmaxBin = 225000000UL ;
2555         if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2556                 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX,     0);
2557                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT,   1);
2558                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI,    1);
2559                 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM,      0);
2560                 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS,   1);
2561                 status += MXL_ControlWrite(fe, DN_SEL_FREQ,         2);
2562                 divider_val = 16 ;
2563                 Fmax = FmaxBin ;
2564                 Fmin = FminBin ;
2565         }
2566         FminBin = 225000000UL ;
2567         FmaxBin = 300000000UL ;
2568         if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2569                 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX,     0);
2570                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT,   1);
2571                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI,    0);
2572                 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM,      0);
2573                 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS,   1);
2574                 status += MXL_ControlWrite(fe, DN_SEL_FREQ,         4);
2575                 divider_val = 8 ;
2576                 Fmax = 340000000UL ;
2577                 Fmin = FminBin ;
2578         }
2579         FminBin = 300000000UL ;
2580         FmaxBin = 340000000UL ;
2581         if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2582                 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX,     1);
2583                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT,   0);
2584                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI,    0);
2585                 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM,      0);
2586                 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS,   1);
2587                 status += MXL_ControlWrite(fe, DN_SEL_FREQ,         0);
2588                 divider_val = 8 ;
2589                 Fmax = FmaxBin ;
2590                 Fmin = 225000000UL ;
2591         }
2592         FminBin = 340000000UL ;
2593         FmaxBin = 450000000UL ;
2594         if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2595                 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX,     1);
2596                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT,   0);
2597                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI,    1);
2598                 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM,      0);
2599                 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS,   2);
2600                 status += MXL_ControlWrite(fe, DN_SEL_FREQ,         0);
2601                 divider_val = 8 ;
2602                 Fmax = FmaxBin ;
2603                 Fmin = FminBin ;
2604         }
2605         FminBin = 450000000UL ;
2606         FmaxBin = 680000000UL ;
2607         if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2608                 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX,     0);
2609                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT,   1);
2610                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI,    0);
2611                 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM,      1);
2612                 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS,   1);
2613                 status += MXL_ControlWrite(fe, DN_SEL_FREQ,         0);
2614                 divider_val = 4 ;
2615                 Fmax = FmaxBin ;
2616                 Fmin = FminBin ;
2617         }
2618         FminBin = 680000000UL ;
2619         FmaxBin = 900000000UL ;
2620         if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2621                 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX,     0);
2622                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT,   1);
2623                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI,    1);
2624                 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM,      1);
2625                 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS,   1);
2626                 status += MXL_ControlWrite(fe, DN_SEL_FREQ,         0);
2627                 divider_val = 4 ;
2628                 Fmax = FmaxBin ;
2629                 Fmin = FminBin ;
2630         }
2631
2632         /*      CHCAL_INT_MOD_RF
2633          *      CHCAL_FRAC_MOD_RF
2634          *      RFSYN_LPF_R
2635          *      CHCAL_EN_INT_RF
2636          */
2637         /* Equation E3 RFSYN_VCO_BIAS */
2638         E3 = (((Fmax-state->RF_LO)/1000)*32)/((Fmax-Fmin)/1000) + 8 ;
2639         status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, E3);
2640
2641         /* Equation E4 CHCAL_INT_MOD_RF */
2642         E4 = (state->RF_LO*divider_val/1000)/(2*state->Fxtal*Kdbl_RF/1000);
2643         MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, E4);
2644
2645         /* Equation E5 CHCAL_FRAC_MOD_RF CHCAL_EN_INT_RF */
2646         E5 = ((2<<17)*(state->RF_LO/10000*divider_val -
2647                 (E4*(2*state->Fxtal*Kdbl_RF)/10000))) /
2648                 (2*state->Fxtal*Kdbl_RF/10000);
2649
2650         status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, E5);
2651
2652         /* Equation E5A RFSYN_LPF_R */
2653         E5A = (((Fmax - state->RF_LO)/1000)*4/((Fmax-Fmin)/1000)) + 1 ;
2654         status += MXL_ControlWrite(fe, RFSYN_LPF_R, E5A);
2655
2656         /* Euqation E5B CHCAL_EN_INIT_RF */
2657         status += MXL_ControlWrite(fe, CHCAL_EN_INT_RF, ((E5 == 0) ? 1 : 0));
2658         /*if (E5 == 0)
2659          *      status += MXL_ControlWrite(fe, CHCAL_EN_INT_RF, 1);
2660          *else
2661          *      status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, E5);
2662          */
2663
2664         /*
2665          * Set TG Synth
2666          *
2667          * Look-Up table implementation for:
2668          *      TG_LO_DIVVAL
2669          *      TG_LO_SELVAL
2670          *
2671          * Set divider_val, Fmax, Fmix to use in Equations
2672          */
2673         if (state->TG_LO < 33000000UL)
2674                 return -1;
2675
2676         FminBin = 33000000UL ;
2677         FmaxBin = 50000000UL ;
2678         if (state->TG_LO >= FminBin && state->TG_LO <= FmaxBin) {
2679                 status += MXL_ControlWrite(fe, TG_LO_DIVVAL,    0x6);
2680                 status += MXL_ControlWrite(fe, TG_LO_SELVAL,    0x0);
2681                 divider_val = 36 ;
2682                 Fmax = FmaxBin ;
2683                 Fmin = FminBin ;
2684         }
2685         FminBin = 50000000UL ;
2686         FmaxBin = 67000000UL ;
2687         if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2688                 status += MXL_ControlWrite(fe, TG_LO_DIVVAL,    0x1);
2689                 status += MXL_ControlWrite(fe, TG_LO_SELVAL,    0x0);
2690                 divider_val = 24 ;
2691                 Fmax = FmaxBin ;
2692                 Fmin = FminBin ;
2693         }
2694         FminBin = 67000000UL ;
2695         FmaxBin = 100000000UL ;
2696         if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2697                 status += MXL_ControlWrite(fe, TG_LO_DIVVAL,    0xC);
2698                 status += MXL_ControlWrite(fe, TG_LO_SELVAL,    0x2);
2699                 divider_val = 18 ;
2700                 Fmax = FmaxBin ;
2701                 Fmin = FminBin ;
2702         }
2703         FminBin = 100000000UL ;
2704         FmaxBin = 150000000UL ;
2705         if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2706                 status += MXL_ControlWrite(fe, TG_LO_DIVVAL,    0x8);
2707                 status += MXL_ControlWrite(fe, TG_LO_SELVAL,    0x2);
2708                 divider_val = 12 ;
2709                 Fmax = FmaxBin ;
2710                 Fmin = FminBin ;
2711         }
2712         FminBin = 150000000UL ;
2713         FmaxBin = 200000000UL ;
2714         if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2715                 status += MXL_ControlWrite(fe, TG_LO_DIVVAL,    0x0);
2716                 status += MXL_ControlWrite(fe, TG_LO_SELVAL,    0x2);
2717                 divider_val = 8 ;
2718                 Fmax = FmaxBin ;
2719                 Fmin = FminBin ;
2720         }
2721         FminBin = 200000000UL ;
2722         FmaxBin = 300000000UL ;
2723         if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2724                 status += MXL_ControlWrite(fe, TG_LO_DIVVAL,    0x8);
2725                 status += MXL_ControlWrite(fe, TG_LO_SELVAL,    0x3);
2726                 divider_val = 6 ;
2727                 Fmax = FmaxBin ;
2728                 Fmin = FminBin ;
2729         }
2730         FminBin = 300000000UL ;
2731         FmaxBin = 400000000UL ;
2732         if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2733                 status += MXL_ControlWrite(fe, TG_LO_DIVVAL,    0x0);
2734                 status += MXL_ControlWrite(fe, TG_LO_SELVAL,    0x3);
2735                 divider_val = 4 ;
2736                 Fmax = FmaxBin ;
2737                 Fmin = FminBin ;
2738         }
2739         FminBin = 400000000UL ;
2740         FmaxBin = 600000000UL ;
2741         if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2742                 status += MXL_ControlWrite(fe, TG_LO_DIVVAL,    0x8);
2743                 status += MXL_ControlWrite(fe, TG_LO_SELVAL,    0x7);
2744                 divider_val = 3 ;
2745                 Fmax = FmaxBin ;
2746                 Fmin = FminBin ;
2747         }
2748         FminBin = 600000000UL ;
2749         FmaxBin = 900000000UL ;
2750         if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2751                 status += MXL_ControlWrite(fe, TG_LO_DIVVAL,    0x0);
2752                 status += MXL_ControlWrite(fe, TG_LO_SELVAL,    0x7);
2753                 divider_val = 2 ;
2754                 Fmax = FmaxBin ;
2755                 Fmin = FminBin ;
2756         }
2757
2758         /* TG_DIV_VAL */
2759         tg_divval = (state->TG_LO*divider_val/100000) *
2760                 (MXL_Ceiling(state->Fxtal, 1000000) * 100) /
2761                 (state->Fxtal/1000);
2762
2763         status += MXL_ControlWrite(fe, TG_DIV_VAL, tg_divval);
2764
2765         if (state->TG_LO > 600000000UL)
2766                 status += MXL_ControlWrite(fe, TG_DIV_VAL, tg_divval + 1);
2767
2768         Fmax = 1800000000UL ;
2769         Fmin = 1200000000UL ;
2770
2771         /* prevent overflow of 32 bit unsigned integer, use
2772          * following equation. Edit for v2.6.4
2773          */
2774         /* Fref_TF = Fref_TG * 1000 */
2775         Fref_TG = (state->Fxtal/1000) / MXL_Ceiling(state->Fxtal, 1000000);
2776
2777         /* Fvco = Fvco/10 */
2778         Fvco = (state->TG_LO/10000) * divider_val * Fref_TG;
2779
2780         tg_lo = (((Fmax/10 - Fvco)/100)*32) / ((Fmax-Fmin)/1000)+8;
2781
2782         /* below equation is same as above but much harder to debug.
2783          * tg_lo = ( ((Fmax/10000 * Xtal_Int)/100) -
2784          * ((state->TG_LO/10000)*divider_val *
2785          * (state->Fxtal/10000)/100) )*32/((Fmax-Fmin)/10000 *
2786          * Xtal_Int/100) + 8;
2787          */
2788
2789         status += MXL_ControlWrite(fe, TG_VCO_BIAS , tg_lo);
2790
2791         /* add for 2.6.5 Special setting for QAM */
2792         if (state->Mod_Type == MXL_QAM) {
2793                 if (state->RF_IN < 680000000)
2794                         status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3);
2795                 else
2796                         status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 2);
2797         }
2798
2799         /* Off Chip Tracking Filter Control */
2800         if (state->TF_Type == MXL_TF_OFF) {
2801                 /* Tracking Filter Off State; turn off all the banks */
2802                 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
2803                 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
2804                 status += MXL_SetGPIO(fe, 3, 1); /* Bank1 Off */
2805                 status += MXL_SetGPIO(fe, 1, 1); /* Bank2 Off */
2806                 status += MXL_SetGPIO(fe, 4, 1); /* Bank3 Off */
2807         }
2808
2809         if (state->TF_Type == MXL_TF_C) /* Tracking Filter type C */ {
2810                 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
2811                 status += MXL_ControlWrite(fe, DAC_DIN_A, 0);
2812
2813                 if (state->RF_IN >= 43000000 && state->RF_IN < 150000000) {
2814                         status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
2815                         status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
2816                         status += MXL_SetGPIO(fe, 3, 0);
2817                         status += MXL_SetGPIO(fe, 1, 1);
2818                         status += MXL_SetGPIO(fe, 4, 1);
2819                 }
2820                 if (state->RF_IN >= 150000000 && state->RF_IN < 280000000) {
2821                         status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
2822                         status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
2823                         status += MXL_SetGPIO(fe, 3, 1);
2824                         status += MXL_SetGPIO(fe, 1, 0);
2825                         status += MXL_SetGPIO(fe, 4, 1);
2826                 }
2827                 if (state->RF_IN >= 280000000 && state->RF_IN < 360000000) {
2828                         status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
2829                         status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
2830                         status += MXL_SetGPIO(fe, 3, 1);
2831                         status += MXL_SetGPIO(fe, 1, 0);
2832                         status += MXL_SetGPIO(fe, 4, 0);
2833                 }
2834                 if (state->RF_IN >= 360000000 && state->RF_IN < 560000000) {
2835                         status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
2836                         status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
2837                         status += MXL_SetGPIO(fe, 3, 1);
2838                         status += MXL_SetGPIO(fe, 1, 1);
2839                         status += MXL_SetGPIO(fe, 4, 0);
2840                 }
2841                 if (state->RF_IN >= 560000000 && state->RF_IN < 580000000) {
2842                         status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
2843                         status += MXL_ControlWrite(fe, DAC_DIN_B, 29);
2844                         status += MXL_SetGPIO(fe, 3, 1);
2845                         status += MXL_SetGPIO(fe, 1, 1);
2846                         status += MXL_SetGPIO(fe, 4, 0);
2847                 }
2848                 if (state->RF_IN >= 580000000 && state->RF_IN < 630000000) {
2849                         status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
2850                         status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
2851                         status += MXL_SetGPIO(fe, 3, 1);
2852                         status += MXL_SetGPIO(fe, 1, 1);
2853                         status += MXL_SetGPIO(fe, 4, 0);
2854                 }
2855                 if (state->RF_IN >= 630000000 && state->RF_IN < 700000000) {
2856                         status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
2857                         status += MXL_ControlWrite(fe, DAC_DIN_B, 16);
2858                         status += MXL_SetGPIO(fe, 3, 1);
2859                         status += MXL_SetGPIO(fe, 1, 1);
2860                         status += MXL_SetGPIO(fe, 4, 1);
2861                 }
2862                 if (state->RF_IN >= 700000000 && state->RF_IN < 760000000) {
2863                         status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
2864                         status += MXL_ControlWrite(fe, DAC_DIN_B, 7);
2865                         status += MXL_SetGPIO(fe, 3, 1);
2866                         status += MXL_SetGPIO(fe, 1, 1);
2867                         status += MXL_SetGPIO(fe, 4, 1);
2868                 }
2869                 if (state->RF_IN >= 760000000 && state->RF_IN <= 900000000) {
2870                         status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
2871                         status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
2872                         status += MXL_SetGPIO(fe, 3, 1);
2873                         status += MXL_SetGPIO(fe, 1, 1);
2874                         status += MXL_SetGPIO(fe, 4, 1);
2875                 }
2876         }
2877
2878         if (state->TF_Type == MXL_TF_C_H) {
2879
2880                 /* Tracking Filter type C-H for Hauppauge only */
2881                 status += MXL_ControlWrite(fe, DAC_DIN_A, 0);
2882
2883                 if (state->RF_IN >= 43000000 && state->RF_IN < 150000000) {
2884                         status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
2885                         status += MXL_SetGPIO(fe, 4, 0);
2886                         status += MXL_SetGPIO(fe, 3, 1);
2887                         status += MXL_SetGPIO(fe, 1, 1);
2888                 }
2889                 if (state->RF_IN >= 150000000 && state->RF_IN < 280000000) {
2890                         status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
2891                         status += MXL_SetGPIO(fe, 4, 1);
2892                         status += MXL_SetGPIO(fe, 3, 0);
2893                         status += MXL_SetGPIO(fe, 1, 1);
2894                 }
2895                 if (state->RF_IN >= 280000000 && state->RF_IN < 360000000) {
2896                         status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
2897                         status += MXL_SetGPIO(fe, 4, 1);
2898                         status += MXL_SetGPIO(fe, 3, 0);
2899                         status += MXL_SetGPIO(fe, 1, 0);
2900                 }
2901                 if (state->RF_IN >= 360000000 && state->RF_IN < 560000000) {
2902                         status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
2903                         status += MXL_SetGPIO(fe, 4, 1);
2904                         status += MXL_SetGPIO(fe, 3, 1);
2905                         status += MXL_SetGPIO(fe, 1, 0);
2906                 }
2907                 if (state->RF_IN >= 560000000 && state->RF_IN < 580000000) {
2908                         status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
2909                         status += MXL_SetGPIO(fe, 4, 1);
2910                         status += MXL_SetGPIO(fe, 3, 1);
2911                         status += MXL_SetGPIO(fe, 1, 0);
2912                 }
2913                 if (state->RF_IN >= 580000000 && state->RF_IN < 630000000) {
2914                         status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
2915                         status += MXL_SetGPIO(fe, 4, 1);
2916                         status += MXL_SetGPIO(fe, 3, 1);
2917                         status += MXL_SetGPIO(fe, 1, 0);
2918                 }
2919                 if (state->RF_IN >= 630000000 && state->RF_IN < 700000000) {
2920                         status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
2921                         status += MXL_SetGPIO(fe, 4, 1);
2922                         status += MXL_SetGPIO(fe, 3, 1);
2923                         status += MXL_SetGPIO(fe, 1, 1);
2924                 }
2925                 if (state->RF_IN >= 700000000 && state->RF_IN < 760000000) {
2926                         status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
2927                         status += MXL_SetGPIO(fe, 4, 1);
2928                         status += MXL_SetGPIO(fe, 3, 1);
2929                         status += MXL_SetGPIO(fe, 1, 1);
2930                 }
2931                 if (state->RF_IN >= 760000000 && state->RF_IN <= 900000000) {
2932                         status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
2933                         status += MXL_SetGPIO(fe, 4, 1);
2934                         status += MXL_SetGPIO(fe, 3, 1);
2935                         status += MXL_SetGPIO(fe, 1, 1);
2936                 }
2937         }
2938
2939         if (state->TF_Type == MXL_TF_D) { /* Tracking Filter type D */
2940
2941                 status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
2942
2943                 if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) {
2944                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
2945                         status += MXL_SetGPIO(fe, 4, 0);
2946                         status += MXL_SetGPIO(fe, 1, 1);
2947                         status += MXL_SetGPIO(fe, 3, 1);
2948                 }
2949                 if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) {
2950                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
2951                         status += MXL_SetGPIO(fe, 4, 0);
2952                         status += MXL_SetGPIO(fe, 1, 0);
2953                         status += MXL_SetGPIO(fe, 3, 1);
2954                 }
2955                 if (state->RF_IN >= 250000000 && state->RF_IN < 310000000) {
2956                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
2957                         status += MXL_SetGPIO(fe, 4, 1);
2958                         status += MXL_SetGPIO(fe, 1, 0);
2959                         status += MXL_SetGPIO(fe, 3, 1);
2960                 }
2961                 if (state->RF_IN >= 310000000 && state->RF_IN < 360000000) {
2962                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
2963                         status += MXL_SetGPIO(fe, 4, 1);
2964                         status += MXL_SetGPIO(fe, 1, 0);
2965                         status += MXL_SetGPIO(fe, 3, 0);
2966                 }
2967                 if (state->RF_IN >= 360000000 && state->RF_IN < 470000000) {
2968                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
2969                         status += MXL_SetGPIO(fe, 4, 1);
2970                         status += MXL_SetGPIO(fe, 1, 1);
2971                         status += MXL_SetGPIO(fe, 3, 0);
2972                 }
2973                 if (state->RF_IN >= 470000000 && state->RF_IN < 640000000) {
2974                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
2975                         status += MXL_SetGPIO(fe, 4, 1);
2976                         status += MXL_SetGPIO(fe, 1, 1);
2977                         status += MXL_SetGPIO(fe, 3, 0);
2978                 }
2979                 if (state->RF_IN >= 640000000 && state->RF_IN <= 900000000) {
2980                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
2981                         status += MXL_SetGPIO(fe, 4, 1);
2982                         status += MXL_SetGPIO(fe, 1, 1);
2983                         status += MXL_SetGPIO(fe, 3, 1);
2984                 }
2985         }
2986
2987         if (state->TF_Type == MXL_TF_D_L) {
2988
2989                 /* Tracking Filter type D-L for Lumanate ONLY change 2.6.3 */
2990                 status += MXL_ControlWrite(fe, DAC_DIN_A, 0);
2991
2992                 /* if UHF and terrestrial => Turn off Tracking Filter */
2993                 if (state->RF_IN >= 471000000 &&
2994                         (state->RF_IN - 471000000)%6000000 != 0) {
2995                         /* Turn off all the banks */
2996                         status += MXL_SetGPIO(fe, 3, 1);
2997                         status += MXL_SetGPIO(fe, 1, 1);
2998                         status += MXL_SetGPIO(fe, 4, 1);
2999                         status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
3000                         status += MXL_ControlWrite(fe, AGC_IF, 10);
3001                 } else {
3002                         /* if VHF or cable => Turn on Tracking Filter */
3003                         if (state->RF_IN >= 43000000 &&
3004                                 state->RF_IN < 140000000) {
3005
3006                                 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
3007                                 status += MXL_SetGPIO(fe, 4, 1);
3008                                 status += MXL_SetGPIO(fe, 1, 1);
3009                                 status += MXL_SetGPIO(fe, 3, 0);
3010                         }
3011                         if (state->RF_IN >= 140000000 &&
3012                                 state->RF_IN < 240000000) {
3013                                 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
3014                                 status += MXL_SetGPIO(fe, 4, 1);
3015                                 status += MXL_SetGPIO(fe, 1, 0);
3016                                 status += MXL_SetGPIO(fe, 3, 0);
3017                         }
3018                         if (state->RF_IN >= 240000000 &&
3019                                 state->RF_IN < 340000000) {
3020                                 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
3021                                 status += MXL_SetGPIO(fe, 4, 0);
3022                                 status += MXL_SetGPIO(fe, 1, 1);
3023                                 status += MXL_SetGPIO(fe, 3, 0);
3024                         }
3025                         if (state->RF_IN >= 340000000 &&
3026                                 state->RF_IN < 430000000) {
3027                                 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
3028                                 status += MXL_SetGPIO(fe, 4, 0);
3029                                 status += MXL_SetGPIO(fe, 1, 0);
3030                                 status += MXL_SetGPIO(fe, 3, 1);
3031                         }
3032                         if (state->RF_IN >= 430000000 &&
3033                                 state->RF_IN < 470000000) {
3034                                 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
3035                                 status += MXL_SetGPIO(fe, 4, 1);
3036                                 status += MXL_SetGPIO(fe, 1, 0);
3037                                 status += MXL_SetGPIO(fe, 3, 1);
3038                         }
3039                         if (state->RF_IN >= 470000000 &&
3040                                 state->RF_IN < 570000000) {
3041                                 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
3042                                 status += MXL_SetGPIO(fe, 4, 0);
3043                                 status += MXL_SetGPIO(fe, 1, 0);
3044                                 status += MXL_SetGPIO(fe, 3, 1);
3045                         }
3046                         if (state->RF_IN >= 570000000 &&
3047                                 state->RF_IN < 620000000) {
3048                                 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
3049                                 status += MXL_SetGPIO(fe, 4, 0);
3050                                 status += MXL_SetGPIO(fe, 1, 1);
3051                                 status += MXL_SetGPIO(fe, 3, 1);
3052                         }
3053                         if (state->RF_IN >= 620000000 &&
3054                                 state->RF_IN < 760000000) {
3055                                 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
3056                                 status += MXL_SetGPIO(fe, 4, 0);
3057                                 status += MXL_SetGPIO(fe, 1, 1);
3058                                 status += MXL_SetGPIO(fe, 3, 1);
3059                         }
3060                         if (state->RF_IN >= 760000000 &&
3061                                 state->RF_IN <= 900000000) {
3062                                 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
3063                                 status += MXL_SetGPIO(fe, 4, 1);
3064                                 status += MXL_SetGPIO(fe, 1, 1);
3065                                 status += MXL_SetGPIO(fe, 3, 1);
3066                         }
3067                 }
3068         }
3069
3070         if (state->TF_Type == MXL_TF_E) /* Tracking Filter type E */ {
3071
3072                 status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
3073
3074                 if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) {
3075                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3076                         status += MXL_SetGPIO(fe, 4, 0);
3077                         status += MXL_SetGPIO(fe, 1, 1);
3078                         status += MXL_SetGPIO(fe, 3, 1);
3079                 }
3080                 if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) {
3081                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3082                         status += MXL_SetGPIO(fe, 4, 0);
3083                         status += MXL_SetGPIO(fe, 1, 0);
3084                         status += MXL_SetGPIO(fe, 3, 1);
3085                 }
3086                 if (state->RF_IN >= 250000000 && state->RF_IN < 310000000) {
3087                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3088                         status += MXL_SetGPIO(fe, 4, 1);
3089                         status += MXL_SetGPIO(fe, 1, 0);
3090                         status += MXL_SetGPIO(fe, 3, 1);
3091                 }
3092                 if (state->RF_IN >= 310000000 && state->RF_IN < 360000000) {
3093                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3094                         status += MXL_SetGPIO(fe, 4, 1);
3095                         status += MXL_SetGPIO(fe, 1, 0);
3096                         status += MXL_SetGPIO(fe, 3, 0);
3097                 }
3098                 if (state->RF_IN >= 360000000 && state->RF_IN < 470000000) {
3099                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3100                         status += MXL_SetGPIO(fe, 4, 1);
3101                         status += MXL_SetGPIO(fe, 1, 1);
3102                         status += MXL_SetGPIO(fe, 3, 0);
3103                 }
3104                 if (state->RF_IN >= 470000000 && state->RF_IN < 640000000) {
3105                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3106                         status += MXL_SetGPIO(fe, 4, 1);
3107                         status += MXL_SetGPIO(fe, 1, 1);
3108                         status += MXL_SetGPIO(fe, 3, 0);
3109                 }
3110                 if (state->RF_IN >= 640000000 && state->RF_IN <= 900000000) {
3111                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3112                         status += MXL_SetGPIO(fe, 4, 1);
3113                         status += MXL_SetGPIO(fe, 1, 1);
3114                         status += MXL_SetGPIO(fe, 3, 1);
3115                 }
3116         }
3117
3118         if (state->TF_Type == MXL_TF_F) {
3119
3120                 /* Tracking Filter type F */
3121                 status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
3122
3123                 if (state->RF_IN >= 43000000 && state->RF_IN < 160000000) {
3124                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3125                         status += MXL_SetGPIO(fe, 4, 0);
3126                         status += MXL_SetGPIO(fe, 1, 1);
3127                         status += MXL_SetGPIO(fe, 3, 1);
3128                 }
3129                 if (state->RF_IN >= 160000000 && state->RF_IN < 210000000) {
3130                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3131                         status += MXL_SetGPIO(fe, 4, 0);
3132                         status += MXL_SetGPIO(fe, 1, 0);
3133                         status += MXL_SetGPIO(fe, 3, 1);
3134                 }
3135                 if (state->RF_IN >= 210000000 && state->RF_IN < 300000000) {
3136                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3137                         status += MXL_SetGPIO(fe, 4, 1);
3138                         status += MXL_SetGPIO(fe, 1, 0);
3139                         status += MXL_SetGPIO(fe, 3, 1);
3140                 }
3141                 if (state->RF_IN >= 300000000 && state->RF_IN < 390000000) {
3142                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3143                         status += MXL_SetGPIO(fe, 4, 1);
3144                         status += MXL_SetGPIO(fe, 1, 0);
3145                         status += MXL_SetGPIO(fe, 3, 0);
3146                 }
3147                 if (state->RF_IN >= 390000000 && state->RF_IN < 515000000) {
3148                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3149                         status += MXL_SetGPIO(fe, 4, 1);
3150                         status += MXL_SetGPIO(fe, 1, 1);
3151                         status += MXL_SetGPIO(fe, 3, 0);
3152                 }
3153                 if (state->RF_IN >= 515000000 && state->RF_IN < 650000000) {
3154                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3155                         status += MXL_SetGPIO(fe, 4, 1);
3156                         status += MXL_SetGPIO(fe, 1, 1);
3157                         status += MXL_SetGPIO(fe, 3, 0);
3158                 }
3159                 if (state->RF_IN >= 650000000 && state->RF_IN <= 900000000) {
3160                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3161                         status += MXL_SetGPIO(fe, 4, 1);
3162                         status += MXL_SetGPIO(fe, 1, 1);
3163                         status += MXL_SetGPIO(fe, 3, 1);
3164                 }
3165         }
3166
3167         if (state->TF_Type == MXL_TF_E_2) {
3168
3169                 /* Tracking Filter type E_2 */
3170                 status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
3171
3172                 if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) {
3173                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3174                         status += MXL_SetGPIO(fe, 4, 0);
3175                         status += MXL_SetGPIO(fe, 1, 1);
3176                         status += MXL_SetGPIO(fe, 3, 1);
3177                 }
3178                 if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) {
3179                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3180                         status += MXL_SetGPIO(fe, 4, 0);
3181                         status += MXL_SetGPIO(fe, 1, 0);
3182                         status += MXL_SetGPIO(fe, 3, 1);
3183                 }
3184                 if (state->RF_IN >= 250000000 && state->RF_IN < 350000000) {
3185                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3186                         status += MXL_SetGPIO(fe, 4, 1);
3187                         status += MXL_SetGPIO(fe, 1, 0);
3188                         status += MXL_SetGPIO(fe, 3, 1);
3189                 }
3190                 if (state->RF_IN >= 350000000 && state->RF_IN < 400000000) {
3191                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3192                         status += MXL_SetGPIO(fe, 4, 1);
3193                         status += MXL_SetGPIO(fe, 1, 0);
3194                         status += MXL_SetGPIO(fe, 3, 0);
3195                 }
3196                 if (state->RF_IN >= 400000000 && state->RF_IN < 570000000) {
3197                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3198                         status += MXL_SetGPIO(fe, 4, 1);
3199                         status += MXL_SetGPIO(fe, 1, 1);
3200                         status += MXL_SetGPIO(fe, 3, 0);
3201                 }
3202                 if (state->RF_IN >= 570000000 && state->RF_IN < 770000000) {
3203                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3204                         status += MXL_SetGPIO(fe, 4, 1);
3205                         status += MXL_SetGPIO(fe, 1, 1);
3206                         status += MXL_SetGPIO(fe, 3, 0);
3207                 }
3208                 if (state->RF_IN >= 770000000 && state->RF_IN <= 900000000) {
3209                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3210                         status += MXL_SetGPIO(fe, 4, 1);
3211                         status += MXL_SetGPIO(fe, 1, 1);
3212                         status += MXL_SetGPIO(fe, 3, 1);
3213                 }
3214         }
3215
3216         if (state->TF_Type == MXL_TF_G) {
3217
3218                 /* Tracking Filter type G add for v2.6.8 */
3219                 status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
3220
3221                 if (state->RF_IN >= 50000000 && state->RF_IN < 190000000) {
3222
3223                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3224                         status += MXL_SetGPIO(fe, 4, 0);
3225                         status += MXL_SetGPIO(fe, 1, 1);
3226                         status += MXL_SetGPIO(fe, 3, 1);
3227                 }
3228                 if (state->RF_IN >= 190000000 && state->RF_IN < 280000000) {
3229                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3230                         status += MXL_SetGPIO(fe, 4, 0);
3231                         status += MXL_SetGPIO(fe, 1, 0);
3232                         status += MXL_SetGPIO(fe, 3, 1);
3233                 }
3234                 if (state->RF_IN >= 280000000 && state->RF_IN < 350000000) {
3235                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3236                         status += MXL_SetGPIO(fe, 4, 1);
3237                         status += MXL_SetGPIO(fe, 1, 0);
3238                         status += MXL_SetGPIO(fe, 3, 1);
3239                 }
3240                 if (state->RF_IN >= 350000000 && state->RF_IN < 400000000) {
3241                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3242                         status += MXL_SetGPIO(fe, 4, 1);
3243                         status += MXL_SetGPIO(fe, 1, 0);
3244                         status += MXL_SetGPIO(fe, 3, 0);
3245                 }
3246                 if (state->RF_IN >= 400000000 && state->RF_IN < 470000000) {
3247                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3248                         status += MXL_SetGPIO(fe, 4, 1);
3249                         status += MXL_SetGPIO(fe, 1, 0);
3250                         status += MXL_SetGPIO(fe, 3, 1);
3251                 }
3252                 if (state->RF_IN >= 470000000 && state->RF_IN < 640000000) {
3253                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3254                         status += MXL_SetGPIO(fe, 4, 1);
3255                         status += MXL_SetGPIO(fe, 1, 1);
3256                         status += MXL_SetGPIO(fe, 3, 0);
3257                 }
3258                 if (state->RF_IN >= 640000000 && state->RF_IN < 820000000) {
3259                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3260                         status += MXL_SetGPIO(fe, 4, 1);
3261                         status += MXL_SetGPIO(fe, 1, 1);
3262                         status += MXL_SetGPIO(fe, 3, 0);
3263                 }
3264                 if (state->RF_IN >= 820000000 && state->RF_IN <= 900000000) {
3265                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3266                         status += MXL_SetGPIO(fe, 4, 1);
3267                         status += MXL_SetGPIO(fe, 1, 1);
3268                         status += MXL_SetGPIO(fe, 3, 1);
3269                 }
3270         }
3271
3272         if (state->TF_Type == MXL_TF_E_NA) {
3273
3274                 /* Tracking Filter type E-NA for Empia ONLY change for 2.6.8 */
3275                 status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
3276
3277                 /* if UHF and terrestrial=> Turn off Tracking Filter */
3278                 if (state->RF_IN >= 471000000 &&
3279                         (state->RF_IN - 471000000)%6000000 != 0) {
3280
3281                         /* Turn off all the banks */
3282                         status += MXL_SetGPIO(fe, 3, 1);
3283                         status += MXL_SetGPIO(fe, 1, 1);
3284                         status += MXL_SetGPIO(fe, 4, 1);
3285                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3286
3287                         /* 2.6.12 Turn on RSSI */
3288                         status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
3289                         status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
3290                         status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1);
3291                         status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
3292
3293                         /* RSSI reference point */
3294                         status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5);
3295                         status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3);
3296                         status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 2);
3297
3298                         /* following parameter is from analog OTA mode,
3299                          * can be change to seek better performance */
3300                         status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3);
3301                 } else {
3302                 /* if VHF or Cable =>  Turn on Tracking Filter */
3303
3304                 /* 2.6.12 Turn off RSSI */
3305                 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0);
3306
3307                 /* change back from above condition */
3308                 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 5);
3309
3310
3311                 if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) {
3312
3313                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3314                         status += MXL_SetGPIO(fe, 4, 0);
3315                         status += MXL_SetGPIO(fe, 1, 1);
3316                         status += MXL_SetGPIO(fe, 3, 1);
3317                 }
3318                 if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) {
3319                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3320                         status += MXL_SetGPIO(fe, 4, 0);
3321                         status += MXL_SetGPIO(fe, 1, 0);
3322                         status += MXL_SetGPIO(fe, 3, 1);
3323                 }
3324                 if (state->RF_IN >= 250000000 && state->RF_IN < 350000000) {
3325                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3326                         status += MXL_SetGPIO(fe, 4, 1);
3327                         status += MXL_SetGPIO(fe, 1, 0);
3328                         status += MXL_SetGPIO(fe, 3, 1);
3329                 }
3330                 if (state->RF_IN >= 350000000 && state->RF_IN < 400000000) {
3331                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3332                         status += MXL_SetGPIO(fe, 4, 1);
3333                         status += MXL_SetGPIO(fe, 1, 0);
3334                         status += MXL_SetGPIO(fe, 3, 0);
3335                 }
3336                 if (state->RF_IN >= 400000000 && state->RF_IN < 570000000) {
3337                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3338                         status += MXL_SetGPIO(fe, 4, 1);
3339                         status += MXL_SetGPIO(fe, 1, 1);
3340                         status += MXL_SetGPIO(fe, 3, 0);
3341                 }
3342                 if (state->RF_IN >= 570000000 && state->RF_IN < 770000000) {
3343                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3344                         status += MXL_SetGPIO(fe, 4, 1);
3345                         status += MXL_SetGPIO(fe, 1, 1);
3346                         status += MXL_SetGPIO(fe, 3, 0);
3347                 }
3348                 if (state->RF_IN >= 770000000 && state->RF_IN <= 900000000) {
3349                         status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3350                         status += MXL_SetGPIO(fe, 4, 1);
3351                         status += MXL_SetGPIO(fe, 1, 1);
3352                         status += MXL_SetGPIO(fe, 3, 1);
3353                 }
3354                 }
3355         }
3356         return status ;
3357 }
3358
3359 static u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val)
3360 {
3361         u16 status = 0;
3362
3363         if (GPIO_Num == 1)
3364                 status += MXL_ControlWrite(fe, GPIO_1B, GPIO_Val ? 0 : 1);
3365
3366         /* GPIO2 is not available */
3367
3368         if (GPIO_Num == 3) {
3369                 if (GPIO_Val == 1) {
3370                         status += MXL_ControlWrite(fe, GPIO_3, 0);
3371                         status += MXL_ControlWrite(fe, GPIO_3B, 0);
3372                 }
3373                 if (GPIO_Val == 0) {
3374                         status += MXL_ControlWrite(fe, GPIO_3, 1);
3375                         status += MXL_ControlWrite(fe, GPIO_3B, 1);
3376                 }
3377                 if (GPIO_Val == 3) { /* tri-state */
3378                         status += MXL_ControlWrite(fe, GPIO_3, 0);
3379                         status += MXL_ControlWrite(fe, GPIO_3B, 1);
3380                 }
3381         }
3382         if (GPIO_Num == 4) {
3383                 if (GPIO_Val == 1) {
3384                         status += MXL_ControlWrite(fe, GPIO_4, 0);
3385                         status += MXL_ControlWrite(fe, GPIO_4B, 0);
3386                 }
3387                 if (GPIO_Val == 0) {
3388                         status += MXL_ControlWrite(fe, GPIO_4, 1);
3389                         status += MXL_ControlWrite(fe, GPIO_4B, 1);
3390                 }
3391                 if (GPIO_Val == 3) { /* tri-state */
3392                         status += MXL_ControlWrite(fe, GPIO_4, 0);
3393                         status += MXL_ControlWrite(fe, GPIO_4B, 1);
3394                 }
3395         }
3396
3397         return status;
3398 }
3399
3400 static u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value)
3401 {
3402         u16 status = 0;
3403
3404         /* Will write ALL Matching Control Name */
3405         /* Write Matching INIT Control */
3406         status += MXL_ControlWrite_Group(fe, ControlNum, value, 1);
3407         /* Write Matching CH Control */
3408         status += MXL_ControlWrite_Group(fe, ControlNum, value, 2);
3409 #ifdef _MXL_INTERNAL
3410         /* Write Matching MXL Control */
3411         status += MXL_ControlWrite_Group(fe, ControlNum, value, 3);
3412 #endif
3413         return status;
3414 }
3415
3416 static u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum,
3417         u32 value, u16 controlGroup)
3418 {
3419         struct mxl5005s_state *state = fe->tuner_priv;
3420         u16 i, j, k;
3421         u32 highLimit;
3422         u32 ctrlVal;
3423
3424         if (controlGroup == 1) /* Initial Control */ {
3425
3426                 for (i = 0; i < state->Init_Ctrl_Num; i++) {
3427
3428                         if (controlNum == state->Init_Ctrl[i].Ctrl_Num) {
3429
3430                                 highLimit = 1 << state->Init_Ctrl[i].size;
3431                                 if (value < highLimit) {
3432                                         for (j = 0; j < state->Init_Ctrl[i].size; j++) {
3433                                                 state->Init_Ctrl[i].val[j] = (u8)((value >> j) & 0x01);
3434                                                 MXL_RegWriteBit(fe, (u8)(state->Init_Ctrl[i].addr[j]),
3435                                                         (u8)(state->Init_Ctrl[i].bit[j]),
3436                                                         (u8)((value>>j) & 0x01));
3437                                         }
3438                                         ctrlVal = 0;
3439                                         for (k = 0; k < state->Init_Ctrl[i].size; k++)
3440                                                 ctrlVal += state->Init_Ctrl[i].val[k] * (1 << k);
3441                                 } else
3442                                         return -1;
3443                         }
3444                 }
3445         }
3446         if (controlGroup == 2) /* Chan change Control */ {
3447
3448                 for (i = 0; i < state->CH_Ctrl_Num; i++) {
3449
3450                         if (controlNum == state->CH_Ctrl[i].Ctrl_Num) {
3451
3452                                 highLimit = 1 << state->CH_Ctrl[i].size;
3453                                 if (value < highLimit) {
3454                                         for (j = 0; j < state->CH_Ctrl[i].size; j++) {
3455                                                 state->CH_Ctrl[i].val[j] = (u8)((value >> j) & 0x01);
3456                                                 MXL_RegWriteBit(fe, (u8)(state->CH_Ctrl[i].addr[j]),
3457                                                         (u8)(state->CH_Ctrl[i].bit[j]),
3458                                                         (u8)((value>>j) & 0x01));
3459                                         }
3460                                         ctrlVal = 0;
3461                                         for (k = 0; k < state->CH_Ctrl[i].size; k++)
3462                                                 ctrlVal += state->CH_Ctrl[i].val[k] * (1 << k);
3463                                 } else
3464                                         return -1;
3465                         }
3466                 }
3467         }
3468 #ifdef _MXL_INTERNAL
3469         if (controlGroup == 3) /* Maxlinear Control */ {
3470
3471                 for (i = 0; i < state->MXL_Ctrl_Num; i++) {
3472
3473                         if (controlNum == state->MXL_Ctrl[i].Ctrl_Num) {
3474
3475                                 highLimit = (1 << state->MXL_Ctrl[i].size);
3476                                 if (value < highLimit) {
3477                                         for (j = 0; j < state->MXL_Ctrl[i].size; j++) {
3478                                                 state->MXL_Ctrl[i].val[j] = (u8)((value >> j) & 0x01);
3479                                                 MXL_RegWriteBit(fe, (u8)(state->MXL_Ctrl[i].addr[j]),
3480                                                         (u8)(state->MXL_Ctrl[i].bit[j]),
3481                                                         (u8)((value>>j) & 0x01));
3482                                         }
3483                                         ctrlVal = 0;
3484                                         for (k = 0; k < state->MXL_Ctrl[i].size; k++)
3485                                                 ctrlVal += state->MXL_Ctrl[i].val[k] * (1 << k);
3486                                 } else
3487                                         return -1;
3488                         }
3489                 }
3490         }
3491 #endif
3492         return 0 ; /* successful return */
3493 }
3494
3495 static u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal)
3496 {
3497         struct mxl5005s_state *state = fe->tuner_priv;
3498         int i ;
3499
3500         for (i = 0; i < 104; i++) {
3501                 if (RegNum == state->TunerRegs[i].Reg_Num) {
3502                         state->TunerRegs[i].Reg_Val = RegVal;
3503                         return 0;
3504                 }
3505         }
3506
3507         return 1;
3508 }
3509
3510 static u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal)
3511 {
3512         struct mxl5005s_state *state = fe->tuner_priv;
3513         int i ;
3514
3515         for (i = 0; i < 104; i++) {
3516                 if (RegNum == state->TunerRegs[i].Reg_Num) {
3517                         *RegVal = (u8)(state->TunerRegs[i].Reg_Val);
3518                         return 0;
3519                 }
3520         }
3521
3522         return 1;
3523 }
3524
3525 static u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value)
3526 {
3527         struct mxl5005s_state *state = fe->tuner_priv;
3528         u32 ctrlVal ;
3529         u16 i, k ;
3530
3531         for (i = 0; i < state->Init_Ctrl_Num ; i++) {
3532
3533                 if (controlNum == state->Init_Ctrl[i].Ctrl_Num) {
3534
3535                         ctrlVal = 0;
3536                         for (k = 0; k < state->Init_Ctrl[i].size; k++)
3537                                 ctrlVal += state->Init_Ctrl[i].val[k] * (1<<k);
3538                         *value = ctrlVal;
3539                         return 0;
3540                 }
3541         }
3542
3543         for (i = 0; i < state->CH_Ctrl_Num ; i++) {
3544
3545                 if (controlNum == state->CH_Ctrl[i].Ctrl_Num) {
3546
3547                         ctrlVal = 0;
3548                         for (k = 0; k < state->CH_Ctrl[i].size; k++)
3549                                 ctrlVal += state->CH_Ctrl[i].val[k] * (1 << k);
3550                         *value = ctrlVal;
3551                         return 0;
3552
3553                 }
3554         }
3555
3556 #ifdef _MXL_INTERNAL
3557         for (i = 0; i < state->MXL_Ctrl_Num ; i++) {
3558
3559                 if (controlNum == state->MXL_Ctrl[i].Ctrl_Num) {
3560
3561                         ctrlVal = 0;
3562                         for (k = 0; k < state->MXL_Ctrl[i].size; k++)
3563                                 ctrlVal += state->MXL_Ctrl[i].val[k] * (1<<k);
3564                         *value = ctrlVal;
3565                         return 0;
3566
3567                 }
3568         }
3569 #endif
3570         return 1;
3571 }
3572
3573 static u16 MXL_ControlRegRead(struct dvb_frontend *fe, u16 controlNum,
3574         u8 *RegNum, int *count)
3575 {
3576         struct mxl5005s_state *state = fe->tuner_priv;
3577         u16 i, j, k ;
3578         u16 Count ;
3579
3580         for (i = 0; i < state->Init_Ctrl_Num ; i++) {
3581
3582                 if (controlNum == state->Init_Ctrl[i].Ctrl_Num) {
3583
3584                         Count = 1;
3585                         RegNum[0] = (u8)(state->Init_Ctrl[i].addr[0]);
3586
3587                         for (k = 1; k < state->Init_Ctrl[i].size; k++) {
3588
3589                                 for (j = 0; j < Count; j++) {
3590
3591                                         if (state->Init_Ctrl[i].addr[k] !=
3592                                                 RegNum[j]) {
3593
3594                                                 Count++;
3595                                                 RegNum[Count-1] = (u8)(state->Init_Ctrl[i].addr[k]);
3596
3597                                         }
3598                                 }
3599
3600                         }
3601                         *count = Count;
3602                         return 0;
3603                 }
3604         }
3605         for (i = 0; i < state->CH_Ctrl_Num ; i++) {
3606
3607                 if (controlNum == state->CH_Ctrl[i].Ctrl_Num) {
3608
3609                         Count = 1;
3610                         RegNum[0] = (u8)(state->CH_Ctrl[i].addr[0]);
3611
3612                         for (k = 1; k < state->CH_Ctrl[i].size; k++) {
3613
3614                                 for (j = 0; j < Count; j++) {
3615
3616                                         if (state->CH_Ctrl[i].addr[k] !=
3617                                                 RegNum[j]) {
3618
3619                                                 Count++;
3620                                                 RegNum[Count-1] = (u8)(state->CH_Ctrl[i].addr[k]);
3621
3622                                         }
3623                                 }
3624                         }
3625                         *count = Count;
3626                         return 0;
3627                 }
3628         }
3629 #ifdef _MXL_INTERNAL
3630         for (i = 0; i < state->MXL_Ctrl_Num ; i++) {
3631
3632                 if (controlNum == state->MXL_Ctrl[i].Ctrl_Num) {
3633
3634                         Count = 1;
3635                         RegNum[0] = (u8)(state->MXL_Ctrl[i].addr[0]);
3636
3637                         for (k = 1; k < state->MXL_Ctrl[i].size; k++) {
3638
3639                                 for (j = 0; j < Count; j++) {
3640
3641                                         if (state->MXL_Ctrl[i].addr[k] !=
3642                                                 RegNum[j]) {
3643
3644                                                 Count++;
3645                                                 RegNum[Count-1] = (u8)state->MXL_Ctrl[i].addr[k];
3646
3647                                         }
3648                                 }
3649                         }
3650                         *count = Count;
3651                         return 0;
3652                 }
3653         }
3654 #endif
3655         *count = 0;
3656         return 1;
3657 }
3658
3659 static void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit,
3660         u8 bitVal)
3661 {
3662         struct mxl5005s_state *state = fe->tuner_priv;
3663         int i ;
3664
3665         const u8 AND_MAP[8] = {
3666                 0xFE, 0xFD, 0xFB, 0xF7,
3667                 0xEF, 0xDF, 0xBF, 0x7F } ;
3668
3669         const u8 OR_MAP[8] = {
3670                 0x01, 0x02, 0x04, 0x08,
3671                 0x10, 0x20, 0x40, 0x80 } ;
3672
3673         for (i = 0; i < state->TunerRegs_Num; i++) {
3674                 if (state->TunerRegs[i].Reg_Num == address) {
3675                         if (bitVal)
3676                                 state->TunerRegs[i].Reg_Val |= OR_MAP[bit];
3677                         else
3678                                 state->TunerRegs[i].Reg_Val &= AND_MAP[bit];
3679                         break ;
3680                 }
3681         }
3682 }
3683
3684 static u32 MXL_Ceiling(u32 value, u32 resolution)
3685 {
3686         return (value/resolution + (value % resolution > 0 ? 1 : 0));
3687 }
3688
3689 /* Retrieve the Initialzation Registers */
3690 static u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 *RegNum,
3691         u8 *RegVal, int *count)
3692 {
3693         u16 status = 0;
3694         int i ;
3695
3696         u8 RegAddr[] = {
3697                 11, 12, 13, 22, 32, 43, 44, 53, 56, 59, 73,
3698                 76, 77, 91, 134, 135, 137, 147,
3699                 156, 166, 167, 168, 25 };
3700
3701         *count = sizeof(RegAddr) / sizeof(u8);
3702
3703         status += MXL_BlockInit(fe);
3704
3705         for (i = 0 ; i < *count; i++) {
3706                 RegNum[i] = RegAddr[i];
3707                 status += MXL_RegRead(fe, RegNum[i], &RegVal[i]);
3708         }
3709
3710         return status;
3711 }
3712
3713 static u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal,
3714         int *count)
3715 {
3716         u16 status = 0;
3717         int i ;
3718
3719 /* add 77, 166, 167, 168 register for 2.6.12 */
3720 #ifdef _MXL_PRODUCTION
3721         u8 RegAddr[] = {14, 15, 16, 17, 22, 43, 65, 68, 69, 70, 73, 92, 93, 106,
3722            107, 108, 109, 110, 111, 112, 136, 138, 149, 77, 166, 167, 168 } ;
3723 #else
3724         u8 RegAddr[] = {14, 15, 16, 17, 22, 43, 68, 69, 70, 73, 92, 93, 106,
3725            107, 108, 109, 110, 111, 112, 136, 138, 149, 77, 166, 167, 168 } ;
3726         /*
3727         u8 RegAddr[171];
3728         for (i = 0; i <= 170; i++)
3729                 RegAddr[i] = i;
3730         */
3731 #endif
3732
3733         *count = sizeof(RegAddr) / sizeof(u8);
3734
3735         for (i = 0 ; i < *count; i++) {
3736                 RegNum[i] = RegAddr[i];
3737                 status += MXL_RegRead(fe, RegNum[i], &RegVal[i]);
3738         }
3739
3740         return status;
3741 }
3742
3743 static u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum,
3744         u8 *RegVal, int *count)
3745 {
3746         u16 status = 0;
3747         int i;
3748
3749         u8 RegAddr[] = {43, 136};
3750
3751         *count = sizeof(RegAddr) / sizeof(u8);
3752
3753         for (i = 0; i < *count; i++) {
3754                 RegNum[i] = RegAddr[i];
3755                 status += MXL_RegRead(fe, RegNum[i], &RegVal[i]);
3756         }
3757
3758         return status;
3759 }
3760
3761 static u16 MXL_GetCHRegister_LowIF(struct dvb_frontend *fe, u8 *RegNum,
3762         u8 *RegVal, int *count)
3763 {
3764         u16 status = 0;
3765         int i;
3766
3767         u8 RegAddr[] = { 138 };
3768
3769         *count = sizeof(RegAddr) / sizeof(u8);
3770
3771         for (i = 0; i < *count; i++) {
3772                 RegNum[i] = RegAddr[i];
3773                 status += MXL_RegRead(fe, RegNum[i], &RegVal[i]);
3774         }
3775
3776         return status;
3777 }
3778
3779 static u16 MXL_GetMasterControl(u8 *MasterReg, int state)
3780 {
3781         if (state == 1) /* Load_Start */
3782                 *MasterReg = 0xF3;
3783         if (state == 2) /* Power_Down */
3784                 *MasterReg = 0x41;
3785         if (state == 3) /* Synth_Reset */
3786                 *MasterReg = 0xB1;
3787         if (state == 4) /* Seq_Off */
3788                 *MasterReg = 0xF1;
3789
3790         return 0;
3791 }
3792
3793 #ifdef _MXL_PRODUCTION
3794 static u16 MXL_VCORange_Test(struct dvb_frontend *fe, int VCO_Range)
3795 {
3796         struct mxl5005s_state *state = fe->tuner_priv;
3797         u16 status = 0 ;
3798
3799         if (VCO_Range == 1) {
3800                 status += MXL_ControlWrite(fe, RFSYN_EN_DIV, 1);
3801                 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
3802                 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
3803                 status += MXL_ControlWrite(fe, RFSYN_DIVM, 1);
3804                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
3805                 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
3806                 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
3807                 if (state->Mode == 0 && state->IF_Mode == 1) {
3808                         /* Analog Low IF Mode */
3809                         status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
3810                         status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
3811                         status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 56);
3812                         status += MXL_ControlWrite(fe,
3813                                 CHCAL_FRAC_MOD_RF, 180224);
3814                 }
3815                 if (state->Mode == 0 && state->IF_Mode == 0) {
3816                         /* Analog Zero IF Mode */
3817                         status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
3818                         status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
3819                         status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 56);
3820                         status += MXL_ControlWrite(fe,
3821                                 CHCAL_FRAC_MOD_RF, 222822);
3822                 }
3823                 if (state->Mode == 1) /* Digital Mode */ {
3824                         status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
3825                         status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
3826                         status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 56);
3827                         status += MXL_ControlWrite(fe,
3828                                 CHCAL_FRAC_MOD_RF, 229376);
3829                 }
3830         }
3831
3832         if (VCO_Range == 2) {
3833                 status += MXL_ControlWrite(fe, RFSYN_EN_DIV, 1);
3834                 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
3835                 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
3836                 status += MXL_ControlWrite(fe, RFSYN_DIVM, 1);
3837                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
3838                 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
3839                 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
3840                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
3841                 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
3842                 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 41);
3843                 if (state->Mode == 0 && state->IF_Mode == 1) {
3844                         /* Analog Low IF Mode */
3845                         status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
3846                         status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
3847                         status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42);
3848                         status += MXL_ControlWrite(fe,
3849                                 CHCAL_FRAC_MOD_RF, 206438);
3850                 }
3851                 if (state->Mode == 0 && state->IF_Mode == 0) {
3852                         /* Analog Zero IF Mode */
3853                         status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
3854                         status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
3855                         status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42);
3856                         status += MXL_ControlWrite(fe,
3857                                 CHCAL_FRAC_MOD_RF, 206438);
3858                 }
3859                 if (state->Mode == 1) /* Digital Mode */ {
3860                         status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
3861                         status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
3862                         status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 41);
3863                         status += MXL_ControlWrite(fe,
3864                                 CHCAL_FRAC_MOD_RF, 16384);
3865                 }
3866         }
3867
3868         if (VCO_Range == 3) {
3869                 status += MXL_ControlWrite(fe, RFSYN_EN_DIV, 1);
3870                 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
3871                 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
3872                 status += MXL_ControlWrite(fe, RFSYN_DIVM, 1);
3873                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
3874                 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
3875                 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
3876                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
3877                 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
3878                 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42);
3879                 if (state->Mode == 0 && state->IF_Mode == 1) {
3880                         /* Analog Low IF Mode */
3881                         status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
3882                         status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
3883                         status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 44);
3884                         status += MXL_ControlWrite(fe,
3885                                 CHCAL_FRAC_MOD_RF, 173670);
3886                 }
3887                 if (state->Mode == 0 && state->IF_Mode == 0) {
3888                         /* Analog Zero IF Mode */
3889                         status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
3890                         status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
3891                         status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 44);
3892                         status += MXL_ControlWrite(fe,
3893                                 CHCAL_FRAC_MOD_RF, 173670);
3894                 }
3895                 if (state->Mode == 1) /* Digital Mode */ {
3896                         status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
3897                         status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
3898                         status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42);
3899                         status += MXL_ControlWrite(fe,
3900                                 CHCAL_FRAC_MOD_RF, 245760);
3901                 }
3902         }
3903
3904         if (VCO_Range == 4) {
3905                 status += MXL_ControlWrite(fe, RFSYN_EN_DIV, 1);
3906                 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
3907                 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
3908                 status += MXL_ControlWrite(fe, RFSYN_DIVM, 1);
3909                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
3910                 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
3911                 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
3912                 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
3913                 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
3914                 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27);
3915                 if (state->Mode == 0 && state->IF_Mode == 1) {
3916                         /* Analog Low IF Mode */
3917                         status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
3918                         status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
3919                         status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27);
3920                         status += MXL_ControlWrite(fe,
3921                                 CHCAL_FRAC_MOD_RF, 206438);
3922                 }
3923                 if (state->Mode == 0 && state->IF_Mode == 0) {
3924                         /* Analog Zero IF Mode */
3925                         status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
3926                         status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
3927                         status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27);
3928                         status += MXL_ControlWrite(fe,
3929                                 CHCAL_FRAC_MOD_RF, 206438);
3930                 }
3931                 if (state->Mode == 1) /* Digital Mode */ {
3932                         status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
3933                         status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
3934                         status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27);
3935                         status += MXL_ControlWrite(fe,
3936                                 CHCAL_FRAC_MOD_RF, 212992);
3937                 }
3938         }
3939
3940         return status;
3941 }
3942
3943 static u16 MXL_Hystersis_Test(struct dvb_frontend *fe, int Hystersis)
3944 {
3945         struct mxl5005s_state *state = fe->tuner_priv;
3946         u16 status = 0;
3947
3948         if (Hystersis == 1)
3949                 status += MXL_ControlWrite(fe, DN_BYPASS_AGC_I2C, 1);
3950
3951         return status;
3952 }
3953 #endif
3954 /* End: Reference driver code found in the Realtek driver that
3955  * is copyright MaxLinear */
3956
3957 /* ----------------------------------------------------------------
3958  * Begin: Everything after here is new code to adapt the
3959  * proprietary Realtek driver into a Linux API tuner.
3960  * Copyright (C) 2008 Steven Toth <stoth@hauppauge.com>
3961  */
3962 static int mxl5005s_reset(struct dvb_frontend *fe)
3963 {
3964         struct mxl5005s_state *state = fe->tuner_priv;
3965         int ret = 0;
3966
3967         u8 buf[2] = { 0xff, 0x00 };
3968         struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0,
3969                                .buf = buf, .len = 2 };
3970
3971         dprintk(2, "%s()\n", __func__);
3972
3973         if (fe->ops.i2c_gate_ctrl)
3974                 fe->ops.i2c_gate_ctrl(fe, 1);
3975
3976         if (i2c_transfer(state->i2c, &msg, 1) != 1) {
3977                 printk(KERN_WARNING "mxl5005s I2C reset failed\n");
3978                 ret = -EREMOTEIO;
3979         }
3980
3981         if (fe->ops.i2c_gate_ctrl)
3982                 fe->ops.i2c_gate_ctrl(fe, 0);
3983
3984         return ret;
3985 }
3986
3987 /* Write a single byte to a single reg, latch the value if required by
3988  * following the transaction with the latch byte.
3989  */
3990 static int mxl5005s_writereg(struct dvb_frontend *fe, u8 reg, u8 val, int latch)
3991 {
3992         struct mxl5005s_state *state = fe->tuner_priv;
3993         u8 buf[3] = { reg, val, MXL5005S_LATCH_BYTE };
3994         struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0,
3995                                .buf = buf, .len = 3 };
3996
3997         if (latch == 0)
3998                 msg.len = 2;
3999
4000         dprintk(2, "%s(0x%x, 0x%x, 0x%x)\n", __func__, reg, val, msg.addr);
4001
4002         if (i2c_transfer(state->i2c, &msg, 1) != 1) {
4003                 printk(KERN_WARNING "mxl5005s I2C write failed\n");
4004                 return -EREMOTEIO;
4005         }
4006         return 0;
4007 }
4008
4009 static int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable,
4010         u8 *datatable, u8 len)
4011 {
4012         int ret = 0, i;
4013
4014         if (fe->ops.i2c_gate_ctrl)
4015                 fe->ops.i2c_gate_ctrl(fe, 1);
4016
4017         for (i = 0 ; i < len-1; i++) {
4018                 ret = mxl5005s_writereg(fe, addrtable[i], datatable[i], 0);
4019                 if (ret < 0)
4020                         break;
4021         }
4022
4023         ret = mxl5005s_writereg(fe, addrtable[i], datatable[i], 1);
4024
4025         if (fe->ops.i2c_gate_ctrl)
4026                 fe->ops.i2c_gate_ctrl(fe, 0);
4027
4028         return ret;
4029 }
4030
4031 static int mxl5005s_init(struct dvb_frontend *fe)
4032 {
4033         dprintk(1, "%s()\n", __func__);
4034         return mxl5005s_reconfigure(fe, MXL_QAM, MXL5005S_BANDWIDTH_6MHZ);
4035 }
4036
4037 static int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type,
4038         u32 bandwidth)
4039 {
4040         struct mxl5005s_state *state = fe->tuner_priv;
4041
4042         u8 AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX];
4043         u8 ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX];
4044         int TableLen;
4045
4046         dprintk(1, "%s(type=%d, bw=%d)\n", __func__, mod_type, bandwidth);
4047
4048         mxl5005s_reset(fe);
4049
4050         /* Tuner initialization stage 0 */
4051         MXL_GetMasterControl(ByteTable, MC_SYNTH_RESET);
4052         AddrTable[0] = MASTER_CONTROL_ADDR;
4053         ByteTable[0] |= state->config->AgcMasterByte;
4054
4055         mxl5005s_writeregs(fe, AddrTable, ByteTable, 1);
4056
4057         mxl5005s_AssignTunerMode(fe, mod_type, bandwidth);
4058
4059         /* Tuner initialization stage 1 */
4060         MXL_GetInitRegister(fe, AddrTable, ByteTable, &TableLen);
4061
4062         mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen);
4063
4064         return 0;
4065 }
4066
4067 static int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type,
4068         u32 bandwidth)
4069 {
4070         struct mxl5005s_state *state = fe->tuner_priv;
4071         struct mxl5005s_config *c = state->config;
4072
4073         InitTunerControls(fe);
4074
4075         /* Set MxL5005S parameters. */
4076         MXL5005_TunerConfig(
4077                 fe,
4078                 c->mod_mode,
4079                 c->if_mode,
4080                 bandwidth,
4081                 c->if_freq,
4082                 c->xtal_freq,
4083                 c->agc_mode,
4084                 c->top,
4085                 c->output_load,
4086                 c->clock_out,
4087                 c->div_out,
4088                 c->cap_select,
4089                 c->rssi_enable,
4090                 mod_type,
4091                 c->tracking_filter);
4092
4093         return 0;
4094 }
4095
4096 static int mxl5005s_set_params(struct dvb_frontend *fe,
4097                                struct dvb_frontend_parameters *params)
4098 {
4099         struct mxl5005s_state *state = fe->tuner_priv;
4100         u32 req_mode, req_bw = 0;
4101         int ret;
4102
4103         dprintk(1, "%s()\n", __func__);
4104
4105         if (fe->ops.info.type == FE_ATSC) {
4106                 switch (params->u.vsb.modulation) {
4107                 case VSB_8:
4108                         req_mode = MXL_ATSC; break;
4109                 default:
4110                 case QAM_64:
4111                 case QAM_256:
4112                 case QAM_AUTO:
4113                         req_mode = MXL_QAM; break;
4114                 }
4115         } else
4116                 req_mode = MXL_DVBT;
4117
4118         /* Change tuner for new modulation type if reqd */
4119         if (req_mode != state->current_mode) {
4120                 switch (req_mode) {
4121                 case VSB_8:
4122                 case QAM_64:
4123                 case QAM_256:
4124                 case QAM_AUTO:
4125                         req_bw  = MXL5005S_BANDWIDTH_6MHZ;
4126                         break;
4127                 default:
4128                         /* Assume DVB-T */
4129                         switch (params->u.ofdm.bandwidth) {
4130                         case BANDWIDTH_6_MHZ:
4131                                 req_bw  = MXL5005S_BANDWIDTH_6MHZ;
4132                                 break;
4133                         case BANDWIDTH_7_MHZ:
4134                                 req_bw  = MXL5005S_BANDWIDTH_7MHZ;
4135                                 break;
4136                         case BANDWIDTH_AUTO:
4137                         case BANDWIDTH_8_MHZ:
4138                                 req_bw  = MXL5005S_BANDWIDTH_8MHZ;
4139                                 break;
4140                         }
4141                 }
4142
4143                 state->current_mode = req_mode;
4144                 ret = mxl5005s_reconfigure(fe, req_mode, req_bw);
4145
4146         } else
4147                 ret = 0;
4148
4149         if (ret == 0) {
4150                 dprintk(1, "%s() freq=%d\n", __func__, params->frequency);
4151                 ret = mxl5005s_SetRfFreqHz(fe, params->frequency);
4152         }
4153
4154         return ret;
4155 }
4156
4157 static int mxl5005s_get_frequency(struct dvb_frontend *fe, u32 *frequency)
4158 {
4159         struct mxl5005s_state *state = fe->tuner_priv;
4160         dprintk(1, "%s()\n", __func__);
4161
4162         *frequency = state->RF_IN;
4163
4164         return 0;
4165 }
4166
4167 static int mxl5005s_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
4168 {
4169         struct mxl5005s_state *state = fe->tuner_priv;
4170         dprintk(1, "%s()\n", __func__);
4171
4172         *bandwidth = state->Chan_Bandwidth;
4173
4174         return 0;
4175 }
4176
4177 static int mxl5005s_release(struct dvb_frontend *fe)
4178 {
4179         dprintk(1, "%s()\n", __func__);
4180         kfree(fe->tuner_priv);
4181         fe->tuner_priv = NULL;
4182         return 0;
4183 }
4184
4185 static const struct dvb_tuner_ops mxl5005s_tuner_ops = {
4186         .info = {
4187                 .name           = "MaxLinear MXL5005S",
4188                 .frequency_min  =  48000000,
4189                 .frequency_max  = 860000000,
4190                 .frequency_step =     50000,
4191         },
4192
4193         .release       = mxl5005s_release,
4194         .init          = mxl5005s_init,
4195
4196         .set_params    = mxl5005s_set_params,
4197         .get_frequency = mxl5005s_get_frequency,
4198         .get_bandwidth = mxl5005s_get_bandwidth,
4199 };
4200
4201 struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe,
4202                                      struct i2c_adapter *i2c,
4203                                      struct mxl5005s_config *config)
4204 {
4205         struct mxl5005s_state *state = NULL;
4206         dprintk(1, "%s()\n", __func__);
4207
4208         state = kzalloc(sizeof(struct mxl5005s_state), GFP_KERNEL);
4209         if (state == NULL)
4210                 return NULL;
4211
4212         state->frontend = fe;
4213         state->config = config;
4214         state->i2c = i2c;
4215         state->current_mode = MXL_QAM;
4216
4217         printk(KERN_INFO "MXL5005S: Attached at address 0x%02x\n",
4218                 config->i2c_address);
4219
4220         memcpy(&fe->ops.tuner_ops, &mxl5005s_tuner_ops,
4221                 sizeof(struct dvb_tuner_ops));
4222
4223         fe->tuner_priv = state;
4224         return fe;
4225 }
4226 EXPORT_SYMBOL(mxl5005s_attach);
4227
4228 MODULE_DESCRIPTION("MaxLinear MXL5005S silicon tuner driver");
4229 MODULE_AUTHOR("Steven Toth");
4230 MODULE_LICENSE("GPL");