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   1 /*
   2  *  linux/drivers/ide/pci/slc90e66.c    Version 0.12    May 12, 2006
   3  *
   4  *  Copyright (C) 2000-2002 Andre Hedrick <andre@linux-ide.org>
   5  *  Copyright (C) 2006 MontaVista Software, Inc. <source@mvista.com>
   6  *
   7  * This is a look-alike variation of the ICH0 PIIX4 Ultra-66,
   8  * but this keeps the ISA-Bridge and slots alive.
   9  *
  10  */
  11
  12 #include <linux/types.h>
  13 #include <linux/module.h>
  14 #include <linux/kernel.h>
  15 #include <linux/ioport.h>
  16 #include <linux/pci.h>
  17 #include <linux/hdreg.h>
  18 #include <linux/ide.h>
  19 #include <linux/delay.h>
  20 #include <linux/init.h>
  21
  22 #include <asm/io.h>
  23
  24 static u8 slc90e66_ratemask (ide_drive_t *drive)
  25 {
  26         u8 mode = 2;
  27
  28         if (!eighty_ninty_three(drive))
  29                 mode = min(mode, (u8)1);
  30         return mode;
  31 }
  32
  33 static u8 slc90e66_dma_2_pio (u8 xfer_rate) {
  34         switch(xfer_rate) {
  35                 case XFER_UDMA_4:
  36                 case XFER_UDMA_3:
  37                 case XFER_UDMA_2:
  38                 case XFER_UDMA_1:
  39                 case XFER_UDMA_0:
  40                 case XFER_MW_DMA_2:
  41                 case XFER_PIO_4:
  42                         return 4;
  43                 case XFER_MW_DMA_1:
  44                 case XFER_PIO_3:
  45                         return 3;
  46                 case XFER_SW_DMA_2:
  47                 case XFER_PIO_2:
  48                         return 2;
  49                 case XFER_MW_DMA_0:
  50                 case XFER_SW_DMA_1:
  51                 case XFER_SW_DMA_0:
  52                 case XFER_PIO_1:
  53                 case XFER_PIO_0:
  54                 case XFER_PIO_SLOW:
  55                 default:
  56                         return 0;
  57         }
  58 }
  59
  60 /*
  61  *  Based on settings done by AMI BIOS
  62  *  (might be useful if drive is not registered in CMOS for any reason).
  63  */
  64 static void slc90e66_tune_drive (ide_drive_t *drive, u8 pio)
  65 {
  66         ide_hwif_t *hwif        = HWIF(drive);
  67         struct pci_dev *dev     = hwif->pci_dev;
  68         int is_slave            = (&hwif->drives[1] == drive);
  69         int master_port         = hwif->channel ? 0x42 : 0x40;
  70         int slave_port          = 0x44;
  71         unsigned long flags;
  72         u16 master_data;
  73         u8 slave_data;
  74                                  /* ISP  RTC */
  75         static const u8 timings[][2]= {
  76                                     { 0, 0 },
  77                                     { 0, 0 },
  78                                     { 1, 0 },
  79                                     { 2, 1 },
  80                                     { 2, 3 }, };
  81
  82         pio = ide_get_best_pio_mode(drive, pio, 5, NULL);
  83         spin_lock_irqsave(&ide_lock, flags);
  84         pci_read_config_word(dev, master_port, &master_data);
  85         if (is_slave) {
  86                 master_data = master_data | 0x4000;
  87                 if (pio > 1)
  88                         /* enable PPE, IE and TIME */
  89                         master_data = master_data | 0x0070;
  90                 pci_read_config_byte(dev, slave_port, &slave_data);
  91                 slave_data = slave_data & (hwif->channel ? 0x0f : 0xf0);
  92                 slave_data = slave_data | (((timings[pio][0] << 2) | timings[pio][1]) << (hwif->channel ? 4 : 0));
  93         } else {
  94                 master_data = master_data & 0xccf8;
  95                 if (pio > 1)
  96                         /* enable PPE, IE and TIME */
  97                         master_data = master_data | 0x0007;
  98                 master_data = master_data | (timings[pio][0] << 12) | (timings[pio][1] << 8);
  99         }
 100         pci_write_config_word(dev, master_port, master_data);
 101         if (is_slave)
 102                 pci_write_config_byte(dev, slave_port, slave_data);
 103         spin_unlock_irqrestore(&ide_lock, flags);
 104 }
 105
 106 static int slc90e66_tune_chipset (ide_drive_t *drive, u8 xferspeed)
 107 {
 108         ide_hwif_t *hwif        = HWIF(drive);
 109         struct pci_dev *dev     = hwif->pci_dev;
 110         u8 maslave              = hwif->channel ? 0x42 : 0x40;
 111         u8 speed        = ide_rate_filter(slc90e66_ratemask(drive), xferspeed);
 112         int sitre = 0, a_speed  = 7 << (drive->dn * 4);
 113         int u_speed = 0, u_flag = 1 << drive->dn;
 114         u16                     reg4042, reg44, reg48, reg4a;
 115
 116         pci_read_config_word(dev, maslave, &reg4042);
 117         sitre = (reg4042 & 0x4000) ? 1 : 0;
 118         pci_read_config_word(dev, 0x44, &reg44);
 119         pci_read_config_word(dev, 0x48, &reg48);
 120         pci_read_config_word(dev, 0x4a, &reg4a);
 121
 122         switch(speed) {
 123                 case XFER_UDMA_4:       u_speed = 4 << (drive->dn * 4); break;
 124                 case XFER_UDMA_3:       u_speed = 3 << (drive->dn * 4); break;
 125                 case XFER_UDMA_2:       u_speed = 2 << (drive->dn * 4); break;
 126                 case XFER_UDMA_1:       u_speed = 1 << (drive->dn * 4); break;
 127                 case XFER_UDMA_0:       u_speed = 0 << (drive->dn * 4); break;
 128                 case XFER_MW_DMA_2:
 129                 case XFER_MW_DMA_1:
 130                 case XFER_SW_DMA_2:     break;
 131                 case XFER_PIO_4:
 132                 case XFER_PIO_3:
 133                 case XFER_PIO_2:
 134                 case XFER_PIO_0:        break;
 135                 default:                return -1;
 136         }
 137
 138         if (speed >= XFER_UDMA_0) {
 139                 if (!(reg48 & u_flag))
 140                         pci_write_config_word(dev, 0x48, reg48|u_flag);
 141                 /* FIXME: (reg4a & a_speed) ? */
 142                 if ((reg4a & u_speed) != u_speed) {
 143                         pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
 144                         pci_read_config_word(dev, 0x4a, &reg4a);
 145                         pci_write_config_word(dev, 0x4a, reg4a|u_speed);
 146                 }
 147         } else {
 148                 if (reg48 & u_flag)
 149                         pci_write_config_word(dev, 0x48, reg48 & ~u_flag);
 150                 if (reg4a & a_speed)
 151                         pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
 152         }
 153
 154         slc90e66_tune_drive(drive, slc90e66_dma_2_pio(speed));
 155         return (ide_config_drive_speed(drive, speed));
 156 }
 157
 158 static int slc90e66_config_drive_for_dma (ide_drive_t *drive)
 159 {
 160         u8 speed = ide_dma_speed(drive, slc90e66_ratemask(drive));
 161
 162         if (!speed)
 163                 return 0;
 164
 165         (void) slc90e66_tune_chipset(drive, speed);
 166         return ide_dma_enable(drive);
 167 }
 168
 169 static int slc90e66_config_drive_xfer_rate (ide_drive_t *drive)
 170 {
 171         ide_hwif_t *hwif        = HWIF(drive);
 172         struct hd_driveid *id   = drive->id;
 173
 174         drive->init_speed = 0;
 175
 176         if (id && (id->capability & 1) && drive->autodma) {
 177
 178                 if (ide_use_dma(drive) && slc90e66_config_drive_for_dma(drive))
 179                         return hwif->ide_dma_on(drive);
 180
 181                 goto fast_ata_pio;
 182
 183         } else if ((id->capability & 8) || (id->field_valid & 2)) {
 184 fast_ata_pio:
 185                 (void) hwif->speedproc(drive, XFER_PIO_0 +
 186                                        ide_get_best_pio_mode(drive, 255, 4, NULL));
 187                 return hwif->ide_dma_off_quietly(drive);
 188         }
 189         /* IORDY not supported */
 190         return 0;
 191 }
 192
 193 static void __devinit init_hwif_slc90e66 (ide_hwif_t *hwif)
 194 {
 195         u8 reg47 = 0;
 196         u8 mask = hwif->channel ? 0x01 : 0x02;  /* bit0:Primary */
 197
 198         hwif->autodma = 0;
 199
 200         if (!hwif->irq)
 201                 hwif->irq = hwif->channel ? 15 : 14;
 202
 203         hwif->speedproc = &slc90e66_tune_chipset;
 204         hwif->tuneproc = &slc90e66_tune_drive;
 205
 206         pci_read_config_byte(hwif->pci_dev, 0x47, &reg47);
 207
 208         if (!hwif->dma_base) {
 209                 hwif->drives[0].autotune = 1;
 210                 hwif->drives[1].autotune = 1;
 211                 return;
 212         }
 213
 214         hwif->atapi_dma = 1;
 215         hwif->ultra_mask = 0x1f;
 216         hwif->mwdma_mask = 0x07;
 217         hwif->swdma_mask = 0x07;
 218
 219         if (!(hwif->udma_four))
 220                 /* bit[0(1)]: 0:80, 1:40 */
 221                 hwif->udma_four = (reg47 & mask) ? 0 : 1;
 222
 223         hwif->ide_dma_check = &slc90e66_config_drive_xfer_rate;
 224         if (!noautodma)
 225                 hwif->autodma = 1;
 226         hwif->drives[0].autodma = hwif->autodma;
 227         hwif->drives[1].autodma = hwif->autodma;
 228 }
 229
 230 static ide_pci_device_t slc90e66_chipset __devinitdata = {
 231         .name           = "SLC90E66",
 232         .init_hwif      = init_hwif_slc90e66,
 233         .channels       = 2,
 234         .autodma        = AUTODMA,
 235         .enablebits     = {{0x41,0x80,0x80}, {0x43,0x80,0x80}},
 236         .bootable       = ON_BOARD,
 237 };
 238
 239 static int __devinit slc90e66_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 240 {
 241         return ide_setup_pci_device(dev, &slc90e66_chipset);
 242 }
 243
 244 static struct pci_device_id slc90e66_pci_tbl[] = {
 245         { PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1), 0},
 246         { 0, },
 247 };
 248 MODULE_DEVICE_TABLE(pci, slc90e66_pci_tbl);
 249
 250 static struct pci_driver driver = {
 251         .name           = "SLC90e66_IDE",
 252         .id_table       = slc90e66_pci_tbl,
 253         .probe          = slc90e66_init_one,
 254 };
 255
 256 static int __init slc90e66_ide_init(void)
 257 {
 258         return ide_pci_register_driver(&driver);
 259 }
 260
 261 module_init(slc90e66_ide_init);
 262
 263 MODULE_AUTHOR("Andre Hedrick");
 264 MODULE_DESCRIPTION("PCI driver module for SLC90E66 IDE");
 265 MODULE_LICENSE("GPL");