git.oblomov.eu Git - linux-2.6/blob - drivers/net/typhoon.c

   1 /* typhoon.c: A Linux Ethernet device driver for 3Com 3CR990 family of NICs */
   2 /*
   3         Written 2002-2004 by David Dillow <dave@thedillows.org>
   4         Based on code written 1998-2000 by Donald Becker <becker@scyld.com> and
   5         Linux 2.2.x driver by David P. McLean <davidpmclean@yahoo.com>.
   6
   7         This software may be used and distributed according to the terms of
   8         the GNU General Public License (GPL), incorporated herein by reference.
   9         Drivers based on or derived from this code fall under the GPL and must
  10         retain the authorship, copyright and license notice.  This file is not
  11         a complete program and may only be used when the entire operating
  12         system is licensed under the GPL.
  13
  14         This software is available on a public web site. It may enable
  15         cryptographic capabilities of the 3Com hardware, and may be
  16         exported from the United States under License Exception "TSU"
  17         pursuant to 15 C.F.R. Section 740.13(e).
  18
  19         This work was funded by the National Library of Medicine under
  20         the Department of Energy project number 0274DD06D1 and NLM project
  21         number Y1-LM-2015-01.
  22
  23         This driver is designed for the 3Com 3CR990 Family of cards with the
  24         3XP Processor. It has been tested on x86 and sparc64.
  25
  26         KNOWN ISSUES:
  27         *) The current firmware always strips the VLAN tag off, even if
  28                 we tell it not to. You should filter VLANs at the switch
  29                 as a workaround (good practice in any event) until we can
  30                 get this fixed.
  31         *) Cannot DMA Rx packets to a 2 byte aligned address. Also firmware
  32                 issue. Hopefully 3Com will fix it.
  33         *) Waiting for a command response takes 8ms due to non-preemptable
  34                 polling. Only significant for getting stats and creating
  35                 SAs, but an ugly wart never the less.
  36
  37         TODO:
  38         *) Doesn't do IPSEC offloading. Yet. Keep yer pants on, it's coming.
  39         *) Add more support for ethtool (especially for NIC stats)
  40         *) Allow disabling of RX checksum offloading
  41         *) Fix MAC changing to work while the interface is up
  42                 (Need to put commands on the TX ring, which changes
  43                 the locking)
  44         *) Add in FCS to {rx,tx}_bytes, since the hardware doesn't. See
  45                 http://oss.sgi.com/cgi-bin/mesg.cgi?a=netdev&i=20031215152211.7003fe8e.rddunlap%40osdl.org
  46 */
  47
  48 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
  49  * Setting to > 1518 effectively disables this feature.
  50  */
  51 static int rx_copybreak = 200;
  52
  53 /* Should we use MMIO or Port IO?
  54  * 0: Port IO
  55  * 1: MMIO
  56  * 2: Try MMIO, fallback to Port IO
  57  */
  58 static unsigned int use_mmio = 2;
  59
  60 /* end user-configurable values */
  61
  62 /* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
  63  */
  64 static const int multicast_filter_limit = 32;
  65
  66 /* Operational parameters that are set at compile time. */
  67
  68 /* Keep the ring sizes a power of two for compile efficiency.
  69  * The compiler will convert <unsigned>'%'<2^N> into a bit mask.
  70  * Making the Tx ring too large decreases the effectiveness of channel
  71  * bonding and packet priority.
  72  * There are no ill effects from too-large receive rings.
  73  *
  74  * We don't currently use the Hi Tx ring so, don't make it very big.
  75  *
  76  * Beware that if we start using the Hi Tx ring, we will need to change
  77  * typhoon_num_free_tx() and typhoon_tx_complete() to account for that.
  78  */
  79 #define TXHI_ENTRIES            2
  80 #define TXLO_ENTRIES            128
  81 #define RX_ENTRIES              32
  82 #define COMMAND_ENTRIES         16
  83 #define RESPONSE_ENTRIES        32
  84
  85 #define COMMAND_RING_SIZE       (COMMAND_ENTRIES * sizeof(struct cmd_desc))
  86 #define RESPONSE_RING_SIZE      (RESPONSE_ENTRIES * sizeof(struct resp_desc))
  87
  88 /* The 3XP will preload and remove 64 entries from the free buffer
  89  * list, and we need one entry to keep the ring from wrapping, so
  90  * to keep this a power of two, we use 128 entries.
  91  */
  92 #define RXFREE_ENTRIES          128
  93 #define RXENT_ENTRIES           (RXFREE_ENTRIES - 1)
  94
  95 /* Operational parameters that usually are not changed. */
  96
  97 /* Time in jiffies before concluding the transmitter is hung. */
  98 #define TX_TIMEOUT  (2*HZ)
  99
 100 #define PKT_BUF_SZ              1536
 101
 102 #define DRV_MODULE_NAME         "typhoon"
 103 #define DRV_MODULE_VERSION      "1.5.8"
 104 #define DRV_MODULE_RELDATE      "06/11/09"
 105 #define PFX                     DRV_MODULE_NAME ": "
 106 #define ERR_PFX                 KERN_ERR PFX
 107
 108 #include <linux/module.h>
 109 #include <linux/kernel.h>
 110 #include <linux/string.h>
 111 #include <linux/timer.h>
 112 #include <linux/errno.h>
 113 #include <linux/ioport.h>
 114 #include <linux/slab.h>
 115 #include <linux/interrupt.h>
 116 #include <linux/pci.h>
 117 #include <linux/netdevice.h>
 118 #include <linux/etherdevice.h>
 119 #include <linux/skbuff.h>
 120 #include <linux/mm.h>
 121 #include <linux/init.h>
 122 #include <linux/delay.h>
 123 #include <linux/ethtool.h>
 124 #include <linux/if_vlan.h>
 125 #include <linux/crc32.h>
 126 #include <linux/bitops.h>
 127 #include <asm/processor.h>
 128 #include <asm/io.h>
 129 #include <asm/uaccess.h>
 130 #include <linux/in6.h>
 131 #include <linux/version.h>
 132 #include <linux/dma-mapping.h>
 133
 134 #include "typhoon.h"
 135 #include "typhoon-firmware.h"
 136
 137 static char version[] __devinitdata =
 138     "typhoon.c: version " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 139
 140 MODULE_AUTHOR("David Dillow <dave@thedillows.org>");
 141 MODULE_VERSION(DRV_MODULE_VERSION);
 142 MODULE_LICENSE("GPL");
 143 MODULE_DESCRIPTION("3Com Typhoon Family (3C990, 3CR990, and variants)");
 144 MODULE_PARM_DESC(rx_copybreak, "Packets smaller than this are copied and "
 145                                "the buffer given back to the NIC. Default "
 146                                "is 200.");
 147 MODULE_PARM_DESC(use_mmio, "Use MMIO (1) or PIO(0) to access the NIC. "
 148                            "Default is to try MMIO and fallback to PIO.");
 149 module_param(rx_copybreak, int, 0);
 150 module_param(use_mmio, int, 0);
 151
 152 #if defined(NETIF_F_TSO) && MAX_SKB_FRAGS > 32
 153 #warning Typhoon only supports 32 entries in its SG list for TSO, disabling TSO
 154 #undef NETIF_F_TSO
 155 #endif
 156
 157 #if TXLO_ENTRIES <= (2 * MAX_SKB_FRAGS)
 158 #error TX ring too small!
 159 #endif
 160
 161 struct typhoon_card_info {
 162         char *name;
 163         int capabilities;
 164 };
 165
 166 #define TYPHOON_CRYPTO_NONE             0x00
 167 #define TYPHOON_CRYPTO_DES              0x01
 168 #define TYPHOON_CRYPTO_3DES             0x02
 169 #define TYPHOON_CRYPTO_VARIABLE         0x04
 170 #define TYPHOON_FIBER                   0x08
 171 #define TYPHOON_WAKEUP_NEEDS_RESET      0x10
 172
 173 enum typhoon_cards {
 174         TYPHOON_TX = 0, TYPHOON_TX95, TYPHOON_TX97, TYPHOON_SVR,
 175         TYPHOON_SVR95, TYPHOON_SVR97, TYPHOON_TXM, TYPHOON_BSVR,
 176         TYPHOON_FX95, TYPHOON_FX97, TYPHOON_FX95SVR, TYPHOON_FX97SVR,
 177         TYPHOON_FXM,
 178 };
 179
 180 /* directly indexed by enum typhoon_cards, above */
 181 static struct typhoon_card_info typhoon_card_info[] __devinitdata = {
 182         { "3Com Typhoon (3C990-TX)",
 183                 TYPHOON_CRYPTO_NONE},
 184         { "3Com Typhoon (3CR990-TX-95)",
 185                 TYPHOON_CRYPTO_DES},
 186         { "3Com Typhoon (3CR990-TX-97)",
 187                 TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES},
 188         { "3Com Typhoon (3C990SVR)",
 189                 TYPHOON_CRYPTO_NONE},
 190         { "3Com Typhoon (3CR990SVR95)",
 191                 TYPHOON_CRYPTO_DES},
 192         { "3Com Typhoon (3CR990SVR97)",
 193                 TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES},
 194         { "3Com Typhoon2 (3C990B-TX-M)",
 195                 TYPHOON_CRYPTO_VARIABLE},
 196         { "3Com Typhoon2 (3C990BSVR)",
 197                 TYPHOON_CRYPTO_VARIABLE},
 198         { "3Com Typhoon (3CR990-FX-95)",
 199                 TYPHOON_CRYPTO_DES | TYPHOON_FIBER},
 200         { "3Com Typhoon (3CR990-FX-97)",
 201                 TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES | TYPHOON_FIBER},
 202         { "3Com Typhoon (3CR990-FX-95 Server)",
 203                 TYPHOON_CRYPTO_DES | TYPHOON_FIBER},
 204         { "3Com Typhoon (3CR990-FX-97 Server)",
 205                 TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES | TYPHOON_FIBER},
 206         { "3Com Typhoon2 (3C990B-FX-97)",
 207                 TYPHOON_CRYPTO_VARIABLE | TYPHOON_FIBER},
 208 };
 209
 210 /* Notes on the new subsystem numbering scheme:
 211  * bits 0-1 indicate crypto capabilities: (0) variable, (1) DES, or (2) 3DES
 212  * bit 4 indicates if this card has secured firmware (we don't support it)
 213  * bit 8 indicates if this is a (0) copper or (1) fiber card
 214  * bits 12-16 indicate card type: (0) client and (1) server
 215  */
 216 static struct pci_device_id typhoon_pci_tbl[] = {
 217         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990,
 218           PCI_ANY_ID, PCI_ANY_ID, 0, 0,TYPHOON_TX },
 219         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_TX_95,
 220           PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_TX95 },
 221         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_TX_97,
 222           PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_TX97 },
 223         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990B,
 224           PCI_ANY_ID, 0x1000, 0, 0, TYPHOON_TXM },
 225         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990B,
 226           PCI_ANY_ID, 0x1102, 0, 0, TYPHOON_FXM },
 227         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990B,
 228           PCI_ANY_ID, 0x2000, 0, 0, TYPHOON_BSVR },
 229         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
 230           PCI_ANY_ID, 0x1101, 0, 0, TYPHOON_FX95 },
 231         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
 232           PCI_ANY_ID, 0x1102, 0, 0, TYPHOON_FX97 },
 233         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
 234           PCI_ANY_ID, 0x2101, 0, 0, TYPHOON_FX95SVR },
 235         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
 236           PCI_ANY_ID, 0x2102, 0, 0, TYPHOON_FX97SVR },
 237         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990SVR95,
 238           PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_SVR95 },
 239         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990SVR97,
 240           PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_SVR97 },
 241         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990SVR,
 242           PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_SVR },
 243         { 0, }
 244 };
 245 MODULE_DEVICE_TABLE(pci, typhoon_pci_tbl);
 246
 247 /* Define the shared memory area
 248  * Align everything the 3XP will normally be using.
 249  * We'll need to move/align txHi if we start using that ring.
 250  */
 251 #define __3xp_aligned   ____cacheline_aligned
 252 struct typhoon_shared {
 253         struct typhoon_interface        iface;
 254         struct typhoon_indexes          indexes                 __3xp_aligned;
 255         struct tx_desc                  txLo[TXLO_ENTRIES]      __3xp_aligned;
 256         struct rx_desc                  rxLo[RX_ENTRIES]        __3xp_aligned;
 257         struct rx_desc                  rxHi[RX_ENTRIES]        __3xp_aligned;
 258         struct cmd_desc                 cmd[COMMAND_ENTRIES]    __3xp_aligned;
 259         struct resp_desc                resp[RESPONSE_ENTRIES]  __3xp_aligned;
 260         struct rx_free                  rxBuff[RXFREE_ENTRIES]  __3xp_aligned;
 261         u32                             zeroWord;
 262         struct tx_desc                  txHi[TXHI_ENTRIES];
 263 } __attribute__ ((packed));
 264
 265 struct rxbuff_ent {
 266         struct sk_buff *skb;
 267         dma_addr_t      dma_addr;
 268 };
 269
 270 struct typhoon {
 271         /* Tx cache line section */
 272         struct transmit_ring    txLoRing        ____cacheline_aligned;
 273         struct pci_dev *        tx_pdev;
 274         void __iomem            *tx_ioaddr;
 275         u32                     txlo_dma_addr;
 276
 277         /* Irq/Rx cache line section */
 278         void __iomem            *ioaddr         ____cacheline_aligned;
 279         struct typhoon_indexes *indexes;
 280         u8                      awaiting_resp;
 281         u8                      duplex;
 282         u8                      speed;
 283         u8                      card_state;
 284         struct basic_ring       rxLoRing;
 285         struct pci_dev *        pdev;
 286         struct net_device *     dev;
 287         struct napi_struct      napi;
 288         spinlock_t              state_lock;
 289         struct vlan_group *     vlgrp;
 290         struct basic_ring       rxHiRing;
 291         struct basic_ring       rxBuffRing;
 292         struct rxbuff_ent       rxbuffers[RXENT_ENTRIES];
 293
 294         /* general section */
 295         spinlock_t              command_lock    ____cacheline_aligned;
 296         struct basic_ring       cmdRing;
 297         struct basic_ring       respRing;
 298         struct net_device_stats stats;
 299         struct net_device_stats stats_saved;
 300         const char *            name;
 301         struct typhoon_shared * shared;
 302         dma_addr_t              shared_dma;
 303         __le16                  xcvr_select;
 304         __le16                  wol_events;
 305         __le32                  offload;
 306
 307         /* unused stuff (future use) */
 308         int                     capabilities;
 309         struct transmit_ring    txHiRing;
 310 };
 311
 312 enum completion_wait_values {
 313         NoWait = 0, WaitNoSleep, WaitSleep,
 314 };
 315
 316 /* These are the values for the typhoon.card_state variable.
 317  * These determine where the statistics will come from in get_stats().
 318  * The sleep image does not support the statistics we need.
 319  */
 320 enum state_values {
 321         Sleeping = 0, Running,
 322 };
 323
 324 /* PCI writes are not guaranteed to be posted in order, but outstanding writes
 325  * cannot pass a read, so this forces current writes to post.
 326  */
 327 #define typhoon_post_pci_writes(x) \
 328         do { if(likely(use_mmio)) ioread32(x+TYPHOON_REG_HEARTBEAT); } while(0)
 329
 330 /* We'll wait up to six seconds for a reset, and half a second normally.
 331  */
 332 #define TYPHOON_UDELAY                  50
 333 #define TYPHOON_RESET_TIMEOUT_SLEEP     (6 * HZ)
 334 #define TYPHOON_RESET_TIMEOUT_NOSLEEP   ((6 * 1000000) / TYPHOON_UDELAY)
 335 #define TYPHOON_WAIT_TIMEOUT            ((1000000 / 2) / TYPHOON_UDELAY)
 336
 337 #if defined(NETIF_F_TSO)
 338 #define skb_tso_size(x)         (skb_shinfo(x)->gso_size)
 339 #define TSO_NUM_DESCRIPTORS     2
 340 #define TSO_OFFLOAD_ON          TYPHOON_OFFLOAD_TCP_SEGMENT
 341 #else
 342 #define NETIF_F_TSO             0
 343 #define skb_tso_size(x)         0
 344 #define TSO_NUM_DESCRIPTORS     0
 345 #define TSO_OFFLOAD_ON          0
 346 #endif
 347
 348 static inline void
 349 typhoon_inc_index(u32 *index, const int count, const int num_entries)
 350 {
 351         /* Increment a ring index -- we can use this for all rings execept
 352          * the Rx rings, as they use different size descriptors
 353          * otherwise, everything is the same size as a cmd_desc
 354          */
 355         *index += count * sizeof(struct cmd_desc);
 356         *index %= num_entries * sizeof(struct cmd_desc);
 357 }
 358
 359 static inline void
 360 typhoon_inc_cmd_index(u32 *index, const int count)
 361 {
 362         typhoon_inc_index(index, count, COMMAND_ENTRIES);
 363 }
 364
 365 static inline void
 366 typhoon_inc_resp_index(u32 *index, const int count)
 367 {
 368         typhoon_inc_index(index, count, RESPONSE_ENTRIES);
 369 }
 370
 371 static inline void
 372 typhoon_inc_rxfree_index(u32 *index, const int count)
 373 {
 374         typhoon_inc_index(index, count, RXFREE_ENTRIES);
 375 }
 376
 377 static inline void
 378 typhoon_inc_tx_index(u32 *index, const int count)
 379 {
 380         /* if we start using the Hi Tx ring, this needs updateing */
 381         typhoon_inc_index(index, count, TXLO_ENTRIES);
 382 }
 383
 384 static inline void
 385 typhoon_inc_rx_index(u32 *index, const int count)
 386 {
 387         /* sizeof(struct rx_desc) != sizeof(struct cmd_desc) */
 388         *index += count * sizeof(struct rx_desc);
 389         *index %= RX_ENTRIES * sizeof(struct rx_desc);
 390 }
 391
 392 static int
 393 typhoon_reset(void __iomem *ioaddr, int wait_type)
 394 {
 395         int i, err = 0;
 396         int timeout;
 397
 398         if(wait_type == WaitNoSleep)
 399                 timeout = TYPHOON_RESET_TIMEOUT_NOSLEEP;
 400         else
 401                 timeout = TYPHOON_RESET_TIMEOUT_SLEEP;
 402
 403         iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
 404         iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);
 405
 406         iowrite32(TYPHOON_RESET_ALL, ioaddr + TYPHOON_REG_SOFT_RESET);
 407         typhoon_post_pci_writes(ioaddr);
 408         udelay(1);
 409         iowrite32(TYPHOON_RESET_NONE, ioaddr + TYPHOON_REG_SOFT_RESET);
 410
 411         if(wait_type != NoWait) {
 412                 for(i = 0; i < timeout; i++) {
 413                         if(ioread32(ioaddr + TYPHOON_REG_STATUS) ==
 414                            TYPHOON_STATUS_WAITING_FOR_HOST)
 415                                 goto out;
 416
 417                         if(wait_type == WaitSleep)
 418                                 schedule_timeout_uninterruptible(1);
 419                         else
 420                                 udelay(TYPHOON_UDELAY);
 421                 }
 422
 423                 err = -ETIMEDOUT;
 424         }
 425
 426 out:
 427         iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
 428         iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);
 429
 430         /* The 3XP seems to need a little extra time to complete the load
 431          * of the sleep image before we can reliably boot it. Failure to
 432          * do this occasionally results in a hung adapter after boot in
 433          * typhoon_init_one() while trying to read the MAC address or
 434          * putting the card to sleep. 3Com's driver waits 5ms, but
 435          * that seems to be overkill. However, if we can sleep, we might
 436          * as well give it that much time. Otherwise, we'll give it 500us,
 437          * which should be enough (I've see it work well at 100us, but still
 438          * saw occasional problems.)
 439          */
 440         if(wait_type == WaitSleep)
 441                 msleep(5);
 442         else
 443                 udelay(500);
 444         return err;
 445 }
 446
 447 static int
 448 typhoon_wait_status(void __iomem *ioaddr, u32 wait_value)
 449 {
 450         int i, err = 0;
 451
 452         for(i = 0; i < TYPHOON_WAIT_TIMEOUT; i++) {
 453                 if(ioread32(ioaddr + TYPHOON_REG_STATUS) == wait_value)
 454                         goto out;
 455                 udelay(TYPHOON_UDELAY);
 456         }
 457
 458         err = -ETIMEDOUT;
 459
 460 out:
 461         return err;
 462 }
 463
 464 static inline void
 465 typhoon_media_status(struct net_device *dev, struct resp_desc *resp)
 466 {
 467         if(resp->parm1 & TYPHOON_MEDIA_STAT_NO_LINK)
 468                 netif_carrier_off(dev);
 469         else
 470                 netif_carrier_on(dev);
 471 }
 472
 473 static inline void
 474 typhoon_hello(struct typhoon *tp)
 475 {
 476         struct basic_ring *ring = &tp->cmdRing;
 477         struct cmd_desc *cmd;
 478
 479         /* We only get a hello request if we've not sent anything to the
 480          * card in a long while. If the lock is held, then we're in the
 481          * process of issuing a command, so we don't need to respond.
 482          */
 483         if(spin_trylock(&tp->command_lock)) {
 484                 cmd = (struct cmd_desc *)(ring->ringBase + ring->lastWrite);
 485                 typhoon_inc_cmd_index(&ring->lastWrite, 1);
 486
 487                 INIT_COMMAND_NO_RESPONSE(cmd, TYPHOON_CMD_HELLO_RESP);
 488                 smp_wmb();
 489                 iowrite32(ring->lastWrite, tp->ioaddr + TYPHOON_REG_CMD_READY);
 490                 spin_unlock(&tp->command_lock);
 491         }
 492 }
 493
 494 static int
 495 typhoon_process_response(struct typhoon *tp, int resp_size,
 496                                 struct resp_desc *resp_save)
 497 {
 498         struct typhoon_indexes *indexes = tp->indexes;
 499         struct resp_desc *resp;
 500         u8 *base = tp->respRing.ringBase;
 501         int count, len, wrap_len;
 502         u32 cleared;
 503         u32 ready;
 504
 505         cleared = le32_to_cpu(indexes->respCleared);
 506         ready = le32_to_cpu(indexes->respReady);
 507         while(cleared != ready) {
 508                 resp = (struct resp_desc *)(base + cleared);
 509                 count = resp->numDesc + 1;
 510                 if(resp_save && resp->seqNo) {
 511                         if(count > resp_size) {
 512                                 resp_save->flags = TYPHOON_RESP_ERROR;
 513                                 goto cleanup;
 514                         }
 515
 516                         wrap_len = 0;
 517                         len = count * sizeof(*resp);
 518                         if(unlikely(cleared + len > RESPONSE_RING_SIZE)) {
 519                                 wrap_len = cleared + len - RESPONSE_RING_SIZE;
 520                                 len = RESPONSE_RING_SIZE - cleared;
 521                         }
 522
 523                         memcpy(resp_save, resp, len);
 524                         if(unlikely(wrap_len)) {
 525                                 resp_save += len / sizeof(*resp);
 526                                 memcpy(resp_save, base, wrap_len);
 527                         }
 528
 529                         resp_save = NULL;
 530                 } else if(resp->cmd == TYPHOON_CMD_READ_MEDIA_STATUS) {
 531                         typhoon_media_status(tp->dev, resp);
 532                 } else if(resp->cmd == TYPHOON_CMD_HELLO_RESP) {
 533                         typhoon_hello(tp);
 534                 } else {
 535                         printk(KERN_ERR "%s: dumping unexpected response "
 536                                "0x%04x:%d:0x%02x:0x%04x:%08x:%08x\n",
 537                                tp->name, le16_to_cpu(resp->cmd),
 538                                resp->numDesc, resp->flags,
 539                                le16_to_cpu(resp->parm1),
 540                                le32_to_cpu(resp->parm2),
 541                                le32_to_cpu(resp->parm3));
 542                 }
 543
 544 cleanup:
 545                 typhoon_inc_resp_index(&cleared, count);
 546         }
 547
 548         indexes->respCleared = cpu_to_le32(cleared);
 549         wmb();
 550         return (resp_save == NULL);
 551 }
 552
 553 static inline int
 554 typhoon_num_free(int lastWrite, int lastRead, int ringSize)
 555 {
 556         /* this works for all descriptors but rx_desc, as they are a
 557          * different size than the cmd_desc -- everyone else is the same
 558          */
 559         lastWrite /= sizeof(struct cmd_desc);
 560         lastRead /= sizeof(struct cmd_desc);
 561         return (ringSize + lastRead - lastWrite - 1) % ringSize;
 562 }
 563
 564 static inline int
 565 typhoon_num_free_cmd(struct typhoon *tp)
 566 {
 567         int lastWrite = tp->cmdRing.lastWrite;
 568         int cmdCleared = le32_to_cpu(tp->indexes->cmdCleared);
 569
 570         return typhoon_num_free(lastWrite, cmdCleared, COMMAND_ENTRIES);
 571 }
 572
 573 static inline int
 574 typhoon_num_free_resp(struct typhoon *tp)
 575 {
 576         int respReady = le32_to_cpu(tp->indexes->respReady);
 577         int respCleared = le32_to_cpu(tp->indexes->respCleared);
 578
 579         return typhoon_num_free(respReady, respCleared, RESPONSE_ENTRIES);
 580 }
 581
 582 static inline int
 583 typhoon_num_free_tx(struct transmit_ring *ring)
 584 {
 585         /* if we start using the Hi Tx ring, this needs updating */
 586         return typhoon_num_free(ring->lastWrite, ring->lastRead, TXLO_ENTRIES);
 587 }
 588
 589 static int
 590 typhoon_issue_command(struct typhoon *tp, int num_cmd, struct cmd_desc *cmd,
 591                       int num_resp, struct resp_desc *resp)
 592 {
 593         struct typhoon_indexes *indexes = tp->indexes;
 594         struct basic_ring *ring = &tp->cmdRing;
 595         struct resp_desc local_resp;
 596         int i, err = 0;
 597         int got_resp;
 598         int freeCmd, freeResp;
 599         int len, wrap_len;
 600
 601         spin_lock(&tp->command_lock);
 602
 603         freeCmd = typhoon_num_free_cmd(tp);
 604         freeResp = typhoon_num_free_resp(tp);
 605
 606         if(freeCmd < num_cmd || freeResp < num_resp) {
 607                 printk("%s: no descs for cmd, had (needed) %d (%d) cmd, "
 608                         "%d (%d) resp\n", tp->name, freeCmd, num_cmd,
 609                         freeResp, num_resp);
 610                 err = -ENOMEM;
 611                 goto out;
 612         }
 613
 614         if(cmd->flags & TYPHOON_CMD_RESPOND) {
 615                 /* If we're expecting a response, but the caller hasn't given
 616                  * us a place to put it, we'll provide one.
 617                  */
 618                 tp->awaiting_resp = 1;
 619                 if(resp == NULL) {
 620                         resp = &local_resp;
 621                         num_resp = 1;
 622                 }
 623         }
 624
 625         wrap_len = 0;
 626         len = num_cmd * sizeof(*cmd);
 627         if(unlikely(ring->lastWrite + len > COMMAND_RING_SIZE)) {
 628                 wrap_len = ring->lastWrite + len - COMMAND_RING_SIZE;
 629                 len = COMMAND_RING_SIZE - ring->lastWrite;
 630         }
 631
 632         memcpy(ring->ringBase + ring->lastWrite, cmd, len);
 633         if(unlikely(wrap_len)) {
 634                 struct cmd_desc *wrap_ptr = cmd;
 635                 wrap_ptr += len / sizeof(*cmd);
 636                 memcpy(ring->ringBase, wrap_ptr, wrap_len);
 637         }
 638
 639         typhoon_inc_cmd_index(&ring->lastWrite, num_cmd);
 640
 641         /* "I feel a presence... another warrior is on the mesa."
 642          */
 643         wmb();
 644         iowrite32(ring->lastWrite, tp->ioaddr + TYPHOON_REG_CMD_READY);
 645         typhoon_post_pci_writes(tp->ioaddr);
 646
 647         if((cmd->flags & TYPHOON_CMD_RESPOND) == 0)
 648                 goto out;
 649
 650         /* Ugh. We'll be here about 8ms, spinning our thumbs, unable to
 651          * preempt or do anything other than take interrupts. So, don't
 652          * wait for a response unless you have to.
 653          *
 654          * I've thought about trying to sleep here, but we're called
 655          * from many contexts that don't allow that. Also, given the way
 656          * 3Com has implemented irq coalescing, we would likely timeout --
 657          * this has been observed in real life!
 658          *
 659          * The big killer is we have to wait to get stats from the card,
 660          * though we could go to a periodic refresh of those if we don't
 661          * mind them getting somewhat stale. The rest of the waiting
 662          * commands occur during open/close/suspend/resume, so they aren't
 663          * time critical. Creating SAs in the future will also have to
 664          * wait here.
 665          */
 666         got_resp = 0;
 667         for(i = 0; i < TYPHOON_WAIT_TIMEOUT && !got_resp; i++) {
 668                 if(indexes->respCleared != indexes->respReady)
 669                         got_resp = typhoon_process_response(tp, num_resp,
 670                                                                 resp);
 671                 udelay(TYPHOON_UDELAY);
 672         }
 673
 674         if(!got_resp) {
 675                 err = -ETIMEDOUT;
 676                 goto out;
 677         }
 678
 679         /* Collect the error response even if we don't care about the
 680          * rest of the response
 681          */
 682         if(resp->flags & TYPHOON_RESP_ERROR)
 683                 err = -EIO;
 684
 685 out:
 686         if(tp->awaiting_resp) {
 687                 tp->awaiting_resp = 0;
 688                 smp_wmb();
 689
 690                 /* Ugh. If a response was added to the ring between
 691                  * the call to typhoon_process_response() and the clearing
 692                  * of tp->awaiting_resp, we could have missed the interrupt
 693                  * and it could hang in the ring an indeterminate amount of
 694                  * time. So, check for it, and interrupt ourselves if this
 695                  * is the case.
 696                  */
 697                 if(indexes->respCleared != indexes->respReady)
 698                         iowrite32(1, tp->ioaddr + TYPHOON_REG_SELF_INTERRUPT);
 699         }
 700
 701         spin_unlock(&tp->command_lock);
 702         return err;
 703 }
 704
 705 static void
 706 typhoon_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
 707 {
 708         struct typhoon *tp = netdev_priv(dev);
 709         struct cmd_desc xp_cmd;
 710         int err;
 711
 712         spin_lock_bh(&tp->state_lock);
 713         if(!tp->vlgrp != !grp) {
 714                 /* We've either been turned on for the first time, or we've
 715                  * been turned off. Update the 3XP.
 716                  */
 717                 if(grp)
 718                         tp->offload |= TYPHOON_OFFLOAD_VLAN;
 719                 else
 720                         tp->offload &= ~TYPHOON_OFFLOAD_VLAN;
 721
 722                 /* If the interface is up, the runtime is running -- and we
 723                  * must be up for the vlan core to call us.
 724                  *
 725                  * Do the command outside of the spin lock, as it is slow.
 726                  */
 727                 INIT_COMMAND_WITH_RESPONSE(&xp_cmd,
 728                                         TYPHOON_CMD_SET_OFFLOAD_TASKS);
 729                 xp_cmd.parm2 = tp->offload;
 730                 xp_cmd.parm3 = tp->offload;
 731                 spin_unlock_bh(&tp->state_lock);
 732                 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
 733                 if(err < 0)
 734                         printk("%s: vlan offload error %d\n", tp->name, -err);
 735                 spin_lock_bh(&tp->state_lock);
 736         }
 737
 738         /* now make the change visible */
 739         tp->vlgrp = grp;
 740         spin_unlock_bh(&tp->state_lock);
 741 }
 742
 743 static inline void
 744 typhoon_tso_fill(struct sk_buff *skb, struct transmit_ring *txRing,
 745                         u32 ring_dma)
 746 {
 747         struct tcpopt_desc *tcpd;
 748         u32 tcpd_offset = ring_dma;
 749
 750         tcpd = (struct tcpopt_desc *) (txRing->ringBase + txRing->lastWrite);
 751         tcpd_offset += txRing->lastWrite;
 752         tcpd_offset += offsetof(struct tcpopt_desc, bytesTx);
 753         typhoon_inc_tx_index(&txRing->lastWrite, 1);
 754
 755         tcpd->flags = TYPHOON_OPT_DESC | TYPHOON_OPT_TCP_SEG;
 756         tcpd->numDesc = 1;
 757         tcpd->mss_flags = cpu_to_le16(skb_tso_size(skb));
 758         tcpd->mss_flags |= TYPHOON_TSO_FIRST | TYPHOON_TSO_LAST;
 759         tcpd->respAddrLo = cpu_to_le32(tcpd_offset);
 760         tcpd->bytesTx = cpu_to_le32(skb->len);
 761         tcpd->status = 0;
 762 }
 763
 764 static int
 765 typhoon_start_tx(struct sk_buff *skb, struct net_device *dev)
 766 {
 767         struct typhoon *tp = netdev_priv(dev);
 768         struct transmit_ring *txRing;
 769         struct tx_desc *txd, *first_txd;
 770         dma_addr_t skb_dma;
 771         int numDesc;
 772
 773         /* we have two rings to choose from, but we only use txLo for now
 774          * If we start using the Hi ring as well, we'll need to update
 775          * typhoon_stop_runtime(), typhoon_interrupt(), typhoon_num_free_tx(),
 776          * and TXHI_ENTRIES to match, as well as update the TSO code below
 777          * to get the right DMA address
 778          */
 779         txRing = &tp->txLoRing;
 780
 781         /* We need one descriptor for each fragment of the sk_buff, plus the
 782          * one for the ->data area of it.
 783          *
 784          * The docs say a maximum of 16 fragment descriptors per TCP option
 785          * descriptor, then make a new packet descriptor and option descriptor
 786          * for the next 16 fragments. The engineers say just an option
 787          * descriptor is needed. I've tested up to 26 fragments with a single
 788          * packet descriptor/option descriptor combo, so I use that for now.
 789          *
 790          * If problems develop with TSO, check this first.
 791          */
 792         numDesc = skb_shinfo(skb)->nr_frags + 1;
 793         if (skb_is_gso(skb))
 794                 numDesc++;
 795
 796         /* When checking for free space in the ring, we need to also
 797          * account for the initial Tx descriptor, and we always must leave
 798          * at least one descriptor unused in the ring so that it doesn't
 799          * wrap and look empty.
 800          *
 801          * The only time we should loop here is when we hit the race
 802          * between marking the queue awake and updating the cleared index.
 803          * Just loop and it will appear. This comes from the acenic driver.
 804          */
 805         while(unlikely(typhoon_num_free_tx(txRing) < (numDesc + 2)))
 806                 smp_rmb();
 807
 808         first_txd = (struct tx_desc *) (txRing->ringBase + txRing->lastWrite);
 809         typhoon_inc_tx_index(&txRing->lastWrite, 1);
 810
 811         first_txd->flags = TYPHOON_TX_DESC | TYPHOON_DESC_VALID;
 812         first_txd->numDesc = 0;
 813         first_txd->len = 0;
 814         first_txd->tx_addr = (u64)((unsigned long) skb);
 815         first_txd->processFlags = 0;
 816
 817         if(skb->ip_summed == CHECKSUM_PARTIAL) {
 818                 /* The 3XP will figure out if this is UDP/TCP */
 819                 first_txd->processFlags |= TYPHOON_TX_PF_TCP_CHKSUM;
 820                 first_txd->processFlags |= TYPHOON_TX_PF_UDP_CHKSUM;
 821                 first_txd->processFlags |= TYPHOON_TX_PF_IP_CHKSUM;
 822         }
 823
 824         if(vlan_tx_tag_present(skb)) {
 825                 first_txd->processFlags |=
 826                     TYPHOON_TX_PF_INSERT_VLAN | TYPHOON_TX_PF_VLAN_PRIORITY;
 827                 first_txd->processFlags |=
 828                     cpu_to_le32(ntohs(vlan_tx_tag_get(skb)) <<
 829                                 TYPHOON_TX_PF_VLAN_TAG_SHIFT);
 830         }
 831
 832         if (skb_is_gso(skb)) {
 833                 first_txd->processFlags |= TYPHOON_TX_PF_TCP_SEGMENT;
 834                 first_txd->numDesc++;
 835
 836                 typhoon_tso_fill(skb, txRing, tp->txlo_dma_addr);
 837         }
 838
 839         txd = (struct tx_desc *) (txRing->ringBase + txRing->lastWrite);
 840         typhoon_inc_tx_index(&txRing->lastWrite, 1);
 841
 842         /* No need to worry about padding packet -- the firmware pads
 843          * it with zeros to ETH_ZLEN for us.
 844          */
 845         if(skb_shinfo(skb)->nr_frags == 0) {
 846                 skb_dma = pci_map_single(tp->tx_pdev, skb->data, skb->len,
 847                                        PCI_DMA_TODEVICE);
 848                 txd->flags = TYPHOON_FRAG_DESC | TYPHOON_DESC_VALID;
 849                 txd->len = cpu_to_le16(skb->len);
 850                 txd->frag.addr = cpu_to_le32(skb_dma);
 851                 txd->frag.addrHi = 0;
 852                 first_txd->numDesc++;
 853         } else {
 854                 int i, len;
 855
 856                 len = skb_headlen(skb);
 857                 skb_dma = pci_map_single(tp->tx_pdev, skb->data, len,
 858                                          PCI_DMA_TODEVICE);
 859                 txd->flags = TYPHOON_FRAG_DESC | TYPHOON_DESC_VALID;
 860                 txd->len = cpu_to_le16(len);
 861                 txd->frag.addr = cpu_to_le32(skb_dma);
 862                 txd->frag.addrHi = 0;
 863                 first_txd->numDesc++;
 864
 865                 for(i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
 866                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
 867                         void *frag_addr;
 868
 869                         txd = (struct tx_desc *) (txRing->ringBase +
 870                                                 txRing->lastWrite);
 871                         typhoon_inc_tx_index(&txRing->lastWrite, 1);
 872
 873                         len = frag->size;
 874                         frag_addr = (void *) page_address(frag->page) +
 875                                                 frag->page_offset;
 876                         skb_dma = pci_map_single(tp->tx_pdev, frag_addr, len,
 877                                          PCI_DMA_TODEVICE);
 878                         txd->flags = TYPHOON_FRAG_DESC | TYPHOON_DESC_VALID;
 879                         txd->len = cpu_to_le16(len);
 880                         txd->frag.addr = cpu_to_le32(skb_dma);
 881                         txd->frag.addrHi = 0;
 882                         first_txd->numDesc++;
 883                 }
 884         }
 885
 886         /* Kick the 3XP
 887          */
 888         wmb();
 889         iowrite32(txRing->lastWrite, tp->tx_ioaddr + txRing->writeRegister);
 890
 891         dev->trans_start = jiffies;
 892
 893         /* If we don't have room to put the worst case packet on the
 894          * queue, then we must stop the queue. We need 2 extra
 895          * descriptors -- one to prevent ring wrap, and one for the
 896          * Tx header.
 897          */
 898         numDesc = MAX_SKB_FRAGS + TSO_NUM_DESCRIPTORS + 1;
 899
 900         if(typhoon_num_free_tx(txRing) < (numDesc + 2)) {
 901                 netif_stop_queue(dev);
 902
 903                 /* A Tx complete IRQ could have gotten inbetween, making
 904                  * the ring free again. Only need to recheck here, since
 905                  * Tx is serialized.
 906                  */
 907                 if(typhoon_num_free_tx(txRing) >= (numDesc + 2))
 908                         netif_wake_queue(dev);
 909         }
 910
 911         return 0;
 912 }
 913
 914 static void
 915 typhoon_set_rx_mode(struct net_device *dev)
 916 {
 917         struct typhoon *tp = netdev_priv(dev);
 918         struct cmd_desc xp_cmd;
 919         u32 mc_filter[2];
 920         __le16 filter;
 921
 922         filter = TYPHOON_RX_FILTER_DIRECTED | TYPHOON_RX_FILTER_BROADCAST;
 923         if(dev->flags & IFF_PROMISC) {
 924                 filter |= TYPHOON_RX_FILTER_PROMISCOUS;
 925         } else if((dev->mc_count > multicast_filter_limit) ||
 926                   (dev->flags & IFF_ALLMULTI)) {
 927                 /* Too many to match, or accept all multicasts. */
 928                 filter |= TYPHOON_RX_FILTER_ALL_MCAST;
 929         } else if(dev->mc_count) {
 930                 struct dev_mc_list *mclist;
 931                 int i;
 932
 933                 memset(mc_filter, 0, sizeof(mc_filter));
 934                 for(i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
 935                     i++, mclist = mclist->next) {
 936                         int bit = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3f;
 937                         mc_filter[bit >> 5] |= 1 << (bit & 0x1f);
 938                 }
 939
 940                 INIT_COMMAND_NO_RESPONSE(&xp_cmd,
 941                                          TYPHOON_CMD_SET_MULTICAST_HASH);
 942                 xp_cmd.parm1 = TYPHOON_MCAST_HASH_SET;
 943                 xp_cmd.parm2 = cpu_to_le32(mc_filter[0]);
 944                 xp_cmd.parm3 = cpu_to_le32(mc_filter[1]);
 945                 typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
 946
 947                 filter |= TYPHOON_RX_FILTER_MCAST_HASH;
 948         }
 949
 950         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_RX_FILTER);
 951         xp_cmd.parm1 = filter;
 952         typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
 953 }
 954
 955 static int
 956 typhoon_do_get_stats(struct typhoon *tp)
 957 {
 958         struct net_device_stats *stats = &tp->stats;
 959         struct net_device_stats *saved = &tp->stats_saved;
 960         struct cmd_desc xp_cmd;
 961         struct resp_desc xp_resp[7];
 962         struct stats_resp *s = (struct stats_resp *) xp_resp;
 963         int err;
 964
 965         INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_STATS);
 966         err = typhoon_issue_command(tp, 1, &xp_cmd, 7, xp_resp);
 967         if(err < 0)
 968                 return err;
 969
 970         /* 3Com's Linux driver uses txMultipleCollisions as it's
 971          * collisions value, but there is some other collision info as well...
 972          *
 973          * The extra status reported would be a good candidate for
 974          * ethtool_ops->get_{strings,stats}()
 975          */
 976         stats->tx_packets = le32_to_cpu(s->txPackets);
 977         stats->tx_bytes = le64_to_cpu(s->txBytes);
 978         stats->tx_errors = le32_to_cpu(s->txCarrierLost);
 979         stats->tx_carrier_errors = le32_to_cpu(s->txCarrierLost);
 980         stats->collisions = le32_to_cpu(s->txMultipleCollisions);
 981         stats->rx_packets = le32_to_cpu(s->rxPacketsGood);
 982         stats->rx_bytes = le64_to_cpu(s->rxBytesGood);
 983         stats->rx_fifo_errors = le32_to_cpu(s->rxFifoOverruns);
 984         stats->rx_errors = le32_to_cpu(s->rxFifoOverruns) +
 985                         le32_to_cpu(s->BadSSD) + le32_to_cpu(s->rxCrcErrors);
 986         stats->rx_crc_errors = le32_to_cpu(s->rxCrcErrors);
 987         stats->rx_length_errors = le32_to_cpu(s->rxOversized);
 988         tp->speed = (s->linkStatus & TYPHOON_LINK_100MBPS) ?
 989                         SPEED_100 : SPEED_10;
 990         tp->duplex = (s->linkStatus & TYPHOON_LINK_FULL_DUPLEX) ?
 991                         DUPLEX_FULL : DUPLEX_HALF;
 992
 993         /* add in the saved statistics
 994          */
 995         stats->tx_packets += saved->tx_packets;
 996         stats->tx_bytes += saved->tx_bytes;
 997         stats->tx_errors += saved->tx_errors;
 998         stats->collisions += saved->collisions;
 999         stats->rx_packets += saved->rx_packets;
1000         stats->rx_bytes += saved->rx_bytes;
1001         stats->rx_fifo_errors += saved->rx_fifo_errors;
1002         stats->rx_errors += saved->rx_errors;
1003         stats->rx_crc_errors += saved->rx_crc_errors;
1004         stats->rx_length_errors += saved->rx_length_errors;
1005
1006         return 0;
1007 }
1008
1009 static struct net_device_stats *
1010 typhoon_get_stats(struct net_device *dev)
1011 {
1012         struct typhoon *tp = netdev_priv(dev);
1013         struct net_device_stats *stats = &tp->stats;
1014         struct net_device_stats *saved = &tp->stats_saved;
1015
1016         smp_rmb();
1017         if(tp->card_state == Sleeping)
1018                 return saved;
1019
1020         if(typhoon_do_get_stats(tp) < 0) {
1021                 printk(KERN_ERR "%s: error getting stats\n", dev->name);
1022                 return saved;
1023         }
1024
1025         return stats;
1026 }
1027
1028 static int
1029 typhoon_set_mac_address(struct net_device *dev, void *addr)
1030 {
1031         struct sockaddr *saddr = (struct sockaddr *) addr;
1032
1033         if(netif_running(dev))
1034                 return -EBUSY;
1035
1036         memcpy(dev->dev_addr, saddr->sa_data, dev->addr_len);
1037         return 0;
1038 }
1039
1040 static void
1041 typhoon_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1042 {
1043         struct typhoon *tp = netdev_priv(dev);
1044         struct pci_dev *pci_dev = tp->pdev;
1045         struct cmd_desc xp_cmd;
1046         struct resp_desc xp_resp[3];
1047
1048         smp_rmb();
1049         if(tp->card_state == Sleeping) {
1050                 strcpy(info->fw_version, "Sleep image");
1051         } else {
1052                 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_VERSIONS);
1053                 if(typhoon_issue_command(tp, 1, &xp_cmd, 3, xp_resp) < 0) {
1054                         strcpy(info->fw_version, "Unknown runtime");
1055                 } else {
1056                         u32 sleep_ver = le32_to_cpu(xp_resp[0].parm2);
1057                         snprintf(info->fw_version, 32, "%02x.%03x.%03x",
1058                                  sleep_ver >> 24, (sleep_ver >> 12) & 0xfff,
1059                                  sleep_ver & 0xfff);
1060                 }
1061         }
1062
1063         strcpy(info->driver, DRV_MODULE_NAME);
1064         strcpy(info->version, DRV_MODULE_VERSION);
1065         strcpy(info->bus_info, pci_name(pci_dev));
1066 }
1067
1068 static int
1069 typhoon_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1070 {
1071         struct typhoon *tp = netdev_priv(dev);
1072
1073         cmd->supported = SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
1074                                 SUPPORTED_Autoneg;
1075
1076         switch (tp->xcvr_select) {
1077         case TYPHOON_XCVR_10HALF:
1078                 cmd->advertising = ADVERTISED_10baseT_Half;
1079                 break;
1080         case TYPHOON_XCVR_10FULL:
1081                 cmd->advertising = ADVERTISED_10baseT_Full;
1082                 break;
1083         case TYPHOON_XCVR_100HALF:
1084                 cmd->advertising = ADVERTISED_100baseT_Half;
1085                 break;
1086         case TYPHOON_XCVR_100FULL:
1087                 cmd->advertising = ADVERTISED_100baseT_Full;
1088                 break;
1089         case TYPHOON_XCVR_AUTONEG:
1090                 cmd->advertising = ADVERTISED_10baseT_Half |
1091                                             ADVERTISED_10baseT_Full |
1092                                             ADVERTISED_100baseT_Half |
1093                                             ADVERTISED_100baseT_Full |
1094                                             ADVERTISED_Autoneg;
1095                 break;
1096         }
1097
1098         if(tp->capabilities & TYPHOON_FIBER) {
1099                 cmd->supported |= SUPPORTED_FIBRE;
1100                 cmd->advertising |= ADVERTISED_FIBRE;
1101                 cmd->port = PORT_FIBRE;
1102         } else {
1103                 cmd->supported |= SUPPORTED_10baseT_Half |
1104                                         SUPPORTED_10baseT_Full |
1105                                         SUPPORTED_TP;
1106                 cmd->advertising |= ADVERTISED_TP;
1107                 cmd->port = PORT_TP;
1108         }
1109
1110         /* need to get stats to make these link speed/duplex valid */
1111         typhoon_do_get_stats(tp);
1112         cmd->speed = tp->speed;
1113         cmd->duplex = tp->duplex;
1114         cmd->phy_address = 0;
1115         cmd->transceiver = XCVR_INTERNAL;
1116         if(tp->xcvr_select == TYPHOON_XCVR_AUTONEG)
1117                 cmd->autoneg = AUTONEG_ENABLE;
1118         else
1119                 cmd->autoneg = AUTONEG_DISABLE;
1120         cmd->maxtxpkt = 1;
1121         cmd->maxrxpkt = 1;
1122
1123         return 0;
1124 }
1125
1126 static int
1127 typhoon_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1128 {
1129         struct typhoon *tp = netdev_priv(dev);
1130         struct cmd_desc xp_cmd;
1131         __le16 xcvr;
1132         int err;
1133
1134         err = -EINVAL;
1135         if(cmd->autoneg == AUTONEG_ENABLE) {
1136                 xcvr = TYPHOON_XCVR_AUTONEG;
1137         } else {
1138                 if(cmd->duplex == DUPLEX_HALF) {
1139                         if(cmd->speed == SPEED_10)
1140                                 xcvr = TYPHOON_XCVR_10HALF;
1141                         else if(cmd->speed == SPEED_100)
1142                                 xcvr = TYPHOON_XCVR_100HALF;
1143                         else
1144                                 goto out;
1145                 } else if(cmd->duplex == DUPLEX_FULL) {
1146                         if(cmd->speed == SPEED_10)
1147                                 xcvr = TYPHOON_XCVR_10FULL;
1148                         else if(cmd->speed == SPEED_100)
1149                                 xcvr = TYPHOON_XCVR_100FULL;
1150                         else
1151                                 goto out;
1152                 } else
1153                         goto out;
1154         }
1155
1156         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_XCVR_SELECT);
1157         xp_cmd.parm1 = xcvr;
1158         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1159         if(err < 0)
1160                 goto out;
1161
1162         tp->xcvr_select = xcvr;
1163         if(cmd->autoneg == AUTONEG_ENABLE) {
1164                 tp->speed = 0xff;       /* invalid */
1165                 tp->duplex = 0xff;      /* invalid */
1166         } else {
1167                 tp->speed = cmd->speed;
1168                 tp->duplex = cmd->duplex;
1169         }
1170
1171 out:
1172         return err;
1173 }
1174
1175 static void
1176 typhoon_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1177 {
1178         struct typhoon *tp = netdev_priv(dev);
1179
1180         wol->supported = WAKE_PHY | WAKE_MAGIC;
1181         wol->wolopts = 0;
1182         if(tp->wol_events & TYPHOON_WAKE_LINK_EVENT)
1183                 wol->wolopts |= WAKE_PHY;
1184         if(tp->wol_events & TYPHOON_WAKE_MAGIC_PKT)
1185                 wol->wolopts |= WAKE_MAGIC;
1186         memset(&wol->sopass, 0, sizeof(wol->sopass));
1187 }
1188
1189 static int
1190 typhoon_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1191 {
1192         struct typhoon *tp = netdev_priv(dev);
1193
1194         if(wol->wolopts & ~(WAKE_PHY | WAKE_MAGIC))
1195                 return -EINVAL;
1196
1197         tp->wol_events = 0;
1198         if(wol->wolopts & WAKE_PHY)
1199                 tp->wol_events |= TYPHOON_WAKE_LINK_EVENT;
1200         if(wol->wolopts & WAKE_MAGIC)
1201                 tp->wol_events |= TYPHOON_WAKE_MAGIC_PKT;
1202
1203         return 0;
1204 }
1205
1206 static u32
1207 typhoon_get_rx_csum(struct net_device *dev)
1208 {
1209         /* For now, we don't allow turning off RX checksums.
1210          */
1211         return 1;
1212 }
1213
1214 static void
1215 typhoon_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
1216 {
1217         ering->rx_max_pending = RXENT_ENTRIES;
1218         ering->rx_mini_max_pending = 0;
1219         ering->rx_jumbo_max_pending = 0;
1220         ering->tx_max_pending = TXLO_ENTRIES - 1;
1221
1222         ering->rx_pending = RXENT_ENTRIES;
1223         ering->rx_mini_pending = 0;
1224         ering->rx_jumbo_pending = 0;
1225         ering->tx_pending = TXLO_ENTRIES - 1;
1226 }
1227
1228 static const struct ethtool_ops typhoon_ethtool_ops = {
1229         .get_settings           = typhoon_get_settings,
1230         .set_settings           = typhoon_set_settings,
1231         .get_drvinfo            = typhoon_get_drvinfo,
1232         .get_wol                = typhoon_get_wol,
1233         .set_wol                = typhoon_set_wol,
1234         .get_link               = ethtool_op_get_link,
1235         .get_rx_csum            = typhoon_get_rx_csum,
1236         .set_tx_csum            = ethtool_op_set_tx_csum,
1237         .set_sg                 = ethtool_op_set_sg,
1238         .set_tso                = ethtool_op_set_tso,
1239         .get_ringparam          = typhoon_get_ringparam,
1240 };
1241
1242 static int
1243 typhoon_wait_interrupt(void __iomem *ioaddr)
1244 {
1245         int i, err = 0;
1246
1247         for(i = 0; i < TYPHOON_WAIT_TIMEOUT; i++) {
1248                 if(ioread32(ioaddr + TYPHOON_REG_INTR_STATUS) &
1249                    TYPHOON_INTR_BOOTCMD)
1250                         goto out;
1251                 udelay(TYPHOON_UDELAY);
1252         }
1253
1254         err = -ETIMEDOUT;
1255
1256 out:
1257         iowrite32(TYPHOON_INTR_BOOTCMD, ioaddr + TYPHOON_REG_INTR_STATUS);
1258         return err;
1259 }
1260
1261 #define shared_offset(x)        offsetof(struct typhoon_shared, x)
1262
1263 static void
1264 typhoon_init_interface(struct typhoon *tp)
1265 {
1266         struct typhoon_interface *iface = &tp->shared->iface;
1267         dma_addr_t shared_dma;
1268
1269         memset(tp->shared, 0, sizeof(struct typhoon_shared));
1270
1271         /* The *Hi members of iface are all init'd to zero by the memset().
1272          */
1273         shared_dma = tp->shared_dma + shared_offset(indexes);
1274         iface->ringIndex = cpu_to_le32(shared_dma);
1275
1276         shared_dma = tp->shared_dma + shared_offset(txLo);
1277         iface->txLoAddr = cpu_to_le32(shared_dma);
1278         iface->txLoSize = cpu_to_le32(TXLO_ENTRIES * sizeof(struct tx_desc));
1279
1280         shared_dma = tp->shared_dma + shared_offset(txHi);
1281         iface->txHiAddr = cpu_to_le32(shared_dma);
1282         iface->txHiSize = cpu_to_le32(TXHI_ENTRIES * sizeof(struct tx_desc));
1283
1284         shared_dma = tp->shared_dma + shared_offset(rxBuff);
1285         iface->rxBuffAddr = cpu_to_le32(shared_dma);
1286         iface->rxBuffSize = cpu_to_le32(RXFREE_ENTRIES *
1287                                         sizeof(struct rx_free));
1288
1289         shared_dma = tp->shared_dma + shared_offset(rxLo);
1290         iface->rxLoAddr = cpu_to_le32(shared_dma);
1291         iface->rxLoSize = cpu_to_le32(RX_ENTRIES * sizeof(struct rx_desc));
1292
1293         shared_dma = tp->shared_dma + shared_offset(rxHi);
1294         iface->rxHiAddr = cpu_to_le32(shared_dma);
1295         iface->rxHiSize = cpu_to_le32(RX_ENTRIES * sizeof(struct rx_desc));
1296
1297         shared_dma = tp->shared_dma + shared_offset(cmd);
1298         iface->cmdAddr = cpu_to_le32(shared_dma);
1299         iface->cmdSize = cpu_to_le32(COMMAND_RING_SIZE);
1300
1301         shared_dma = tp->shared_dma + shared_offset(resp);
1302         iface->respAddr = cpu_to_le32(shared_dma);
1303         iface->respSize = cpu_to_le32(RESPONSE_RING_SIZE);
1304
1305         shared_dma = tp->shared_dma + shared_offset(zeroWord);
1306         iface->zeroAddr = cpu_to_le32(shared_dma);
1307
1308         tp->indexes = &tp->shared->indexes;
1309         tp->txLoRing.ringBase = (u8 *) tp->shared->txLo;
1310         tp->txHiRing.ringBase = (u8 *) tp->shared->txHi;
1311         tp->rxLoRing.ringBase = (u8 *) tp->shared->rxLo;
1312         tp->rxHiRing.ringBase = (u8 *) tp->shared->rxHi;
1313         tp->rxBuffRing.ringBase = (u8 *) tp->shared->rxBuff;
1314         tp->cmdRing.ringBase = (u8 *) tp->shared->cmd;
1315         tp->respRing.ringBase = (u8 *) tp->shared->resp;
1316
1317         tp->txLoRing.writeRegister = TYPHOON_REG_TX_LO_READY;
1318         tp->txHiRing.writeRegister = TYPHOON_REG_TX_HI_READY;
1319
1320         tp->txlo_dma_addr = le32_to_cpu(iface->txLoAddr);
1321         tp->card_state = Sleeping;
1322         smp_wmb();
1323
1324         tp->offload = TYPHOON_OFFLOAD_IP_CHKSUM | TYPHOON_OFFLOAD_TCP_CHKSUM;
1325         tp->offload |= TYPHOON_OFFLOAD_UDP_CHKSUM | TSO_OFFLOAD_ON;
1326
1327         spin_lock_init(&tp->command_lock);
1328         spin_lock_init(&tp->state_lock);
1329 }
1330
1331 static void
1332 typhoon_init_rings(struct typhoon *tp)
1333 {
1334         memset(tp->indexes, 0, sizeof(struct typhoon_indexes));
1335
1336         tp->txLoRing.lastWrite = 0;
1337         tp->txHiRing.lastWrite = 0;
1338         tp->rxLoRing.lastWrite = 0;
1339         tp->rxHiRing.lastWrite = 0;
1340         tp->rxBuffRing.lastWrite = 0;
1341         tp->cmdRing.lastWrite = 0;
1342         tp->cmdRing.lastWrite = 0;
1343
1344         tp->txLoRing.lastRead = 0;
1345         tp->txHiRing.lastRead = 0;
1346 }
1347
1348 static int
1349 typhoon_download_firmware(struct typhoon *tp)
1350 {
1351         void __iomem *ioaddr = tp->ioaddr;
1352         struct pci_dev *pdev = tp->pdev;
1353         struct typhoon_file_header *fHdr;
1354         struct typhoon_section_header *sHdr;
1355         u8 *image_data;
1356         void *dpage;
1357         dma_addr_t dpage_dma;
1358         __sum16 csum;
1359         u32 irqEnabled;
1360         u32 irqMasked;
1361         u32 numSections;
1362         u32 section_len;
1363         u32 len;
1364         u32 load_addr;
1365         u32 hmac;
1366         int i;
1367         int err;
1368
1369         err = -EINVAL;
1370         fHdr = (struct typhoon_file_header *) typhoon_firmware_image;
1371         image_data = (u8 *) fHdr;
1372
1373         if(memcmp(fHdr->tag, "TYPHOON", 8)) {
1374                 printk(KERN_ERR "%s: Invalid firmware image!\n", tp->name);
1375                 goto err_out;
1376         }
1377
1378         /* Cannot just map the firmware image using pci_map_single() as
1379          * the firmware is part of the kernel/module image, so we allocate
1380          * some consistent memory to copy the sections into, as it is simpler,
1381          * and short-lived. If we ever split out and require a userland
1382          * firmware loader, then we can revisit this.
1383          */
1384         err = -ENOMEM;
1385         dpage = pci_alloc_consistent(pdev, PAGE_SIZE, &dpage_dma);
1386         if(!dpage) {
1387                 printk(KERN_ERR "%s: no DMA mem for firmware\n", tp->name);
1388                 goto err_out;
1389         }
1390
1391         irqEnabled = ioread32(ioaddr + TYPHOON_REG_INTR_ENABLE);
1392         iowrite32(irqEnabled | TYPHOON_INTR_BOOTCMD,
1393                ioaddr + TYPHOON_REG_INTR_ENABLE);
1394         irqMasked = ioread32(ioaddr + TYPHOON_REG_INTR_MASK);
1395         iowrite32(irqMasked | TYPHOON_INTR_BOOTCMD,
1396                ioaddr + TYPHOON_REG_INTR_MASK);
1397
1398         err = -ETIMEDOUT;
1399         if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
1400                 printk(KERN_ERR "%s: card ready timeout\n", tp->name);
1401                 goto err_out_irq;
1402         }
1403
1404         numSections = le32_to_cpu(fHdr->numSections);
1405         load_addr = le32_to_cpu(fHdr->startAddr);
1406
1407         iowrite32(TYPHOON_INTR_BOOTCMD, ioaddr + TYPHOON_REG_INTR_STATUS);
1408         iowrite32(load_addr, ioaddr + TYPHOON_REG_DOWNLOAD_BOOT_ADDR);
1409         hmac = le32_to_cpu(fHdr->hmacDigest[0]);
1410         iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_0);
1411         hmac = le32_to_cpu(fHdr->hmacDigest[1]);
1412         iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_1);
1413         hmac = le32_to_cpu(fHdr->hmacDigest[2]);
1414         iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_2);
1415         hmac = le32_to_cpu(fHdr->hmacDigest[3]);
1416         iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_3);
1417         hmac = le32_to_cpu(fHdr->hmacDigest[4]);
1418         iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_4);
1419         typhoon_post_pci_writes(ioaddr);
1420         iowrite32(TYPHOON_BOOTCMD_RUNTIME_IMAGE, ioaddr + TYPHOON_REG_COMMAND);
1421
1422         image_data += sizeof(struct typhoon_file_header);
1423
1424         /* The ioread32() in typhoon_wait_interrupt() will force the
1425          * last write to the command register to post, so
1426          * we don't need a typhoon_post_pci_writes() after it.
1427          */
1428         for(i = 0; i < numSections; i++) {
1429                 sHdr = (struct typhoon_section_header *) image_data;
1430                 image_data += sizeof(struct typhoon_section_header);
1431                 load_addr = le32_to_cpu(sHdr->startAddr);
1432                 section_len = le32_to_cpu(sHdr->len);
1433
1434                 while(section_len) {
1435                         len = min_t(u32, section_len, PAGE_SIZE);
1436
1437                         if(typhoon_wait_interrupt(ioaddr) < 0 ||
1438                            ioread32(ioaddr + TYPHOON_REG_STATUS) !=
1439                            TYPHOON_STATUS_WAITING_FOR_SEGMENT) {
1440                                 printk(KERN_ERR "%s: segment ready timeout\n",
1441                                        tp->name);
1442                                 goto err_out_irq;
1443                         }
1444
1445                         /* Do an pseudo IPv4 checksum on the data -- first
1446                          * need to convert each u16 to cpu order before
1447                          * summing. Fortunately, due to the properties of
1448                          * the checksum, we can do this once, at the end.
1449                          */
1450                         csum = csum_fold(csum_partial_copy_nocheck(image_data,
1451                                                                   dpage, len,
1452                                                                   0));
1453
1454                         iowrite32(len, ioaddr + TYPHOON_REG_BOOT_LENGTH);
1455                         iowrite32(le16_to_cpu((__force __le16)csum),
1456                                         ioaddr + TYPHOON_REG_BOOT_CHECKSUM);
1457                         iowrite32(load_addr,
1458                                         ioaddr + TYPHOON_REG_BOOT_DEST_ADDR);
1459                         iowrite32(0, ioaddr + TYPHOON_REG_BOOT_DATA_HI);
1460                         iowrite32(dpage_dma, ioaddr + TYPHOON_REG_BOOT_DATA_LO);
1461                         typhoon_post_pci_writes(ioaddr);
1462                         iowrite32(TYPHOON_BOOTCMD_SEG_AVAILABLE,
1463                                ioaddr + TYPHOON_REG_COMMAND);
1464
1465                         image_data += len;
1466                         load_addr += len;
1467                         section_len -= len;
1468                 }
1469         }
1470
1471         if(typhoon_wait_interrupt(ioaddr) < 0 ||
1472            ioread32(ioaddr + TYPHOON_REG_STATUS) !=
1473            TYPHOON_STATUS_WAITING_FOR_SEGMENT) {
1474                 printk(KERN_ERR "%s: final segment ready timeout\n", tp->name);
1475                 goto err_out_irq;
1476         }
1477
1478         iowrite32(TYPHOON_BOOTCMD_DNLD_COMPLETE, ioaddr + TYPHOON_REG_COMMAND);
1479
1480         if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_WAITING_FOR_BOOT) < 0) {
1481                 printk(KERN_ERR "%s: boot ready timeout, status 0x%0x\n",
1482                        tp->name, ioread32(ioaddr + TYPHOON_REG_STATUS));
1483                 goto err_out_irq;
1484         }
1485
1486         err = 0;
1487
1488 err_out_irq:
1489         iowrite32(irqMasked, ioaddr + TYPHOON_REG_INTR_MASK);
1490         iowrite32(irqEnabled, ioaddr + TYPHOON_REG_INTR_ENABLE);
1491
1492         pci_free_consistent(pdev, PAGE_SIZE, dpage, dpage_dma);
1493
1494 err_out:
1495         return err;
1496 }
1497
1498 static int
1499 typhoon_boot_3XP(struct typhoon *tp, u32 initial_status)
1500 {
1501         void __iomem *ioaddr = tp->ioaddr;
1502
1503         if(typhoon_wait_status(ioaddr, initial_status) < 0) {
1504                 printk(KERN_ERR "%s: boot ready timeout\n", tp->name);
1505                 goto out_timeout;
1506         }
1507
1508         iowrite32(0, ioaddr + TYPHOON_REG_BOOT_RECORD_ADDR_HI);
1509         iowrite32(tp->shared_dma, ioaddr + TYPHOON_REG_BOOT_RECORD_ADDR_LO);
1510         typhoon_post_pci_writes(ioaddr);
1511         iowrite32(TYPHOON_BOOTCMD_REG_BOOT_RECORD,
1512                                 ioaddr + TYPHOON_REG_COMMAND);
1513
1514         if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_RUNNING) < 0) {
1515                 printk(KERN_ERR "%s: boot finish timeout (status 0x%x)\n",
1516                        tp->name, ioread32(ioaddr + TYPHOON_REG_STATUS));
1517                 goto out_timeout;
1518         }
1519
1520         /* Clear the Transmit and Command ready registers
1521          */
1522         iowrite32(0, ioaddr + TYPHOON_REG_TX_HI_READY);
1523         iowrite32(0, ioaddr + TYPHOON_REG_CMD_READY);
1524         iowrite32(0, ioaddr + TYPHOON_REG_TX_LO_READY);
1525         typhoon_post_pci_writes(ioaddr);
1526         iowrite32(TYPHOON_BOOTCMD_BOOT, ioaddr + TYPHOON_REG_COMMAND);
1527
1528         return 0;
1529
1530 out_timeout:
1531         return -ETIMEDOUT;
1532 }
1533
1534 static u32
1535 typhoon_clean_tx(struct typhoon *tp, struct transmit_ring *txRing,
1536                         volatile __le32 * index)
1537 {
1538         u32 lastRead = txRing->lastRead;
1539         struct tx_desc *tx;
1540         dma_addr_t skb_dma;
1541         int dma_len;
1542         int type;
1543
1544         while(lastRead != le32_to_cpu(*index)) {
1545                 tx = (struct tx_desc *) (txRing->ringBase + lastRead);
1546                 type = tx->flags & TYPHOON_TYPE_MASK;
1547
1548                 if(type == TYPHOON_TX_DESC) {
1549                         /* This tx_desc describes a packet.
1550                          */
1551                         unsigned long ptr = tx->tx_addr;
1552                         struct sk_buff *skb = (struct sk_buff *) ptr;
1553                         dev_kfree_skb_irq(skb);
1554                 } else if(type == TYPHOON_FRAG_DESC) {
1555                         /* This tx_desc describes a memory mapping. Free it.
1556                          */
1557                         skb_dma = (dma_addr_t) le32_to_cpu(tx->frag.addr);
1558                         dma_len = le16_to_cpu(tx->len);
1559                         pci_unmap_single(tp->pdev, skb_dma, dma_len,
1560                                        PCI_DMA_TODEVICE);
1561                 }
1562
1563                 tx->flags = 0;
1564                 typhoon_inc_tx_index(&lastRead, 1);
1565         }
1566
1567         return lastRead;
1568 }
1569
1570 static void
1571 typhoon_tx_complete(struct typhoon *tp, struct transmit_ring *txRing,
1572                         volatile __le32 * index)
1573 {
1574         u32 lastRead;
1575         int numDesc = MAX_SKB_FRAGS + 1;
1576
1577         /* This will need changing if we start to use the Hi Tx ring. */
1578         lastRead = typhoon_clean_tx(tp, txRing, index);
1579         if(netif_queue_stopped(tp->dev) && typhoon_num_free(txRing->lastWrite,
1580                                 lastRead, TXLO_ENTRIES) > (numDesc + 2))
1581                 netif_wake_queue(tp->dev);
1582
1583         txRing->lastRead = lastRead;
1584         smp_wmb();
1585 }
1586
1587 static void
1588 typhoon_recycle_rx_skb(struct typhoon *tp, u32 idx)
1589 {
1590         struct typhoon_indexes *indexes = tp->indexes;
1591         struct rxbuff_ent *rxb = &tp->rxbuffers[idx];
1592         struct basic_ring *ring = &tp->rxBuffRing;
1593         struct rx_free *r;
1594
1595         if((ring->lastWrite + sizeof(*r)) % (RXFREE_ENTRIES * sizeof(*r)) ==
1596                                 le32_to_cpu(indexes->rxBuffCleared)) {
1597                 /* no room in ring, just drop the skb
1598                  */
1599                 dev_kfree_skb_any(rxb->skb);
1600                 rxb->skb = NULL;
1601                 return;
1602         }
1603
1604         r = (struct rx_free *) (ring->ringBase + ring->lastWrite);
1605         typhoon_inc_rxfree_index(&ring->lastWrite, 1);
1606         r->virtAddr = idx;
1607         r->physAddr = cpu_to_le32(rxb->dma_addr);
1608
1609         /* Tell the card about it */
1610         wmb();
1611         indexes->rxBuffReady = cpu_to_le32(ring->lastWrite);
1612 }
1613
1614 static int
1615 typhoon_alloc_rx_skb(struct typhoon *tp, u32 idx)
1616 {
1617         struct typhoon_indexes *indexes = tp->indexes;
1618         struct rxbuff_ent *rxb = &tp->rxbuffers[idx];
1619         struct basic_ring *ring = &tp->rxBuffRing;
1620         struct rx_free *r;
1621         struct sk_buff *skb;
1622         dma_addr_t dma_addr;
1623
1624         rxb->skb = NULL;
1625
1626         if((ring->lastWrite + sizeof(*r)) % (RXFREE_ENTRIES * sizeof(*r)) ==
1627                                 le32_to_cpu(indexes->rxBuffCleared))
1628                 return -ENOMEM;
1629
1630         skb = dev_alloc_skb(PKT_BUF_SZ);
1631         if(!skb)
1632                 return -ENOMEM;
1633
1634 #if 0
1635         /* Please, 3com, fix the firmware to allow DMA to a unaligned
1636          * address! Pretty please?
1637          */
1638         skb_reserve(skb, 2);
1639 #endif
1640
1641         skb->dev = tp->dev;
1642         dma_addr = pci_map_single(tp->pdev, skb->data,
1643                                   PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
1644
1645         /* Since no card does 64 bit DAC, the high bits will never
1646          * change from zero.
1647          */
1648         r = (struct rx_free *) (ring->ringBase + ring->lastWrite);
1649         typhoon_inc_rxfree_index(&ring->lastWrite, 1);
1650         r->virtAddr = idx;
1651         r->physAddr = cpu_to_le32(dma_addr);
1652         rxb->skb = skb;
1653         rxb->dma_addr = dma_addr;
1654
1655         /* Tell the card about it */
1656         wmb();
1657         indexes->rxBuffReady = cpu_to_le32(ring->lastWrite);
1658         return 0;
1659 }
1660
1661 static int
1662 typhoon_rx(struct typhoon *tp, struct basic_ring *rxRing, volatile __le32 * ready,
1663            volatile __le32 * cleared, int budget)
1664 {
1665         struct rx_desc *rx;
1666         struct sk_buff *skb, *new_skb;
1667         struct rxbuff_ent *rxb;
1668         dma_addr_t dma_addr;
1669         u32 local_ready;
1670         u32 rxaddr;
1671         int pkt_len;
1672         u32 idx;
1673         __le32 csum_bits;
1674         int received;
1675
1676         received = 0;
1677         local_ready = le32_to_cpu(*ready);
1678         rxaddr = le32_to_cpu(*cleared);
1679         while(rxaddr != local_ready && budget > 0) {
1680                 rx = (struct rx_desc *) (rxRing->ringBase + rxaddr);
1681                 idx = rx->addr;
1682                 rxb = &tp->rxbuffers[idx];
1683                 skb = rxb->skb;
1684                 dma_addr = rxb->dma_addr;
1685
1686                 typhoon_inc_rx_index(&rxaddr, 1);
1687
1688                 if(rx->flags & TYPHOON_RX_ERROR) {
1689                         typhoon_recycle_rx_skb(tp, idx);
1690                         continue;
1691                 }
1692
1693                 pkt_len = le16_to_cpu(rx->frameLen);
1694
1695                 if(pkt_len < rx_copybreak &&
1696                    (new_skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1697                         skb_reserve(new_skb, 2);
1698                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr,
1699                                                     PKT_BUF_SZ,
1700                                                     PCI_DMA_FROMDEVICE);
1701                         skb_copy_to_linear_data(new_skb, skb->data, pkt_len);
1702                         pci_dma_sync_single_for_device(tp->pdev, dma_addr,
1703                                                        PKT_BUF_SZ,
1704                                                        PCI_DMA_FROMDEVICE);
1705                         skb_put(new_skb, pkt_len);
1706                         typhoon_recycle_rx_skb(tp, idx);
1707                 } else {
1708                         new_skb = skb;
1709                         skb_put(new_skb, pkt_len);
1710                         pci_unmap_single(tp->pdev, dma_addr, PKT_BUF_SZ,
1711                                        PCI_DMA_FROMDEVICE);
1712                         typhoon_alloc_rx_skb(tp, idx);
1713                 }
1714                 new_skb->protocol = eth_type_trans(new_skb, tp->dev);
1715                 csum_bits = rx->rxStatus & (TYPHOON_RX_IP_CHK_GOOD |
1716                         TYPHOON_RX_UDP_CHK_GOOD | TYPHOON_RX_TCP_CHK_GOOD);
1717                 if(csum_bits ==
1718                    (TYPHOON_RX_IP_CHK_GOOD | TYPHOON_RX_TCP_CHK_GOOD)
1719                    || csum_bits ==
1720                    (TYPHOON_RX_IP_CHK_GOOD | TYPHOON_RX_UDP_CHK_GOOD)) {
1721                         new_skb->ip_summed = CHECKSUM_UNNECESSARY;
1722                 } else
1723                         new_skb->ip_summed = CHECKSUM_NONE;
1724
1725                 spin_lock(&tp->state_lock);
1726                 if(tp->vlgrp != NULL && rx->rxStatus & TYPHOON_RX_VLAN)
1727                         vlan_hwaccel_receive_skb(new_skb, tp->vlgrp,
1728                                                  ntohl(rx->vlanTag) & 0xffff);
1729                 else
1730                         netif_receive_skb(new_skb);
1731                 spin_unlock(&tp->state_lock);
1732
1733                 tp->dev->last_rx = jiffies;
1734                 received++;
1735                 budget--;
1736         }
1737         *cleared = cpu_to_le32(rxaddr);
1738
1739         return received;
1740 }
1741
1742 static void
1743 typhoon_fill_free_ring(struct typhoon *tp)
1744 {
1745         u32 i;
1746
1747         for(i = 0; i < RXENT_ENTRIES; i++) {
1748                 struct rxbuff_ent *rxb = &tp->rxbuffers[i];
1749                 if(rxb->skb)
1750                         continue;
1751                 if(typhoon_alloc_rx_skb(tp, i) < 0)
1752                         break;
1753         }
1754 }
1755
1756 static int
1757 typhoon_poll(struct napi_struct *napi, int budget)
1758 {
1759         struct typhoon *tp = container_of(napi, struct typhoon, napi);
1760         struct net_device *dev = tp->dev;
1761         struct typhoon_indexes *indexes = tp->indexes;
1762         int work_done;
1763
1764         rmb();
1765         if(!tp->awaiting_resp && indexes->respReady != indexes->respCleared)
1766                         typhoon_process_response(tp, 0, NULL);
1767
1768         if(le32_to_cpu(indexes->txLoCleared) != tp->txLoRing.lastRead)
1769                 typhoon_tx_complete(tp, &tp->txLoRing, &indexes->txLoCleared);
1770
1771         work_done = 0;
1772
1773         if(indexes->rxHiCleared != indexes->rxHiReady) {
1774                 work_done += typhoon_rx(tp, &tp->rxHiRing, &indexes->rxHiReady,
1775                                         &indexes->rxHiCleared, budget);
1776         }
1777
1778         if(indexes->rxLoCleared != indexes->rxLoReady) {
1779                 work_done += typhoon_rx(tp, &tp->rxLoRing, &indexes->rxLoReady,
1780                                         &indexes->rxLoCleared, budget - work_done);
1781         }
1782
1783         if(le32_to_cpu(indexes->rxBuffCleared) == tp->rxBuffRing.lastWrite) {
1784                 /* rxBuff ring is empty, try to fill it. */
1785                 typhoon_fill_free_ring(tp);
1786         }
1787
1788         if (work_done < budget) {
1789                 netif_rx_complete(dev, napi);
1790                 iowrite32(TYPHOON_INTR_NONE,
1791                                 tp->ioaddr + TYPHOON_REG_INTR_MASK);
1792                 typhoon_post_pci_writes(tp->ioaddr);
1793         }
1794
1795         return work_done;
1796 }
1797
1798 static irqreturn_t
1799 typhoon_interrupt(int irq, void *dev_instance)
1800 {
1801         struct net_device *dev = dev_instance;
1802         struct typhoon *tp = dev->priv;
1803         void __iomem *ioaddr = tp->ioaddr;
1804         u32 intr_status;
1805
1806         intr_status = ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
1807         if(!(intr_status & TYPHOON_INTR_HOST_INT))
1808                 return IRQ_NONE;
1809
1810         iowrite32(intr_status, ioaddr + TYPHOON_REG_INTR_STATUS);
1811
1812         if (netif_rx_schedule_prep(dev, &tp->napi)) {
1813                 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
1814                 typhoon_post_pci_writes(ioaddr);
1815                 __netif_rx_schedule(dev, &tp->napi);
1816         } else {
1817                 printk(KERN_ERR "%s: Error, poll already scheduled\n",
1818                        dev->name);
1819         }
1820         return IRQ_HANDLED;
1821 }
1822
1823 static void
1824 typhoon_free_rx_rings(struct typhoon *tp)
1825 {
1826         u32 i;
1827
1828         for(i = 0; i < RXENT_ENTRIES; i++) {
1829                 struct rxbuff_ent *rxb = &tp->rxbuffers[i];
1830                 if(rxb->skb) {
1831                         pci_unmap_single(tp->pdev, rxb->dma_addr, PKT_BUF_SZ,
1832                                        PCI_DMA_FROMDEVICE);
1833                         dev_kfree_skb(rxb->skb);
1834                         rxb->skb = NULL;
1835                 }
1836         }
1837 }
1838
1839 static int
1840 typhoon_sleep(struct typhoon *tp, pci_power_t state, __le16 events)
1841 {
1842         struct pci_dev *pdev = tp->pdev;
1843         void __iomem *ioaddr = tp->ioaddr;
1844         struct cmd_desc xp_cmd;
1845         int err;
1846
1847         INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_ENABLE_WAKE_EVENTS);
1848         xp_cmd.parm1 = events;
1849         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1850         if(err < 0) {
1851                 printk(KERN_ERR "%s: typhoon_sleep(): wake events cmd err %d\n",
1852                                 tp->name, err);
1853                 return err;
1854         }
1855
1856         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_GOTO_SLEEP);
1857         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1858         if(err < 0) {
1859                 printk(KERN_ERR "%s: typhoon_sleep(): sleep cmd err %d\n",
1860                                 tp->name, err);
1861                 return err;
1862         }
1863
1864         if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_SLEEPING) < 0)
1865                 return -ETIMEDOUT;
1866
1867         /* Since we cannot monitor the status of the link while sleeping,
1868          * tell the world it went away.
1869          */
1870         netif_carrier_off(tp->dev);
1871
1872         pci_enable_wake(tp->pdev, state, 1);
1873         pci_disable_device(pdev);
1874         return pci_set_power_state(pdev, state);
1875 }
1876
1877 static int
1878 typhoon_wakeup(struct typhoon *tp, int wait_type)
1879 {
1880         struct pci_dev *pdev = tp->pdev;
1881         void __iomem *ioaddr = tp->ioaddr;
1882
1883         pci_set_power_state(pdev, PCI_D0);
1884         pci_restore_state(pdev);
1885
1886         /* Post 2.x.x versions of the Sleep Image require a reset before
1887          * we can download the Runtime Image. But let's not make users of
1888          * the old firmware pay for the reset.
1889          */
1890         iowrite32(TYPHOON_BOOTCMD_WAKEUP, ioaddr + TYPHOON_REG_COMMAND);
1891         if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_WAITING_FOR_HOST) < 0 ||
1892                         (tp->capabilities & TYPHOON_WAKEUP_NEEDS_RESET))
1893                 return typhoon_reset(ioaddr, wait_type);
1894
1895         return 0;
1896 }
1897
1898 static int
1899 typhoon_start_runtime(struct typhoon *tp)
1900 {
1901         struct net_device *dev = tp->dev;
1902         void __iomem *ioaddr = tp->ioaddr;
1903         struct cmd_desc xp_cmd;
1904         int err;
1905
1906         typhoon_init_rings(tp);
1907         typhoon_fill_free_ring(tp);
1908
1909         err = typhoon_download_firmware(tp);
1910         if(err < 0) {
1911                 printk("%s: cannot load runtime on 3XP\n", tp->name);
1912                 goto error_out;
1913         }
1914
1915         if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_BOOT) < 0) {
1916                 printk("%s: cannot boot 3XP\n", tp->name);
1917                 err = -EIO;
1918                 goto error_out;
1919         }
1920
1921         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_MAX_PKT_SIZE);
1922         xp_cmd.parm1 = cpu_to_le16(PKT_BUF_SZ);
1923         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1924         if(err < 0)
1925                 goto error_out;
1926
1927         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_MAC_ADDRESS);
1928         xp_cmd.parm1 = cpu_to_le16(ntohs(*(__be16 *)&dev->dev_addr[0]));
1929         xp_cmd.parm2 = cpu_to_le32(ntohl(*(__be32 *)&dev->dev_addr[2]));
1930         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1931         if(err < 0)
1932                 goto error_out;
1933
1934         /* Disable IRQ coalescing -- we can reenable it when 3Com gives
1935          * us some more information on how to control it.
1936          */
1937         INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_IRQ_COALESCE_CTRL);
1938         xp_cmd.parm1 = 0;
1939         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1940         if(err < 0)
1941                 goto error_out;
1942
1943         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_XCVR_SELECT);
1944         xp_cmd.parm1 = tp->xcvr_select;
1945         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1946         if(err < 0)
1947                 goto error_out;
1948
1949         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_VLAN_TYPE_WRITE);
1950         xp_cmd.parm1 = __constant_cpu_to_le16(ETH_P_8021Q);
1951         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1952         if(err < 0)
1953                 goto error_out;
1954
1955         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_OFFLOAD_TASKS);
1956         spin_lock_bh(&tp->state_lock);
1957         xp_cmd.parm2 = tp->offload;
1958         xp_cmd.parm3 = tp->offload;
1959         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1960         spin_unlock_bh(&tp->state_lock);
1961         if(err < 0)
1962                 goto error_out;
1963
1964         typhoon_set_rx_mode(dev);
1965
1966         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_TX_ENABLE);
1967         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1968         if(err < 0)
1969                 goto error_out;
1970
1971         INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_RX_ENABLE);
1972         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1973         if(err < 0)
1974                 goto error_out;
1975
1976         tp->card_state = Running;
1977         smp_wmb();
1978
1979         iowrite32(TYPHOON_INTR_ENABLE_ALL, ioaddr + TYPHOON_REG_INTR_ENABLE);
1980         iowrite32(TYPHOON_INTR_NONE, ioaddr + TYPHOON_REG_INTR_MASK);
1981         typhoon_post_pci_writes(ioaddr);
1982
1983         return 0;
1984
1985 error_out:
1986         typhoon_reset(ioaddr, WaitNoSleep);
1987         typhoon_free_rx_rings(tp);
1988         typhoon_init_rings(tp);
1989         return err;
1990 }
1991
1992 static int
1993 typhoon_stop_runtime(struct typhoon *tp, int wait_type)
1994 {
1995         struct typhoon_indexes *indexes = tp->indexes;
1996         struct transmit_ring *txLo = &tp->txLoRing;
1997         void __iomem *ioaddr = tp->ioaddr;
1998         struct cmd_desc xp_cmd;
1999         int i;
2000
2001         /* Disable interrupts early, since we can't schedule a poll
2002          * when called with !netif_running(). This will be posted
2003          * when we force the posting of the command.
2004          */
2005         iowrite32(TYPHOON_INTR_NONE, ioaddr + TYPHOON_REG_INTR_ENABLE);
2006
2007         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_RX_DISABLE);
2008         typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
2009
2010         /* Wait 1/2 sec for any outstanding transmits to occur
2011          * We'll cleanup after the reset if this times out.
2012          */
2013         for(i = 0; i < TYPHOON_WAIT_TIMEOUT; i++) {
2014                 if(indexes->txLoCleared == cpu_to_le32(txLo->lastWrite))
2015                         break;
2016                 udelay(TYPHOON_UDELAY);
2017         }
2018
2019         if(i == TYPHOON_WAIT_TIMEOUT)
2020                 printk(KERN_ERR
2021                        "%s: halt timed out waiting for Tx to complete\n",
2022                        tp->name);
2023
2024         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_TX_DISABLE);
2025         typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
2026
2027         /* save the statistics so when we bring the interface up again,
2028          * the values reported to userspace are correct.
2029          */
2030         tp->card_state = Sleeping;
2031         smp_wmb();
2032         typhoon_do_get_stats(tp);
2033         memcpy(&tp->stats_saved, &tp->stats, sizeof(struct net_device_stats));
2034
2035         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_HALT);
2036         typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
2037
2038         if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_HALTED) < 0)
2039                 printk(KERN_ERR "%s: timed out waiting for 3XP to halt\n",
2040                        tp->name);
2041
2042         if(typhoon_reset(ioaddr, wait_type) < 0) {
2043                 printk(KERN_ERR "%s: unable to reset 3XP\n", tp->name);
2044                 return -ETIMEDOUT;
2045         }
2046
2047         /* cleanup any outstanding Tx packets */
2048         if(indexes->txLoCleared != cpu_to_le32(txLo->lastWrite)) {
2049                 indexes->txLoCleared = cpu_to_le32(txLo->lastWrite);
2050                 typhoon_clean_tx(tp, &tp->txLoRing, &indexes->txLoCleared);
2051         }
2052
2053         return 0;
2054 }
2055
2056 static void
2057 typhoon_tx_timeout(struct net_device *dev)
2058 {
2059         struct typhoon *tp = netdev_priv(dev);
2060
2061         if(typhoon_reset(tp->ioaddr, WaitNoSleep) < 0) {
2062                 printk(KERN_WARNING "%s: could not reset in tx timeout\n",
2063                                         dev->name);
2064                 goto truely_dead;
2065         }
2066
2067         /* If we ever start using the Hi ring, it will need cleaning too */
2068         typhoon_clean_tx(tp, &tp->txLoRing, &tp->indexes->txLoCleared);
2069         typhoon_free_rx_rings(tp);
2070
2071         if(typhoon_start_runtime(tp) < 0) {
2072                 printk(KERN_ERR "%s: could not start runtime in tx timeout\n",
2073                                         dev->name);
2074                 goto truely_dead;
2075         }
2076
2077         netif_wake_queue(dev);
2078         return;
2079
2080 truely_dead:
2081         /* Reset the hardware, and turn off carrier to avoid more timeouts */
2082         typhoon_reset(tp->ioaddr, NoWait);
2083         netif_carrier_off(dev);
2084 }
2085
2086 static int
2087 typhoon_open(struct net_device *dev)
2088 {
2089         struct typhoon *tp = netdev_priv(dev);
2090         int err;
2091
2092         err = typhoon_wakeup(tp, WaitSleep);
2093         if(err < 0) {
2094                 printk(KERN_ERR "%s: unable to wakeup device\n", dev->name);
2095                 goto out_sleep;
2096         }
2097
2098         err = request_irq(dev->irq, &typhoon_interrupt, IRQF_SHARED,
2099                                 dev->name, dev);
2100         if(err < 0)
2101                 goto out_sleep;
2102
2103         napi_enable(&tp->napi);
2104
2105         err = typhoon_start_runtime(tp);
2106         if(err < 0) {
2107                 napi_disable(&tp->napi);
2108                 goto out_irq;
2109         }
2110
2111         netif_start_queue(dev);
2112         return 0;
2113
2114 out_irq:
2115         free_irq(dev->irq, dev);
2116
2117 out_sleep:
2118         if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
2119                 printk(KERN_ERR "%s: unable to reboot into sleep img\n",
2120                                 dev->name);
2121                 typhoon_reset(tp->ioaddr, NoWait);
2122                 goto out;
2123         }
2124
2125         if(typhoon_sleep(tp, PCI_D3hot, 0) < 0)
2126                 printk(KERN_ERR "%s: unable to go back to sleep\n", dev->name);
2127
2128 out:
2129         return err;
2130 }
2131
2132 static int
2133 typhoon_close(struct net_device *dev)
2134 {
2135         struct typhoon *tp = netdev_priv(dev);
2136
2137         netif_stop_queue(dev);
2138         napi_disable(&tp->napi);
2139
2140         if(typhoon_stop_runtime(tp, WaitSleep) < 0)
2141                 printk(KERN_ERR "%s: unable to stop runtime\n", dev->name);
2142
2143         /* Make sure there is no irq handler running on a different CPU. */
2144         free_irq(dev->irq, dev);
2145
2146         typhoon_free_rx_rings(tp);
2147         typhoon_init_rings(tp);
2148
2149         if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0)
2150                 printk(KERN_ERR "%s: unable to boot sleep image\n", dev->name);
2151
2152         if(typhoon_sleep(tp, PCI_D3hot, 0) < 0)
2153                 printk(KERN_ERR "%s: unable to put card to sleep\n", dev->name);
2154
2155         return 0;
2156 }
2157
2158 #ifdef CONFIG_PM
2159 static int
2160 typhoon_resume(struct pci_dev *pdev)
2161 {
2162         struct net_device *dev = pci_get_drvdata(pdev);
2163         struct typhoon *tp = netdev_priv(dev);
2164
2165         /* If we're down, resume when we are upped.
2166          */
2167         if(!netif_running(dev))
2168                 return 0;
2169
2170         if(typhoon_wakeup(tp, WaitNoSleep) < 0) {
2171                 printk(KERN_ERR "%s: critical: could not wake up in resume\n",
2172                                 dev->name);
2173                 goto reset;
2174         }
2175
2176         if(typhoon_start_runtime(tp) < 0) {
2177                 printk(KERN_ERR "%s: critical: could not start runtime in "
2178                                 "resume\n", dev->name);
2179                 goto reset;
2180         }
2181
2182         netif_device_attach(dev);
2183         return 0;
2184
2185 reset:
2186         typhoon_reset(tp->ioaddr, NoWait);
2187         return -EBUSY;
2188 }
2189
2190 static int
2191 typhoon_suspend(struct pci_dev *pdev, pm_message_t state)
2192 {
2193         struct net_device *dev = pci_get_drvdata(pdev);
2194         struct typhoon *tp = netdev_priv(dev);
2195         struct cmd_desc xp_cmd;
2196
2197         /* If we're down, we're already suspended.
2198          */
2199         if(!netif_running(dev))
2200                 return 0;
2201
2202         spin_lock_bh(&tp->state_lock);
2203         if(tp->vlgrp && tp->wol_events & TYPHOON_WAKE_MAGIC_PKT) {
2204                 spin_unlock_bh(&tp->state_lock);
2205                 printk(KERN_ERR "%s: cannot do WAKE_MAGIC with VLANS\n",
2206                                 dev->name);
2207                 return -EBUSY;
2208         }
2209         spin_unlock_bh(&tp->state_lock);
2210
2211         netif_device_detach(dev);
2212
2213         if(typhoon_stop_runtime(tp, WaitNoSleep) < 0) {
2214                 printk(KERN_ERR "%s: unable to stop runtime\n", dev->name);
2215                 goto need_resume;
2216         }
2217
2218         typhoon_free_rx_rings(tp);
2219         typhoon_init_rings(tp);
2220
2221         if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
2222                 printk(KERN_ERR "%s: unable to boot sleep image\n", dev->name);
2223                 goto need_resume;
2224         }
2225
2226         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_MAC_ADDRESS);
2227         xp_cmd.parm1 = cpu_to_le16(ntohs(*(__be16 *)&dev->dev_addr[0]));
2228         xp_cmd.parm2 = cpu_to_le32(ntohl(*(__be32 *)&dev->dev_addr[2]));
2229         if(typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL) < 0) {
2230                 printk(KERN_ERR "%s: unable to set mac address in suspend\n",
2231                                 dev->name);
2232                 goto need_resume;
2233         }
2234
2235         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_RX_FILTER);
2236         xp_cmd.parm1 = TYPHOON_RX_FILTER_DIRECTED | TYPHOON_RX_FILTER_BROADCAST;
2237         if(typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL) < 0) {
2238                 printk(KERN_ERR "%s: unable to set rx filter in suspend\n",
2239                                 dev->name);
2240                 goto need_resume;
2241         }
2242
2243         if(typhoon_sleep(tp, pci_choose_state(pdev, state), tp->wol_events) < 0) {
2244                 printk(KERN_ERR "%s: unable to put card to sleep\n", dev->name);
2245                 goto need_resume;
2246         }
2247
2248         return 0;
2249
2250 need_resume:
2251         typhoon_resume(pdev);
2252         return -EBUSY;
2253 }
2254 #endif
2255
2256 static int __devinit
2257 typhoon_test_mmio(struct pci_dev *pdev)
2258 {
2259         void __iomem *ioaddr = pci_iomap(pdev, 1, 128);
2260         int mode = 0;
2261         u32 val;
2262
2263         if(!ioaddr)
2264                 goto out;
2265
2266         if(ioread32(ioaddr + TYPHOON_REG_STATUS) !=
2267                                 TYPHOON_STATUS_WAITING_FOR_HOST)
2268                 goto out_unmap;
2269
2270         iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
2271         iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);
2272         iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_ENABLE);
2273
2274         /* Ok, see if we can change our interrupt status register by
2275          * sending ourselves an interrupt. If so, then MMIO works.
2276          * The 50usec delay is arbitrary -- it could probably be smaller.
2277          */
2278         val = ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
2279         if((val & TYPHOON_INTR_SELF) == 0) {
2280                 iowrite32(1, ioaddr + TYPHOON_REG_SELF_INTERRUPT);
2281                 ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
2282                 udelay(50);
2283                 val = ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
2284                 if(val & TYPHOON_INTR_SELF)
2285                         mode = 1;
2286         }
2287
2288         iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
2289         iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);
2290         iowrite32(TYPHOON_INTR_NONE, ioaddr + TYPHOON_REG_INTR_ENABLE);
2291         ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
2292
2293 out_unmap:
2294         pci_iounmap(pdev, ioaddr);
2295
2296 out:
2297         if(!mode)
2298                 printk(KERN_INFO PFX "falling back to port IO\n");
2299         return mode;
2300 }
2301
2302 static int __devinit
2303 typhoon_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2304 {
2305         static int did_version = 0;
2306         struct net_device *dev;
2307         struct typhoon *tp;
2308         int card_id = (int) ent->driver_data;
2309         void __iomem *ioaddr;
2310         void *shared;
2311         dma_addr_t shared_dma;
2312         struct cmd_desc xp_cmd;
2313         struct resp_desc xp_resp[3];
2314         int err = 0;
2315         DECLARE_MAC_BUF(mac);
2316
2317         if(!did_version++)
2318                 printk(KERN_INFO "%s", version);
2319
2320         dev = alloc_etherdev(sizeof(*tp));
2321         if(dev == NULL) {
2322                 printk(ERR_PFX "%s: unable to alloc new net device\n",
2323                        pci_name(pdev));
2324                 err = -ENOMEM;
2325                 goto error_out;
2326         }
2327         SET_NETDEV_DEV(dev, &pdev->dev);
2328
2329         err = pci_enable_device(pdev);
2330         if(err < 0) {
2331                 printk(ERR_PFX "%s: unable to enable device\n",
2332                        pci_name(pdev));
2333                 goto error_out_dev;
2334         }
2335
2336         err = pci_set_mwi(pdev);
2337         if(err < 0) {
2338                 printk(ERR_PFX "%s: unable to set MWI\n", pci_name(pdev));
2339                 goto error_out_disable;
2340         }
2341
2342         err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2343         if(err < 0) {
2344                 printk(ERR_PFX "%s: No usable DMA configuration\n",
2345                        pci_name(pdev));
2346                 goto error_out_mwi;
2347         }
2348
2349         /* sanity checks on IO and MMIO BARs
2350          */
2351         if(!(pci_resource_flags(pdev, 0) & IORESOURCE_IO)) {
2352                 printk(ERR_PFX
2353                        "%s: region #1 not a PCI IO resource, aborting\n",
2354                        pci_name(pdev));
2355                 err = -ENODEV;
2356                 goto error_out_mwi;
2357         }
2358         if(pci_resource_len(pdev, 0) < 128) {
2359                 printk(ERR_PFX "%s: Invalid PCI IO region size, aborting\n",
2360                        pci_name(pdev));
2361                 err = -ENODEV;
2362                 goto error_out_mwi;
2363         }
2364         if(!(pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
2365                 printk(ERR_PFX
2366                        "%s: region #1 not a PCI MMIO resource, aborting\n",
2367                        pci_name(pdev));
2368                 err = -ENODEV;
2369                 goto error_out_mwi;
2370         }
2371         if(pci_resource_len(pdev, 1) < 128) {
2372                 printk(ERR_PFX "%s: Invalid PCI MMIO region size, aborting\n",
2373                        pci_name(pdev));
2374                 err = -ENODEV;
2375                 goto error_out_mwi;
2376         }
2377
2378         err = pci_request_regions(pdev, "typhoon");
2379         if(err < 0) {
2380                 printk(ERR_PFX "%s: could not request regions\n",
2381                        pci_name(pdev));
2382                 goto error_out_mwi;
2383         }
2384
2385         /* map our registers
2386          */
2387         if(use_mmio != 0 && use_mmio != 1)
2388                 use_mmio = typhoon_test_mmio(pdev);
2389
2390         ioaddr = pci_iomap(pdev, use_mmio, 128);
2391         if (!ioaddr) {
2392                 printk(ERR_PFX "%s: cannot remap registers, aborting\n",
2393                        pci_name(pdev));
2394                 err = -EIO;
2395                 goto error_out_regions;
2396         }
2397
2398         /* allocate pci dma space for rx and tx descriptor rings
2399          */
2400         shared = pci_alloc_consistent(pdev, sizeof(struct typhoon_shared),
2401                                       &shared_dma);
2402         if(!shared) {
2403                 printk(ERR_PFX "%s: could not allocate DMA memory\n",
2404                        pci_name(pdev));
2405                 err = -ENOMEM;
2406                 goto error_out_remap;
2407         }
2408
2409         dev->irq = pdev->irq;
2410         tp = netdev_priv(dev);
2411         tp->shared = (struct typhoon_shared *) shared;
2412         tp->shared_dma = shared_dma;
2413         tp->pdev = pdev;
2414         tp->tx_pdev = pdev;
2415         tp->ioaddr = ioaddr;
2416         tp->tx_ioaddr = ioaddr;
2417         tp->dev = dev;
2418
2419         /* Init sequence:
2420          * 1) Reset the adapter to clear any bad juju
2421          * 2) Reload the sleep image
2422          * 3) Boot the sleep image
2423          * 4) Get the hardware address.
2424          * 5) Put the card to sleep.
2425          */
2426         if (typhoon_reset(ioaddr, WaitSleep) < 0) {
2427                 printk(ERR_PFX "%s: could not reset 3XP\n", pci_name(pdev));
2428                 err = -EIO;
2429                 goto error_out_dma;
2430         }
2431
2432         /* Now that we've reset the 3XP and are sure it's not going to
2433          * write all over memory, enable bus mastering, and save our
2434          * state for resuming after a suspend.
2435          */
2436         pci_set_master(pdev);
2437         pci_save_state(pdev);
2438
2439         /* dev->name is not valid until we register, but we need to
2440          * use some common routines to initialize the card. So that those
2441          * routines print the right name, we keep our oun pointer to the name
2442          */
2443         tp->name = pci_name(pdev);
2444
2445         typhoon_init_interface(tp);
2446         typhoon_init_rings(tp);
2447
2448         if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
2449                 printk(ERR_PFX "%s: cannot boot 3XP sleep image\n",
2450                        pci_name(pdev));
2451                 err = -EIO;
2452                 goto error_out_reset;
2453         }
2454
2455         INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_MAC_ADDRESS);
2456         if(typhoon_issue_command(tp, 1, &xp_cmd, 1, xp_resp) < 0) {
2457                 printk(ERR_PFX "%s: cannot read MAC address\n",
2458                        pci_name(pdev));
2459                 err = -EIO;
2460                 goto error_out_reset;
2461         }
2462
2463         *(__be16 *)&dev->dev_addr[0] = htons(le16_to_cpu(xp_resp[0].parm1));
2464         *(__be32 *)&dev->dev_addr[2] = htonl(le32_to_cpu(xp_resp[0].parm2));
2465
2466         if(!is_valid_ether_addr(dev->dev_addr)) {
2467                 printk(ERR_PFX "%s: Could not obtain valid ethernet address, "
2468                        "aborting\n", pci_name(pdev));
2469                 goto error_out_reset;
2470         }
2471
2472         /* Read the Sleep Image version last, so the response is valid
2473          * later when we print out the version reported.
2474          */
2475         INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_VERSIONS);
2476         if(typhoon_issue_command(tp, 1, &xp_cmd, 3, xp_resp) < 0) {
2477                 printk(ERR_PFX "%s: Could not get Sleep Image version\n",
2478                         pci_name(pdev));
2479                 goto error_out_reset;
2480         }
2481
2482         tp->capabilities = typhoon_card_info[card_id].capabilities;
2483         tp->xcvr_select = TYPHOON_XCVR_AUTONEG;
2484
2485         /* Typhoon 1.0 Sleep Images return one response descriptor to the
2486          * READ_VERSIONS command. Those versions are OK after waking up
2487          * from sleep without needing a reset. Typhoon 1.1+ Sleep Images
2488          * seem to need a little extra help to get started. Since we don't
2489          * know how to nudge it along, just kick it.
2490          */
2491         if(xp_resp[0].numDesc != 0)
2492                 tp->capabilities |= TYPHOON_WAKEUP_NEEDS_RESET;
2493
2494         if(typhoon_sleep(tp, PCI_D3hot, 0) < 0) {
2495                 printk(ERR_PFX "%s: cannot put adapter to sleep\n",
2496                        pci_name(pdev));
2497                 err = -EIO;
2498                 goto error_out_reset;
2499         }
2500
2501         /* The chip-specific entries in the device structure. */
2502         dev->open               = typhoon_open;
2503         dev->hard_start_xmit    = typhoon_start_tx;
2504         dev->stop               = typhoon_close;
2505         dev->set_multicast_list = typhoon_set_rx_mode;
2506         dev->tx_timeout         = typhoon_tx_timeout;
2507         netif_napi_add(dev, &tp->napi, typhoon_poll, 16);
2508         dev->watchdog_timeo     = TX_TIMEOUT;
2509         dev->get_stats          = typhoon_get_stats;
2510         dev->set_mac_address    = typhoon_set_mac_address;
2511         dev->vlan_rx_register   = typhoon_vlan_rx_register;
2512
2513         SET_ETHTOOL_OPS(dev, &typhoon_ethtool_ops);
2514
2515         /* We can handle scatter gather, up to 16 entries, and
2516          * we can do IP checksumming (only version 4, doh...)
2517          */
2518         dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
2519         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2520         dev->features |= NETIF_F_TSO;
2521
2522         if(register_netdev(dev) < 0)
2523                 goto error_out_reset;
2524
2525         /* fixup our local name */
2526         tp->name = dev->name;
2527
2528         pci_set_drvdata(pdev, dev);
2529
2530         printk(KERN_INFO "%s: %s at %s 0x%llx, %s\n",
2531                dev->name, typhoon_card_info[card_id].name,
2532                use_mmio ? "MMIO" : "IO",
2533                (unsigned long long)pci_resource_start(pdev, use_mmio),
2534                print_mac(mac, dev->dev_addr));
2535
2536         /* xp_resp still contains the response to the READ_VERSIONS command.
2537          * For debugging, let the user know what version he has.
2538          */
2539         if(xp_resp[0].numDesc == 0) {
2540                 /* This is the Typhoon 1.0 type Sleep Image, last 16 bits
2541                  * of version is Month/Day of build.
2542                  */
2543                 u16 monthday = le32_to_cpu(xp_resp[0].parm2) & 0xffff;
2544                 printk(KERN_INFO "%s: Typhoon 1.0 Sleep Image built "
2545                         "%02u/%02u/2000\n", dev->name, monthday >> 8,
2546                         monthday & 0xff);
2547         } else if(xp_resp[0].numDesc == 2) {
2548                 /* This is the Typhoon 1.1+ type Sleep Image
2549                  */
2550                 u32 sleep_ver = le32_to_cpu(xp_resp[0].parm2);
2551                 u8 *ver_string = (u8 *) &xp_resp[1];
2552                 ver_string[25] = 0;
2553                 printk(KERN_INFO "%s: Typhoon 1.1+ Sleep Image version "
2554                         "%02x.%03x.%03x %s\n", dev->name, sleep_ver >> 24,
2555                         (sleep_ver >> 12) & 0xfff, sleep_ver & 0xfff,
2556                         ver_string);
2557         } else {
2558                 printk(KERN_WARNING "%s: Unknown Sleep Image version "
2559                         "(%u:%04x)\n", dev->name, xp_resp[0].numDesc,
2560                         le32_to_cpu(xp_resp[0].parm2));
2561         }
2562
2563         return 0;
2564
2565 error_out_reset:
2566         typhoon_reset(ioaddr, NoWait);
2567
2568 error_out_dma:
2569         pci_free_consistent(pdev, sizeof(struct typhoon_shared),
2570                             shared, shared_dma);
2571 error_out_remap:
2572         pci_iounmap(pdev, ioaddr);
2573 error_out_regions:
2574         pci_release_regions(pdev);
2575 error_out_mwi:
2576         pci_clear_mwi(pdev);
2577 error_out_disable:
2578         pci_disable_device(pdev);
2579 error_out_dev:
2580         free_netdev(dev);
2581 error_out:
2582         return err;
2583 }
2584
2585 static void __devexit
2586 typhoon_remove_one(struct pci_dev *pdev)
2587 {
2588         struct net_device *dev = pci_get_drvdata(pdev);
2589         struct typhoon *tp = netdev_priv(dev);
2590
2591         unregister_netdev(dev);
2592         pci_set_power_state(pdev, PCI_D0);
2593         pci_restore_state(pdev);
2594         typhoon_reset(tp->ioaddr, NoWait);
2595         pci_iounmap(pdev, tp->ioaddr);
2596         pci_free_consistent(pdev, sizeof(struct typhoon_shared),
2597                             tp->shared, tp->shared_dma);
2598         pci_release_regions(pdev);
2599         pci_clear_mwi(pdev);
2600         pci_disable_device(pdev);
2601         pci_set_drvdata(pdev, NULL);
2602         free_netdev(dev);
2603 }
2604
2605 static struct pci_driver typhoon_driver = {
2606         .name           = DRV_MODULE_NAME,
2607         .id_table       = typhoon_pci_tbl,
2608         .probe          = typhoon_init_one,
2609         .remove         = __devexit_p(typhoon_remove_one),
2610 #ifdef CONFIG_PM
2611         .suspend        = typhoon_suspend,
2612         .resume         = typhoon_resume,
2613 #endif
2614 };
2615
2616 static int __init
2617 typhoon_init(void)
2618 {
2619         return pci_register_driver(&typhoon_driver);
2620 }
2621
2622 static void __exit
2623 typhoon_cleanup(void)
2624 {
2625         pci_unregister_driver(&typhoon_driver);
2626 }
2627
2628 module_init(typhoon_init);
2629 module_exit(typhoon_cleanup);