1 #ifndef __ASM_X86_PROCESSOR_H
2 #define __ASM_X86_PROCESSOR_H
4 #include <asm/processor-flags.h>
6 /* migration helpers, for KVM - will be removed in 2.6.25: */
8 #define Xgt_desc_struct desc_ptr
10 /* Forward declaration, a strange C thing */
15 #include <asm/math_emu.h>
16 #include <asm/segment.h>
17 #include <asm/types.h>
18 #include <asm/sigcontext.h>
19 #include <asm/current.h>
20 #include <asm/cpufeature.h>
21 #include <asm/system.h>
23 #include <asm/percpu.h>
25 #include <asm/desc_defs.h>
28 #include <linux/personality.h>
29 #include <linux/cpumask.h>
30 #include <linux/cache.h>
31 #include <linux/threads.h>
32 #include <linux/init.h>
35 * Default implementation of macro that returns current
36 * instruction pointer ("program counter").
38 static inline void *current_text_addr(void)
42 asm volatile("mov $1f, %0; 1:":"=r" (pc));
47 #ifdef CONFIG_X86_VSMP
48 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
49 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
51 # define ARCH_MIN_TASKALIGN 16
52 # define ARCH_MIN_MMSTRUCT_ALIGN 0
56 * CPU type and hardware bug flags. Kept separately for each CPU.
57 * Members of this structure are referenced in head.S, so think twice
58 * before touching them. [mj]
62 __u8 x86; /* CPU family */
63 __u8 x86_vendor; /* CPU vendor */
67 char wp_works_ok; /* It doesn't on 386's */
69 /* Problems on some 486Dx4's and old 386's: */
78 /* Number of 4K pages in DTLB/ITLB combined(in pages): */
82 /* CPUID returned core id bits: */
84 /* Max extended CPUID function supported: */
85 __u32 extended_cpuid_level;
87 /* Maximum supported CPUID level, -1=no CPUID: */
89 __u32 x86_capability[NCAPINTS];
90 char x86_vendor_id[16];
91 char x86_model_id[64];
92 /* in KB - valid for CPUS which support this call: */
94 int x86_cache_alignment; /* In bytes */
96 unsigned long loops_per_jiffy;
98 /* cpus sharing the last level cache: */
99 cpumask_t llc_shared_map;
101 /* cpuid returned max cores value: */
104 u16 x86_clflush_size;
106 /* number of cores as seen by the OS: */
108 /* Physical processor id: */
112 /* Index into per_cpu list: */
115 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
117 #define X86_VENDOR_INTEL 0
118 #define X86_VENDOR_CYRIX 1
119 #define X86_VENDOR_AMD 2
120 #define X86_VENDOR_UMC 3
121 #define X86_VENDOR_NEXGEN 4
122 #define X86_VENDOR_CENTAUR 5
123 #define X86_VENDOR_TRANSMETA 7
124 #define X86_VENDOR_NSC 8
125 #define X86_VENDOR_NUM 9
127 #define X86_VENDOR_UNKNOWN 0xff
130 * capabilities of CPUs
132 extern struct cpuinfo_x86 boot_cpu_data;
133 extern struct cpuinfo_x86 new_cpu_data;
135 extern struct tss_struct doublefault_tss;
136 extern __u32 cleared_cpu_caps[NCAPINTS];
139 DECLARE_PER_CPU(struct cpuinfo_x86, cpu_info);
140 #define cpu_data(cpu) per_cpu(cpu_info, cpu)
141 #define current_cpu_data cpu_data(smp_processor_id())
143 #define cpu_data(cpu) boot_cpu_data
144 #define current_cpu_data boot_cpu_data
147 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
149 extern void cpu_detect(struct cpuinfo_x86 *c);
151 extern void identify_cpu(struct cpuinfo_x86 *);
152 extern void identify_boot_cpu(void);
153 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
154 extern void print_cpu_info(struct cpuinfo_x86 *);
155 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
156 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
157 extern unsigned short num_cache_leaves;
159 #if defined(CONFIG_X86_HT) || defined(CONFIG_X86_64)
160 extern void detect_ht(struct cpuinfo_x86 *c);
162 static inline void detect_ht(struct cpuinfo_x86 *c) {}
165 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
166 unsigned int *ecx, unsigned int *edx)
168 /* ecx is often an input as well as an output. */
174 : "0" (*eax), "2" (*ecx));
177 static inline void load_cr3(pgd_t *pgdir)
179 write_cr3(__pa(pgdir));
183 /* This is the TSS defined by the hardware. */
185 unsigned short back_link, __blh;
187 unsigned short ss0, __ss0h;
189 /* ss1 caches MSR_IA32_SYSENTER_CS: */
190 unsigned short ss1, __ss1h;
192 unsigned short ss2, __ss2h;
204 unsigned short es, __esh;
205 unsigned short cs, __csh;
206 unsigned short ss, __ssh;
207 unsigned short ds, __dsh;
208 unsigned short fs, __fsh;
209 unsigned short gs, __gsh;
210 unsigned short ldt, __ldth;
211 unsigned short trace;
212 unsigned short io_bitmap_base;
214 } __attribute__((packed));
228 } __attribute__((packed)) ____cacheline_aligned;
234 #define IO_BITMAP_BITS 65536
235 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
236 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
237 #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap)
238 #define INVALID_IO_BITMAP_OFFSET 0x8000
239 #define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000
243 * The hardware state:
245 struct x86_hw_tss x86_tss;
248 * The extra 1 is there because the CPU will access an
249 * additional byte beyond the end of the IO permission
250 * bitmap. The extra byte must be all 1 bits, and must
251 * be within the limit.
253 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
255 * Cache the current maximum and the last task that used the bitmap:
257 unsigned long io_bitmap_max;
258 struct thread_struct *io_bitmap_owner;
261 * Pad the TSS to be cacheline-aligned (size is 0x100):
263 unsigned long __cacheline_filler[35];
265 * .. and then another 0x100 bytes for the emergency kernel stack:
267 unsigned long stack[64];
269 } __attribute__((packed));
271 DECLARE_PER_CPU(struct tss_struct, init_tss);
274 * Save the original ist values for checking stack pointers during debugging
277 unsigned long ist[7];
280 #define MXCSR_DEFAULT 0x1f80
282 struct i387_fsave_struct {
290 /* 8*10 bytes for each FP-reg = 80 bytes: */
292 /* Software status information: */
296 struct i387_fxsave_struct {
315 /* 8*16 bytes for each FP-reg = 128 bytes: */
317 /* 16*16 bytes for each XMM-reg = 256 bytes: */
321 } __attribute__((aligned(16)));
323 struct i387_soft_struct {
331 /* 8*10 bytes for each FP-reg = 80 bytes: */
344 struct i387_fsave_struct fsave;
345 struct i387_fxsave_struct fxsave;
346 struct i387_soft_struct soft;
350 DECLARE_PER_CPU(u8, cpu_llc_id);
352 DECLARE_PER_CPU(struct orig_ist, orig_ist);
355 extern void print_cpu_info(struct cpuinfo_x86 *);
356 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
357 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
358 extern unsigned short num_cache_leaves;
360 struct thread_struct {
361 /* Cached TLS descriptors: */
362 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
366 unsigned long sysenter_cs;
368 unsigned long usersp; /* Copy from PDA */
371 unsigned short fsindex;
372 unsigned short gsindex;
377 /* Hardware debugging registers: */
378 unsigned long debugreg0;
379 unsigned long debugreg1;
380 unsigned long debugreg2;
381 unsigned long debugreg3;
382 unsigned long debugreg6;
383 unsigned long debugreg7;
386 unsigned long trap_no;
387 unsigned long error_code;
388 /* Floating point info: */
389 union i387_union i387 __attribute__((aligned(16)));;
391 /* Virtual 86 mode info */
392 struct vm86_struct __user *vm86_info;
393 unsigned long screen_bitmap;
394 unsigned long v86flags;
395 unsigned long v86mask;
396 unsigned long saved_sp0;
397 unsigned int saved_fs;
398 unsigned int saved_gs;
400 /* IO permissions: */
401 unsigned long *io_bitmap_ptr;
403 /* Max allowed port in the bitmap, in bytes: */
404 unsigned io_bitmap_max;
405 /* MSR_IA32_DEBUGCTLMSR value to switch in if TIF_DEBUGCTLMSR is set. */
406 unsigned long debugctlmsr;
407 /* Debug Store - if not 0 points to a DS Save Area configuration;
408 * goes into MSR_IA32_DS_AREA */
409 unsigned long ds_area_msr;
412 static inline unsigned long native_get_debugreg(int regno)
414 unsigned long val = 0; /* Damn you, gcc! */
418 asm("mov %%db0, %0" :"=r" (val)); break;
420 asm("mov %%db1, %0" :"=r" (val)); break;
422 asm("mov %%db2, %0" :"=r" (val)); break;
424 asm("mov %%db3, %0" :"=r" (val)); break;
426 asm("mov %%db6, %0" :"=r" (val)); break;
428 asm("mov %%db7, %0" :"=r" (val)); break;
435 static inline void native_set_debugreg(int regno, unsigned long value)
439 asm("mov %0, %%db0" ::"r" (value));
442 asm("mov %0, %%db1" ::"r" (value));
445 asm("mov %0, %%db2" ::"r" (value));
448 asm("mov %0, %%db3" ::"r" (value));
451 asm("mov %0, %%db6" ::"r" (value));
454 asm("mov %0, %%db7" ::"r" (value));
462 * Set IOPL bits in EFLAGS from given mask
464 static inline void native_set_iopl_mask(unsigned mask)
469 __asm__ __volatile__ ("pushfl;"
476 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
481 native_load_sp0(struct tss_struct *tss, struct thread_struct *thread)
483 tss->x86_tss.sp0 = thread->sp0;
485 /* Only happens when SEP is enabled, no need to test "SEP"arately: */
486 if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
487 tss->x86_tss.ss1 = thread->sysenter_cs;
488 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
493 static inline void native_swapgs(void)
496 asm volatile("swapgs" ::: "memory");
500 #ifdef CONFIG_PARAVIRT
501 #include <asm/paravirt.h>
503 #define __cpuid native_cpuid
504 #define paravirt_enabled() 0
507 * These special macros can be used to get or set a debugging register
509 #define get_debugreg(var, register) \
510 (var) = native_get_debugreg(register)
511 #define set_debugreg(value, register) \
512 native_set_debugreg(register, value)
515 load_sp0(struct tss_struct *tss, struct thread_struct *thread)
517 native_load_sp0(tss, thread);
520 #define set_iopl_mask native_set_iopl_mask
521 #define SWAPGS swapgs
522 #endif /* CONFIG_PARAVIRT */
525 * Save the cr4 feature set we're using (ie
526 * Pentium 4MB enable and PPro Global page
527 * enable), so that any CPU's that boot up
528 * after us can get the correct flags.
530 extern unsigned long mmu_cr4_features;
532 static inline void set_in_cr4(unsigned long mask)
536 mmu_cr4_features |= mask;
542 static inline void clear_in_cr4(unsigned long mask)
546 mmu_cr4_features &= ~mask;
552 struct microcode_header {
560 unsigned int datasize;
561 unsigned int totalsize;
562 unsigned int reserved[3];
566 struct microcode_header hdr;
567 unsigned int bits[0];
570 typedef struct microcode microcode_t;
571 typedef struct microcode_header microcode_header_t;
573 /* microcode format is extended from prescott processors */
574 struct extended_signature {
580 struct extended_sigtable {
583 unsigned int reserved[3];
584 struct extended_signature sigs[0];
593 * create a kernel thread without removing it from tasklists
595 extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
597 /* Free all resources held by a thread. */
598 extern void release_thread(struct task_struct *);
600 /* Prepare to copy thread state - unlazy all lazy state */
601 extern void prepare_to_copy(struct task_struct *tsk);
603 unsigned long get_wchan(struct task_struct *p);
606 * Generic CPUID function
607 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
608 * resulting in stale register contents being returned.
610 static inline void cpuid(unsigned int op,
611 unsigned int *eax, unsigned int *ebx,
612 unsigned int *ecx, unsigned int *edx)
616 __cpuid(eax, ebx, ecx, edx);
619 /* Some CPUID calls want 'count' to be placed in ecx */
620 static inline void cpuid_count(unsigned int op, int count,
621 unsigned int *eax, unsigned int *ebx,
622 unsigned int *ecx, unsigned int *edx)
626 __cpuid(eax, ebx, ecx, edx);
630 * CPUID functions returning a single datum
632 static inline unsigned int cpuid_eax(unsigned int op)
634 unsigned int eax, ebx, ecx, edx;
636 cpuid(op, &eax, &ebx, &ecx, &edx);
641 static inline unsigned int cpuid_ebx(unsigned int op)
643 unsigned int eax, ebx, ecx, edx;
645 cpuid(op, &eax, &ebx, &ecx, &edx);
650 static inline unsigned int cpuid_ecx(unsigned int op)
652 unsigned int eax, ebx, ecx, edx;
654 cpuid(op, &eax, &ebx, &ecx, &edx);
659 static inline unsigned int cpuid_edx(unsigned int op)
661 unsigned int eax, ebx, ecx, edx;
663 cpuid(op, &eax, &ebx, &ecx, &edx);
668 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
669 static inline void rep_nop(void)
671 __asm__ __volatile__("rep; nop" ::: "memory");
674 static inline void cpu_relax(void)
679 /* Stop speculative execution: */
680 static inline void sync_core(void)
684 asm volatile("cpuid" : "=a" (tmp) : "0" (1)
685 : "ebx", "ecx", "edx", "memory");
689 __monitor(const void *eax, unsigned long ecx, unsigned long edx)
691 /* "monitor %eax, %ecx, %edx;" */
693 ".byte 0x0f, 0x01, 0xc8;"
694 :: "a" (eax), "c" (ecx), "d"(edx));
697 static inline void __mwait(unsigned long eax, unsigned long ecx)
699 /* "mwait %eax, %ecx;" */
701 ".byte 0x0f, 0x01, 0xc9;"
702 :: "a" (eax), "c" (ecx));
705 static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
707 /* "mwait %eax, %ecx;" */
709 "sti; .byte 0x0f, 0x01, 0xc9;"
710 :: "a" (eax), "c" (ecx));
713 extern void mwait_idle_with_hints(unsigned long eax, unsigned long ecx);
715 extern int force_mwait;
717 extern void select_idle_routine(const struct cpuinfo_x86 *c);
719 extern unsigned long boot_option_idle_override;
721 extern void enable_sep_cpu(void);
722 extern int sysenter_setup(void);
724 /* Defined in head.S */
725 extern struct desc_ptr early_gdt_descr;
727 extern void cpu_set_gdt(int);
728 extern void switch_to_new_gdt(void);
729 extern void cpu_init(void);
730 extern void init_gdt(int cpu);
733 * from system description table in BIOS. Mostly for MCA use, but
734 * others may find it useful:
736 extern unsigned int machine_id;
737 extern unsigned int machine_submodel_id;
738 extern unsigned int BIOS_revision;
740 /* Boot loader type from the setup header: */
741 extern int bootloader_type;
743 extern char ignore_fpu_irq;
745 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
746 #define ARCH_HAS_PREFETCHW
747 #define ARCH_HAS_SPINLOCK_PREFETCH
750 # define BASE_PREFETCH ASM_NOP4
751 # define ARCH_HAS_PREFETCH
753 # define BASE_PREFETCH "prefetcht0 (%1)"
757 * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
759 * It's not worth to care about 3dnow prefetches for the K6
760 * because they are microcoded there and very slow.
762 static inline void prefetch(const void *x)
764 alternative_input(BASE_PREFETCH,
771 * 3dnow prefetch to get an exclusive cache line.
772 * Useful for spinlocks to avoid one state transition in the
773 * cache coherency protocol:
775 static inline void prefetchw(const void *x)
777 alternative_input(BASE_PREFETCH,
783 static inline void spin_lock_prefetch(const void *x)
790 * User space process size: 3GB (default).
792 #define TASK_SIZE PAGE_OFFSET
793 #define STACK_TOP TASK_SIZE
794 #define STACK_TOP_MAX STACK_TOP
796 #define INIT_THREAD { \
797 .sp0 = sizeof(init_stack) + (long)&init_stack, \
799 .sysenter_cs = __KERNEL_CS, \
800 .io_bitmap_ptr = NULL, \
801 .fs = __KERNEL_PERCPU, \
805 * Note that the .io_bitmap member must be extra-big. This is because
806 * the CPU will access an additional byte beyond the end of the IO
807 * permission bitmap. The extra byte must be all 1 bits, and must
808 * be within the limit.
812 .sp0 = sizeof(init_stack) + (long)&init_stack, \
813 .ss0 = __KERNEL_DS, \
814 .ss1 = __KERNEL_CS, \
815 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
817 .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, \
820 extern unsigned long thread_saved_pc(struct task_struct *tsk);
822 #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
823 #define KSTK_TOP(info) \
825 unsigned long *__ptr = (unsigned long *)(info); \
826 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
830 * The below -8 is to reserve 8 bytes on top of the ring0 stack.
831 * This is necessary to guarantee that the entire "struct pt_regs"
832 * is accessable even if the CPU haven't stored the SS/ESP registers
833 * on the stack (interrupt gate does not save these registers
834 * when switching to the same priv ring).
835 * Therefore beware: accessing the ss/esp fields of the
836 * "struct pt_regs" is possible, but they may contain the
837 * completely wrong values.
839 #define task_pt_regs(task) \
841 struct pt_regs *__regs__; \
842 __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
846 #define KSTK_ESP(task) (task_pt_regs(task)->sp)
850 * User space process size. 47bits minus one guard page.
852 #define TASK_SIZE64 (0x800000000000UL - 4096)
854 /* This decides where the kernel will search for a free chunk of vm
855 * space during mmap's.
857 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \
858 0xc0000000 : 0xFFFFe000)
860 #define TASK_SIZE (test_thread_flag(TIF_IA32) ? \
861 IA32_PAGE_OFFSET : TASK_SIZE64)
862 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_IA32)) ? \
863 IA32_PAGE_OFFSET : TASK_SIZE64)
865 #define STACK_TOP TASK_SIZE
866 #define STACK_TOP_MAX TASK_SIZE64
868 #define INIT_THREAD { \
869 .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
873 .x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
877 * Return saved PC of a blocked thread.
878 * What is this good for? it will be always the scheduler or ret_from_fork.
880 #define thread_saved_pc(t) (*(unsigned long *)((t)->thread.sp - 8))
882 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1)
883 #define KSTK_ESP(tsk) -1 /* sorry. doesn't work for syscall. */
884 #endif /* CONFIG_X86_64 */
886 extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
887 unsigned long new_sp);
890 * This decides where the kernel will search for a free chunk of vm
891 * space during mmap's.
893 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
895 #define KSTK_EIP(task) (task_pt_regs(task)->ip)