manual update from upstream:
[linux-2.6] / arch / mips / kernel / smp_mt.c
1 /*
2  * Copyright (C) 2004, 2005 MIPS Technologies, Inc.  All rights reserved.
3  *
4  *  Elizabeth Clarke (beth@mips.com)
5  *
6  *  This program is free software; you can distribute it and/or modify it
7  *  under the terms of the GNU General Public License (Version 2) as
8  *  published by the Free Software Foundation.
9  *
10  *  This program is distributed in the hope it will be useful, but WITHOUT
11  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
13  *  for more details.
14  *
15  *  You should have received a copy of the GNU General Public License along
16  *  with this program; if not, write to the Free Software Foundation, Inc.,
17  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
18  *
19  */
20 #include <linux/kernel.h>
21 #include <linux/sched.h>
22 #include <linux/cpumask.h>
23 #include <linux/interrupt.h>
24 #include <linux/compiler.h>
25
26 #include <asm/atomic.h>
27 #include <asm/cpu.h>
28 #include <asm/processor.h>
29 #include <asm/system.h>
30 #include <asm/hardirq.h>
31 #include <asm/mmu_context.h>
32 #include <asm/smp.h>
33 #include <asm/time.h>
34 #include <asm/mipsregs.h>
35 #include <asm/mipsmtregs.h>
36 #include <asm/cacheflush.h>
37 #include <asm/mips-boards/maltaint.h>
38
39 #define MIPS_CPU_IPI_RESCHED_IRQ 0
40 #define MIPS_CPU_IPI_CALL_IRQ 1
41
42 static int cpu_ipi_resched_irq, cpu_ipi_call_irq;
43
44 #if 0
45 static void dump_mtregisters(int vpe, int tc)
46 {
47         printk("vpe %d tc %d\n", vpe, tc);
48
49         settc(tc);
50
51         printk("  c0 status  0x%lx\n", read_vpe_c0_status());
52         printk("  vpecontrol 0x%lx\n", read_vpe_c0_vpecontrol());
53         printk("  vpeconf0    0x%lx\n", read_vpe_c0_vpeconf0());
54         printk("  tcstatus 0x%lx\n", read_tc_c0_tcstatus());
55         printk("  tcrestart 0x%lx\n", read_tc_c0_tcrestart());
56         printk("  tcbind 0x%lx\n", read_tc_c0_tcbind());
57         printk("  tchalt 0x%lx\n", read_tc_c0_tchalt());
58 }
59 #endif
60
61 void __init sanitize_tlb_entries(void)
62 {
63         int i, tlbsiz;
64         unsigned long mvpconf0, ncpu;
65
66         if (!cpu_has_mipsmt)
67                 return;
68
69         set_c0_mvpcontrol(MVPCONTROL_VPC);
70
71         /* Disable TLB sharing */
72         clear_c0_mvpcontrol(MVPCONTROL_STLB);
73
74         mvpconf0 = read_c0_mvpconf0();
75
76         printk(KERN_INFO "MVPConf0 0x%lx TLBS %lx PTLBE %ld\n", mvpconf0,
77                    (mvpconf0 & MVPCONF0_TLBS) >> MVPCONF0_TLBS_SHIFT,
78                            (mvpconf0 & MVPCONF0_PTLBE) >> MVPCONF0_PTLBE_SHIFT);
79
80         tlbsiz = (mvpconf0 & MVPCONF0_PTLBE) >> MVPCONF0_PTLBE_SHIFT;
81         ncpu = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
82
83         printk(" tlbsiz %d ncpu %ld\n", tlbsiz, ncpu);
84
85         if (tlbsiz > 0) {
86                 /* share them out across the vpe's */
87                 tlbsiz /= ncpu;
88
89                 printk(KERN_INFO "setting Config1.MMU_size to %d\n", tlbsiz);
90
91                 for (i = 0; i < ncpu; i++) {
92                         settc(i);
93
94                         if (i == 0)
95                                 write_c0_config1((read_c0_config1() & ~(0x3f << 25)) | (tlbsiz << 25));
96                         else
97                                 write_vpe_c0_config1((read_vpe_c0_config1() & ~(0x3f << 25)) |
98                                                    (tlbsiz << 25));
99                 }
100         }
101
102         clear_c0_mvpcontrol(MVPCONTROL_VPC);
103 }
104
105 #if 0
106 /*
107  * Use c0_MVPConf0 to find out how many CPUs are available, setting up
108  * phys_cpu_present_map and the logical/physical mappings.
109  */
110 void __init prom_build_cpu_map(void)
111 {
112         int i, num, ncpus;
113
114         cpus_clear(phys_cpu_present_map);
115
116         /* assume we boot on cpu 0.... */
117         cpu_set(0, phys_cpu_present_map);
118         __cpu_number_map[0] = 0;
119         __cpu_logical_map[0] = 0;
120
121         if (cpu_has_mipsmt) {
122                 ncpus = ((read_c0_mvpconf0() & (MVPCONF0_PVPE)) >> MVPCONF0_PVPE_SHIFT) + 1;
123                 for (i=1, num=0; i< NR_CPUS && i<ncpus; i++) {
124                         cpu_set(i, phys_cpu_present_map);
125                         __cpu_number_map[i] = ++num;
126                         __cpu_logical_map[num] = i;
127                 }
128
129                 printk(KERN_INFO "%i available secondary CPU(s)\n", num);
130         }
131 }
132 #endif
133
134 static void ipi_resched_dispatch (struct pt_regs *regs)
135 {
136         do_IRQ(MIPS_CPU_IPI_RESCHED_IRQ, regs);
137 }
138
139 static void ipi_call_dispatch (struct pt_regs *regs)
140 {
141         do_IRQ(MIPS_CPU_IPI_CALL_IRQ, regs);
142 }
143
144 irqreturn_t ipi_resched_interrupt(int irq, void *dev_id, struct pt_regs *regs)
145 {
146         return IRQ_HANDLED;
147 }
148
149 irqreturn_t ipi_call_interrupt(int irq, void *dev_id, struct pt_regs *regs)
150 {
151         smp_call_function_interrupt();
152
153         return IRQ_HANDLED;
154 }
155
156 static struct irqaction irq_resched = {
157         .handler        = ipi_resched_interrupt,
158         .flags          = SA_INTERRUPT,
159         .name           = "IPI_resched"
160 };
161
162 static struct irqaction irq_call = {
163         .handler        = ipi_call_interrupt,
164         .flags          = SA_INTERRUPT,
165         .name           = "IPI_call"
166 };
167
168 /*
169  * Common setup before any secondaries are started
170  * Make sure all CPU's are in a sensible state before we boot any of the
171  * secondarys
172  */
173 void prom_prepare_cpus(unsigned int max_cpus)
174 {
175         unsigned long val;
176         int i, num;
177
178         if (!cpu_has_mipsmt)
179                 return;
180
181         /* disable MT so we can configure */
182         dvpe();
183         dmt();
184
185         /* Put MVPE's into 'configuration state' */
186         set_c0_mvpcontrol(MVPCONTROL_VPC);
187
188         val = read_c0_mvpconf0();
189
190         /* we'll always have more TC's than VPE's, so loop setting everything
191            to a sensible state */
192         for (i = 0, num = 0; i <= ((val & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT); i++) {
193                 settc(i);
194
195                 /* VPE's */
196                 if (i <= ((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT)) {
197
198                         /* deactivate all but vpe0 */
199                         if (i != 0) {
200                                 unsigned long tmp = read_vpe_c0_vpeconf0();
201
202                                 tmp &= ~VPECONF0_VPA;
203
204                                 /* master VPE */
205                                 tmp |= VPECONF0_MVP;
206                                 write_vpe_c0_vpeconf0(tmp);
207
208                                 /* Record this as available CPU */
209                                 if (i < max_cpus) {
210                                         cpu_set(i, phys_cpu_present_map);
211                                         __cpu_number_map[i]     = ++num;
212                                         __cpu_logical_map[num]  = i;
213                                 }
214                         }
215
216                         /* disable multi-threading with TC's */
217                         write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() & ~VPECONTROL_TE);
218
219                         if (i != 0) {
220                                 write_vpe_c0_status((read_c0_status() & ~(ST0_IM | ST0_IE | ST0_KSU)) | ST0_CU0);
221                                 write_vpe_c0_cause(read_vpe_c0_cause() & ~CAUSEF_IP);
222
223                                 /* set config to be the same as vpe0, particularly kseg0 coherency alg */
224                                 write_vpe_c0_config( read_c0_config());
225                         }
226
227                 }
228
229                 /* TC's */
230
231                 if (i != 0) {
232                         unsigned long tmp;
233
234                         /* bind a TC to each VPE, May as well put all excess TC's
235                            on the last VPE */
236                         if ( i >= (((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT)+1) )
237                                 write_tc_c0_tcbind(read_tc_c0_tcbind() | ((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) );
238                         else {
239                                 write_tc_c0_tcbind( read_tc_c0_tcbind() | i);
240
241                                 /* and set XTC */
242                                 write_vpe_c0_vpeconf0( read_vpe_c0_vpeconf0() | (i << VPECONF0_XTC_SHIFT));
243                         }
244
245                         tmp = read_tc_c0_tcstatus();
246
247                         /* mark not allocated and not dynamically allocatable */
248                         tmp &= ~(TCSTATUS_A | TCSTATUS_DA);
249                         tmp |= TCSTATUS_IXMT;           /* interrupt exempt */
250                         write_tc_c0_tcstatus(tmp);
251
252                         write_tc_c0_tchalt(TCHALT_H);
253                 }
254         }
255
256         /* Release config state */
257         clear_c0_mvpcontrol(MVPCONTROL_VPC);
258
259         /* We'll wait until starting the secondaries before starting MVPE */
260
261         printk(KERN_INFO "Detected %i available secondary CPU(s)\n", num);
262
263         /* set up ipi interrupts */
264         if (cpu_has_vint) {
265                 set_vi_handler (MIPS_CPU_IPI_RESCHED_IRQ, ipi_resched_dispatch);
266                 set_vi_handler (MIPS_CPU_IPI_CALL_IRQ, ipi_call_dispatch);
267         }
268
269         cpu_ipi_resched_irq = MIPSCPU_INT_BASE + MIPS_CPU_IPI_RESCHED_IRQ;
270         cpu_ipi_call_irq = MIPSCPU_INT_BASE + MIPS_CPU_IPI_CALL_IRQ;
271
272         setup_irq(cpu_ipi_resched_irq, &irq_resched);
273         setup_irq(cpu_ipi_call_irq, &irq_call);
274
275         /* need to mark IPI's as IRQ_PER_CPU */
276         irq_desc[cpu_ipi_resched_irq].status |= IRQ_PER_CPU;
277         irq_desc[cpu_ipi_call_irq].status |= IRQ_PER_CPU;
278 }
279
280 /*
281  * Setup the PC, SP, and GP of a secondary processor and start it
282  * running!
283  * smp_bootstrap is the place to resume from
284  * __KSTK_TOS(idle) is apparently the stack pointer
285  * (unsigned long)idle->thread_info the gp
286  * assumes a 1:1 mapping of TC => VPE
287  */
288 void prom_boot_secondary(int cpu, struct task_struct *idle)
289 {
290         dvpe();
291         set_c0_mvpcontrol(MVPCONTROL_VPC);
292
293         settc(cpu);
294
295         /* restart */
296         write_tc_c0_tcrestart((unsigned long)&smp_bootstrap);
297
298         /* enable the tc this vpe/cpu will be running */
299         write_tc_c0_tcstatus((read_tc_c0_tcstatus() & ~TCSTATUS_IXMT) | TCSTATUS_A);
300
301         write_tc_c0_tchalt(0);
302
303         /* enable the VPE */
304         write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | VPECONF0_VPA);
305
306         /* stack pointer */
307         write_tc_gpr_sp( __KSTK_TOS(idle));
308
309         /* global pointer */
310         write_tc_gpr_gp((unsigned long)idle->thread_info);
311
312         flush_icache_range((unsigned long)idle->thread_info,
313                                            (unsigned long)idle->thread_info +
314                                            sizeof(struct thread_info));
315
316         /* finally out of configuration and into chaos */
317         clear_c0_mvpcontrol(MVPCONTROL_VPC);
318
319         evpe(EVPE_ENABLE);
320 }
321
322 void prom_init_secondary(void)
323 {
324         write_c0_status((read_c0_status() & ~ST0_IM ) |
325                         (STATUSF_IP0 | STATUSF_IP1 | STATUSF_IP7));
326 }
327
328 void prom_smp_finish(void)
329 {
330         write_c0_compare(read_c0_count() + (8* mips_hpt_frequency/HZ));
331
332         local_irq_enable();
333 }
334
335 void prom_cpus_done(void)
336 {
337 }
338
339 void core_send_ipi(int cpu, unsigned int action)
340 {
341         int i;
342         unsigned long flags;
343         int vpflags;
344
345         local_irq_save (flags);
346
347         vpflags = dvpe();       /* cant access the other CPU's registers whilst MVPE enabled */
348
349         switch (action) {
350         case SMP_CALL_FUNCTION:
351                 i = C_SW1;
352                 break;
353
354         case SMP_RESCHEDULE_YOURSELF:
355         default:
356                 i = C_SW0;
357                 break;
358         }
359
360         /* 1:1 mapping of vpe and tc... */
361         settc(cpu);
362         write_vpe_c0_cause(read_vpe_c0_cause() | i);
363         evpe(vpflags);
364
365         local_irq_restore(flags);
366 }