2 * drivers/video/aty/radeon_base.c
4 * framebuffer driver for ATI Radeon chipset video boards
6 * Copyright 2003 Ben. Herrenschmidt <benh@kernel.crashing.org>
7 * Copyright 2000 Ani Joshi <ajoshi@kernel.crashing.org>
9 * i2c bits from Luca Tettamanti <kronos@kronoz.cjb.net>
11 * Special thanks to ATI DevRel team for their hardware donations.
13 * ...Insert GPL boilerplate here...
15 * Significant portions of this driver apdated from XFree86 Radeon
16 * driver which has the following copyright notice:
18 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
19 * VA Linux Systems Inc., Fremont, California.
21 * All Rights Reserved.
23 * Permission is hereby granted, free of charge, to any person obtaining
24 * a copy of this software and associated documentation files (the
25 * "Software"), to deal in the Software without restriction, including
26 * without limitation on the rights to use, copy, modify, merge,
27 * publish, distribute, sublicense, and/or sell copies of the Software,
28 * and to permit persons to whom the Software is furnished to do so,
29 * subject to the following conditions:
31 * The above copyright notice and this permission notice (including the
32 * next paragraph) shall be included in all copies or substantial
33 * portions of the Software.
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
37 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
39 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
41 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
42 * DEALINGS IN THE SOFTWARE.
44 * XFree86 driver authors:
46 * Kevin E. Martin <martin@xfree86.org>
47 * Rickard E. Faith <faith@valinux.com>
48 * Alan Hourihane <alanh@fairlite.demon.co.uk>
53 #define RADEON_VERSION "0.2.0"
57 #include <linux/module.h>
58 #include <linux/moduleparam.h>
59 #include <linux/kernel.h>
60 #include <linux/errno.h>
61 #include <linux/string.h>
62 #include <linux/ctype.h>
64 #include <linux/slab.h>
65 #include <linux/delay.h>
66 #include <linux/time.h>
68 #include <linux/ioport.h>
69 #include <linux/init.h>
70 #include <linux/pci.h>
71 #include <linux/vmalloc.h>
72 #include <linux/device.h>
75 #include <linux/uaccess.h>
79 #include <asm/pci-bridge.h>
80 #include "../macmodes.h"
82 #ifdef CONFIG_BOOTX_TEXT
83 #include <asm/btext.h>
86 #endif /* CONFIG_PPC_OF */
92 #include <video/radeon.h>
93 #include <linux/radeonfb.h>
95 #include "../edid.h" // MOVE THAT TO include/video
98 #define MAX_MAPPED_VRAM (2048*2048*4)
99 #define MIN_MAPPED_VRAM (1024*768*1)
101 #define CHIP_DEF(id, family, flags) \
102 { PCI_VENDOR_ID_ATI, id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (flags) | (CHIP_FAMILY_##family) }
104 static struct pci_device_id radeonfb_pci_table[] = {
105 /* Radeon Xpress 200m */
106 CHIP_DEF(PCI_CHIP_RS480_5955, RS480, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
107 CHIP_DEF(PCI_CHIP_RS482_5975, RS480, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
109 CHIP_DEF(PCI_CHIP_RADEON_LY, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
110 CHIP_DEF(PCI_CHIP_RADEON_LZ, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
112 CHIP_DEF(PCI_CHIP_RV100_QY, RV100, CHIP_HAS_CRTC2),
113 CHIP_DEF(PCI_CHIP_RV100_QZ, RV100, CHIP_HAS_CRTC2),
114 CHIP_DEF(PCI_CHIP_RN50, RV100, CHIP_HAS_CRTC2),
115 /* Radeon IGP320M (U1) */
116 CHIP_DEF(PCI_CHIP_RS100_4336, RS100, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
117 /* Radeon IGP320 (A3) */
118 CHIP_DEF(PCI_CHIP_RS100_4136, RS100, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
119 /* IGP330M/340M/350M (U2) */
120 CHIP_DEF(PCI_CHIP_RS200_4337, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
121 /* IGP330/340/350 (A4) */
122 CHIP_DEF(PCI_CHIP_RS200_4137, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
123 /* Mobility 7000 IGP */
124 CHIP_DEF(PCI_CHIP_RS250_4437, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
126 CHIP_DEF(PCI_CHIP_RS250_4237, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
128 CHIP_DEF(PCI_CHIP_R200_BB, R200, CHIP_HAS_CRTC2),
129 CHIP_DEF(PCI_CHIP_R200_BC, R200, CHIP_HAS_CRTC2),
131 CHIP_DEF(PCI_CHIP_R200_QH, R200, CHIP_HAS_CRTC2),
133 CHIP_DEF(PCI_CHIP_R200_QL, R200, CHIP_HAS_CRTC2),
135 CHIP_DEF(PCI_CHIP_R200_QM, R200, CHIP_HAS_CRTC2),
137 CHIP_DEF(PCI_CHIP_RADEON_LW, RV200, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
138 CHIP_DEF(PCI_CHIP_RADEON_LX, RV200, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
140 CHIP_DEF(PCI_CHIP_RV200_QW, RV200, CHIP_HAS_CRTC2),
141 CHIP_DEF(PCI_CHIP_RV200_QX, RV200, CHIP_HAS_CRTC2),
143 CHIP_DEF(PCI_CHIP_RV250_Ld, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
144 CHIP_DEF(PCI_CHIP_RV250_Le, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
145 CHIP_DEF(PCI_CHIP_RV250_Lf, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
146 CHIP_DEF(PCI_CHIP_RV250_Lg, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
148 CHIP_DEF(PCI_CHIP_RV250_If, RV250, CHIP_HAS_CRTC2),
149 CHIP_DEF(PCI_CHIP_RV250_Ig, RV250, CHIP_HAS_CRTC2),
151 CHIP_DEF(PCI_CHIP_RC410_5A62, RC410, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
152 /* Mobility 9100 IGP (U3) */
153 CHIP_DEF(PCI_CHIP_RS300_5835, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
154 CHIP_DEF(PCI_CHIP_RS350_7835, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
156 CHIP_DEF(PCI_CHIP_RS300_5834, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
157 CHIP_DEF(PCI_CHIP_RS350_7834, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
158 /* Mobility 9200 (M9+) */
159 CHIP_DEF(PCI_CHIP_RV280_5C61, RV280, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
160 CHIP_DEF(PCI_CHIP_RV280_5C63, RV280, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
162 CHIP_DEF(PCI_CHIP_RV280_5960, RV280, CHIP_HAS_CRTC2),
163 CHIP_DEF(PCI_CHIP_RV280_5961, RV280, CHIP_HAS_CRTC2),
164 CHIP_DEF(PCI_CHIP_RV280_5962, RV280, CHIP_HAS_CRTC2),
165 CHIP_DEF(PCI_CHIP_RV280_5964, RV280, CHIP_HAS_CRTC2),
167 CHIP_DEF(PCI_CHIP_R300_AD, R300, CHIP_HAS_CRTC2),
168 CHIP_DEF(PCI_CHIP_R300_AE, R300, CHIP_HAS_CRTC2),
169 /* 9600TX / FireGL Z1 */
170 CHIP_DEF(PCI_CHIP_R300_AF, R300, CHIP_HAS_CRTC2),
171 CHIP_DEF(PCI_CHIP_R300_AG, R300, CHIP_HAS_CRTC2),
172 /* 9700/9500/Pro/FireGL X1 */
173 CHIP_DEF(PCI_CHIP_R300_ND, R300, CHIP_HAS_CRTC2),
174 CHIP_DEF(PCI_CHIP_R300_NE, R300, CHIP_HAS_CRTC2),
175 CHIP_DEF(PCI_CHIP_R300_NF, R300, CHIP_HAS_CRTC2),
176 CHIP_DEF(PCI_CHIP_R300_NG, R300, CHIP_HAS_CRTC2),
177 /* Mobility M10/M11 */
178 CHIP_DEF(PCI_CHIP_RV350_NP, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
179 CHIP_DEF(PCI_CHIP_RV350_NQ, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
180 CHIP_DEF(PCI_CHIP_RV350_NR, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
181 CHIP_DEF(PCI_CHIP_RV350_NS, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
182 CHIP_DEF(PCI_CHIP_RV350_NT, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
183 CHIP_DEF(PCI_CHIP_RV350_NV, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
185 CHIP_DEF(PCI_CHIP_RV350_AP, RV350, CHIP_HAS_CRTC2),
186 CHIP_DEF(PCI_CHIP_RV350_AQ, RV350, CHIP_HAS_CRTC2),
187 CHIP_DEF(PCI_CHIP_RV360_AR, RV350, CHIP_HAS_CRTC2),
188 CHIP_DEF(PCI_CHIP_RV350_AS, RV350, CHIP_HAS_CRTC2),
189 CHIP_DEF(PCI_CHIP_RV350_AT, RV350, CHIP_HAS_CRTC2),
190 CHIP_DEF(PCI_CHIP_RV350_AV, RV350, CHIP_HAS_CRTC2),
191 /* 9800/Pro/FileGL X2 */
192 CHIP_DEF(PCI_CHIP_R350_AH, R350, CHIP_HAS_CRTC2),
193 CHIP_DEF(PCI_CHIP_R350_AI, R350, CHIP_HAS_CRTC2),
194 CHIP_DEF(PCI_CHIP_R350_AJ, R350, CHIP_HAS_CRTC2),
195 CHIP_DEF(PCI_CHIP_R350_AK, R350, CHIP_HAS_CRTC2),
196 CHIP_DEF(PCI_CHIP_R350_NH, R350, CHIP_HAS_CRTC2),
197 CHIP_DEF(PCI_CHIP_R350_NI, R350, CHIP_HAS_CRTC2),
198 CHIP_DEF(PCI_CHIP_R360_NJ, R350, CHIP_HAS_CRTC2),
199 CHIP_DEF(PCI_CHIP_R350_NK, R350, CHIP_HAS_CRTC2),
201 CHIP_DEF(PCI_CHIP_RV380_3E50, RV380, CHIP_HAS_CRTC2),
202 CHIP_DEF(PCI_CHIP_RV380_3E54, RV380, CHIP_HAS_CRTC2),
203 CHIP_DEF(PCI_CHIP_RV380_3150, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
204 CHIP_DEF(PCI_CHIP_RV380_3154, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
205 CHIP_DEF(PCI_CHIP_RV370_5B60, RV380, CHIP_HAS_CRTC2),
206 CHIP_DEF(PCI_CHIP_RV370_5B62, RV380, CHIP_HAS_CRTC2),
207 CHIP_DEF(PCI_CHIP_RV370_5B63, RV380, CHIP_HAS_CRTC2),
208 CHIP_DEF(PCI_CHIP_RV370_5B64, RV380, CHIP_HAS_CRTC2),
209 CHIP_DEF(PCI_CHIP_RV370_5B65, RV380, CHIP_HAS_CRTC2),
210 CHIP_DEF(PCI_CHIP_RV370_5460, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
211 CHIP_DEF(PCI_CHIP_RV370_5464, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
212 CHIP_DEF(PCI_CHIP_R420_JH, R420, CHIP_HAS_CRTC2),
213 CHIP_DEF(PCI_CHIP_R420_JI, R420, CHIP_HAS_CRTC2),
214 CHIP_DEF(PCI_CHIP_R420_JJ, R420, CHIP_HAS_CRTC2),
215 CHIP_DEF(PCI_CHIP_R420_JK, R420, CHIP_HAS_CRTC2),
216 CHIP_DEF(PCI_CHIP_R420_JL, R420, CHIP_HAS_CRTC2),
217 CHIP_DEF(PCI_CHIP_R420_JM, R420, CHIP_HAS_CRTC2),
218 CHIP_DEF(PCI_CHIP_R420_JN, R420, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
219 CHIP_DEF(PCI_CHIP_R420_JP, R420, CHIP_HAS_CRTC2),
220 CHIP_DEF(PCI_CHIP_R423_UH, R420, CHIP_HAS_CRTC2),
221 CHIP_DEF(PCI_CHIP_R423_UI, R420, CHIP_HAS_CRTC2),
222 CHIP_DEF(PCI_CHIP_R423_UJ, R420, CHIP_HAS_CRTC2),
223 CHIP_DEF(PCI_CHIP_R423_UK, R420, CHIP_HAS_CRTC2),
224 CHIP_DEF(PCI_CHIP_R423_UQ, R420, CHIP_HAS_CRTC2),
225 CHIP_DEF(PCI_CHIP_R423_UR, R420, CHIP_HAS_CRTC2),
226 CHIP_DEF(PCI_CHIP_R423_UT, R420, CHIP_HAS_CRTC2),
227 CHIP_DEF(PCI_CHIP_R423_5D57, R420, CHIP_HAS_CRTC2),
228 /* Original Radeon/7200 */
229 CHIP_DEF(PCI_CHIP_RADEON_QD, RADEON, 0),
230 CHIP_DEF(PCI_CHIP_RADEON_QE, RADEON, 0),
231 CHIP_DEF(PCI_CHIP_RADEON_QF, RADEON, 0),
232 CHIP_DEF(PCI_CHIP_RADEON_QG, RADEON, 0),
235 MODULE_DEVICE_TABLE(pci, radeonfb_pci_table);
244 /* these common regs are cleared before mode setting so they do not
245 * interfere with anything
247 static reg_val common_regs[] = {
249 { OVR_WID_LEFT_RIGHT, 0 },
250 { OVR_WID_TOP_BOTTOM, 0 },
251 { OV0_SCALE_CNTL, 0 },
256 { CAP0_TRIG_CNTL, 0 },
257 { CAP1_TRIG_CNTL, 0 },
264 static char *mode_option;
265 static char *monitor_layout;
266 static int noaccel = 0;
267 static int default_dynclk = -2;
268 static int nomodeset = 0;
269 static int ignore_edid = 0;
270 static int mirror = 0;
271 static int panel_yres = 0;
272 static int force_dfp = 0;
273 static int force_measure_pll = 0;
275 static int nomtrr = 0;
277 static int force_sleep;
278 static int ignore_devlist;
279 #ifdef CONFIG_PMAC_BACKLIGHT
280 static int backlight = 1;
282 static int backlight = 0;
289 static void radeon_unmap_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev)
291 if (!rinfo->bios_seg)
293 pci_unmap_rom(dev, rinfo->bios_seg);
296 static int __devinit radeon_map_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev)
303 /* If this is a primary card, there is a shadow copy of the
304 * ROM somewhere in the first meg. We will just ignore the copy
305 * and use the ROM directly.
308 /* Fix from ATI for problem with Radeon hardware not leaving ROM enabled */
310 temp = INREG(MPP_TB_CONFIG);
313 OUTREG(MPP_TB_CONFIG, temp);
314 temp = INREG(MPP_TB_CONFIG);
316 rom = pci_map_rom(dev, &rom_size);
318 printk(KERN_ERR "radeonfb (%s): ROM failed to map\n",
319 pci_name(rinfo->pdev));
323 rinfo->bios_seg = rom;
325 /* Very simple test to make sure it appeared */
326 if (BIOS_IN16(0) != 0xaa55) {
327 printk(KERN_DEBUG "radeonfb (%s): Invalid ROM signature %x "
328 "should be 0xaa55\n",
329 pci_name(rinfo->pdev), BIOS_IN16(0));
332 /* Look for the PCI data to check the ROM type */
333 dptr = BIOS_IN16(0x18);
335 /* Check the PCI data signature. If it's wrong, we still assume a normal x86 ROM
336 * for now, until I've verified this works everywhere. The goal here is more
337 * to phase out Open Firmware images.
339 * Currently, we only look at the first PCI data, we could iteratre and deal with
340 * them all, and we should use fb_bios_start relative to start of image and not
341 * relative start of ROM, but so far, I never found a dual-image ATI card
344 * u32 signature; + 0x00
347 * u16 reserved_1; + 0x08
349 * u8 drevision; + 0x0c
350 * u8 class_hi; + 0x0d
351 * u16 class_lo; + 0x0e
353 * u16 irevision; + 0x12
355 * u8 indicator; + 0x15
356 * u16 reserved_2; + 0x16
359 if (BIOS_IN32(dptr) != (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) {
360 printk(KERN_WARNING "radeonfb (%s): PCI DATA signature in ROM"
361 "incorrect: %08x\n", pci_name(rinfo->pdev), BIOS_IN32(dptr));
364 rom_type = BIOS_IN8(dptr + 0x14);
367 printk(KERN_INFO "radeonfb: Found Intel x86 BIOS ROM Image\n");
370 printk(KERN_INFO "radeonfb: Found Open Firmware ROM Image\n");
373 printk(KERN_INFO "radeonfb: Found HP PA-RISC ROM Image\n");
376 printk(KERN_INFO "radeonfb: Found unknown type %d ROM Image\n", rom_type);
380 /* Locate the flat panel infos, do some sanity checking !!! */
381 rinfo->fp_bios_start = BIOS_IN16(0x48);
385 rinfo->bios_seg = NULL;
386 radeon_unmap_ROM(rinfo, dev);
391 static int __devinit radeon_find_mem_vbios(struct radeonfb_info *rinfo)
393 /* I simplified this code as we used to miss the signatures in
394 * a lot of case. It's now closer to XFree, we just don't check
395 * for signatures at all... Something better will have to be done
396 * if we end up having conflicts
399 void __iomem *rom_base = NULL;
401 for(segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
402 rom_base = ioremap(segstart, 0x10000);
403 if (rom_base == NULL)
405 if (readb(rom_base) == 0x55 && readb(rom_base + 1) == 0xaa)
410 if (rom_base == NULL)
413 /* Locate the flat panel infos, do some sanity checking !!! */
414 rinfo->bios_seg = rom_base;
415 rinfo->fp_bios_start = BIOS_IN16(0x48);
421 #if defined(CONFIG_PPC_OF) || defined(CONFIG_SPARC)
423 * Read XTAL (ref clock), SCLK and MCLK from Open Firmware device
424 * tree. Hopefully, ATI OF driver is kind enough to fill these
426 static int __devinit radeon_read_xtal_OF (struct radeonfb_info *rinfo)
428 struct device_node *dp = rinfo->of_node;
433 val = of_get_property(dp, "ATY,RefCLK", NULL);
435 printk(KERN_WARNING "radeonfb: No ATY,RefCLK property !\n");
439 rinfo->pll.ref_clk = (*val) / 10;
441 val = of_get_property(dp, "ATY,SCLK", NULL);
443 rinfo->pll.sclk = (*val) / 10;
445 val = of_get_property(dp, "ATY,MCLK", NULL);
447 rinfo->pll.mclk = (*val) / 10;
451 #endif /* CONFIG_PPC_OF || CONFIG_SPARC */
454 * Read PLL infos from chip registers
456 static int __devinit radeon_probe_pll_params(struct radeonfb_info *rinfo)
458 unsigned char ppll_div_sel;
460 unsigned sclk, mclk, tmp, ref_div;
461 int hTotal, vTotal, num, denom, m, n;
462 unsigned long long hz, vclk;
464 struct timeval start_tv, stop_tv;
465 long total_secs, total_usecs;
468 /* Ugh, we cut interrupts, bad bad bad, but we want some precision
472 /* Flush PCI buffers ? */
473 tmp = INREG16(DEVICE_ID);
477 for(i=0; i<1000000; i++)
478 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0)
481 do_gettimeofday(&start_tv);
483 for(i=0; i<1000000; i++)
484 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) != 0)
487 for(i=0; i<1000000; i++)
488 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0)
491 do_gettimeofday(&stop_tv);
495 total_secs = stop_tv.tv_sec - start_tv.tv_sec;
498 total_usecs = stop_tv.tv_usec - start_tv.tv_usec;
499 total_usecs += total_secs * 1000000;
501 total_usecs = -total_usecs;
502 hz = 1000000/total_usecs;
504 hTotal = ((INREG(CRTC_H_TOTAL_DISP) & 0x1ff) + 1) * 8;
505 vTotal = ((INREG(CRTC_V_TOTAL_DISP) & 0x3ff) + 1);
506 vclk = (long long)hTotal * (long long)vTotal * hz;
508 switch((INPLL(PPLL_REF_DIV) & 0x30000) >> 16) {
515 n = ((INPLL(M_SPLL_REF_FB_DIV) >> 16) & 0xff);
516 m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff);
521 n = ((INPLL(M_SPLL_REF_FB_DIV) >> 8) & 0xff);
522 m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff);
528 ppll_div_sel = INREG8(CLOCK_CNTL_INDEX + 1) & 0x3;
529 radeon_pll_errata_after_index(rinfo);
531 n = (INPLL(PPLL_DIV_0 + ppll_div_sel) & 0x7ff);
532 m = (INPLL(PPLL_REF_DIV) & 0x3ff);
537 switch ((INPLL(PPLL_DIV_0 + ppll_div_sel) >> 16) & 0x7) {
559 do_div(vclk, 1000 * num);
562 if ((xtal > 26900) && (xtal < 27100))
564 else if ((xtal > 14200) && (xtal < 14400))
566 else if ((xtal > 29400) && (xtal < 29600))
569 printk(KERN_WARNING "xtal calculation failed: %ld\n", xtal);
573 tmp = INPLL(M_SPLL_REF_FB_DIV);
574 ref_div = INPLL(PPLL_REF_DIV) & 0x3ff;
576 Ns = (tmp & 0xff0000) >> 16;
577 Nm = (tmp & 0xff00) >> 8;
579 sclk = round_div((2 * Ns * xtal), (2 * M));
580 mclk = round_div((2 * Nm * xtal), (2 * M));
582 /* we're done, hopefully these are sane values */
583 rinfo->pll.ref_clk = xtal;
584 rinfo->pll.ref_div = ref_div;
585 rinfo->pll.sclk = sclk;
586 rinfo->pll.mclk = mclk;
592 * Retrieve PLL infos by different means (BIOS, Open Firmware, register probing...)
594 static void __devinit radeon_get_pllinfo(struct radeonfb_info *rinfo)
597 * In the case nothing works, these are defaults; they are mostly
598 * incomplete, however. It does provide ppll_max and _min values
599 * even for most other methods, however.
601 switch (rinfo->chipset) {
602 case PCI_DEVICE_ID_ATI_RADEON_QW:
603 case PCI_DEVICE_ID_ATI_RADEON_QX:
604 rinfo->pll.ppll_max = 35000;
605 rinfo->pll.ppll_min = 12000;
606 rinfo->pll.mclk = 23000;
607 rinfo->pll.sclk = 23000;
608 rinfo->pll.ref_clk = 2700;
610 case PCI_DEVICE_ID_ATI_RADEON_QL:
611 case PCI_DEVICE_ID_ATI_RADEON_QN:
612 case PCI_DEVICE_ID_ATI_RADEON_QO:
613 case PCI_DEVICE_ID_ATI_RADEON_Ql:
614 case PCI_DEVICE_ID_ATI_RADEON_BB:
615 rinfo->pll.ppll_max = 35000;
616 rinfo->pll.ppll_min = 12000;
617 rinfo->pll.mclk = 27500;
618 rinfo->pll.sclk = 27500;
619 rinfo->pll.ref_clk = 2700;
621 case PCI_DEVICE_ID_ATI_RADEON_Id:
622 case PCI_DEVICE_ID_ATI_RADEON_Ie:
623 case PCI_DEVICE_ID_ATI_RADEON_If:
624 case PCI_DEVICE_ID_ATI_RADEON_Ig:
625 rinfo->pll.ppll_max = 35000;
626 rinfo->pll.ppll_min = 12000;
627 rinfo->pll.mclk = 25000;
628 rinfo->pll.sclk = 25000;
629 rinfo->pll.ref_clk = 2700;
631 case PCI_DEVICE_ID_ATI_RADEON_ND:
632 case PCI_DEVICE_ID_ATI_RADEON_NE:
633 case PCI_DEVICE_ID_ATI_RADEON_NF:
634 case PCI_DEVICE_ID_ATI_RADEON_NG:
635 rinfo->pll.ppll_max = 40000;
636 rinfo->pll.ppll_min = 20000;
637 rinfo->pll.mclk = 27000;
638 rinfo->pll.sclk = 27000;
639 rinfo->pll.ref_clk = 2700;
641 case PCI_DEVICE_ID_ATI_RADEON_QD:
642 case PCI_DEVICE_ID_ATI_RADEON_QE:
643 case PCI_DEVICE_ID_ATI_RADEON_QF:
644 case PCI_DEVICE_ID_ATI_RADEON_QG:
646 rinfo->pll.ppll_max = 35000;
647 rinfo->pll.ppll_min = 12000;
648 rinfo->pll.mclk = 16600;
649 rinfo->pll.sclk = 16600;
650 rinfo->pll.ref_clk = 2700;
653 rinfo->pll.ref_div = INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK;
656 #if defined(CONFIG_PPC_OF) || defined(CONFIG_SPARC)
658 * Retrieve PLL infos from Open Firmware first
660 if (!force_measure_pll && radeon_read_xtal_OF(rinfo) == 0) {
661 printk(KERN_INFO "radeonfb: Retrieved PLL infos from Open Firmware\n");
664 #endif /* CONFIG_PPC_OF || CONFIG_SPARC */
667 * Check out if we have an X86 which gave us some PLL informations
668 * and if yes, retrieve them
670 if (!force_measure_pll && rinfo->bios_seg) {
671 u16 pll_info_block = BIOS_IN16(rinfo->fp_bios_start + 0x30);
673 rinfo->pll.sclk = BIOS_IN16(pll_info_block + 0x08);
674 rinfo->pll.mclk = BIOS_IN16(pll_info_block + 0x0a);
675 rinfo->pll.ref_clk = BIOS_IN16(pll_info_block + 0x0e);
676 rinfo->pll.ref_div = BIOS_IN16(pll_info_block + 0x10);
677 rinfo->pll.ppll_min = BIOS_IN32(pll_info_block + 0x12);
678 rinfo->pll.ppll_max = BIOS_IN32(pll_info_block + 0x16);
680 printk(KERN_INFO "radeonfb: Retrieved PLL infos from BIOS\n");
685 * We didn't get PLL parameters from either OF or BIOS, we try to
688 if (radeon_probe_pll_params(rinfo) == 0) {
689 printk(KERN_INFO "radeonfb: Retrieved PLL infos from registers\n");
694 * Fall back to already-set defaults...
696 printk(KERN_INFO "radeonfb: Used default PLL infos\n");
700 * Some methods fail to retrieve SCLK and MCLK values, we apply default
701 * settings in this case (200Mhz). If that really happne often, we could
702 * fetch from registers instead...
704 if (rinfo->pll.mclk == 0)
705 rinfo->pll.mclk = 20000;
706 if (rinfo->pll.sclk == 0)
707 rinfo->pll.sclk = 20000;
709 printk("radeonfb: Reference=%d.%02d MHz (RefDiv=%d) Memory=%d.%02d Mhz, System=%d.%02d MHz\n",
710 rinfo->pll.ref_clk / 100, rinfo->pll.ref_clk % 100,
712 rinfo->pll.mclk / 100, rinfo->pll.mclk % 100,
713 rinfo->pll.sclk / 100, rinfo->pll.sclk % 100);
714 printk("radeonfb: PLL min %d max %d\n", rinfo->pll.ppll_min, rinfo->pll.ppll_max);
717 static int radeonfb_check_var (struct fb_var_screeninfo *var, struct fb_info *info)
719 struct radeonfb_info *rinfo = info->par;
720 struct fb_var_screeninfo v;
724 if (radeon_match_mode(rinfo, &v, var))
727 switch (v.bits_per_pixel) {
729 v.bits_per_pixel = 8;
732 v.bits_per_pixel = 16;
735 #if 0 /* Doesn't seem to work */
736 v.bits_per_pixel = 24;
741 v.bits_per_pixel = 32;
747 switch (var_to_depth(&v)) {
750 v.red.offset = v.green.offset = v.blue.offset = 0;
751 v.red.length = v.green.length = v.blue.length = 8;
752 v.transp.offset = v.transp.length = 0;
760 v.red.length = v.green.length = v.blue.length = 5;
761 v.transp.offset = v.transp.length = 0;
772 v.transp.offset = v.transp.length = 0;
780 v.red.length = v.blue.length = v.green.length = 8;
781 v.transp.offset = v.transp.length = 0;
789 v.red.length = v.blue.length = v.green.length = 8;
790 v.transp.offset = 24;
794 printk ("radeonfb: mode %dx%dx%d rejected, color depth invalid\n",
795 var->xres, var->yres, var->bits_per_pixel);
799 if (v.yres_virtual < v.yres)
800 v.yres_virtual = v.yres;
801 if (v.xres_virtual < v.xres)
802 v.xres_virtual = v.xres;
805 /* XXX I'm adjusting xres_virtual to the pitch, that may help XFree
806 * with some panels, though I don't quite like this solution
808 if (rinfo->info->flags & FBINFO_HWACCEL_DISABLED) {
809 v.xres_virtual = v.xres_virtual & ~7ul;
811 pitch = ((v.xres_virtual * ((v.bits_per_pixel + 1) / 8) + 0x3f)
813 v.xres_virtual = (pitch << 6) / ((v.bits_per_pixel + 1) / 8);
816 if (((v.xres_virtual * v.yres_virtual * nom) / den) > rinfo->mapped_vram)
819 if (v.xres_virtual < v.xres)
820 v.xres = v.xres_virtual;
827 if (v.xoffset > v.xres_virtual - v.xres)
828 v.xoffset = v.xres_virtual - v.xres - 1;
830 if (v.yoffset > v.yres_virtual - v.yres)
831 v.yoffset = v.yres_virtual - v.yres - 1;
833 v.red.msb_right = v.green.msb_right = v.blue.msb_right =
834 v.transp.offset = v.transp.length =
835 v.transp.msb_right = 0;
837 memcpy(var, &v, sizeof(v));
843 static int radeonfb_pan_display (struct fb_var_screeninfo *var,
844 struct fb_info *info)
846 struct radeonfb_info *rinfo = info->par;
848 if ((var->xoffset + var->xres > var->xres_virtual)
849 || (var->yoffset + var->yres > var->yres_virtual))
855 OUTREG(CRTC_OFFSET, ((var->yoffset * var->xres_virtual + var->xoffset)
856 * var->bits_per_pixel / 8) & ~7);
861 static int radeonfb_ioctl (struct fb_info *info, unsigned int cmd,
864 struct radeonfb_info *rinfo = info->par;
871 * TODO: set mirror accordingly for non-Mobility chipsets with 2 CRTC's
872 * and do something better using 2nd CRTC instead of just hackish
873 * routing to second output
875 case FBIO_RADEON_SET_MIRROR:
876 if (!rinfo->is_mobility)
879 rc = get_user(value, (__u32 __user *)arg);
885 tmp = INREG(LVDS_GEN_CNTL);
887 tmp |= (LVDS_ON | LVDS_BLON);
889 tmp = INREG(LVDS_GEN_CNTL);
891 tmp &= ~(LVDS_ON | LVDS_BLON);
894 OUTREG(LVDS_GEN_CNTL, tmp);
897 tmp = INREG(CRTC_EXT_CNTL);
902 tmp = INREG(CRTC_EXT_CNTL);
908 OUTREG(CRTC_EXT_CNTL, tmp);
911 case FBIO_RADEON_GET_MIRROR:
912 if (!rinfo->is_mobility)
915 tmp = INREG(LVDS_GEN_CNTL);
916 if ((LVDS_ON | LVDS_BLON) & tmp)
919 tmp = INREG(CRTC_EXT_CNTL);
920 if (CRTC_CRT_ON & tmp)
923 return put_user(value, (__u32 __user *)arg);
932 int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch)
938 if (rinfo->lock_blank)
941 radeon_engine_idle(rinfo);
943 val = INREG(CRTC_EXT_CNTL);
944 val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS |
947 case FB_BLANK_VSYNC_SUSPEND:
948 val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS);
950 case FB_BLANK_HSYNC_SUSPEND:
951 val |= (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS);
953 case FB_BLANK_POWERDOWN:
954 val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS |
957 case FB_BLANK_NORMAL:
958 val |= CRTC_DISPLAY_DIS;
960 case FB_BLANK_UNBLANK:
964 OUTREG(CRTC_EXT_CNTL, val);
967 switch (rinfo->mon1_type) {
970 OUTREGP(FP_GEN_CNTL, (FP_FPON | FP_TMDS_EN),
971 ~(FP_FPON | FP_TMDS_EN));
973 if (mode_switch || blank == FB_BLANK_NORMAL)
975 OUTREGP(FP_GEN_CNTL, 0, ~(FP_FPON | FP_TMDS_EN));
979 del_timer_sync(&rinfo->lvds_timer);
980 val = INREG(LVDS_GEN_CNTL);
982 u32 target_val = (val & ~LVDS_DISPLAY_DIS) | LVDS_BLON | LVDS_ON
983 | LVDS_EN | (rinfo->init_state.lvds_gen_cntl
984 & (LVDS_DIGON | LVDS_BL_MOD_EN));
985 if ((val ^ target_val) == LVDS_DISPLAY_DIS)
986 OUTREG(LVDS_GEN_CNTL, target_val);
987 else if ((val ^ target_val) != 0) {
988 OUTREG(LVDS_GEN_CNTL, target_val
989 & ~(LVDS_ON | LVDS_BL_MOD_EN));
990 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
991 rinfo->init_state.lvds_gen_cntl |=
992 target_val & LVDS_STATE_MASK;
994 radeon_msleep(rinfo->panel_info.pwr_delay);
995 OUTREG(LVDS_GEN_CNTL, target_val);
998 rinfo->pending_lvds_gen_cntl = target_val;
999 mod_timer(&rinfo->lvds_timer,
1001 msecs_to_jiffies(rinfo->panel_info.pwr_delay));
1005 val |= LVDS_DISPLAY_DIS;
1006 OUTREG(LVDS_GEN_CNTL, val);
1008 /* We don't do a full switch-off on a simple mode switch */
1009 if (mode_switch || blank == FB_BLANK_NORMAL)
1012 /* Asic bug, when turning off LVDS_ON, we have to make sure
1013 * RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off
1015 tmp_pix_clks = INPLL(PIXCLKS_CNTL);
1016 if (rinfo->is_mobility || rinfo->is_IGP)
1017 OUTPLLP(PIXCLKS_CNTL, 0, ~PIXCLK_LVDS_ALWAYS_ONb);
1018 val &= ~(LVDS_BL_MOD_EN);
1019 OUTREG(LVDS_GEN_CNTL, val);
1021 val &= ~(LVDS_ON | LVDS_EN);
1022 OUTREG(LVDS_GEN_CNTL, val);
1024 rinfo->pending_lvds_gen_cntl = val;
1025 mod_timer(&rinfo->lvds_timer,
1027 msecs_to_jiffies(rinfo->panel_info.pwr_delay));
1028 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
1029 rinfo->init_state.lvds_gen_cntl |= val & LVDS_STATE_MASK;
1030 if (rinfo->is_mobility || rinfo->is_IGP)
1031 OUTPLL(PIXCLKS_CNTL, tmp_pix_clks);
1035 // todo: powerdown DAC
1043 static int radeonfb_blank (int blank, struct fb_info *info)
1045 struct radeonfb_info *rinfo = info->par;
1050 return radeon_screen_blank(rinfo, blank, 0);
1053 static int radeon_setcolreg (unsigned regno, unsigned red, unsigned green,
1054 unsigned blue, unsigned transp,
1055 struct radeonfb_info *rinfo)
1067 rinfo->palette[regno].red = red;
1068 rinfo->palette[regno].green = green;
1069 rinfo->palette[regno].blue = blue;
1074 if (!rinfo->asleep) {
1075 if (rinfo->bpp == 16) {
1078 if (rinfo->depth == 16 && regno > 63)
1080 if (rinfo->depth == 15 && regno > 31)
1083 /* For 565, the green component is mixed one order
1086 if (rinfo->depth == 16) {
1087 OUTREG(PALETTE_INDEX, pindex>>1);
1088 OUTREG(PALETTE_DATA,
1089 (rinfo->palette[regno>>1].red << 16) |
1091 (rinfo->palette[regno>>1].blue));
1092 green = rinfo->palette[regno<<1].green;
1096 if (rinfo->depth != 16 || regno < 32) {
1097 OUTREG(PALETTE_INDEX, pindex);
1098 OUTREG(PALETTE_DATA, (red << 16) |
1099 (green << 8) | blue);
1103 u32 *pal = rinfo->info->pseudo_palette;
1104 switch (rinfo->depth) {
1106 pal[regno] = (regno << 10) | (regno << 5) | regno;
1109 pal[regno] = (regno << 11) | (regno << 5) | regno;
1112 pal[regno] = (regno << 16) | (regno << 8) | regno;
1115 i = (regno << 8) | regno;
1116 pal[regno] = (i << 16) | i;
1123 static int radeonfb_setcolreg (unsigned regno, unsigned red, unsigned green,
1124 unsigned blue, unsigned transp,
1125 struct fb_info *info)
1127 struct radeonfb_info *rinfo = info->par;
1128 u32 dac_cntl2, vclk_cntl = 0;
1131 if (!rinfo->asleep) {
1132 if (rinfo->is_mobility) {
1133 vclk_cntl = INPLL(VCLK_ECP_CNTL);
1134 OUTPLL(VCLK_ECP_CNTL,
1135 vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb);
1138 /* Make sure we are on first palette */
1139 if (rinfo->has_CRTC2) {
1140 dac_cntl2 = INREG(DAC_CNTL2);
1141 dac_cntl2 &= ~DAC2_PALETTE_ACCESS_CNTL;
1142 OUTREG(DAC_CNTL2, dac_cntl2);
1146 rc = radeon_setcolreg (regno, red, green, blue, transp, rinfo);
1148 if (!rinfo->asleep && rinfo->is_mobility)
1149 OUTPLL(VCLK_ECP_CNTL, vclk_cntl);
1154 static int radeonfb_setcmap(struct fb_cmap *cmap, struct fb_info *info)
1156 struct radeonfb_info *rinfo = info->par;
1157 u16 *red, *green, *blue, *transp;
1158 u32 dac_cntl2, vclk_cntl = 0;
1159 int i, start, rc = 0;
1161 if (!rinfo->asleep) {
1162 if (rinfo->is_mobility) {
1163 vclk_cntl = INPLL(VCLK_ECP_CNTL);
1164 OUTPLL(VCLK_ECP_CNTL,
1165 vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb);
1168 /* Make sure we are on first palette */
1169 if (rinfo->has_CRTC2) {
1170 dac_cntl2 = INREG(DAC_CNTL2);
1171 dac_cntl2 &= ~DAC2_PALETTE_ACCESS_CNTL;
1172 OUTREG(DAC_CNTL2, dac_cntl2);
1177 green = cmap->green;
1179 transp = cmap->transp;
1180 start = cmap->start;
1182 for (i = 0; i < cmap->len; i++) {
1183 u_int hred, hgreen, hblue, htransp = 0xffff;
1189 htransp = *transp++;
1190 rc = radeon_setcolreg (start++, hred, hgreen, hblue, htransp,
1196 if (!rinfo->asleep && rinfo->is_mobility)
1197 OUTPLL(VCLK_ECP_CNTL, vclk_cntl);
1202 static void radeon_save_state (struct radeonfb_info *rinfo,
1203 struct radeon_regs *save)
1206 save->crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
1207 save->crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
1208 save->crtc_more_cntl = INREG(CRTC_MORE_CNTL);
1209 save->dac_cntl = INREG(DAC_CNTL);
1210 save->crtc_h_total_disp = INREG(CRTC_H_TOTAL_DISP);
1211 save->crtc_h_sync_strt_wid = INREG(CRTC_H_SYNC_STRT_WID);
1212 save->crtc_v_total_disp = INREG(CRTC_V_TOTAL_DISP);
1213 save->crtc_v_sync_strt_wid = INREG(CRTC_V_SYNC_STRT_WID);
1214 save->crtc_pitch = INREG(CRTC_PITCH);
1215 save->surface_cntl = INREG(SURFACE_CNTL);
1218 save->fp_crtc_h_total_disp = INREG(FP_CRTC_H_TOTAL_DISP);
1219 save->fp_crtc_v_total_disp = INREG(FP_CRTC_V_TOTAL_DISP);
1220 save->fp_gen_cntl = INREG(FP_GEN_CNTL);
1221 save->fp_h_sync_strt_wid = INREG(FP_H_SYNC_STRT_WID);
1222 save->fp_horz_stretch = INREG(FP_HORZ_STRETCH);
1223 save->fp_v_sync_strt_wid = INREG(FP_V_SYNC_STRT_WID);
1224 save->fp_vert_stretch = INREG(FP_VERT_STRETCH);
1225 save->lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
1226 save->lvds_pll_cntl = INREG(LVDS_PLL_CNTL);
1227 save->tmds_crc = INREG(TMDS_CRC);
1228 save->tmds_transmitter_cntl = INREG(TMDS_TRANSMITTER_CNTL);
1229 save->vclk_ecp_cntl = INPLL(VCLK_ECP_CNTL);
1232 save->clk_cntl_index = INREG(CLOCK_CNTL_INDEX) & ~0x3f;
1233 radeon_pll_errata_after_index(rinfo);
1234 save->ppll_div_3 = INPLL(PPLL_DIV_3);
1235 save->ppll_ref_div = INPLL(PPLL_REF_DIV);
1239 static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *mode)
1243 /* Workaround from XFree */
1244 if (rinfo->is_mobility) {
1245 /* A temporal workaround for the occational blanking on certain laptop
1246 * panels. This appears to related to the PLL divider registers
1247 * (fail to lock?). It occurs even when all dividers are the same
1248 * with their old settings. In this case we really don't need to
1249 * fiddle with PLL registers. By doing this we can avoid the blanking
1250 * problem with some panels.
1252 if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) &&
1253 (mode->ppll_div_3 == (INPLL(PPLL_DIV_3) &
1254 (PPLL_POST3_DIV_MASK | PPLL_FB3_DIV_MASK)))) {
1255 /* We still have to force a switch to selected PPLL div thanks to
1256 * an XFree86 driver bug which will switch it away in some cases
1257 * even when using UseFDev */
1258 OUTREGP(CLOCK_CNTL_INDEX,
1259 mode->clk_cntl_index & PPLL_DIV_SEL_MASK,
1260 ~PPLL_DIV_SEL_MASK);
1261 radeon_pll_errata_after_index(rinfo);
1262 radeon_pll_errata_after_data(rinfo);
1267 /* Swich VCKL clock input to CPUCLK so it stays fed while PPLL updates*/
1268 OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_CPUCLK, ~VCLK_SRC_SEL_MASK);
1270 /* Reset PPLL & enable atomic update */
1272 PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN,
1273 ~(PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
1275 /* Switch to selected PPLL divider */
1276 OUTREGP(CLOCK_CNTL_INDEX,
1277 mode->clk_cntl_index & PPLL_DIV_SEL_MASK,
1278 ~PPLL_DIV_SEL_MASK);
1279 radeon_pll_errata_after_index(rinfo);
1280 radeon_pll_errata_after_data(rinfo);
1282 /* Set PPLL ref. div */
1283 if (IS_R300_VARIANT(rinfo) ||
1284 rinfo->family == CHIP_FAMILY_RS300 ||
1285 rinfo->family == CHIP_FAMILY_RS400 ||
1286 rinfo->family == CHIP_FAMILY_RS480) {
1287 if (mode->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
1288 /* When restoring console mode, use saved PPLL_REF_DIV
1291 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, 0);
1293 /* R300 uses ref_div_acc field as real ref divider */
1294 OUTPLLP(PPLL_REF_DIV,
1295 (mode->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
1296 ~R300_PPLL_REF_DIV_ACC_MASK);
1299 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK);
1301 /* Set PPLL divider 3 & post divider*/
1302 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK);
1303 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK);
1306 while (INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R)
1308 OUTPLLP(PPLL_REF_DIV, PPLL_ATOMIC_UPDATE_W, ~PPLL_ATOMIC_UPDATE_W);
1310 /* Wait read update complete */
1311 /* FIXME: Certain revisions of R300 can't recover here. Not sure of
1312 the cause yet, but this workaround will mask the problem for now.
1313 Other chips usually will pass at the very first test, so the
1314 workaround shouldn't have any effect on them. */
1315 for (i = 0; (i < 10000 && INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); i++)
1318 OUTPLL(HTOTAL_CNTL, 0);
1320 /* Clear reset & atomic update */
1321 OUTPLLP(PPLL_CNTL, 0,
1322 ~(PPLL_RESET | PPLL_SLEEP | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
1324 /* We may want some locking ... oh well */
1327 /* Switch back VCLK source to PPLL */
1328 OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_PPLLCLK, ~VCLK_SRC_SEL_MASK);
1332 * Timer function for delayed LVDS panel power up/down
1334 static void radeon_lvds_timer_func(unsigned long data)
1336 struct radeonfb_info *rinfo = (struct radeonfb_info *)data;
1338 radeon_engine_idle(rinfo);
1340 OUTREG(LVDS_GEN_CNTL, rinfo->pending_lvds_gen_cntl);
1344 * Apply a video mode. This will apply the whole register set, including
1345 * the PLL registers, to the card
1347 void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode,
1351 int primary_mon = PRIMARY_MONITOR(rinfo);
1356 radeon_engine_idle(rinfo);
1359 radeon_screen_blank(rinfo, FB_BLANK_NORMAL, 0);
1361 for (i=0; i<10; i++)
1362 OUTREG(common_regs[i].reg, common_regs[i].val);
1364 /* Apply surface registers */
1365 for (i=0; i<8; i++) {
1366 OUTREG(SURFACE0_LOWER_BOUND + 0x10*i, mode->surf_lower_bound[i]);
1367 OUTREG(SURFACE0_UPPER_BOUND + 0x10*i, mode->surf_upper_bound[i]);
1368 OUTREG(SURFACE0_INFO + 0x10*i, mode->surf_info[i]);
1371 OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl);
1372 OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl,
1373 ~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS));
1374 OUTREG(CRTC_MORE_CNTL, mode->crtc_more_cntl);
1375 OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING);
1376 OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp);
1377 OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid);
1378 OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp);
1379 OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid);
1380 OUTREG(CRTC_OFFSET, 0);
1381 OUTREG(CRTC_OFFSET_CNTL, 0);
1382 OUTREG(CRTC_PITCH, mode->crtc_pitch);
1383 OUTREG(SURFACE_CNTL, mode->surface_cntl);
1385 radeon_write_pll_regs(rinfo, mode);
1387 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1388 OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp);
1389 OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp);
1390 OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid);
1391 OUTREG(FP_V_SYNC_STRT_WID, mode->fp_v_sync_strt_wid);
1392 OUTREG(FP_HORZ_STRETCH, mode->fp_horz_stretch);
1393 OUTREG(FP_VERT_STRETCH, mode->fp_vert_stretch);
1394 OUTREG(FP_GEN_CNTL, mode->fp_gen_cntl);
1395 OUTREG(TMDS_CRC, mode->tmds_crc);
1396 OUTREG(TMDS_TRANSMITTER_CNTL, mode->tmds_transmitter_cntl);
1400 radeon_screen_blank(rinfo, FB_BLANK_UNBLANK, 0);
1402 OUTPLL(VCLK_ECP_CNTL, mode->vclk_ecp_cntl);
1408 * Calculate the PLL values for a given mode
1410 static void radeon_calc_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *regs,
1428 int fb_div, pll_output_freq = 0;
1431 /* Check if the DVO port is enabled and sourced from the primary CRTC. I'm
1432 * not sure which model starts having FP2_GEN_CNTL, I assume anything more
1433 * recent than an r(v)100...
1436 /* XXX I had reports of flicker happening with the cinema display
1437 * on TMDS1 that seem to be fixed if I also forbit odd dividers in
1438 * this case. This could just be a bandwidth calculation issue, I
1439 * haven't implemented the bandwidth code yet, but in the meantime,
1440 * forcing uses_dvo to 1 fixes it and shouln't have bad side effects,
1441 * I haven't seen a case were were absolutely needed an odd PLL
1442 * divider. I'll find a better fix once I have more infos on the
1443 * real cause of the problem.
1445 while (rinfo->has_CRTC2) {
1446 u32 fp2_gen_cntl = INREG(FP2_GEN_CNTL);
1447 u32 disp_output_cntl;
1450 /* FP2 path not enabled */
1451 if ((fp2_gen_cntl & FP2_ON) == 0)
1453 /* Not all chip revs have the same format for this register,
1454 * extract the source selection
1456 if (rinfo->family == CHIP_FAMILY_R200 || IS_R300_VARIANT(rinfo)) {
1457 source = (fp2_gen_cntl >> 10) & 0x3;
1458 /* sourced from transform unit, check for transform unit
1462 disp_output_cntl = INREG(DISP_OUTPUT_CNTL);
1463 source = (disp_output_cntl >> 12) & 0x3;
1466 source = (fp2_gen_cntl >> 13) & 0x1;
1467 /* sourced from CRTC2 -> exit */
1471 /* so we end up on CRTC1, let's set uses_dvo to 1 now */
1478 if (freq > rinfo->pll.ppll_max)
1479 freq = rinfo->pll.ppll_max;
1480 if (freq*12 < rinfo->pll.ppll_min)
1481 freq = rinfo->pll.ppll_min / 12;
1482 pr_debug("freq = %lu, PLL min = %u, PLL max = %u\n",
1483 freq, rinfo->pll.ppll_min, rinfo->pll.ppll_max);
1485 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
1486 pll_output_freq = post_div->divider * freq;
1487 /* If we output to the DVO port (external TMDS), we don't allow an
1488 * odd PLL divider as those aren't supported on this path
1490 if (uses_dvo && (post_div->divider & 1))
1492 if (pll_output_freq >= rinfo->pll.ppll_min &&
1493 pll_output_freq <= rinfo->pll.ppll_max)
1497 /* If we fall through the bottom, try the "default value"
1498 given by the terminal post_div->bitvalue */
1499 if ( !post_div->divider ) {
1500 post_div = &post_divs[post_div->bitvalue];
1501 pll_output_freq = post_div->divider * freq;
1503 pr_debug("ref_div = %d, ref_clk = %d, output_freq = %d\n",
1504 rinfo->pll.ref_div, rinfo->pll.ref_clk,
1507 /* If we fall through the bottom, try the "default value"
1508 given by the terminal post_div->bitvalue */
1509 if ( !post_div->divider ) {
1510 post_div = &post_divs[post_div->bitvalue];
1511 pll_output_freq = post_div->divider * freq;
1513 pr_debug("ref_div = %d, ref_clk = %d, output_freq = %d\n",
1514 rinfo->pll.ref_div, rinfo->pll.ref_clk,
1517 fb_div = round_div(rinfo->pll.ref_div*pll_output_freq,
1518 rinfo->pll.ref_clk);
1519 regs->ppll_ref_div = rinfo->pll.ref_div;
1520 regs->ppll_div_3 = fb_div | (post_div->bitvalue << 16);
1522 pr_debug("post div = 0x%x\n", post_div->bitvalue);
1523 pr_debug("fb_div = 0x%x\n", fb_div);
1524 pr_debug("ppll_div_3 = 0x%x\n", regs->ppll_div_3);
1527 static int radeonfb_set_par(struct fb_info *info)
1529 struct radeonfb_info *rinfo = info->par;
1530 struct fb_var_screeninfo *mode = &info->var;
1531 struct radeon_regs *newmode;
1532 int hTotal, vTotal, hSyncStart, hSyncEnd,
1533 hSyncPol, vSyncStart, vSyncEnd, vSyncPol, cSync;
1534 u8 hsync_adj_tab[] = {0, 0x12, 9, 9, 6, 5};
1535 u8 hsync_fudge_fp[] = {2, 2, 0, 0, 5, 5};
1536 u32 sync, h_sync_pol, v_sync_pol, dotClock, pixClock;
1540 int hsync_start, hsync_fudge, bytpp, hsync_wid, vsync_wid;
1541 int primary_mon = PRIMARY_MONITOR(rinfo);
1542 int depth = var_to_depth(mode);
1545 newmode = kmalloc(sizeof(struct radeon_regs), GFP_KERNEL);
1549 /* We always want engine to be idle on a mode switch, even
1550 * if we won't actually change the mode
1552 radeon_engine_idle(rinfo);
1554 hSyncStart = mode->xres + mode->right_margin;
1555 hSyncEnd = hSyncStart + mode->hsync_len;
1556 hTotal = hSyncEnd + mode->left_margin;
1558 vSyncStart = mode->yres + mode->lower_margin;
1559 vSyncEnd = vSyncStart + mode->vsync_len;
1560 vTotal = vSyncEnd + mode->upper_margin;
1561 pixClock = mode->pixclock;
1564 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1565 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1567 if (primary_mon == MT_DFP || primary_mon == MT_LCD) {
1568 if (rinfo->panel_info.xres < mode->xres)
1569 mode->xres = rinfo->panel_info.xres;
1570 if (rinfo->panel_info.yres < mode->yres)
1571 mode->yres = rinfo->panel_info.yres;
1573 hTotal = mode->xres + rinfo->panel_info.hblank;
1574 hSyncStart = mode->xres + rinfo->panel_info.hOver_plus;
1575 hSyncEnd = hSyncStart + rinfo->panel_info.hSync_width;
1577 vTotal = mode->yres + rinfo->panel_info.vblank;
1578 vSyncStart = mode->yres + rinfo->panel_info.vOver_plus;
1579 vSyncEnd = vSyncStart + rinfo->panel_info.vSync_width;
1581 h_sync_pol = !rinfo->panel_info.hAct_high;
1582 v_sync_pol = !rinfo->panel_info.vAct_high;
1584 pixClock = 100000000 / rinfo->panel_info.clock;
1586 if (rinfo->panel_info.use_bios_dividers) {
1588 newmode->ppll_div_3 = rinfo->panel_info.fbk_divider |
1589 (rinfo->panel_info.post_divider << 16);
1590 newmode->ppll_ref_div = rinfo->panel_info.ref_divider;
1593 dotClock = 1000000000 / pixClock;
1594 freq = dotClock / 10; /* x100 */
1596 pr_debug("hStart = %d, hEnd = %d, hTotal = %d\n",
1597 hSyncStart, hSyncEnd, hTotal);
1598 pr_debug("vStart = %d, vEnd = %d, vTotal = %d\n",
1599 vSyncStart, vSyncEnd, vTotal);
1601 hsync_wid = (hSyncEnd - hSyncStart) / 8;
1602 vsync_wid = vSyncEnd - vSyncStart;
1605 else if (hsync_wid > 0x3f) /* max */
1610 else if (vsync_wid > 0x1f) /* max */
1613 hSyncPol = mode->sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1614 vSyncPol = mode->sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1616 cSync = mode->sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;
1618 format = radeon_get_dstbpp(depth);
1619 bytpp = mode->bits_per_pixel >> 3;
1621 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD))
1622 hsync_fudge = hsync_fudge_fp[format-1];
1624 hsync_fudge = hsync_adj_tab[format-1];
1626 hsync_start = hSyncStart - 8 + hsync_fudge;
1628 newmode->crtc_gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN |
1631 /* Clear auto-center etc... */
1632 newmode->crtc_more_cntl = rinfo->init_state.crtc_more_cntl;
1633 newmode->crtc_more_cntl &= 0xfffffff0;
1635 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1636 newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN;
1638 newmode->crtc_ext_cntl |= CRTC_CRT_ON;
1640 newmode->crtc_gen_cntl &= ~(CRTC_DBL_SCAN_EN |
1643 newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN |
1647 newmode->dac_cntl = /* INREG(DAC_CNTL) | */ DAC_MASK_ALL | DAC_VGA_ADR_EN |
1650 newmode->crtc_h_total_disp = ((((hTotal / 8) - 1) & 0x3ff) |
1651 (((mode->xres / 8) - 1) << 16));
1653 newmode->crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) |
1654 (hsync_wid << 16) | (h_sync_pol << 23));
1656 newmode->crtc_v_total_disp = ((vTotal - 1) & 0xffff) |
1657 ((mode->yres - 1) << 16);
1659 newmode->crtc_v_sync_strt_wid = (((vSyncStart - 1) & 0xfff) |
1660 (vsync_wid << 16) | (v_sync_pol << 23));
1662 if (!(info->flags & FBINFO_HWACCEL_DISABLED)) {
1663 /* We first calculate the engine pitch */
1664 rinfo->pitch = ((mode->xres_virtual * ((mode->bits_per_pixel + 1) / 8) + 0x3f)
1667 /* Then, re-multiply it to get the CRTC pitch */
1668 newmode->crtc_pitch = (rinfo->pitch << 3) / ((mode->bits_per_pixel + 1) / 8);
1670 newmode->crtc_pitch = (mode->xres_virtual >> 3);
1672 newmode->crtc_pitch |= (newmode->crtc_pitch << 16);
1675 * It looks like recent chips have a problem with SURFACE_CNTL,
1676 * setting SURF_TRANSLATION_DIS completely disables the
1677 * swapper as well, so we leave it unset now.
1679 newmode->surface_cntl = 0;
1681 #if defined(__BIG_ENDIAN)
1683 /* Setup swapping on both apertures, though we currently
1684 * only use aperture 0, enabling swapper on aperture 1
1687 switch (mode->bits_per_pixel) {
1689 newmode->surface_cntl |= NONSURF_AP0_SWP_16BPP;
1690 newmode->surface_cntl |= NONSURF_AP1_SWP_16BPP;
1694 newmode->surface_cntl |= NONSURF_AP0_SWP_32BPP;
1695 newmode->surface_cntl |= NONSURF_AP1_SWP_32BPP;
1700 /* Clear surface registers */
1701 for (i=0; i<8; i++) {
1702 newmode->surf_lower_bound[i] = 0;
1703 newmode->surf_upper_bound[i] = 0x1f;
1704 newmode->surf_info[i] = 0;
1707 pr_debug("h_total_disp = 0x%x\t hsync_strt_wid = 0x%x\n",
1708 newmode->crtc_h_total_disp, newmode->crtc_h_sync_strt_wid);
1709 pr_debug("v_total_disp = 0x%x\t vsync_strt_wid = 0x%x\n",
1710 newmode->crtc_v_total_disp, newmode->crtc_v_sync_strt_wid);
1712 rinfo->bpp = mode->bits_per_pixel;
1713 rinfo->depth = depth;
1715 pr_debug("pixclock = %lu\n", (unsigned long)pixClock);
1716 pr_debug("freq = %lu\n", (unsigned long)freq);
1718 /* We use PPLL_DIV_3 */
1719 newmode->clk_cntl_index = 0x300;
1721 /* Calculate PPLL value if necessary */
1723 radeon_calc_pll_regs(rinfo, newmode, freq);
1725 newmode->vclk_ecp_cntl = rinfo->init_state.vclk_ecp_cntl;
1727 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1728 unsigned int hRatio, vRatio;
1730 if (mode->xres > rinfo->panel_info.xres)
1731 mode->xres = rinfo->panel_info.xres;
1732 if (mode->yres > rinfo->panel_info.yres)
1733 mode->yres = rinfo->panel_info.yres;
1735 newmode->fp_horz_stretch = (((rinfo->panel_info.xres / 8) - 1)
1736 << HORZ_PANEL_SHIFT);
1737 newmode->fp_vert_stretch = ((rinfo->panel_info.yres - 1)
1738 << VERT_PANEL_SHIFT);
1740 if (mode->xres != rinfo->panel_info.xres) {
1741 hRatio = round_div(mode->xres * HORZ_STRETCH_RATIO_MAX,
1742 rinfo->panel_info.xres);
1743 newmode->fp_horz_stretch = (((((unsigned long)hRatio) & HORZ_STRETCH_RATIO_MASK)) |
1744 (newmode->fp_horz_stretch &
1745 (HORZ_PANEL_SIZE | HORZ_FP_LOOP_STRETCH |
1746 HORZ_AUTO_RATIO_INC)));
1747 newmode->fp_horz_stretch |= (HORZ_STRETCH_BLEND |
1748 HORZ_STRETCH_ENABLE);
1751 newmode->fp_horz_stretch &= ~HORZ_AUTO_RATIO;
1753 if (mode->yres != rinfo->panel_info.yres) {
1754 vRatio = round_div(mode->yres * VERT_STRETCH_RATIO_MAX,
1755 rinfo->panel_info.yres);
1756 newmode->fp_vert_stretch = (((((unsigned long)vRatio) & VERT_STRETCH_RATIO_MASK)) |
1757 (newmode->fp_vert_stretch &
1758 (VERT_PANEL_SIZE | VERT_STRETCH_RESERVED)));
1759 newmode->fp_vert_stretch |= (VERT_STRETCH_BLEND |
1760 VERT_STRETCH_ENABLE);
1763 newmode->fp_vert_stretch &= ~VERT_AUTO_RATIO_EN;
1765 newmode->fp_gen_cntl = (rinfo->init_state.fp_gen_cntl & (u32)
1767 FP_RMX_HVSYNC_CONTROL_EN |
1772 FP_CRTC_USE_SHADOW_VEND |
1775 newmode->fp_gen_cntl |= (FP_CRTC_DONT_SHADOW_VPAR |
1776 FP_CRTC_DONT_SHADOW_HEND |
1779 if (IS_R300_VARIANT(rinfo) ||
1780 (rinfo->family == CHIP_FAMILY_R200)) {
1781 newmode->fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
1783 newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
1785 newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
1787 newmode->fp_gen_cntl |= FP_SEL_CRTC1;
1789 newmode->lvds_gen_cntl = rinfo->init_state.lvds_gen_cntl;
1790 newmode->lvds_pll_cntl = rinfo->init_state.lvds_pll_cntl;
1791 newmode->tmds_crc = rinfo->init_state.tmds_crc;
1792 newmode->tmds_transmitter_cntl = rinfo->init_state.tmds_transmitter_cntl;
1794 if (primary_mon == MT_LCD) {
1795 newmode->lvds_gen_cntl |= (LVDS_ON | LVDS_BLON);
1796 newmode->fp_gen_cntl &= ~(FP_FPON | FP_TMDS_EN);
1799 newmode->fp_gen_cntl |= (FP_FPON | FP_TMDS_EN);
1800 newmode->tmds_transmitter_cntl &= ~(TMDS_PLLRST);
1801 /* TMDS_PLL_EN bit is reversed on RV (and mobility) chips */
1802 if (IS_R300_VARIANT(rinfo) ||
1803 (rinfo->family == CHIP_FAMILY_R200) || !rinfo->has_CRTC2)
1804 newmode->tmds_transmitter_cntl &= ~TMDS_PLL_EN;
1806 newmode->tmds_transmitter_cntl |= TMDS_PLL_EN;
1807 newmode->crtc_ext_cntl &= ~CRTC_CRT_ON;
1810 newmode->fp_crtc_h_total_disp = (((rinfo->panel_info.hblank / 8) & 0x3ff) |
1811 (((mode->xres / 8) - 1) << 16));
1812 newmode->fp_crtc_v_total_disp = (rinfo->panel_info.vblank & 0xffff) |
1813 ((mode->yres - 1) << 16);
1814 newmode->fp_h_sync_strt_wid = ((rinfo->panel_info.hOver_plus & 0x1fff) |
1815 (hsync_wid << 16) | (h_sync_pol << 23));
1816 newmode->fp_v_sync_strt_wid = ((rinfo->panel_info.vOver_plus & 0xfff) |
1817 (vsync_wid << 16) | (v_sync_pol << 23));
1821 if (!rinfo->asleep) {
1822 memcpy(&rinfo->state, newmode, sizeof(*newmode));
1823 radeon_write_mode (rinfo, newmode, 0);
1824 /* (re)initialize the engine */
1825 if (!(info->flags & FBINFO_HWACCEL_DISABLED))
1826 radeonfb_engine_init (rinfo);
1829 if (!(info->flags & FBINFO_HWACCEL_DISABLED))
1830 info->fix.line_length = rinfo->pitch*64;
1832 info->fix.line_length = mode->xres_virtual
1833 * ((mode->bits_per_pixel + 1) / 8);
1834 info->fix.visual = rinfo->depth == 8 ? FB_VISUAL_PSEUDOCOLOR
1835 : FB_VISUAL_DIRECTCOLOR;
1837 #ifdef CONFIG_BOOTX_TEXT
1838 /* Update debug text engine */
1839 btext_update_display(rinfo->fb_base_phys, mode->xres, mode->yres,
1840 rinfo->depth, info->fix.line_length);
1847 static struct fb_ops radeonfb_ops = {
1848 .owner = THIS_MODULE,
1849 .fb_check_var = radeonfb_check_var,
1850 .fb_set_par = radeonfb_set_par,
1851 .fb_setcolreg = radeonfb_setcolreg,
1852 .fb_setcmap = radeonfb_setcmap,
1853 .fb_pan_display = radeonfb_pan_display,
1854 .fb_blank = radeonfb_blank,
1855 .fb_ioctl = radeonfb_ioctl,
1856 .fb_sync = radeonfb_sync,
1857 .fb_fillrect = radeonfb_fillrect,
1858 .fb_copyarea = radeonfb_copyarea,
1859 .fb_imageblit = radeonfb_imageblit,
1863 static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo)
1865 struct fb_info *info = rinfo->info;
1868 info->pseudo_palette = rinfo->pseudo_palette;
1869 info->flags = FBINFO_DEFAULT
1870 | FBINFO_HWACCEL_IMAGEBLIT
1871 | FBINFO_HWACCEL_COPYAREA
1872 | FBINFO_HWACCEL_FILLRECT
1873 | FBINFO_HWACCEL_XPAN
1874 | FBINFO_HWACCEL_YPAN;
1875 info->fbops = &radeonfb_ops;
1876 info->screen_base = rinfo->fb_base;
1877 info->screen_size = rinfo->mapped_vram;
1878 /* Fill fix common fields */
1879 strlcpy(info->fix.id, rinfo->name, sizeof(info->fix.id));
1880 info->fix.smem_start = rinfo->fb_base_phys;
1881 info->fix.smem_len = rinfo->video_ram;
1882 info->fix.type = FB_TYPE_PACKED_PIXELS;
1883 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
1884 info->fix.xpanstep = 8;
1885 info->fix.ypanstep = 1;
1886 info->fix.ywrapstep = 0;
1887 info->fix.type_aux = 0;
1888 info->fix.mmio_start = rinfo->mmio_base_phys;
1889 info->fix.mmio_len = RADEON_REGSIZE;
1890 info->fix.accel = FB_ACCEL_ATI_RADEON;
1892 fb_alloc_cmap(&info->cmap, 256, 0);
1895 info->flags |= FBINFO_HWACCEL_DISABLED;
1901 * This reconfigure the card's internal memory map. In theory, we'd like
1902 * to setup the card's memory at the same address as it's PCI bus address,
1903 * and the AGP aperture right after that so that system RAM on 32 bits
1904 * machines at least, is directly accessible. However, doing so would
1905 * conflict with the current XFree drivers...
1906 * Ultimately, I hope XFree, GATOS and ATI binary drivers will all agree
1907 * on the proper way to set this up and duplicate this here. In the meantime,
1908 * I put the card's memory at 0 in card space and AGP at some random high
1909 * local (0xe0000000 for now) that will be changed by XFree/DRI anyway
1911 #ifdef CONFIG_PPC_OF
1912 #undef SET_MC_FB_FROM_APERTURE
1913 static void fixup_memory_mappings(struct radeonfb_info *rinfo)
1915 u32 save_crtc_gen_cntl, save_crtc2_gen_cntl = 0;
1916 u32 save_crtc_ext_cntl;
1917 u32 aper_base, aper_size;
1920 /* First, we disable display to avoid interfering */
1921 if (rinfo->has_CRTC2) {
1922 save_crtc2_gen_cntl = INREG(CRTC2_GEN_CNTL);
1923 OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl | CRTC2_DISP_REQ_EN_B);
1925 save_crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
1926 save_crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
1928 OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl | CRTC_DISPLAY_DIS);
1929 OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl | CRTC_DISP_REQ_EN_B);
1932 aper_base = INREG(CONFIG_APER_0_BASE);
1933 aper_size = INREG(CONFIG_APER_SIZE);
1935 #ifdef SET_MC_FB_FROM_APERTURE
1936 /* Set framebuffer to be at the same address as set in PCI BAR */
1937 OUTREG(MC_FB_LOCATION,
1938 ((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16));
1939 rinfo->fb_local_base = aper_base;
1941 OUTREG(MC_FB_LOCATION, 0x7fff0000);
1942 rinfo->fb_local_base = 0;
1944 agp_base = aper_base + aper_size;
1945 if (agp_base & 0xf0000000)
1946 agp_base = (aper_base | 0x0fffffff) + 1;
1948 /* Set AGP to be just after the framebuffer on a 256Mb boundary. This
1949 * assumes the FB isn't mapped to 0xf0000000 or above, but this is
1950 * always the case on PPCs afaik.
1952 #ifdef SET_MC_FB_FROM_APERTURE
1953 OUTREG(MC_AGP_LOCATION, 0xffff0000 | (agp_base >> 16));
1955 OUTREG(MC_AGP_LOCATION, 0xffffe000);
1958 /* Fixup the display base addresses & engine offsets while we
1961 #ifdef SET_MC_FB_FROM_APERTURE
1962 OUTREG(DISPLAY_BASE_ADDR, aper_base);
1963 if (rinfo->has_CRTC2)
1964 OUTREG(CRTC2_DISPLAY_BASE_ADDR, aper_base);
1965 OUTREG(OV0_BASE_ADDR, aper_base);
1967 OUTREG(DISPLAY_BASE_ADDR, 0);
1968 if (rinfo->has_CRTC2)
1969 OUTREG(CRTC2_DISPLAY_BASE_ADDR, 0);
1970 OUTREG(OV0_BASE_ADDR, 0);
1974 /* Restore display settings */
1975 OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl);
1976 OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl);
1977 if (rinfo->has_CRTC2)
1978 OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl);
1980 pr_debug("aper_base: %08x MC_FB_LOC to: %08x, MC_AGP_LOC to: %08x\n",
1982 ((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16),
1983 0xffff0000 | (agp_base >> 16));
1985 #endif /* CONFIG_PPC_OF */
1988 static void radeon_identify_vram(struct radeonfb_info *rinfo)
1992 /* framebuffer size */
1993 if ((rinfo->family == CHIP_FAMILY_RS100) ||
1994 (rinfo->family == CHIP_FAMILY_RS200) ||
1995 (rinfo->family == CHIP_FAMILY_RS300) ||
1996 (rinfo->family == CHIP_FAMILY_RC410) ||
1997 (rinfo->family == CHIP_FAMILY_RS400) ||
1998 (rinfo->family == CHIP_FAMILY_RS480) ) {
1999 u32 tom = INREG(NB_TOM);
2000 tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024);
2002 OUTREG(MC_FB_LOCATION, tom);
2003 OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
2004 OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
2005 OUTREG(OV0_BASE_ADDR, (tom & 0xffff) << 16);
2007 /* This is supposed to fix the crtc2 noise problem. */
2008 OUTREG(GRPH2_BUFFER_CNTL, INREG(GRPH2_BUFFER_CNTL) & ~0x7f0000);
2010 if ((rinfo->family == CHIP_FAMILY_RS100) ||
2011 (rinfo->family == CHIP_FAMILY_RS200)) {
2012 /* This is to workaround the asic bug for RMX, some versions
2013 of BIOS dosen't have this register initialized correctly.
2015 OUTREGP(CRTC_MORE_CNTL, CRTC_H_CUTOFF_ACTIVE_EN,
2016 ~CRTC_H_CUTOFF_ACTIVE_EN);
2019 tmp = INREG(CONFIG_MEMSIZE);
2022 /* mem size is bits [28:0], mask off the rest */
2023 rinfo->video_ram = tmp & CONFIG_MEMSIZE_MASK;
2026 * Hack to get around some busted production M6's
2029 if (rinfo->video_ram == 0) {
2030 switch (rinfo->pdev->device) {
2031 case PCI_CHIP_RADEON_LY:
2032 case PCI_CHIP_RADEON_LZ:
2033 rinfo->video_ram = 8192 * 1024;
2042 * Now try to identify VRAM type
2044 if (rinfo->is_IGP || (rinfo->family >= CHIP_FAMILY_R300) ||
2045 (INREG(MEM_SDRAM_MODE_REG) & (1<<30)))
2046 rinfo->vram_ddr = 1;
2048 rinfo->vram_ddr = 0;
2050 tmp = INREG(MEM_CNTL);
2051 if (IS_R300_VARIANT(rinfo)) {
2052 tmp &= R300_MEM_NUM_CHANNELS_MASK;
2054 case 0: rinfo->vram_width = 64; break;
2055 case 1: rinfo->vram_width = 128; break;
2056 case 2: rinfo->vram_width = 256; break;
2057 default: rinfo->vram_width = 128; break;
2059 } else if ((rinfo->family == CHIP_FAMILY_RV100) ||
2060 (rinfo->family == CHIP_FAMILY_RS100) ||
2061 (rinfo->family == CHIP_FAMILY_RS200)){
2062 if (tmp & RV100_MEM_HALF_MODE)
2063 rinfo->vram_width = 32;
2065 rinfo->vram_width = 64;
2067 if (tmp & MEM_NUM_CHANNELS_MASK)
2068 rinfo->vram_width = 128;
2070 rinfo->vram_width = 64;
2073 /* This may not be correct, as some cards can have half of channel disabled
2074 * ToDo: identify these cases
2077 pr_debug("radeonfb (%s): Found %ldk of %s %d bits wide videoram\n",
2078 pci_name(rinfo->pdev),
2079 rinfo->video_ram / 1024,
2080 rinfo->vram_ddr ? "DDR" : "SDRAM",
2088 static ssize_t radeon_show_one_edid(char *buf, loff_t off, size_t count, const u8 *edid)
2090 return memory_read_from_buffer(buf, count, &off, edid, EDID_LENGTH);
2094 static ssize_t radeon_show_edid1(struct kobject *kobj,
2095 struct bin_attribute *bin_attr,
2096 char *buf, loff_t off, size_t count)
2098 struct device *dev = container_of(kobj, struct device, kobj);
2099 struct pci_dev *pdev = to_pci_dev(dev);
2100 struct fb_info *info = pci_get_drvdata(pdev);
2101 struct radeonfb_info *rinfo = info->par;
2103 return radeon_show_one_edid(buf, off, count, rinfo->mon1_EDID);
2107 static ssize_t radeon_show_edid2(struct kobject *kobj,
2108 struct bin_attribute *bin_attr,
2109 char *buf, loff_t off, size_t count)
2111 struct device *dev = container_of(kobj, struct device, kobj);
2112 struct pci_dev *pdev = to_pci_dev(dev);
2113 struct fb_info *info = pci_get_drvdata(pdev);
2114 struct radeonfb_info *rinfo = info->par;
2116 return radeon_show_one_edid(buf, off, count, rinfo->mon2_EDID);
2119 static struct bin_attribute edid1_attr = {
2124 .size = EDID_LENGTH,
2125 .read = radeon_show_edid1,
2128 static struct bin_attribute edid2_attr = {
2133 .size = EDID_LENGTH,
2134 .read = radeon_show_edid2,
2138 static int __devinit radeonfb_pci_register (struct pci_dev *pdev,
2139 const struct pci_device_id *ent)
2141 struct fb_info *info;
2142 struct radeonfb_info *rinfo;
2144 unsigned char c1, c2;
2147 pr_debug("radeonfb_pci_register BEGIN\n");
2149 /* Enable device in PCI config */
2150 ret = pci_enable_device(pdev);
2152 printk(KERN_ERR "radeonfb (%s): Cannot enable PCI device\n",
2157 info = framebuffer_alloc(sizeof(struct radeonfb_info), &pdev->dev);
2159 printk (KERN_ERR "radeonfb (%s): could not allocate memory\n",
2168 spin_lock_init(&rinfo->reg_lock);
2169 init_timer(&rinfo->lvds_timer);
2170 rinfo->lvds_timer.function = radeon_lvds_timer_func;
2171 rinfo->lvds_timer.data = (unsigned long)rinfo;
2173 c1 = ent->device >> 8;
2174 c2 = ent->device & 0xff;
2175 if (isprint(c1) && isprint(c2))
2176 snprintf(rinfo->name, sizeof(rinfo->name),
2177 "ATI Radeon %x \"%c%c\"", ent->device & 0xffff, c1, c2);
2179 snprintf(rinfo->name, sizeof(rinfo->name),
2180 "ATI Radeon %x", ent->device & 0xffff);
2182 rinfo->family = ent->driver_data & CHIP_FAMILY_MASK;
2183 rinfo->chipset = pdev->device;
2184 rinfo->has_CRTC2 = (ent->driver_data & CHIP_HAS_CRTC2) != 0;
2185 rinfo->is_mobility = (ent->driver_data & CHIP_IS_MOBILITY) != 0;
2186 rinfo->is_IGP = (ent->driver_data & CHIP_IS_IGP) != 0;
2188 /* Set base addrs */
2189 rinfo->fb_base_phys = pci_resource_start (pdev, 0);
2190 rinfo->mmio_base_phys = pci_resource_start (pdev, 2);
2192 /* request the mem regions */
2193 ret = pci_request_region(pdev, 0, "radeonfb framebuffer");
2195 printk( KERN_ERR "radeonfb (%s): cannot request region 0.\n",
2196 pci_name(rinfo->pdev));
2197 goto err_release_fb;
2200 ret = pci_request_region(pdev, 2, "radeonfb mmio");
2202 printk( KERN_ERR "radeonfb (%s): cannot request region 2.\n",
2203 pci_name(rinfo->pdev));
2204 goto err_release_pci0;
2207 /* map the regions */
2208 rinfo->mmio_base = ioremap(rinfo->mmio_base_phys, RADEON_REGSIZE);
2209 if (!rinfo->mmio_base) {
2210 printk(KERN_ERR "radeonfb (%s): cannot map MMIO\n",
2211 pci_name(rinfo->pdev));
2213 goto err_release_pci2;
2216 rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16;
2222 if (rinfo->family == CHIP_FAMILY_R300 &&
2223 (INREG(CONFIG_CNTL) & CFG_ATI_REV_ID_MASK)
2225 rinfo->errata |= CHIP_ERRATA_R300_CG;
2227 if (rinfo->family == CHIP_FAMILY_RV200 ||
2228 rinfo->family == CHIP_FAMILY_RS200)
2229 rinfo->errata |= CHIP_ERRATA_PLL_DUMMYREADS;
2231 if (rinfo->family == CHIP_FAMILY_RV100 ||
2232 rinfo->family == CHIP_FAMILY_RS100 ||
2233 rinfo->family == CHIP_FAMILY_RS200)
2234 rinfo->errata |= CHIP_ERRATA_PLL_DELAY;
2236 #if defined(CONFIG_PPC_OF) || defined(CONFIG_SPARC)
2237 /* On PPC, we obtain the OF device-node pointer to the firmware
2238 * data for this chip
2240 rinfo->of_node = pci_device_to_OF_node(pdev);
2241 if (rinfo->of_node == NULL)
2242 printk(KERN_WARNING "radeonfb (%s): Cannot match card to OF node !\n",
2243 pci_name(rinfo->pdev));
2245 #endif /* CONFIG_PPC_OF || CONFIG_SPARC */
2246 #ifdef CONFIG_PPC_OF
2247 /* On PPC, the firmware sets up a memory mapping that tends
2248 * to cause lockups when enabling the engine. We reconfigure
2249 * the card internal memory mappings properly
2251 fixup_memory_mappings(rinfo);
2252 #endif /* CONFIG_PPC_OF */
2254 /* Get VRAM size and type */
2255 radeon_identify_vram(rinfo);
2257 rinfo->mapped_vram = min_t(unsigned long, MAX_MAPPED_VRAM, rinfo->video_ram);
2260 rinfo->fb_base = ioremap (rinfo->fb_base_phys,
2261 rinfo->mapped_vram);
2262 } while (rinfo->fb_base == NULL &&
2263 ((rinfo->mapped_vram /= 2) >= MIN_MAPPED_VRAM));
2265 if (rinfo->fb_base == NULL) {
2266 printk (KERN_ERR "radeonfb (%s): cannot map FB\n",
2267 pci_name(rinfo->pdev));
2272 pr_debug("radeonfb (%s): mapped %ldk videoram\n", pci_name(rinfo->pdev),
2273 rinfo->mapped_vram/1024);
2276 * Map the BIOS ROM if any and retrieve PLL parameters from
2277 * the BIOS. We skip that on mobility chips as the real panel
2278 * values we need aren't in the ROM but in the BIOS image in
2279 * memory. This is definitely not the best meacnism though,
2280 * we really need the arch code to tell us which is the "primary"
2281 * video adapter to use the memory image (or better, the arch
2282 * should provide us a copy of the BIOS image to shield us from
2283 * archs who would store that elsewhere and/or could initialize
2284 * more than one adapter during boot).
2286 if (!rinfo->is_mobility)
2287 radeon_map_ROM(rinfo, pdev);
2290 * On x86, the primary display on laptop may have it's BIOS
2291 * ROM elsewhere, try to locate it at the legacy memory hole.
2292 * We probably need to make sure this is the primary display,
2293 * but that is difficult without some arch support.
2296 if (rinfo->bios_seg == NULL)
2297 radeon_find_mem_vbios(rinfo);
2300 /* If both above failed, try the BIOS ROM again for mobility
2303 if (rinfo->bios_seg == NULL && rinfo->is_mobility)
2304 radeon_map_ROM(rinfo, pdev);
2306 /* Get informations about the board's PLL */
2307 radeon_get_pllinfo(rinfo);
2309 #ifdef CONFIG_FB_RADEON_I2C
2310 /* Register I2C bus */
2311 radeon_create_i2c_busses(rinfo);
2314 /* set all the vital stuff */
2315 radeon_set_fbinfo (rinfo);
2317 /* Probe screen types */
2318 radeon_probe_screens(rinfo, monitor_layout, ignore_edid);
2320 /* Build mode list, check out panel native model */
2321 radeon_check_modes(rinfo, mode_option);
2323 /* Register some sysfs stuff (should be done better) */
2324 if (rinfo->mon1_EDID)
2325 err |= sysfs_create_bin_file(&rinfo->pdev->dev.kobj,
2327 if (rinfo->mon2_EDID)
2328 err |= sysfs_create_bin_file(&rinfo->pdev->dev.kobj,
2331 pr_warning("%s() Creating sysfs files failed, continuing\n",
2334 /* save current mode regs before we switch into the new one
2335 * so we can restore this upon __exit
2337 radeon_save_state (rinfo, &rinfo->init_state);
2338 memcpy(&rinfo->state, &rinfo->init_state, sizeof(struct radeon_regs));
2340 /* Setup Power Management capabilities */
2341 if (default_dynclk < -1) {
2342 /* -2 is special: means ON on mobility chips and do not
2345 radeonfb_pm_init(rinfo, rinfo->is_mobility ? 1 : -1, ignore_devlist, force_sleep);
2347 radeonfb_pm_init(rinfo, default_dynclk, ignore_devlist, force_sleep);
2349 pci_set_drvdata(pdev, info);
2351 /* Register with fbdev layer */
2352 ret = register_framebuffer(info);
2354 printk (KERN_ERR "radeonfb (%s): could not register framebuffer\n",
2355 pci_name(rinfo->pdev));
2360 rinfo->mtrr_hdl = nomtrr ? -1 : mtrr_add(rinfo->fb_base_phys,
2362 MTRR_TYPE_WRCOMB, 1);
2366 radeonfb_bl_init(rinfo);
2368 printk ("radeonfb (%s): %s\n", pci_name(rinfo->pdev), rinfo->name);
2370 if (rinfo->bios_seg)
2371 radeon_unmap_ROM(rinfo, pdev);
2372 pr_debug("radeonfb_pci_register END\n");
2376 iounmap(rinfo->fb_base);
2378 kfree(rinfo->mon1_EDID);
2379 kfree(rinfo->mon2_EDID);
2380 if (rinfo->mon1_modedb)
2381 fb_destroy_modedb(rinfo->mon1_modedb);
2382 fb_dealloc_cmap(&info->cmap);
2383 #ifdef CONFIG_FB_RADEON_I2C
2384 radeon_delete_i2c_busses(rinfo);
2386 if (rinfo->bios_seg)
2387 radeon_unmap_ROM(rinfo, pdev);
2388 iounmap(rinfo->mmio_base);
2390 pci_release_region(pdev, 2);
2392 pci_release_region(pdev, 0);
2394 framebuffer_release(info);
2402 static void __devexit radeonfb_pci_unregister (struct pci_dev *pdev)
2404 struct fb_info *info = pci_get_drvdata(pdev);
2405 struct radeonfb_info *rinfo = info->par;
2410 radeonfb_pm_exit(rinfo);
2412 if (rinfo->mon1_EDID)
2413 sysfs_remove_bin_file(&rinfo->pdev->dev.kobj, &edid1_attr);
2414 if (rinfo->mon2_EDID)
2415 sysfs_remove_bin_file(&rinfo->pdev->dev.kobj, &edid2_attr);
2418 /* restore original state
2420 * Doesn't quite work yet, I suspect if we come from a legacy
2421 * VGA mode (or worse, text mode), we need to do some VGA black
2422 * magic here that I know nothing about. --BenH
2424 radeon_write_mode (rinfo, &rinfo->init_state, 1);
2427 del_timer_sync(&rinfo->lvds_timer);
2430 if (rinfo->mtrr_hdl >= 0)
2431 mtrr_del(rinfo->mtrr_hdl, 0, 0);
2434 unregister_framebuffer(info);
2436 radeonfb_bl_exit(rinfo);
2438 iounmap(rinfo->mmio_base);
2439 iounmap(rinfo->fb_base);
2441 pci_release_region(pdev, 2);
2442 pci_release_region(pdev, 0);
2444 kfree(rinfo->mon1_EDID);
2445 kfree(rinfo->mon2_EDID);
2446 if (rinfo->mon1_modedb)
2447 fb_destroy_modedb(rinfo->mon1_modedb);
2448 #ifdef CONFIG_FB_RADEON_I2C
2449 radeon_delete_i2c_busses(rinfo);
2451 fb_dealloc_cmap(&info->cmap);
2452 framebuffer_release(info);
2456 static struct pci_driver radeonfb_driver = {
2458 .id_table = radeonfb_pci_table,
2459 .probe = radeonfb_pci_register,
2460 .remove = __devexit_p(radeonfb_pci_unregister),
2462 .suspend = radeonfb_pci_suspend,
2463 .resume = radeonfb_pci_resume,
2464 #endif /* CONFIG_PM */
2468 static int __init radeonfb_setup (char *options)
2472 if (!options || !*options)
2475 while ((this_opt = strsep (&options, ",")) != NULL) {
2479 if (!strncmp(this_opt, "noaccel", 7)) {
2481 } else if (!strncmp(this_opt, "mirror", 6)) {
2483 } else if (!strncmp(this_opt, "force_dfp", 9)) {
2485 } else if (!strncmp(this_opt, "panel_yres:", 11)) {
2486 panel_yres = simple_strtoul((this_opt+11), NULL, 0);
2487 } else if (!strncmp(this_opt, "backlight:", 10)) {
2488 backlight = simple_strtoul(this_opt+10, NULL, 0);
2490 } else if (!strncmp(this_opt, "nomtrr", 6)) {
2493 } else if (!strncmp(this_opt, "nomodeset", 9)) {
2495 } else if (!strncmp(this_opt, "force_measure_pll", 17)) {
2496 force_measure_pll = 1;
2497 } else if (!strncmp(this_opt, "ignore_edid", 11)) {
2499 #if defined(CONFIG_PM) && defined(CONFIG_X86)
2500 } else if (!strncmp(this_opt, "force_sleep", 11)) {
2502 } else if (!strncmp(this_opt, "ignore_devlist", 14)) {
2506 mode_option = this_opt;
2512 static int __init radeonfb_init (void)
2515 char *option = NULL;
2517 if (fb_get_options("radeonfb", &option))
2519 radeonfb_setup(option);
2521 return pci_register_driver (&radeonfb_driver);
2525 static void __exit radeonfb_exit (void)
2527 pci_unregister_driver (&radeonfb_driver);
2530 module_init(radeonfb_init);
2531 module_exit(radeonfb_exit);
2533 MODULE_AUTHOR("Ani Joshi");
2534 MODULE_DESCRIPTION("framebuffer driver for ATI Radeon chipset");
2535 MODULE_LICENSE("GPL");
2536 module_param(noaccel, bool, 0);
2537 module_param(default_dynclk, int, 0);
2538 MODULE_PARM_DESC(default_dynclk, "int: -2=enable on mobility only,-1=do not change,0=off,1=on");
2539 MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
2540 module_param(nomodeset, bool, 0);
2541 MODULE_PARM_DESC(nomodeset, "bool: disable actual setting of video mode");
2542 module_param(mirror, bool, 0);
2543 MODULE_PARM_DESC(mirror, "bool: mirror the display to both monitors");
2544 module_param(force_dfp, bool, 0);
2545 MODULE_PARM_DESC(force_dfp, "bool: force display to dfp");
2546 module_param(ignore_edid, bool, 0);
2547 MODULE_PARM_DESC(ignore_edid, "bool: Ignore EDID data when doing DDC probe");
2548 module_param(monitor_layout, charp, 0);
2549 MODULE_PARM_DESC(monitor_layout, "Specify monitor mapping (like XFree86)");
2550 module_param(force_measure_pll, bool, 0);
2551 MODULE_PARM_DESC(force_measure_pll, "Force measurement of PLL (debug)");
2553 module_param(nomtrr, bool, 0);
2554 MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers");
2556 module_param(panel_yres, int, 0);
2557 MODULE_PARM_DESC(panel_yres, "int: set panel yres");
2558 module_param(mode_option, charp, 0);
2559 MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
2560 #if defined(CONFIG_PM) && defined(CONFIG_X86)
2561 module_param(force_sleep, bool, 0);
2562 MODULE_PARM_DESC(force_sleep, "bool: force D2 sleep mode on all hardware");
2563 module_param(ignore_devlist, bool, 0);
2564 MODULE_PARM_DESC(ignore_devlist, "bool: ignore workarounds for bugs in specific laptops");