git.oblomov.eu Git - linux-2.6/blob - drivers/net/defxx.c

   1 /*
   2  * File Name:
   3  *   defxx.c
   4  *
   5  * Copyright Information:
   6  *   Copyright Digital Equipment Corporation 1996.
   7  *
   8  *   This software may be used and distributed according to the terms of
   9  *   the GNU General Public License, incorporated herein by reference.
  10  *
  11  * Abstract:
  12  *   A Linux device driver supporting the Digital Equipment Corporation
  13  *   FDDI EISA and PCI controller families.  Supported adapters include:
  14  *
  15  *              DEC FDDIcontroller/EISA (DEFEA)
  16  *              DEC FDDIcontroller/PCI  (DEFPA)
  17  *
  18  * The original author:
  19  *   LVS        Lawrence V. Stefani <lstefani@yahoo.com>
  20  *
  21  * Maintainers:
  22  *   macro      Maciej W. Rozycki <macro@linux-mips.org>
  23  *
  24  * Credits:
  25  *   I'd like to thank Patricia Cross for helping me get started with
  26  *   Linux, David Davies for a lot of help upgrading and configuring
  27  *   my development system and for answering many OS and driver
  28  *   development questions, and Alan Cox for recommendations and
  29  *   integration help on getting FDDI support into Linux.  LVS
  30  *
  31  * Driver Architecture:
  32  *   The driver architecture is largely based on previous driver work
  33  *   for other operating systems.  The upper edge interface and
  34  *   functions were largely taken from existing Linux device drivers
  35  *   such as David Davies' DE4X5.C driver and Donald Becker's TULIP.C
  36  *   driver.
  37  *
  38  *   Adapter Probe -
  39  *              The driver scans for supported EISA adapters by reading the
  40  *              SLOT ID register for each EISA slot and making a match
  41  *              against the expected value.
  42  *
  43  *   Bus-Specific Initialization -
  44  *              This driver currently supports both EISA and PCI controller
  45  *              families.  While the custom DMA chip and FDDI logic is similar
  46  *              or identical, the bus logic is very different.  After
  47  *              initialization, the     only bus-specific differences is in how the
  48  *              driver enables and disables interrupts.  Other than that, the
  49  *              run-time critical code behaves the same on both families.
  50  *              It's important to note that both adapter families are configured
  51  *              to I/O map, rather than memory map, the adapter registers.
  52  *
  53  *   Driver Open/Close -
  54  *              In the driver open routine, the driver ISR (interrupt service
  55  *              routine) is registered and the adapter is brought to an
  56  *              operational state.  In the driver close routine, the opposite
  57  *              occurs; the driver ISR is deregistered and the adapter is
  58  *              brought to a safe, but closed state.  Users may use consecutive
  59  *              commands to bring the adapter up and down as in the following
  60  *              example:
  61  *                                      ifconfig fddi0 up
  62  *                                      ifconfig fddi0 down
  63  *                                      ifconfig fddi0 up
  64  *
  65  *   Driver Shutdown -
  66  *              Apparently, there is no shutdown or halt routine support under
  67  *              Linux.  This routine would be called during "reboot" or
  68  *              "shutdown" to allow the driver to place the adapter in a safe
  69  *              state before a warm reboot occurs.  To be really safe, the user
  70  *              should close the adapter before shutdown (eg. ifconfig fddi0 down)
  71  *              to ensure that the adapter DMA engine is taken off-line.  However,
  72  *              the current driver code anticipates this problem and always issues
  73  *              a soft reset of the adapter     at the beginning of driver initialization.
  74  *              A future driver enhancement in this area may occur in 2.1.X where
  75  *              Alan indicated that a shutdown handler may be implemented.
  76  *
  77  *   Interrupt Service Routine -
  78  *              The driver supports shared interrupts, so the ISR is registered for
  79  *              each board with the appropriate flag and the pointer to that board's
  80  *              device structure.  This provides the context during interrupt
  81  *              processing to support shared interrupts and multiple boards.
  82  *
  83  *              Interrupt enabling/disabling can occur at many levels.  At the host
  84  *              end, you can disable system interrupts, or disable interrupts at the
  85  *              PIC (on Intel systems).  Across the bus, both EISA and PCI adapters
  86  *              have a bus-logic chip interrupt enable/disable as well as a DMA
  87  *              controller interrupt enable/disable.
  88  *
  89  *              The driver currently enables and disables adapter interrupts at the
  90  *              bus-logic chip and assumes that Linux will take care of clearing or
  91  *              acknowledging any host-based interrupt chips.
  92  *
  93  *   Control Functions -
  94  *              Control functions are those used to support functions such as adding
  95  *              or deleting multicast addresses, enabling or disabling packet
  96  *              reception filters, or other custom/proprietary commands.  Presently,
  97  *              the driver supports the "get statistics", "set multicast list", and
  98  *              "set mac address" functions defined by Linux.  A list of possible
  99  *              enhancements include:
 100  *
 101  *                              - Custom ioctl interface for executing port interface commands
 102  *                              - Custom ioctl interface for adding unicast addresses to
 103  *                                adapter CAM (to support bridge functions).
 104  *                              - Custom ioctl interface for supporting firmware upgrades.
 105  *
 106  *   Hardware (port interface) Support Routines -
 107  *              The driver function names that start with "dfx_hw_" represent
 108  *              low-level port interface routines that are called frequently.  They
 109  *              include issuing a DMA or port control command to the adapter,
 110  *              resetting the adapter, or reading the adapter state.  Since the
 111  *              driver initialization and run-time code must make calls into the
 112  *              port interface, these routines were written to be as generic and
 113  *              usable as possible.
 114  *
 115  *   Receive Path -
 116  *              The adapter DMA engine supports a 256 entry receive descriptor block
 117  *              of which up to 255 entries can be used at any given time.  The
 118  *              architecture is a standard producer, consumer, completion model in
 119  *              which the driver "produces" receive buffers to the adapter, the
 120  *              adapter "consumes" the receive buffers by DMAing incoming packet data,
 121  *              and the driver "completes" the receive buffers by servicing the
 122  *              incoming packet, then "produces" a new buffer and starts the cycle
 123  *              again.  Receive buffers can be fragmented in up to 16 fragments
 124  *              (descriptor     entries).  For simplicity, this driver posts
 125  *              single-fragment receive buffers of 4608 bytes, then allocates a
 126  *              sk_buff, copies the data, then reposts the buffer.  To reduce CPU
 127  *              utilization, a better approach would be to pass up the receive
 128  *              buffer (no extra copy) then allocate and post a replacement buffer.
 129  *              This is a performance enhancement that should be looked into at
 130  *              some point.
 131  *
 132  *   Transmit Path -
 133  *              Like the receive path, the adapter DMA engine supports a 256 entry
 134  *              transmit descriptor block of which up to 255 entries can be used at
 135  *              any     given time.  Transmit buffers can be fragmented in up to 255
 136  *              fragments (descriptor entries).  This driver always posts one
 137  *              fragment per transmit packet request.
 138  *
 139  *              The fragment contains the entire packet from FC to end of data.
 140  *              Before posting the buffer to the adapter, the driver sets a three-byte
 141  *              packet request header (PRH) which is required by the Motorola MAC chip
 142  *              used on the adapters.  The PRH tells the MAC the type of token to
 143  *              receive/send, whether or not to generate and append the CRC, whether
 144  *              synchronous or asynchronous framing is used, etc.  Since the PRH
 145  *              definition is not necessarily consistent across all FDDI chipsets,
 146  *              the driver, rather than the common FDDI packet handler routines,
 147  *              sets these bytes.
 148  *
 149  *              To reduce the amount of descriptor fetches needed per transmit request,
 150  *              the driver takes advantage of the fact that there are at least three
 151  *              bytes available before the skb->data field on the outgoing transmit
 152  *              request.  This is guaranteed by having fddi_setup() in net_init.c set
 153  *              dev->hard_header_len to 24 bytes.  21 bytes accounts for the largest
 154  *              header in an 802.2 SNAP frame.  The other 3 bytes are the extra "pad"
 155  *              bytes which we'll use to store the PRH.
 156  *
 157  *              There's a subtle advantage to adding these pad bytes to the
 158  *              hard_header_len, it ensures that the data portion of the packet for
 159  *              an 802.2 SNAP frame is longword aligned.  Other FDDI driver
 160  *              implementations may not need the extra padding and can start copying
 161  *              or DMAing directly from the FC byte which starts at skb->data.  Should
 162  *              another driver implementation need ADDITIONAL padding, the net_init.c
 163  *              module should be updated and dev->hard_header_len should be increased.
 164  *              NOTE: To maintain the alignment on the data portion of the packet,
 165  *              dev->hard_header_len should always be evenly divisible by 4 and at
 166  *              least 24 bytes in size.
 167  *
 168  * Modification History:
 169  *              Date            Name    Description
 170  *              16-Aug-96       LVS             Created.
 171  *              20-Aug-96       LVS             Updated dfx_probe so that version information
 172  *                                                      string is only displayed if 1 or more cards are
 173  *                                                      found.  Changed dfx_rcv_queue_process to copy
 174  *                                                      3 NULL bytes before FC to ensure that data is
 175  *                                                      longword aligned in receive buffer.
 176  *              09-Sep-96       LVS             Updated dfx_ctl_set_multicast_list to enable
 177  *                                                      LLC group promiscuous mode if multicast list
 178  *                                                      is too large.  LLC individual/group promiscuous
 179  *                                                      mode is now disabled if IFF_PROMISC flag not set.
 180  *                                                      dfx_xmt_queue_pkt no longer checks for NULL skb
 181  *                                                      on Alan Cox recommendation.  Added node address
 182  *                                                      override support.
 183  *              12-Sep-96       LVS             Reset current address to factory address during
 184  *                                                      device open.  Updated transmit path to post a
 185  *                                                      single fragment which includes PRH->end of data.
 186  *              Mar 2000        AC              Did various cleanups for 2.3.x
 187  *              Jun 2000        jgarzik         PCI and resource alloc cleanups
 188  *              Jul 2000        tjeerd          Much cleanup and some bug fixes
 189  *              Sep 2000        tjeerd          Fix leak on unload, cosmetic code cleanup
 190  *              Feb 2001                        Skb allocation fixes
 191  *              Feb 2001        davej           PCI enable cleanups.
 192  *              04 Aug 2003     macro           Converted to the DMA API.
 193  *              14 Aug 2004     macro           Fix device names reported.
 194  *              14 Jun 2005     macro           Use irqreturn_t.
 195  */
 196
 197 /* Include files */
 198
 199 #include <linux/module.h>
 200 #include <linux/kernel.h>
 201 #include <linux/string.h>
 202 #include <linux/errno.h>
 203 #include <linux/ioport.h>
 204 #include <linux/slab.h>
 205 #include <linux/interrupt.h>
 206 #include <linux/pci.h>
 207 #include <linux/delay.h>
 208 #include <linux/init.h>
 209 #include <linux/netdevice.h>
 210 #include <linux/fddidevice.h>
 211 #include <linux/skbuff.h>
 212 #include <linux/bitops.h>
 213
 214 #include <asm/byteorder.h>
 215 #include <asm/io.h>
 216
 217 #include "defxx.h"
 218
 219 /* Version information string should be updated prior to each new release!  */
 220 #define DRV_NAME "defxx"
 221 #define DRV_VERSION "v1.08"
 222 #define DRV_RELDATE "2005/06/14"
 223
 224 static char version[] __devinitdata =
 225         DRV_NAME ": " DRV_VERSION " " DRV_RELDATE
 226         "  Lawrence V. Stefani and others\n";
 227
 228 #define DYNAMIC_BUFFERS 1
 229
 230 #define SKBUFF_RX_COPYBREAK 200
 231 /*
 232  * NEW_SKB_SIZE = PI_RCV_DATA_K_SIZE_MAX+128 to allow 128 byte
 233  * alignment for compatibility with old EISA boards.
 234  */
 235 #define NEW_SKB_SIZE (PI_RCV_DATA_K_SIZE_MAX+128)
 236
 237 /* Define module-wide (static) routines */
 238
 239 static void             dfx_bus_init(struct net_device *dev);
 240 static void             dfx_bus_config_check(DFX_board_t *bp);
 241
 242 static int              dfx_driver_init(struct net_device *dev, const char *print_name);
 243 static int              dfx_adap_init(DFX_board_t *bp, int get_buffers);
 244
 245 static int              dfx_open(struct net_device *dev);
 246 static int              dfx_close(struct net_device *dev);
 247
 248 static void             dfx_int_pr_halt_id(DFX_board_t *bp);
 249 static void             dfx_int_type_0_process(DFX_board_t *bp);
 250 static void             dfx_int_common(struct net_device *dev);
 251 static irqreturn_t      dfx_interrupt(int irq, void *dev_id,
 252                                       struct pt_regs *regs);
 253
 254 static struct           net_device_stats *dfx_ctl_get_stats(struct net_device *dev);
 255 static void             dfx_ctl_set_multicast_list(struct net_device *dev);
 256 static int              dfx_ctl_set_mac_address(struct net_device *dev, void *addr);
 257 static int              dfx_ctl_update_cam(DFX_board_t *bp);
 258 static int              dfx_ctl_update_filters(DFX_board_t *bp);
 259
 260 static int              dfx_hw_dma_cmd_req(DFX_board_t *bp);
 261 static int              dfx_hw_port_ctrl_req(DFX_board_t *bp, PI_UINT32 command, PI_UINT32 data_a, PI_UINT32 data_b, PI_UINT32 *host_data);
 262 static void             dfx_hw_adap_reset(DFX_board_t *bp, PI_UINT32 type);
 263 static int              dfx_hw_adap_state_rd(DFX_board_t *bp);
 264 static int              dfx_hw_dma_uninit(DFX_board_t *bp, PI_UINT32 type);
 265
 266 static int              dfx_rcv_init(DFX_board_t *bp, int get_buffers);
 267 static void             dfx_rcv_queue_process(DFX_board_t *bp);
 268 static void             dfx_rcv_flush(DFX_board_t *bp);
 269
 270 static int              dfx_xmt_queue_pkt(struct sk_buff *skb, struct net_device *dev);
 271 static int              dfx_xmt_done(DFX_board_t *bp);
 272 static void             dfx_xmt_flush(DFX_board_t *bp);
 273
 274 /* Define module-wide (static) variables */
 275
 276 static struct net_device *root_dfx_eisa_dev;
 277
 278 \f
 279 /*
 280  * =======================
 281  * = dfx_port_write_byte =
 282  * = dfx_port_read_byte  =
 283  * = dfx_port_write_long =
 284  * = dfx_port_read_long  =
 285  * =======================
 286  *
 287  * Overview:
 288  *   Routines for reading and writing values from/to adapter
 289  *
 290  * Returns:
 291  *   None
 292  *
 293  * Arguments:
 294  *   bp     - pointer to board information
 295  *   offset - register offset from base I/O address
 296  *   data   - for dfx_port_write_byte and dfx_port_write_long, this
 297  *                        is a value to write.
 298  *                        for dfx_port_read_byte and dfx_port_read_byte, this
 299  *                        is a pointer to store the read value.
 300  *
 301  * Functional Description:
 302  *   These routines perform the correct operation to read or write
 303  *   the adapter register.
 304  *
 305  *   EISA port block base addresses are based on the slot number in which the
 306  *   controller is installed.  For example, if the EISA controller is installed
 307  *   in slot 4, the port block base address is 0x4000.  If the controller is
 308  *   installed in slot 2, the port block base address is 0x2000, and so on.
 309  *   This port block can be used to access PDQ, ESIC, and DEFEA on-board
 310  *   registers using the register offsets defined in DEFXX.H.
 311  *
 312  *   PCI port block base addresses are assigned by the PCI BIOS or system
 313  *       firmware.  There is one 128 byte port block which can be accessed.  It
 314  *   allows for I/O mapping of both PDQ and PFI registers using the register
 315  *   offsets defined in DEFXX.H.
 316  *
 317  * Return Codes:
 318  *   None
 319  *
 320  * Assumptions:
 321  *   bp->base_addr is a valid base I/O address for this adapter.
 322  *   offset is a valid register offset for this adapter.
 323  *
 324  * Side Effects:
 325  *   Rather than produce macros for these functions, these routines
 326  *   are defined using "inline" to ensure that the compiler will
 327  *   generate inline code and not waste a procedure call and return.
 328  *   This provides all the benefits of macros, but with the
 329  *   advantage of strict data type checking.
 330  */
 331
 332 static inline void dfx_port_write_byte(
 333         DFX_board_t     *bp,
 334         int                     offset,
 335         u8                      data
 336         )
 337
 338         {
 339         u16 port = bp->base_addr + offset;
 340
 341         outb(data, port);
 342         }
 343
 344 static inline void dfx_port_read_byte(
 345         DFX_board_t     *bp,
 346         int                     offset,
 347         u8                      *data
 348         )
 349
 350         {
 351         u16 port = bp->base_addr + offset;
 352
 353         *data = inb(port);
 354         }
 355
 356 static inline void dfx_port_write_long(
 357         DFX_board_t     *bp,
 358         int                     offset,
 359         u32                     data
 360         )
 361
 362         {
 363         u16 port = bp->base_addr + offset;
 364
 365         outl(data, port);
 366         }
 367
 368 static inline void dfx_port_read_long(
 369         DFX_board_t     *bp,
 370         int                     offset,
 371         u32                     *data
 372         )
 373
 374         {
 375         u16 port = bp->base_addr + offset;
 376
 377         *data = inl(port);
 378         }
 379
 380 \f
 381 /*
 382  * =============
 383  * = dfx_init_one_pci_or_eisa =
 384  * =============
 385  *
 386  * Overview:
 387  *   Initializes a supported FDDI EISA or PCI controller
 388  *
 389  * Returns:
 390  *   Condition code
 391  *
 392  * Arguments:
 393  *   pdev - pointer to pci device information (NULL for EISA)
 394  *   ioaddr - pointer to port (NULL for PCI)
 395  *
 396  * Functional Description:
 397  *
 398  * Return Codes:
 399  *   0           - This device (fddi0, fddi1, etc) configured successfully
 400  *   -EBUSY      - Failed to get resources, or dfx_driver_init failed.
 401  *
 402  * Assumptions:
 403  *   It compiles so it should work :-( (PCI cards do :-)
 404  *
 405  * Side Effects:
 406  *   Device structures for FDDI adapters (fddi0, fddi1, etc) are
 407  *   initialized and the board resources are read and stored in
 408  *   the device structure.
 409  */
 410 static int __devinit dfx_init_one_pci_or_eisa(struct pci_dev *pdev, long ioaddr)
 411 {
 412         static int version_disp;
 413         char *print_name = DRV_NAME;
 414         struct net_device *dev;
 415         DFX_board_t       *bp;                  /* board pointer */
 416         int alloc_size;                         /* total buffer size used */
 417         int err;
 418
 419         if (!version_disp) {    /* display version info if adapter is found */
 420                 version_disp = 1;       /* set display flag to TRUE so that */
 421                 printk(version);        /* we only display this string ONCE */
 422         }
 423
 424         if (pdev != NULL)
 425                 print_name = pci_name(pdev);
 426
 427         dev = alloc_fddidev(sizeof(*bp));
 428         if (!dev) {
 429                 printk(KERN_ERR "%s: unable to allocate fddidev, aborting\n",
 430                        print_name);
 431                 return -ENOMEM;
 432         }
 433
 434         /* Enable PCI device. */
 435         if (pdev != NULL) {
 436                 err = pci_enable_device (pdev);
 437                 if (err) goto err_out;
 438                 ioaddr = pci_resource_start (pdev, 1);
 439         }
 440
 441         SET_MODULE_OWNER(dev);
 442         if (pdev != NULL)
 443                 SET_NETDEV_DEV(dev, &pdev->dev);
 444
 445         bp = dev->priv;
 446
 447         if (!request_region(ioaddr,
 448                             pdev ? PFI_K_CSR_IO_LEN : PI_ESIC_K_CSR_IO_LEN,
 449                             print_name)) {
 450                 printk(KERN_ERR "%s: Cannot reserve I/O resource "
 451                        "0x%x @ 0x%lx, aborting\n", print_name,
 452                        pdev ? PFI_K_CSR_IO_LEN : PI_ESIC_K_CSR_IO_LEN, ioaddr);
 453                 err = -EBUSY;
 454                 goto err_out;
 455         }
 456
 457         /* Initialize new device structure */
 458
 459         dev->base_addr                  = ioaddr; /* save port (I/O) base address */
 460
 461         dev->get_stats                  = dfx_ctl_get_stats;
 462         dev->open                       = dfx_open;
 463         dev->stop                       = dfx_close;
 464         dev->hard_start_xmit            = dfx_xmt_queue_pkt;
 465         dev->set_multicast_list         = dfx_ctl_set_multicast_list;
 466         dev->set_mac_address            = dfx_ctl_set_mac_address;
 467
 468         if (pdev == NULL) {
 469                 /* EISA board */
 470                 bp->bus_type = DFX_BUS_TYPE_EISA;
 471                 bp->next = root_dfx_eisa_dev;
 472                 root_dfx_eisa_dev = dev;
 473         } else {
 474                 /* PCI board */
 475                 bp->bus_type = DFX_BUS_TYPE_PCI;
 476                 bp->pci_dev = pdev;
 477                 pci_set_drvdata (pdev, dev);
 478                 pci_set_master (pdev);
 479         }
 480
 481         if (dfx_driver_init(dev, print_name) != DFX_K_SUCCESS) {
 482                 err = -ENODEV;
 483                 goto err_out_region;
 484         }
 485
 486         err = register_netdev(dev);
 487         if (err)
 488                 goto err_out_kfree;
 489
 490         printk("%s: registered as %s\n", print_name, dev->name);
 491         return 0;
 492
 493 err_out_kfree:
 494         alloc_size = sizeof(PI_DESCR_BLOCK) +
 495                      PI_CMD_REQ_K_SIZE_MAX + PI_CMD_RSP_K_SIZE_MAX +
 496 #ifndef DYNAMIC_BUFFERS
 497                      (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX) +
 498 #endif
 499                      sizeof(PI_CONSUMER_BLOCK) +
 500                      (PI_ALIGN_K_DESC_BLK - 1);
 501         if (bp->kmalloced)
 502                 pci_free_consistent(pdev, alloc_size,
 503                                     bp->kmalloced, bp->kmalloced_dma);
 504 err_out_region:
 505         release_region(ioaddr, pdev ? PFI_K_CSR_IO_LEN : PI_ESIC_K_CSR_IO_LEN);
 506 err_out:
 507         free_netdev(dev);
 508         return err;
 509 }
 510
 511 static int __devinit dfx_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
 512 {
 513         return dfx_init_one_pci_or_eisa(pdev, 0);
 514 }
 515
 516 static int __init dfx_eisa_init(void)
 517 {
 518         int rc = -ENODEV;
 519         int i;                  /* used in for loops */
 520         u16 port;               /* temporary I/O (port) address */
 521         u32 slot_id;            /* EISA hardware (slot) ID read from adapter */
 522
 523         DBG_printk("In dfx_eisa_init...\n");
 524
 525         /* Scan for FDDI EISA controllers */
 526
 527         for (i=0; i < DFX_MAX_EISA_SLOTS; i++)          /* only scan for up to 16 EISA slots */
 528         {
 529                 port = (i << 12) + PI_ESIC_K_SLOT_ID;   /* port = I/O address for reading slot ID */
 530                 slot_id = inl(port);                                    /* read EISA HW (slot) ID */
 531                 if ((slot_id & 0xF0FFFFFF) == DEFEA_PRODUCT_ID)
 532                 {
 533                         port = (i << 12);                                       /* recalc base addr */
 534
 535                         if (dfx_init_one_pci_or_eisa(NULL, port) == 0) rc = 0;
 536                 }
 537         }
 538         return rc;
 539 }
 540 \f
 541 /*
 542  * ================
 543  * = dfx_bus_init =
 544  * ================
 545  *
 546  * Overview:
 547  *   Initializes EISA and PCI controller bus-specific logic.
 548  *
 549  * Returns:
 550  *   None
 551  *
 552  * Arguments:
 553  *   dev - pointer to device information
 554  *
 555  * Functional Description:
 556  *   Determine and save adapter IRQ in device table,
 557  *   then perform bus-specific logic initialization.
 558  *
 559  * Return Codes:
 560  *   None
 561  *
 562  * Assumptions:
 563  *   dev->base_addr has already been set with the proper
 564  *       base I/O address for this device.
 565  *
 566  * Side Effects:
 567  *   Interrupts are enabled at the adapter bus-specific logic.
 568  *   Note:  Interrupts at the DMA engine (PDQ chip) are not
 569  *   enabled yet.
 570  */
 571
 572 static void __devinit dfx_bus_init(struct net_device *dev)
 573 {
 574         DFX_board_t *bp = dev->priv;
 575         u8                      val;    /* used for I/O read/writes */
 576
 577         DBG_printk("In dfx_bus_init...\n");
 578
 579         /*
 580          * Initialize base I/O address field in bp structure
 581          *
 582          * Note: bp->base_addr is the same as dev->base_addr.
 583          *               It's useful because often we'll need to read
 584          *               or write registers where we already have the
 585          *               bp pointer instead of the dev pointer.  Having
 586          *               the base address in the bp structure will
 587          *               save a pointer dereference.
 588          *
 589          *               IMPORTANT!! This field must be defined before
 590          *               any of the dfx_port_* inline functions are
 591          *               called.
 592          */
 593
 594         bp->base_addr = dev->base_addr;
 595
 596         /* And a pointer back to the net_device struct */
 597         bp->dev = dev;
 598
 599         /* Initialize adapter based on bus type */
 600
 601         if (bp->bus_type == DFX_BUS_TYPE_EISA)
 602                 {
 603                 /* Get the interrupt level from the ESIC chip */
 604
 605                 dfx_port_read_byte(bp, PI_ESIC_K_IO_CONFIG_STAT_0, &val);
 606                 switch ((val & PI_CONFIG_STAT_0_M_IRQ) >> PI_CONFIG_STAT_0_V_IRQ)
 607                         {
 608                         case PI_CONFIG_STAT_0_IRQ_K_9:
 609                                 dev->irq = 9;
 610                                 break;
 611
 612                         case PI_CONFIG_STAT_0_IRQ_K_10:
 613                                 dev->irq = 10;
 614                                 break;
 615
 616                         case PI_CONFIG_STAT_0_IRQ_K_11:
 617                                 dev->irq = 11;
 618                                 break;
 619
 620                         case PI_CONFIG_STAT_0_IRQ_K_15:
 621                                 dev->irq = 15;
 622                                 break;
 623                         }
 624
 625                 /* Enable access to I/O on the board by writing 0x03 to Function Control Register */
 626
 627                 dfx_port_write_byte(bp, PI_ESIC_K_FUNCTION_CNTRL, PI_ESIC_K_FUNCTION_CNTRL_IO_ENB);
 628
 629                 /* Set the I/O decode range of the board */
 630
 631                 val = ((dev->base_addr >> 12) << PI_IO_CMP_V_SLOT);
 632                 dfx_port_write_byte(bp, PI_ESIC_K_IO_CMP_0_1, val);
 633                 dfx_port_write_byte(bp, PI_ESIC_K_IO_CMP_1_1, val);
 634
 635                 /* Enable access to rest of module (including PDQ and packet memory) */
 636
 637                 dfx_port_write_byte(bp, PI_ESIC_K_SLOT_CNTRL, PI_SLOT_CNTRL_M_ENB);
 638
 639                 /*
 640                  * Map PDQ registers into I/O space.  This is done by clearing a bit
 641                  * in Burst Holdoff register.
 642                  */
 643
 644                 dfx_port_read_byte(bp, PI_ESIC_K_BURST_HOLDOFF, &val);
 645                 dfx_port_write_byte(bp, PI_ESIC_K_BURST_HOLDOFF, (val & ~PI_BURST_HOLDOFF_M_MEM_MAP));
 646
 647                 /* Enable interrupts at EISA bus interface chip (ESIC) */
 648
 649                 dfx_port_read_byte(bp, PI_ESIC_K_IO_CONFIG_STAT_0, &val);
 650                 dfx_port_write_byte(bp, PI_ESIC_K_IO_CONFIG_STAT_0, (val | PI_CONFIG_STAT_0_M_INT_ENB));
 651                 }
 652         else
 653                 {
 654                 struct pci_dev *pdev = bp->pci_dev;
 655
 656                 /* Get the interrupt level from the PCI Configuration Table */
 657
 658                 dev->irq = pdev->irq;
 659
 660                 /* Check Latency Timer and set if less than minimal */
 661
 662                 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &val);
 663                 if (val < PFI_K_LAT_TIMER_MIN)  /* if less than min, override with default */
 664                         {
 665                         val = PFI_K_LAT_TIMER_DEF;
 666                         pci_write_config_byte(pdev, PCI_LATENCY_TIMER, val);
 667                         }
 668
 669                 /* Enable interrupts at PCI bus interface chip (PFI) */
 670
 671                 dfx_port_write_long(bp, PFI_K_REG_MODE_CTRL, (PFI_MODE_M_PDQ_INT_ENB | PFI_MODE_M_DMA_ENB));
 672                 }
 673         }
 674
 675 \f
 676 /*
 677  * ========================
 678  * = dfx_bus_config_check =
 679  * ========================
 680  *
 681  * Overview:
 682  *   Checks the configuration (burst size, full-duplex, etc.)  If any parameters
 683  *   are illegal, then this routine will set new defaults.
 684  *
 685  * Returns:
 686  *   None
 687  *
 688  * Arguments:
 689  *   bp - pointer to board information
 690  *
 691  * Functional Description:
 692  *   For Revision 1 FDDI EISA, Revision 2 or later FDDI EISA with rev E or later
 693  *   PDQ, and all FDDI PCI controllers, all values are legal.
 694  *
 695  * Return Codes:
 696  *   None
 697  *
 698  * Assumptions:
 699  *   dfx_adap_init has NOT been called yet so burst size and other items have
 700  *   not been set.
 701  *
 702  * Side Effects:
 703  *   None
 704  */
 705
 706 static void __devinit dfx_bus_config_check(DFX_board_t *bp)
 707 {
 708         int     status;                         /* return code from adapter port control call */
 709         u32     slot_id;                        /* EISA-bus hardware id (DEC3001, DEC3002,...) */
 710         u32     host_data;                      /* LW data returned from port control call */
 711
 712         DBG_printk("In dfx_bus_config_check...\n");
 713
 714         /* Configuration check only valid for EISA adapter */
 715
 716         if (bp->bus_type == DFX_BUS_TYPE_EISA)
 717                 {
 718                 dfx_port_read_long(bp, PI_ESIC_K_SLOT_ID, &slot_id);
 719
 720                 /*
 721                  * First check if revision 2 EISA controller.  Rev. 1 cards used
 722                  * PDQ revision B, so no workaround needed in this case.  Rev. 3
 723                  * cards used PDQ revision E, so no workaround needed in this
 724                  * case, either.  Only Rev. 2 cards used either Rev. D or E
 725                  * chips, so we must verify the chip revision on Rev. 2 cards.
 726                  */
 727
 728                 if (slot_id == DEFEA_PROD_ID_2)
 729                         {
 730                         /*
 731                          * Revision 2 FDDI EISA controller found, so let's check PDQ
 732                          * revision of adapter.
 733                          */
 734
 735                         status = dfx_hw_port_ctrl_req(bp,
 736                                                                                         PI_PCTRL_M_SUB_CMD,
 737                                                                                         PI_SUB_CMD_K_PDQ_REV_GET,
 738                                                                                         0,
 739                                                                                         &host_data);
 740                         if ((status != DFX_K_SUCCESS) || (host_data == 2))
 741                                 {
 742                                 /*
 743                                  * Either we couldn't determine the PDQ revision, or
 744                                  * we determined that it is at revision D.  In either case,
 745                                  * we need to implement the workaround.
 746                                  */
 747
 748                                 /* Ensure that the burst size is set to 8 longwords or less */
 749
 750                                 switch (bp->burst_size)
 751                                         {
 752                                         case PI_PDATA_B_DMA_BURST_SIZE_32:
 753                                         case PI_PDATA_B_DMA_BURST_SIZE_16:
 754                                                 bp->burst_size = PI_PDATA_B_DMA_BURST_SIZE_8;
 755                                                 break;
 756
 757                                         default:
 758                                                 break;
 759                                         }
 760
 761                                 /* Ensure that full-duplex mode is not enabled */
 762
 763                                 bp->full_duplex_enb = PI_SNMP_K_FALSE;
 764                                 }
 765                         }
 766                 }
 767         }
 768
 769 \f
 770 /*
 771  * ===================
 772  * = dfx_driver_init =
 773  * ===================
 774  *
 775  * Overview:
 776  *   Initializes remaining adapter board structure information
 777  *   and makes sure adapter is in a safe state prior to dfx_open().
 778  *
 779  * Returns:
 780  *   Condition code
 781  *
 782  * Arguments:
 783  *   dev - pointer to device information
 784  *   print_name - printable device name
 785  *
 786  * Functional Description:
 787  *   This function allocates additional resources such as the host memory
 788  *   blocks needed by the adapter (eg. descriptor and consumer blocks).
 789  *       Remaining bus initialization steps are also completed.  The adapter
 790  *   is also reset so that it is in the DMA_UNAVAILABLE state.  The OS
 791  *   must call dfx_open() to open the adapter and bring it on-line.
 792  *
 793  * Return Codes:
 794  *   DFX_K_SUCCESS      - initialization succeeded
 795  *   DFX_K_FAILURE      - initialization failed - could not allocate memory
 796  *                                              or read adapter MAC address
 797  *
 798  * Assumptions:
 799  *   Memory allocated from pci_alloc_consistent() call is physically
 800  *   contiguous, locked memory.
 801  *
 802  * Side Effects:
 803  *   Adapter is reset and should be in DMA_UNAVAILABLE state before
 804  *   returning from this routine.
 805  */
 806
 807 static int __devinit dfx_driver_init(struct net_device *dev,
 808                                      const char *print_name)
 809 {
 810         DFX_board_t *bp = dev->priv;
 811         int                     alloc_size;                     /* total buffer size needed */
 812         char            *top_v, *curr_v;        /* virtual addrs into memory block */
 813         dma_addr_t              top_p, curr_p;          /* physical addrs into memory block */
 814         u32                     data;                           /* host data register value */
 815
 816         DBG_printk("In dfx_driver_init...\n");
 817
 818         /* Initialize bus-specific hardware registers */
 819
 820         dfx_bus_init(dev);
 821
 822         /*
 823          * Initialize default values for configurable parameters
 824          *
 825          * Note: All of these parameters are ones that a user may
 826          *       want to customize.  It'd be nice to break these
 827          *               out into Space.c or someplace else that's more
 828          *               accessible/understandable than this file.
 829          */
 830
 831         bp->full_duplex_enb             = PI_SNMP_K_FALSE;
 832         bp->req_ttrt                    = 8 * 12500;            /* 8ms in 80 nanosec units */
 833         bp->burst_size                  = PI_PDATA_B_DMA_BURST_SIZE_DEF;
 834         bp->rcv_bufs_to_post    = RCV_BUFS_DEF;
 835
 836         /*
 837          * Ensure that HW configuration is OK
 838          *
 839          * Note: Depending on the hardware revision, we may need to modify
 840          *       some of the configurable parameters to workaround hardware
 841          *       limitations.  We'll perform this configuration check AFTER
 842          *       setting the parameters to their default values.
 843          */
 844
 845         dfx_bus_config_check(bp);
 846
 847         /* Disable PDQ interrupts first */
 848
 849         dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS);
 850
 851         /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */
 852
 853         (void) dfx_hw_dma_uninit(bp, PI_PDATA_A_RESET_M_SKIP_ST);
 854
 855         /*  Read the factory MAC address from the adapter then save it */
 856
 857         if (dfx_hw_port_ctrl_req(bp, PI_PCTRL_M_MLA, PI_PDATA_A_MLA_K_LO, 0,
 858                                  &data) != DFX_K_SUCCESS) {
 859                 printk("%s: Could not read adapter factory MAC address!\n",
 860                        print_name);
 861                 return(DFX_K_FAILURE);
 862         }
 863         memcpy(&bp->factory_mac_addr[0], &data, sizeof(u32));
 864
 865         if (dfx_hw_port_ctrl_req(bp, PI_PCTRL_M_MLA, PI_PDATA_A_MLA_K_HI, 0,
 866                                  &data) != DFX_K_SUCCESS) {
 867                 printk("%s: Could not read adapter factory MAC address!\n",
 868                        print_name);
 869                 return(DFX_K_FAILURE);
 870         }
 871         memcpy(&bp->factory_mac_addr[4], &data, sizeof(u16));
 872
 873         /*
 874          * Set current address to factory address
 875          *
 876          * Note: Node address override support is handled through
 877          *       dfx_ctl_set_mac_address.
 878          */
 879
 880         memcpy(dev->dev_addr, bp->factory_mac_addr, FDDI_K_ALEN);
 881         if (bp->bus_type == DFX_BUS_TYPE_EISA)
 882                 printk("%s: DEFEA at I/O addr = 0x%lX, IRQ = %d, "
 883                        "Hardware addr = %02X-%02X-%02X-%02X-%02X-%02X\n",
 884                        print_name, dev->base_addr, dev->irq,
 885                        dev->dev_addr[0], dev->dev_addr[1],
 886                        dev->dev_addr[2], dev->dev_addr[3],
 887                        dev->dev_addr[4], dev->dev_addr[5]);
 888         else
 889                 printk("%s: DEFPA at I/O addr = 0x%lX, IRQ = %d, "
 890                        "Hardware addr = %02X-%02X-%02X-%02X-%02X-%02X\n",
 891                        print_name, dev->base_addr, dev->irq,
 892                        dev->dev_addr[0], dev->dev_addr[1],
 893                        dev->dev_addr[2], dev->dev_addr[3],
 894                        dev->dev_addr[4], dev->dev_addr[5]);
 895
 896         /*
 897          * Get memory for descriptor block, consumer block, and other buffers
 898          * that need to be DMA read or written to by the adapter.
 899          */
 900
 901         alloc_size = sizeof(PI_DESCR_BLOCK) +
 902                                         PI_CMD_REQ_K_SIZE_MAX +
 903                                         PI_CMD_RSP_K_SIZE_MAX +
 904 #ifndef DYNAMIC_BUFFERS
 905                                         (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX) +
 906 #endif
 907                                         sizeof(PI_CONSUMER_BLOCK) +
 908                                         (PI_ALIGN_K_DESC_BLK - 1);
 909         bp->kmalloced = top_v = pci_alloc_consistent(bp->pci_dev, alloc_size,
 910                                                      &bp->kmalloced_dma);
 911         if (top_v == NULL) {
 912                 printk("%s: Could not allocate memory for host buffers "
 913                        "and structures!\n", print_name);
 914                 return(DFX_K_FAILURE);
 915         }
 916         memset(top_v, 0, alloc_size);   /* zero out memory before continuing */
 917         top_p = bp->kmalloced_dma;      /* get physical address of buffer */
 918
 919         /*
 920          *  To guarantee the 8K alignment required for the descriptor block, 8K - 1
 921          *  plus the amount of memory needed was allocated.  The physical address
 922          *      is now 8K aligned.  By carving up the memory in a specific order,
 923          *  we'll guarantee the alignment requirements for all other structures.
 924          *
 925          *  Note: If the assumptions change regarding the non-paged, non-cached,
 926          *                physically contiguous nature of the memory block or the address
 927          *                alignments, then we'll need to implement a different algorithm
 928          *                for allocating the needed memory.
 929          */
 930
 931         curr_p = ALIGN(top_p, PI_ALIGN_K_DESC_BLK);
 932         curr_v = top_v + (curr_p - top_p);
 933
 934         /* Reserve space for descriptor block */
 935
 936         bp->descr_block_virt = (PI_DESCR_BLOCK *) curr_v;
 937         bp->descr_block_phys = curr_p;
 938         curr_v += sizeof(PI_DESCR_BLOCK);
 939         curr_p += sizeof(PI_DESCR_BLOCK);
 940
 941         /* Reserve space for command request buffer */
 942
 943         bp->cmd_req_virt = (PI_DMA_CMD_REQ *) curr_v;
 944         bp->cmd_req_phys = curr_p;
 945         curr_v += PI_CMD_REQ_K_SIZE_MAX;
 946         curr_p += PI_CMD_REQ_K_SIZE_MAX;
 947
 948         /* Reserve space for command response buffer */
 949
 950         bp->cmd_rsp_virt = (PI_DMA_CMD_RSP *) curr_v;
 951         bp->cmd_rsp_phys = curr_p;
 952         curr_v += PI_CMD_RSP_K_SIZE_MAX;
 953         curr_p += PI_CMD_RSP_K_SIZE_MAX;
 954
 955         /* Reserve space for the LLC host receive queue buffers */
 956
 957         bp->rcv_block_virt = curr_v;
 958         bp->rcv_block_phys = curr_p;
 959
 960 #ifndef DYNAMIC_BUFFERS
 961         curr_v += (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX);
 962         curr_p += (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX);
 963 #endif
 964
 965         /* Reserve space for the consumer block */
 966
 967         bp->cons_block_virt = (PI_CONSUMER_BLOCK *) curr_v;
 968         bp->cons_block_phys = curr_p;
 969
 970         /* Display virtual and physical addresses if debug driver */
 971
 972         DBG_printk("%s: Descriptor block virt = %0lX, phys = %0X\n",
 973                    print_name,
 974                    (long)bp->descr_block_virt, bp->descr_block_phys);
 975         DBG_printk("%s: Command Request buffer virt = %0lX, phys = %0X\n",
 976                    print_name, (long)bp->cmd_req_virt, bp->cmd_req_phys);
 977         DBG_printk("%s: Command Response buffer virt = %0lX, phys = %0X\n",
 978                    print_name, (long)bp->cmd_rsp_virt, bp->cmd_rsp_phys);
 979         DBG_printk("%s: Receive buffer block virt = %0lX, phys = %0X\n",
 980                    print_name, (long)bp->rcv_block_virt, bp->rcv_block_phys);
 981         DBG_printk("%s: Consumer block virt = %0lX, phys = %0X\n",
 982                    print_name, (long)bp->cons_block_virt, bp->cons_block_phys);
 983
 984         return(DFX_K_SUCCESS);
 985 }
 986
 987 \f
 988 /*
 989  * =================
 990  * = dfx_adap_init =
 991  * =================
 992  *
 993  * Overview:
 994  *   Brings the adapter to the link avail/link unavailable state.
 995  *
 996  * Returns:
 997  *   Condition code
 998  *
 999  * Arguments:
1000  *   bp - pointer to board information
1001  *   get_buffers - non-zero if buffers to be allocated
1002  *
1003  * Functional Description:
1004  *   Issues the low-level firmware/hardware calls necessary to bring
1005  *   the adapter up, or to properly reset and restore adapter during
1006  *   run-time.
1007  *
1008  * Return Codes:
1009  *   DFX_K_SUCCESS - Adapter brought up successfully
1010  *   DFX_K_FAILURE - Adapter initialization failed
1011  *
1012  * Assumptions:
1013  *   bp->reset_type should be set to a valid reset type value before
1014  *   calling this routine.
1015  *
1016  * Side Effects:
1017  *   Adapter should be in LINK_AVAILABLE or LINK_UNAVAILABLE state
1018  *   upon a successful return of this routine.
1019  */
1020
1021 static int dfx_adap_init(DFX_board_t *bp, int get_buffers)
1022         {
1023         DBG_printk("In dfx_adap_init...\n");
1024
1025         /* Disable PDQ interrupts first */
1026
1027         dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS);
1028
1029         /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */
1030
1031         if (dfx_hw_dma_uninit(bp, bp->reset_type) != DFX_K_SUCCESS)
1032                 {
1033                 printk("%s: Could not uninitialize/reset adapter!\n", bp->dev->name);
1034                 return(DFX_K_FAILURE);
1035                 }
1036
1037         /*
1038          * When the PDQ is reset, some false Type 0 interrupts may be pending,
1039          * so we'll acknowledge all Type 0 interrupts now before continuing.
1040          */
1041
1042         dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_0_STATUS, PI_HOST_INT_K_ACK_ALL_TYPE_0);
1043
1044         /*
1045          * Clear Type 1 and Type 2 registers before going to DMA_AVAILABLE state
1046          *
1047          * Note: We only need to clear host copies of these registers.  The PDQ reset
1048          *       takes care of the on-board register values.
1049          */
1050
1051         bp->cmd_req_reg.lword   = 0;
1052         bp->cmd_rsp_reg.lword   = 0;
1053         bp->rcv_xmt_reg.lword   = 0;
1054
1055         /* Clear consumer block before going to DMA_AVAILABLE state */
1056
1057         memset(bp->cons_block_virt, 0, sizeof(PI_CONSUMER_BLOCK));
1058
1059         /* Initialize the DMA Burst Size */
1060
1061         if (dfx_hw_port_ctrl_req(bp,
1062                                                         PI_PCTRL_M_SUB_CMD,
1063                                                         PI_SUB_CMD_K_BURST_SIZE_SET,
1064                                                         bp->burst_size,
1065                                                         NULL) != DFX_K_SUCCESS)
1066                 {
1067                 printk("%s: Could not set adapter burst size!\n", bp->dev->name);
1068                 return(DFX_K_FAILURE);
1069                 }
1070
1071         /*
1072          * Set base address of Consumer Block
1073          *
1074          * Assumption: 32-bit physical address of consumer block is 64 byte
1075          *                         aligned.  That is, bits 0-5 of the address must be zero.
1076          */
1077
1078         if (dfx_hw_port_ctrl_req(bp,
1079                                                         PI_PCTRL_M_CONS_BLOCK,
1080                                                         bp->cons_block_phys,
1081                                                         0,
1082                                                         NULL) != DFX_K_SUCCESS)
1083                 {
1084                 printk("%s: Could not set consumer block address!\n", bp->dev->name);
1085                 return(DFX_K_FAILURE);
1086                 }
1087
1088         /*
1089          * Set base address of Descriptor Block and bring adapter to DMA_AVAILABLE state
1090          *
1091          * Note: We also set the literal and data swapping requirements in this
1092          *           command.  Since this driver presently runs on Intel platforms
1093          *               which are Little Endian, we'll tell the adapter to byte swap
1094          *               data only.  This code will need to change when we support
1095          *               Big Endian systems (eg. PowerPC).
1096          *
1097          * Assumption: 32-bit physical address of descriptor block is 8Kbyte
1098          *             aligned.  That is, bits 0-12 of the address must be zero.
1099          */
1100
1101         if (dfx_hw_port_ctrl_req(bp,
1102                                                         PI_PCTRL_M_INIT,
1103                                                         (u32) (bp->descr_block_phys | PI_PDATA_A_INIT_M_BSWAP_DATA),
1104                                                         0,
1105                                                         NULL) != DFX_K_SUCCESS)
1106                 {
1107                 printk("%s: Could not set descriptor block address!\n", bp->dev->name);
1108                 return(DFX_K_FAILURE);
1109                 }
1110
1111         /* Set transmit flush timeout value */
1112
1113         bp->cmd_req_virt->cmd_type = PI_CMD_K_CHARS_SET;
1114         bp->cmd_req_virt->char_set.item[0].item_code    = PI_ITEM_K_FLUSH_TIME;
1115         bp->cmd_req_virt->char_set.item[0].value                = 3;    /* 3 seconds */
1116         bp->cmd_req_virt->char_set.item[0].item_index   = 0;
1117         bp->cmd_req_virt->char_set.item[1].item_code    = PI_ITEM_K_EOL;
1118         if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS)
1119                 {
1120                 printk("%s: DMA command request failed!\n", bp->dev->name);
1121                 return(DFX_K_FAILURE);
1122                 }
1123
1124         /* Set the initial values for eFDXEnable and MACTReq MIB objects */
1125
1126         bp->cmd_req_virt->cmd_type = PI_CMD_K_SNMP_SET;
1127         bp->cmd_req_virt->snmp_set.item[0].item_code    = PI_ITEM_K_FDX_ENB_DIS;
1128         bp->cmd_req_virt->snmp_set.item[0].value                = bp->full_duplex_enb;
1129         bp->cmd_req_virt->snmp_set.item[0].item_index   = 0;
1130         bp->cmd_req_virt->snmp_set.item[1].item_code    = PI_ITEM_K_MAC_T_REQ;
1131         bp->cmd_req_virt->snmp_set.item[1].value                = bp->req_ttrt;
1132         bp->cmd_req_virt->snmp_set.item[1].item_index   = 0;
1133         bp->cmd_req_virt->snmp_set.item[2].item_code    = PI_ITEM_K_EOL;
1134         if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS)
1135                 {
1136                 printk("%s: DMA command request failed!\n", bp->dev->name);
1137                 return(DFX_K_FAILURE);
1138                 }
1139
1140         /* Initialize adapter CAM */
1141
1142         if (dfx_ctl_update_cam(bp) != DFX_K_SUCCESS)
1143                 {
1144                 printk("%s: Adapter CAM update failed!\n", bp->dev->name);
1145                 return(DFX_K_FAILURE);
1146                 }
1147
1148         /* Initialize adapter filters */
1149
1150         if (dfx_ctl_update_filters(bp) != DFX_K_SUCCESS)
1151                 {
1152                 printk("%s: Adapter filters update failed!\n", bp->dev->name);
1153                 return(DFX_K_FAILURE);
1154                 }
1155
1156         /*
1157          * Remove any existing dynamic buffers (i.e. if the adapter is being
1158          * reinitialized)
1159          */
1160
1161         if (get_buffers)
1162                 dfx_rcv_flush(bp);
1163
1164         /* Initialize receive descriptor block and produce buffers */
1165
1166         if (dfx_rcv_init(bp, get_buffers))
1167                 {
1168                 printk("%s: Receive buffer allocation failed\n", bp->dev->name);
1169                 if (get_buffers)
1170                         dfx_rcv_flush(bp);
1171                 return(DFX_K_FAILURE);
1172                 }
1173
1174         /* Issue START command and bring adapter to LINK_(UN)AVAILABLE state */
1175
1176         bp->cmd_req_virt->cmd_type = PI_CMD_K_START;
1177         if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS)
1178                 {
1179                 printk("%s: Start command failed\n", bp->dev->name);
1180                 if (get_buffers)
1181                         dfx_rcv_flush(bp);
1182                 return(DFX_K_FAILURE);
1183                 }
1184
1185         /* Initialization succeeded, reenable PDQ interrupts */
1186
1187         dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_ENABLE_DEF_INTS);
1188         return(DFX_K_SUCCESS);
1189         }
1190
1191 \f
1192 /*
1193  * ============
1194  * = dfx_open =
1195  * ============
1196  *
1197  * Overview:
1198  *   Opens the adapter
1199  *
1200  * Returns:
1201  *   Condition code
1202  *
1203  * Arguments:
1204  *   dev - pointer to device information
1205  *
1206  * Functional Description:
1207  *   This function brings the adapter to an operational state.
1208  *
1209  * Return Codes:
1210  *   0           - Adapter was successfully opened
1211  *   -EAGAIN - Could not register IRQ or adapter initialization failed
1212  *
1213  * Assumptions:
1214  *   This routine should only be called for a device that was
1215  *   initialized successfully.
1216  *
1217  * Side Effects:
1218  *   Adapter should be in LINK_AVAILABLE or LINK_UNAVAILABLE state
1219  *   if the open is successful.
1220  */
1221
1222 static int dfx_open(struct net_device *dev)
1223 {
1224         int ret;
1225         DFX_board_t     *bp = dev->priv;
1226
1227         DBG_printk("In dfx_open...\n");
1228
1229         /* Register IRQ - support shared interrupts by passing device ptr */
1230
1231         ret = request_irq(dev->irq, dfx_interrupt, SA_SHIRQ, dev->name, dev);
1232         if (ret) {
1233                 printk(KERN_ERR "%s: Requested IRQ %d is busy\n", dev->name, dev->irq);
1234                 return ret;
1235         }
1236
1237         /*
1238          * Set current address to factory MAC address
1239          *
1240          * Note: We've already done this step in dfx_driver_init.
1241          *       However, it's possible that a user has set a node
1242          *               address override, then closed and reopened the
1243          *               adapter.  Unless we reset the device address field
1244          *               now, we'll continue to use the existing modified
1245          *               address.
1246          */
1247
1248         memcpy(dev->dev_addr, bp->factory_mac_addr, FDDI_K_ALEN);
1249
1250         /* Clear local unicast/multicast address tables and counts */
1251
1252         memset(bp->uc_table, 0, sizeof(bp->uc_table));
1253         memset(bp->mc_table, 0, sizeof(bp->mc_table));
1254         bp->uc_count = 0;
1255         bp->mc_count = 0;
1256
1257         /* Disable promiscuous filter settings */
1258
1259         bp->ind_group_prom      = PI_FSTATE_K_BLOCK;
1260         bp->group_prom          = PI_FSTATE_K_BLOCK;
1261
1262         spin_lock_init(&bp->lock);
1263
1264         /* Reset and initialize adapter */
1265
1266         bp->reset_type = PI_PDATA_A_RESET_M_SKIP_ST;    /* skip self-test */
1267         if (dfx_adap_init(bp, 1) != DFX_K_SUCCESS)
1268         {
1269                 printk(KERN_ERR "%s: Adapter open failed!\n", dev->name);
1270                 free_irq(dev->irq, dev);
1271                 return -EAGAIN;
1272         }
1273
1274         /* Set device structure info */
1275         netif_start_queue(dev);
1276         return(0);
1277 }
1278
1279 \f
1280 /*
1281  * =============
1282  * = dfx_close =
1283  * =============
1284  *
1285  * Overview:
1286  *   Closes the device/module.
1287  *
1288  * Returns:
1289  *   Condition code
1290  *
1291  * Arguments:
1292  *   dev - pointer to device information
1293  *
1294  * Functional Description:
1295  *   This routine closes the adapter and brings it to a safe state.
1296  *   The interrupt service routine is deregistered with the OS.
1297  *   The adapter can be opened again with another call to dfx_open().
1298  *
1299  * Return Codes:
1300  *   Always return 0.
1301  *
1302  * Assumptions:
1303  *   No further requests for this adapter are made after this routine is
1304  *   called.  dfx_open() can be called to reset and reinitialize the
1305  *   adapter.
1306  *
1307  * Side Effects:
1308  *   Adapter should be in DMA_UNAVAILABLE state upon completion of this
1309  *   routine.
1310  */
1311
1312 static int dfx_close(struct net_device *dev)
1313 {
1314         DFX_board_t     *bp = dev->priv;
1315
1316         DBG_printk("In dfx_close...\n");
1317
1318         /* Disable PDQ interrupts first */
1319
1320         dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS);
1321
1322         /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */
1323
1324         (void) dfx_hw_dma_uninit(bp, PI_PDATA_A_RESET_M_SKIP_ST);
1325
1326         /*
1327          * Flush any pending transmit buffers
1328          *
1329          * Note: It's important that we flush the transmit buffers
1330          *               BEFORE we clear our copy of the Type 2 register.
1331          *               Otherwise, we'll have no idea how many buffers
1332          *               we need to free.
1333          */
1334
1335         dfx_xmt_flush(bp);
1336
1337         /*
1338          * Clear Type 1 and Type 2 registers after adapter reset
1339          *
1340          * Note: Even though we're closing the adapter, it's
1341          *       possible that an interrupt will occur after
1342          *               dfx_close is called.  Without some assurance to
1343          *               the contrary we want to make sure that we don't
1344          *               process receive and transmit LLC frames and update
1345          *               the Type 2 register with bad information.
1346          */
1347
1348         bp->cmd_req_reg.lword   = 0;
1349         bp->cmd_rsp_reg.lword   = 0;
1350         bp->rcv_xmt_reg.lword   = 0;
1351
1352         /* Clear consumer block for the same reason given above */
1353
1354         memset(bp->cons_block_virt, 0, sizeof(PI_CONSUMER_BLOCK));
1355
1356         /* Release all dynamically allocate skb in the receive ring. */
1357
1358         dfx_rcv_flush(bp);
1359
1360         /* Clear device structure flags */
1361
1362         netif_stop_queue(dev);
1363
1364         /* Deregister (free) IRQ */
1365
1366         free_irq(dev->irq, dev);
1367
1368         return(0);
1369 }
1370
1371 \f
1372 /*
1373  * ======================
1374  * = dfx_int_pr_halt_id =
1375  * ======================
1376  *
1377  * Overview:
1378  *   Displays halt id's in string form.
1379  *
1380  * Returns:
1381  *   None
1382  *
1383  * Arguments:
1384  *   bp - pointer to board information
1385  *
1386  * Functional Description:
1387  *   Determine current halt id and display appropriate string.
1388  *
1389  * Return Codes:
1390  *   None
1391  *
1392  * Assumptions:
1393  *   None
1394  *
1395  * Side Effects:
1396  *   None
1397  */
1398
1399 static void dfx_int_pr_halt_id(DFX_board_t      *bp)
1400         {
1401         PI_UINT32       port_status;                    /* PDQ port status register value */
1402         PI_UINT32       halt_id;                                /* PDQ port status halt ID */
1403
1404         /* Read the latest port status */
1405
1406         dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_STATUS, &port_status);
1407
1408         /* Display halt state transition information */
1409
1410         halt_id = (port_status & PI_PSTATUS_M_HALT_ID) >> PI_PSTATUS_V_HALT_ID;
1411         switch (halt_id)
1412                 {
1413                 case PI_HALT_ID_K_SELFTEST_TIMEOUT:
1414                         printk("%s: Halt ID: Selftest Timeout\n", bp->dev->name);
1415                         break;
1416
1417                 case PI_HALT_ID_K_PARITY_ERROR:
1418                         printk("%s: Halt ID: Host Bus Parity Error\n", bp->dev->name);
1419                         break;
1420
1421                 case PI_HALT_ID_K_HOST_DIR_HALT:
1422                         printk("%s: Halt ID: Host-Directed Halt\n", bp->dev->name);
1423                         break;
1424
1425                 case PI_HALT_ID_K_SW_FAULT:
1426                         printk("%s: Halt ID: Adapter Software Fault\n", bp->dev->name);
1427                         break;
1428
1429                 case PI_HALT_ID_K_HW_FAULT:
1430                         printk("%s: Halt ID: Adapter Hardware Fault\n", bp->dev->name);
1431                         break;
1432
1433                 case PI_HALT_ID_K_PC_TRACE:
1434                         printk("%s: Halt ID: FDDI Network PC Trace Path Test\n", bp->dev->name);
1435                         break;
1436
1437                 case PI_HALT_ID_K_DMA_ERROR:
1438                         printk("%s: Halt ID: Adapter DMA Error\n", bp->dev->name);
1439                         break;
1440
1441                 case PI_HALT_ID_K_IMAGE_CRC_ERROR:
1442                         printk("%s: Halt ID: Firmware Image CRC Error\n", bp->dev->name);
1443                         break;
1444
1445                 case PI_HALT_ID_K_BUS_EXCEPTION:
1446                         printk("%s: Halt ID: 68000 Bus Exception\n", bp->dev->name);
1447                         break;
1448
1449                 default:
1450                         printk("%s: Halt ID: Unknown (code = %X)\n", bp->dev->name, halt_id);
1451                         break;
1452                 }
1453         }
1454
1455 \f
1456 /*
1457  * ==========================
1458  * = dfx_int_type_0_process =
1459  * ==========================
1460  *
1461  * Overview:
1462  *   Processes Type 0 interrupts.
1463  *
1464  * Returns:
1465  *   None
1466  *
1467  * Arguments:
1468  *   bp - pointer to board information
1469  *
1470  * Functional Description:
1471  *   Processes all enabled Type 0 interrupts.  If the reason for the interrupt
1472  *   is a serious fault on the adapter, then an error message is displayed
1473  *   and the adapter is reset.
1474  *
1475  *   One tricky potential timing window is the rapid succession of "link avail"
1476  *   "link unavail" state change interrupts.  The acknowledgement of the Type 0
1477  *   interrupt must be done before reading the state from the Port Status
1478  *   register.  This is true because a state change could occur after reading
1479  *   the data, but before acknowledging the interrupt.  If this state change
1480  *   does happen, it would be lost because the driver is using the old state,
1481  *   and it will never know about the new state because it subsequently
1482  *   acknowledges the state change interrupt.
1483  *
1484  *          INCORRECT                                      CORRECT
1485  *      read type 0 int reasons                   read type 0 int reasons
1486  *      read adapter state                        ack type 0 interrupts
1487  *      ack type 0 interrupts                     read adapter state
1488  *      ... process interrupt ...                 ... process interrupt ...
1489  *
1490  * Return Codes:
1491  *   None
1492  *
1493  * Assumptions:
1494  *   None
1495  *
1496  * Side Effects:
1497  *   An adapter reset may occur if the adapter has any Type 0 error interrupts
1498  *   or if the port status indicates that the adapter is halted.  The driver
1499  *   is responsible for reinitializing the adapter with the current CAM
1500  *   contents and adapter filter settings.
1501  */
1502
1503 static void dfx_int_type_0_process(DFX_board_t  *bp)
1504
1505         {
1506         PI_UINT32       type_0_status;          /* Host Interrupt Type 0 register */
1507         PI_UINT32       state;                          /* current adap state (from port status) */
1508
1509         /*
1510          * Read host interrupt Type 0 register to determine which Type 0
1511          * interrupts are pending.  Immediately write it back out to clear
1512          * those interrupts.
1513          */
1514
1515         dfx_port_read_long(bp, PI_PDQ_K_REG_TYPE_0_STATUS, &type_0_status);
1516         dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_0_STATUS, type_0_status);
1517
1518         /* Check for Type 0 error interrupts */
1519
1520         if (type_0_status & (PI_TYPE_0_STAT_M_NXM |
1521                                                         PI_TYPE_0_STAT_M_PM_PAR_ERR |
1522                                                         PI_TYPE_0_STAT_M_BUS_PAR_ERR))
1523                 {
1524                 /* Check for Non-Existent Memory error */
1525
1526                 if (type_0_status & PI_TYPE_0_STAT_M_NXM)
1527                         printk("%s: Non-Existent Memory Access Error\n", bp->dev->name);
1528
1529                 /* Check for Packet Memory Parity error */
1530
1531                 if (type_0_status & PI_TYPE_0_STAT_M_PM_PAR_ERR)
1532                         printk("%s: Packet Memory Parity Error\n", bp->dev->name);
1533
1534                 /* Check for Host Bus Parity error */
1535
1536                 if (type_0_status & PI_TYPE_0_STAT_M_BUS_PAR_ERR)
1537                         printk("%s: Host Bus Parity Error\n", bp->dev->name);
1538
1539                 /* Reset adapter and bring it back on-line */
1540
1541                 bp->link_available = PI_K_FALSE;        /* link is no longer available */
1542                 bp->reset_type = 0;                                     /* rerun on-board diagnostics */
1543                 printk("%s: Resetting adapter...\n", bp->dev->name);
1544                 if (dfx_adap_init(bp, 0) != DFX_K_SUCCESS)
1545                         {
1546                         printk("%s: Adapter reset failed!  Disabling adapter interrupts.\n", bp->dev->name);
1547                         dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS);
1548                         return;
1549                         }
1550                 printk("%s: Adapter reset successful!\n", bp->dev->name);
1551                 return;
1552                 }
1553
1554         /* Check for transmit flush interrupt */
1555
1556         if (type_0_status & PI_TYPE_0_STAT_M_XMT_FLUSH)
1557                 {
1558                 /* Flush any pending xmt's and acknowledge the flush interrupt */
1559
1560                 bp->link_available = PI_K_FALSE;                /* link is no longer available */
1561                 dfx_xmt_flush(bp);                                              /* flush any outstanding packets */
1562                 (void) dfx_hw_port_ctrl_req(bp,
1563                                                                         PI_PCTRL_M_XMT_DATA_FLUSH_DONE,
1564                                                                         0,
1565                                                                         0,
1566                                                                         NULL);
1567                 }
1568
1569         /* Check for adapter state change */
1570
1571         if (type_0_status & PI_TYPE_0_STAT_M_STATE_CHANGE)
1572                 {
1573                 /* Get latest adapter state */
1574
1575                 state = dfx_hw_adap_state_rd(bp);       /* get adapter state */
1576                 if (state == PI_STATE_K_HALTED)
1577                         {
1578                         /*
1579                          * Adapter has transitioned to HALTED state, try to reset
1580                          * adapter to bring it back on-line.  If reset fails,
1581                          * leave the adapter in the broken state.
1582                          */
1583
1584                         printk("%s: Controller has transitioned to HALTED state!\n", bp->dev->name);
1585                         dfx_int_pr_halt_id(bp);                 /* display halt id as string */
1586
1587                         /* Reset adapter and bring it back on-line */
1588
1589                         bp->link_available = PI_K_FALSE;        /* link is no longer available */
1590                         bp->reset_type = 0;                                     /* rerun on-board diagnostics */
1591                         printk("%s: Resetting adapter...\n", bp->dev->name);
1592                         if (dfx_adap_init(bp, 0) != DFX_K_SUCCESS)
1593                                 {
1594                                 printk("%s: Adapter reset failed!  Disabling adapter interrupts.\n", bp->dev->name);
1595                                 dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS);
1596                                 return;
1597                                 }
1598                         printk("%s: Adapter reset successful!\n", bp->dev->name);
1599                         }
1600                 else if (state == PI_STATE_K_LINK_AVAIL)
1601                         {
1602                         bp->link_available = PI_K_TRUE;         /* set link available flag */
1603                         }
1604                 }
1605         }
1606
1607 \f
1608 /*
1609  * ==================
1610  * = dfx_int_common =
1611  * ==================
1612  *
1613  * Overview:
1614  *   Interrupt service routine (ISR)
1615  *
1616  * Returns:
1617  *   None
1618  *
1619  * Arguments:
1620  *   bp - pointer to board information
1621  *
1622  * Functional Description:
1623  *   This is the ISR which processes incoming adapter interrupts.
1624  *
1625  * Return Codes:
1626  *   None
1627  *
1628  * Assumptions:
1629  *   This routine assumes PDQ interrupts have not been disabled.
1630  *   When interrupts are disabled at the PDQ, the Port Status register
1631  *   is automatically cleared.  This routine uses the Port Status
1632  *   register value to determine whether a Type 0 interrupt occurred,
1633  *   so it's important that adapter interrupts are not normally
1634  *   enabled/disabled at the PDQ.
1635  *
1636  *   It's vital that this routine is NOT reentered for the
1637  *   same board and that the OS is not in another section of
1638  *   code (eg. dfx_xmt_queue_pkt) for the same board on a
1639  *   different thread.
1640  *
1641  * Side Effects:
1642  *   Pending interrupts are serviced.  Depending on the type of
1643  *   interrupt, acknowledging and clearing the interrupt at the
1644  *   PDQ involves writing a register to clear the interrupt bit
1645  *   or updating completion indices.
1646  */
1647
1648 static void dfx_int_common(struct net_device *dev)
1649 {
1650         DFX_board_t     *bp = dev->priv;
1651         PI_UINT32       port_status;            /* Port Status register */
1652
1653         /* Process xmt interrupts - frequent case, so always call this routine */
1654
1655         if(dfx_xmt_done(bp))                            /* free consumed xmt packets */
1656                 netif_wake_queue(dev);
1657
1658         /* Process rcv interrupts - frequent case, so always call this routine */
1659
1660         dfx_rcv_queue_process(bp);              /* service received LLC frames */
1661
1662         /*
1663          * Transmit and receive producer and completion indices are updated on the
1664          * adapter by writing to the Type 2 Producer register.  Since the frequent
1665          * case is that we'll be processing either LLC transmit or receive buffers,
1666          * we'll optimize I/O writes by doing a single register write here.
1667          */
1668
1669         dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_2_PROD, bp->rcv_xmt_reg.lword);
1670
1671         /* Read PDQ Port Status register to find out which interrupts need processing */
1672
1673         dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_STATUS, &port_status);
1674
1675         /* Process Type 0 interrupts (if any) - infrequent, so only call when needed */
1676
1677         if (port_status & PI_PSTATUS_M_TYPE_0_PENDING)
1678                 dfx_int_type_0_process(bp);     /* process Type 0 interrupts */
1679         }
1680
1681 \f
1682 /*
1683  * =================
1684  * = dfx_interrupt =
1685  * =================
1686  *
1687  * Overview:
1688  *   Interrupt processing routine
1689  *
1690  * Returns:
1691  *   Whether a valid interrupt was seen.
1692  *
1693  * Arguments:
1694  *   irq        - interrupt vector
1695  *   dev_id     - pointer to device information
1696  *       regs   - pointer to registers structure
1697  *
1698  * Functional Description:
1699  *   This routine calls the interrupt processing routine for this adapter.  It
1700  *   disables and reenables adapter interrupts, as appropriate.  We can support
1701  *   shared interrupts since the incoming dev_id pointer provides our device
1702  *   structure context.
1703  *
1704  * Return Codes:
1705  *   IRQ_HANDLED - an IRQ was handled.
1706  *   IRQ_NONE    - no IRQ was handled.
1707  *
1708  * Assumptions:
1709  *   The interrupt acknowledgement at the hardware level (eg. ACKing the PIC
1710  *   on Intel-based systems) is done by the operating system outside this
1711  *   routine.
1712  *
1713  *       System interrupts are enabled through this call.
1714  *
1715  * Side Effects:
1716  *   Interrupts are disabled, then reenabled at the adapter.
1717  */
1718
1719 static irqreturn_t dfx_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1720 {
1721         struct net_device       *dev = dev_id;
1722         DFX_board_t             *bp;    /* private board structure pointer */
1723
1724         /* Get board pointer only if device structure is valid */
1725
1726         bp = dev->priv;
1727
1728         /* See if we're already servicing an interrupt */
1729
1730         /* Service adapter interrupts */
1731
1732         if (bp->bus_type == DFX_BUS_TYPE_PCI) {
1733                 u32 status;
1734
1735                 dfx_port_read_long(bp, PFI_K_REG_STATUS, &status);
1736                 if (!(status & PFI_STATUS_M_PDQ_INT))
1737                         return IRQ_NONE;
1738
1739                 spin_lock(&bp->lock);
1740
1741                 /* Disable PDQ-PFI interrupts at PFI */
1742                 dfx_port_write_long(bp, PFI_K_REG_MODE_CTRL,
1743                                     PFI_MODE_M_DMA_ENB);
1744
1745                 /* Call interrupt service routine for this adapter */
1746                 dfx_int_common(dev);
1747
1748                 /* Clear PDQ interrupt status bit and reenable interrupts */
1749                 dfx_port_write_long(bp, PFI_K_REG_STATUS,
1750                                     PFI_STATUS_M_PDQ_INT);
1751                 dfx_port_write_long(bp, PFI_K_REG_MODE_CTRL,
1752                                     (PFI_MODE_M_PDQ_INT_ENB |
1753                                      PFI_MODE_M_DMA_ENB));
1754
1755                 spin_unlock(&bp->lock);
1756         } else {
1757                 u8 status;
1758
1759                 dfx_port_read_byte(bp, PI_ESIC_K_IO_CONFIG_STAT_0, &status);
1760                 if (!(status & PI_CONFIG_STAT_0_M_PEND))
1761                         return IRQ_NONE;
1762
1763                 spin_lock(&bp->lock);
1764
1765                 /* Disable interrupts at the ESIC */
1766                 status &= ~PI_CONFIG_STAT_0_M_INT_ENB;
1767                 dfx_port_write_byte(bp, PI_ESIC_K_IO_CONFIG_STAT_0, status);
1768
1769                 /* Call interrupt service routine for this adapter */
1770                 dfx_int_common(dev);
1771
1772                 /* Reenable interrupts at the ESIC */
1773                 dfx_port_read_byte(bp, PI_ESIC_K_IO_CONFIG_STAT_0, &status);
1774                 status |= PI_CONFIG_STAT_0_M_INT_ENB;
1775                 dfx_port_write_byte(bp, PI_ESIC_K_IO_CONFIG_STAT_0, status);
1776
1777                 spin_unlock(&bp->lock);
1778         }
1779
1780         return IRQ_HANDLED;
1781 }
1782
1783 \f
1784 /*
1785  * =====================
1786  * = dfx_ctl_get_stats =
1787  * =====================
1788  *
1789  * Overview:
1790  *   Get statistics for FDDI adapter
1791  *
1792  * Returns:
1793  *   Pointer to FDDI statistics structure
1794  *
1795  * Arguments:
1796  *   dev - pointer to device information
1797  *
1798  * Functional Description:
1799  *   Gets current MIB objects from adapter, then
1800  *   returns FDDI statistics structure as defined
1801  *   in if_fddi.h.
1802  *
1803  *   Note: Since the FDDI statistics structure is
1804  *   still new and the device structure doesn't
1805  *   have an FDDI-specific get statistics handler,
1806  *   we'll return the FDDI statistics structure as
1807  *   a pointer to an Ethernet statistics structure.
1808  *   That way, at least the first part of the statistics
1809  *   structure can be decoded properly, and it allows
1810  *   "smart" applications to perform a second cast to
1811  *   decode the FDDI-specific statistics.
1812  *
1813  *   We'll have to pay attention to this routine as the
1814  *   device structure becomes more mature and LAN media
1815  *   independent.
1816  *
1817  * Return Codes:
1818  *   None
1819  *
1820  * Assumptions:
1821  *   None
1822  *
1823  * Side Effects:
1824  *   None
1825  */
1826
1827 static struct net_device_stats *dfx_ctl_get_stats(struct net_device *dev)
1828         {
1829         DFX_board_t     *bp = dev->priv;
1830
1831         /* Fill the bp->stats structure with driver-maintained counters */
1832
1833         bp->stats.gen.rx_packets = bp->rcv_total_frames;
1834         bp->stats.gen.tx_packets = bp->xmt_total_frames;
1835         bp->stats.gen.rx_bytes   = bp->rcv_total_bytes;
1836         bp->stats.gen.tx_bytes   = bp->xmt_total_bytes;
1837         bp->stats.gen.rx_errors  = bp->rcv_crc_errors +
1838                                    bp->rcv_frame_status_errors +
1839                                    bp->rcv_length_errors;
1840         bp->stats.gen.tx_errors  = bp->xmt_length_errors;
1841         bp->stats.gen.rx_dropped = bp->rcv_discards;
1842         bp->stats.gen.tx_dropped = bp->xmt_discards;
1843         bp->stats.gen.multicast  = bp->rcv_multicast_frames;
1844         bp->stats.gen.collisions = 0;           /* always zero (0) for FDDI */
1845
1846         /* Get FDDI SMT MIB objects */
1847
1848         bp->cmd_req_virt->cmd_type = PI_CMD_K_SMT_MIB_GET;
1849         if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS)
1850                 return((struct net_device_stats *) &bp->stats);
1851
1852         /* Fill the bp->stats structure with the SMT MIB object values */
1853
1854         memcpy(bp->stats.smt_station_id, &bp->cmd_rsp_virt->smt_mib_get.smt_station_id, sizeof(bp->cmd_rsp_virt->smt_mib_get.smt_station_id));
1855         bp->stats.smt_op_version_id                                     = bp->cmd_rsp_virt->smt_mib_get.smt_op_version_id;
1856         bp->stats.smt_hi_version_id                                     = bp->cmd_rsp_virt->smt_mib_get.smt_hi_version_id;
1857         bp->stats.smt_lo_version_id                                     = bp->cmd_rsp_virt->smt_mib_get.smt_lo_version_id;
1858         memcpy(bp->stats.smt_user_data, &bp->cmd_rsp_virt->smt_mib_get.smt_user_data, sizeof(bp->cmd_rsp_virt->smt_mib_get.smt_user_data));
1859         bp->stats.smt_mib_version_id                            = bp->cmd_rsp_virt->smt_mib_get.smt_mib_version_id;
1860         bp->stats.smt_mac_cts                                           = bp->cmd_rsp_virt->smt_mib_get.smt_mac_ct;
1861         bp->stats.smt_non_master_cts                            = bp->cmd_rsp_virt->smt_mib_get.smt_non_master_ct;
1862         bp->stats.smt_master_cts                                        = bp->cmd_rsp_virt->smt_mib_get.smt_master_ct;
1863         bp->stats.smt_available_paths                           = bp->cmd_rsp_virt->smt_mib_get.smt_available_paths;
1864         bp->stats.smt_config_capabilities                       = bp->cmd_rsp_virt->smt_mib_get.smt_config_capabilities;
1865         bp->stats.smt_config_policy                                     = bp->cmd_rsp_virt->smt_mib_get.smt_config_policy;
1866         bp->stats.smt_connection_policy                         = bp->cmd_rsp_virt->smt_mib_get.smt_connection_policy;
1867         bp->stats.smt_t_notify                                          = bp->cmd_rsp_virt->smt_mib_get.smt_t_notify;
1868         bp->stats.smt_stat_rpt_policy                           = bp->cmd_rsp_virt->smt_mib_get.smt_stat_rpt_policy;
1869         bp->stats.smt_trace_max_expiration                      = bp->cmd_rsp_virt->smt_mib_get.smt_trace_max_expiration;
1870         bp->stats.smt_bypass_present                            = bp->cmd_rsp_virt->smt_mib_get.smt_bypass_present;
1871         bp->stats.smt_ecm_state                                         = bp->cmd_rsp_virt->smt_mib_get.smt_ecm_state;
1872         bp->stats.smt_cf_state                                          = bp->cmd_rsp_virt->smt_mib_get.smt_cf_state;
1873         bp->stats.smt_remote_disconnect_flag            = bp->cmd_rsp_virt->smt_mib_get.smt_remote_disconnect_flag;
1874         bp->stats.smt_station_status                            = bp->cmd_rsp_virt->smt_mib_get.smt_station_status;
1875         bp->stats.smt_peer_wrap_flag                            = bp->cmd_rsp_virt->smt_mib_get.smt_peer_wrap_flag;
1876         bp->stats.smt_time_stamp                                        = bp->cmd_rsp_virt->smt_mib_get.smt_msg_time_stamp.ls;
1877         bp->stats.smt_transition_time_stamp                     = bp->cmd_rsp_virt->smt_mib_get.smt_transition_time_stamp.ls;
1878         bp->stats.mac_frame_status_functions            = bp->cmd_rsp_virt->smt_mib_get.mac_frame_status_functions;
1879         bp->stats.mac_t_max_capability                          = bp->cmd_rsp_virt->smt_mib_get.mac_t_max_capability;
1880         bp->stats.mac_tvx_capability                            = bp->cmd_rsp_virt->smt_mib_get.mac_tvx_capability;
1881         bp->stats.mac_available_paths                           = bp->cmd_rsp_virt->smt_mib_get.mac_available_paths;
1882         bp->stats.mac_current_path                                      = bp->cmd_rsp_virt->smt_mib_get.mac_current_path;
1883         memcpy(bp->stats.mac_upstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_upstream_nbr, FDDI_K_ALEN);
1884         memcpy(bp->stats.mac_downstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_downstream_nbr, FDDI_K_ALEN);
1885         memcpy(bp->stats.mac_old_upstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_old_upstream_nbr, FDDI_K_ALEN);
1886         memcpy(bp->stats.mac_old_downstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_old_downstream_nbr, FDDI_K_ALEN);
1887         bp->stats.mac_dup_address_test                          = bp->cmd_rsp_virt->smt_mib_get.mac_dup_address_test;
1888         bp->stats.mac_requested_paths                           = bp->cmd_rsp_virt->smt_mib_get.mac_requested_paths;
1889         bp->stats.mac_downstream_port_type                      = bp->cmd_rsp_virt->smt_mib_get.mac_downstream_port_type;
1890         memcpy(bp->stats.mac_smt_address, &bp->cmd_rsp_virt->smt_mib_get.mac_smt_address, FDDI_K_ALEN);
1891         bp->stats.mac_t_req                                                     = bp->cmd_rsp_virt->smt_mib_get.mac_t_req;
1892         bp->stats.mac_t_neg                                                     = bp->cmd_rsp_virt->smt_mib_get.mac_t_neg;
1893         bp->stats.mac_t_max                                                     = bp->cmd_rsp_virt->smt_mib_get.mac_t_max;
1894         bp->stats.mac_tvx_value                                         = bp->cmd_rsp_virt->smt_mib_get.mac_tvx_value;
1895         bp->stats.mac_frame_error_threshold                     = bp->cmd_rsp_virt->smt_mib_get.mac_frame_error_threshold;
1896         bp->stats.mac_frame_error_ratio                         = bp->cmd_rsp_virt->smt_mib_get.mac_frame_error_ratio;
1897         bp->stats.mac_rmt_state                                         = bp->cmd_rsp_virt->smt_mib_get.mac_rmt_state;
1898         bp->stats.mac_da_flag                                           = bp->cmd_rsp_virt->smt_mib_get.mac_da_flag;
1899         bp->stats.mac_una_da_flag                                       = bp->cmd_rsp_virt->smt_mib_get.mac_unda_flag;
1900         bp->stats.mac_frame_error_flag                          = bp->cmd_rsp_virt->smt_mib_get.mac_frame_error_flag;
1901         bp->stats.mac_ma_unitdata_available                     = bp->cmd_rsp_virt->smt_mib_get.mac_ma_unitdata_available;
1902         bp->stats.mac_hardware_present                          = bp->cmd_rsp_virt->smt_mib_get.mac_hardware_present;
1903         bp->stats.mac_ma_unitdata_enable                        = bp->cmd_rsp_virt->smt_mib_get.mac_ma_unitdata_enable;
1904         bp->stats.path_tvx_lower_bound                          = bp->cmd_rsp_virt->smt_mib_get.path_tvx_lower_bound;
1905         bp->stats.path_t_max_lower_bound                        = bp->cmd_rsp_virt->smt_mib_get.path_t_max_lower_bound;
1906         bp->stats.path_max_t_req                                        = bp->cmd_rsp_virt->smt_mib_get.path_max_t_req;
1907         memcpy(bp->stats.path_configuration, &bp->cmd_rsp_virt->smt_mib_get.path_configuration, sizeof(bp->cmd_rsp_virt->smt_mib_get.path_configuration));
1908         bp->stats.port_my_type[0]                                       = bp->cmd_rsp_virt->smt_mib_get.port_my_type[0];
1909         bp->stats.port_my_type[1]                                       = bp->cmd_rsp_virt->smt_mib_get.port_my_type[1];
1910         bp->stats.port_neighbor_type[0]                         = bp->cmd_rsp_virt->smt_mib_get.port_neighbor_type[0];
1911         bp->stats.port_neighbor_type[1]                         = bp->cmd_rsp_virt->smt_mib_get.port_neighbor_type[1];
1912         bp->stats.port_connection_policies[0]           = bp->cmd_rsp_virt->smt_mib_get.port_connection_policies[0];
1913         bp->stats.port_connection_policies[1]           = bp->cmd_rsp_virt->smt_mib_get.port_connection_policies[1];
1914         bp->stats.port_mac_indicated[0]                         = bp->cmd_rsp_virt->smt_mib_get.port_mac_indicated[0];
1915         bp->stats.port_mac_indicated[1]                         = bp->cmd_rsp_virt->smt_mib_get.port_mac_indicated[1];
1916         bp->stats.port_current_path[0]                          = bp->cmd_rsp_virt->smt_mib_get.port_current_path[0];
1917         bp->stats.port_current_path[1]                          = bp->cmd_rsp_virt->smt_mib_get.port_current_path[1];
1918         memcpy(&bp->stats.port_requested_paths[0*3], &bp->cmd_rsp_virt->smt_mib_get.port_requested_paths[0], 3);
1919         memcpy(&bp->stats.port_requested_paths[1*3], &bp->cmd_rsp_virt->smt_mib_get.port_requested_paths[1], 3);
1920         bp->stats.port_mac_placement[0]                         = bp->cmd_rsp_virt->smt_mib_get.port_mac_placement[0];
1921         bp->stats.port_mac_placement[1]                         = bp->cmd_rsp_virt->smt_mib_get.port_mac_placement[1];
1922         bp->stats.port_available_paths[0]                       = bp->cmd_rsp_virt->smt_mib_get.port_available_paths[0];
1923         bp->stats.port_available_paths[1]                       = bp->cmd_rsp_virt->smt_mib_get.port_available_paths[1];
1924         bp->stats.port_pmd_class[0]                                     = bp->cmd_rsp_virt->smt_mib_get.port_pmd_class[0];
1925         bp->stats.port_pmd_class[1]                                     = bp->cmd_rsp_virt->smt_mib_get.port_pmd_class[1];
1926         bp->stats.port_connection_capabilities[0]       = bp->cmd_rsp_virt->smt_mib_get.port_connection_capabilities[0];
1927         bp->stats.port_connection_capabilities[1]       = bp->cmd_rsp_virt->smt_mib_get.port_connection_capabilities[1];
1928         bp->stats.port_bs_flag[0]                                       = bp->cmd_rsp_virt->smt_mib_get.port_bs_flag[0];
1929         bp->stats.port_bs_flag[1]                                       = bp->cmd_rsp_virt->smt_mib_get.port_bs_flag[1];
1930         bp->stats.port_ler_estimate[0]                          = bp->cmd_rsp_virt->smt_mib_get.port_ler_estimate[0];
1931         bp->stats.port_ler_estimate[1]                          = bp->cmd_rsp_virt->smt_mib_get.port_ler_estimate[1];
1932         bp->stats.port_ler_cutoff[0]                            = bp->cmd_rsp_virt->smt_mib_get.port_ler_cutoff[0];
1933         bp->stats.port_ler_cutoff[1]                            = bp->cmd_rsp_virt->smt_mib_get.port_ler_cutoff[1];
1934         bp->stats.port_ler_alarm[0]                                     = bp->cmd_rsp_virt->smt_mib_get.port_ler_alarm[0];
1935         bp->stats.port_ler_alarm[1]                                     = bp->cmd_rsp_virt->smt_mib_get.port_ler_alarm[1];
1936         bp->stats.port_connect_state[0]                         = bp->cmd_rsp_virt->smt_mib_get.port_connect_state[0];
1937         bp->stats.port_connect_state[1]                         = bp->cmd_rsp_virt->smt_mib_get.port_connect_state[1];
1938         bp->stats.port_pcm_state[0]                                     = bp->cmd_rsp_virt->smt_mib_get.port_pcm_state[0];
1939         bp->stats.port_pcm_state[1]                                     = bp->cmd_rsp_virt->smt_mib_get.port_pcm_state[1];
1940         bp->stats.port_pc_withhold[0]                           = bp->cmd_rsp_virt->smt_mib_get.port_pc_withhold[0];
1941         bp->stats.port_pc_withhold[1]                           = bp->cmd_rsp_virt->smt_mib_get.port_pc_withhold[1];
1942         bp->stats.port_ler_flag[0]                                      = bp->cmd_rsp_virt->smt_mib_get.port_ler_flag[0];
1943         bp->stats.port_ler_flag[1]                                      = bp->cmd_rsp_virt->smt_mib_get.port_ler_flag[1];
1944         bp->stats.port_hardware_present[0]                      = bp->cmd_rsp_virt->smt_mib_get.port_hardware_present[0];
1945         bp->stats.port_hardware_present[1]                      = bp->cmd_rsp_virt->smt_mib_get.port_hardware_present[1];
1946
1947         /* Get FDDI counters */
1948
1949         bp->cmd_req_virt->cmd_type = PI_CMD_K_CNTRS_GET;
1950         if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS)
1951                 return((struct net_device_stats *) &bp->stats);
1952
1953         /* Fill the bp->stats structure with the FDDI counter values */
1954
1955         bp->stats.mac_frame_cts                         = bp->cmd_rsp_virt->cntrs_get.cntrs.frame_cnt.ls;
1956         bp->stats.mac_copied_cts                        = bp->cmd_rsp_virt->cntrs_get.cntrs.copied_cnt.ls;
1957         bp->stats.mac_transmit_cts                      = bp->cmd_rsp_virt->cntrs_get.cntrs.transmit_cnt.ls;
1958         bp->stats.mac_error_cts                         = bp->cmd_rsp_virt->cntrs_get.cntrs.error_cnt.ls;
1959         bp->stats.mac_lost_cts                          = bp->cmd_rsp_virt->cntrs_get.cntrs.lost_cnt.ls;
1960         bp->stats.port_lct_fail_cts[0]          = bp->cmd_rsp_virt->cntrs_get.cntrs.lct_rejects[0].ls;
1961         bp->stats.port_lct_fail_cts[1]          = bp->cmd_rsp_virt->cntrs_get.cntrs.lct_rejects[1].ls;
1962         bp->stats.port_lem_reject_cts[0]        = bp->cmd_rsp_virt->cntrs_get.cntrs.lem_rejects[0].ls;
1963         bp->stats.port_lem_reject_cts[1]        = bp->cmd_rsp_virt->cntrs_get.cntrs.lem_rejects[1].ls;
1964         bp->stats.port_lem_cts[0]                       = bp->cmd_rsp_virt->cntrs_get.cntrs.link_errors[0].ls;
1965         bp->stats.port_lem_cts[1]                       = bp->cmd_rsp_virt->cntrs_get.cntrs.link_errors[1].ls;
1966
1967         return((struct net_device_stats *) &bp->stats);
1968         }
1969
1970 \f
1971 /*
1972  * ==============================
1973  * = dfx_ctl_set_multicast_list =
1974  * ==============================
1975  *
1976  * Overview:
1977  *   Enable/Disable LLC frame promiscuous mode reception
1978  *   on the adapter and/or update multicast address table.
1979  *
1980  * Returns:
1981  *   None
1982  *
1983  * Arguments:
1984  *   dev - pointer to device information
1985  *
1986  * Functional Description:
1987  *   This routine follows a fairly simple algorithm for setting the
1988  *   adapter filters and CAM:
1989  *
1990  *              if IFF_PROMISC flag is set
1991  *                      enable LLC individual/group promiscuous mode
1992  *              else
1993  *                      disable LLC individual/group promiscuous mode
1994  *                      if number of incoming multicast addresses >
1995  *                                      (CAM max size - number of unicast addresses in CAM)
1996  *                              enable LLC group promiscuous mode
1997  *                              set driver-maintained multicast address count to zero
1998  *                      else
1999  *                              disable LLC group promiscuous mode
2000  *                              set driver-maintained multicast address count to incoming count
2001  *                      update adapter CAM
2002  *              update adapter filters
2003  *
2004  * Return Codes:
2005  *   None
2006  *
2007  * Assumptions:
2008  *   Multicast addresses are presented in canonical (LSB) format.
2009  *
2010  * Side Effects:
2011  *   On-board adapter CAM and filters are updated.
2012  */
2013
2014 static void dfx_ctl_set_multicast_list(struct net_device *dev)
2015         {
2016         DFX_board_t                     *bp = dev->priv;
2017         int                                     i;                      /* used as index in for loop */
2018         struct dev_mc_list      *dmi;           /* ptr to multicast addr entry */
2019
2020         /* Enable LLC frame promiscuous mode, if necessary */
2021
2022         if (dev->flags & IFF_PROMISC)
2023                 bp->ind_group_prom = PI_FSTATE_K_PASS;          /* Enable LLC ind/group prom mode */
2024
2025         /* Else, update multicast address table */
2026
2027         else
2028                 {
2029                 bp->ind_group_prom = PI_FSTATE_K_BLOCK;         /* Disable LLC ind/group prom mode */
2030                 /*
2031                  * Check whether incoming multicast address count exceeds table size
2032                  *
2033                  * Note: The adapters utilize an on-board 64 entry CAM for
2034                  *       supporting perfect filtering of multicast packets
2035                  *               and bridge functions when adding unicast addresses.
2036                  *               There is no hash function available.  To support
2037                  *               additional multicast addresses, the all multicast
2038                  *               filter (LLC group promiscuous mode) must be enabled.
2039                  *
2040                  *               The firmware reserves two CAM entries for SMT-related
2041                  *               multicast addresses, which leaves 62 entries available.
2042                  *               The following code ensures that we're not being asked
2043                  *               to add more than 62 addresses to the CAM.  If we are,
2044                  *               the driver will enable the all multicast filter.
2045                  *               Should the number of multicast addresses drop below
2046                  *               the high water mark, the filter will be disabled and
2047                  *               perfect filtering will be used.
2048                  */
2049
2050                 if (dev->mc_count > (PI_CMD_ADDR_FILTER_K_SIZE - bp->uc_count))
2051                         {
2052                         bp->group_prom  = PI_FSTATE_K_PASS;             /* Enable LLC group prom mode */
2053                         bp->mc_count    = 0;                                    /* Don't add mc addrs to CAM */
2054                         }
2055                 else
2056                         {
2057                         bp->group_prom  = PI_FSTATE_K_BLOCK;    /* Disable LLC group prom mode */
2058                         bp->mc_count    = dev->mc_count;                /* Add mc addrs to CAM */
2059                         }
2060
2061                 /* Copy addresses to multicast address table, then update adapter CAM */
2062
2063                 dmi = dev->mc_list;                             /* point to first multicast addr */
2064                 for (i=0; i < bp->mc_count; i++)
2065                         {
2066                         memcpy(&bp->mc_table[i*FDDI_K_ALEN], dmi->dmi_addr, FDDI_K_ALEN);
2067                         dmi = dmi->next;                        /* point to next multicast addr */
2068                         }
2069                 if (dfx_ctl_update_cam(bp) != DFX_K_SUCCESS)
2070                         {
2071                         DBG_printk("%s: Could not update multicast address table!\n", dev->name);
2072                         }
2073                 else
2074                         {
2075                         DBG_printk("%s: Multicast address table updated!  Added %d addresses.\n", dev->name, bp->mc_count);
2076                         }
2077                 }
2078
2079         /* Update adapter filters */
2080
2081         if (dfx_ctl_update_filters(bp) != DFX_K_SUCCESS)
2082                 {
2083                 DBG_printk("%s: Could not update adapter filters!\n", dev->name);
2084                 }
2085         else
2086                 {
2087                 DBG_printk("%s: Adapter filters updated!\n", dev->name);
2088                 }
2089         }
2090
2091 \f
2092 /*
2093  * ===========================
2094  * = dfx_ctl_set_mac_address =
2095  * ===========================
2096  *
2097  * Overview:
2098  *   Add node address override (unicast address) to adapter
2099  *   CAM and update dev_addr field in device table.
2100  *
2101  * Returns:
2102  *   None
2103  *
2104  * Arguments:
2105  *   dev  - pointer to device information
2106  *   addr - pointer to sockaddr structure containing unicast address to add
2107  *
2108  * Functional Description:
2109  *   The adapter supports node address overrides by adding one or more
2110  *   unicast addresses to the adapter CAM.  This is similar to adding
2111  *   multicast addresses.  In this routine we'll update the driver and
2112  *   device structures with the new address, then update the adapter CAM
2113  *   to ensure that the adapter will copy and strip frames destined and
2114  *   sourced by that address.
2115  *
2116  * Return Codes:
2117  *   Always returns zero.
2118  *
2119  * Assumptions:
2120  *   The address pointed to by addr->sa_data is a valid unicast
2121  *   address and is presented in canonical (LSB) format.
2122  *
2123  * Side Effects:
2124  *   On-board adapter CAM is updated.  On-board adapter filters
2125  *   may be updated.
2126  */
2127
2128 static int dfx_ctl_set_mac_address(struct net_device *dev, void *addr)
2129         {
2130         DFX_board_t             *bp = dev->priv;
2131         struct sockaddr *p_sockaddr = (struct sockaddr *)addr;
2132
2133         /* Copy unicast address to driver-maintained structs and update count */
2134
2135         memcpy(dev->dev_addr, p_sockaddr->sa_data, FDDI_K_ALEN);        /* update device struct */
2136         memcpy(&bp->uc_table[0], p_sockaddr->sa_data, FDDI_K_ALEN);     /* update driver struct */
2137         bp->uc_count = 1;
2138
2139         /*
2140          * Verify we're not exceeding the CAM size by adding unicast address
2141          *
2142          * Note: It's possible that before entering this routine we've
2143          *       already filled the CAM with 62 multicast addresses.
2144          *               Since we need to place the node address override into
2145          *               the CAM, we have to check to see that we're not
2146          *               exceeding the CAM size.  If we are, we have to enable
2147          *               the LLC group (multicast) promiscuous mode filter as
2148          *               in dfx_ctl_set_multicast_list.
2149          */
2150
2151         if ((bp->uc_count + bp->mc_count) > PI_CMD_ADDR_FILTER_K_SIZE)
2152                 {
2153                 bp->group_prom  = PI_FSTATE_K_PASS;             /* Enable LLC group prom mode */
2154                 bp->mc_count    = 0;                                    /* Don't add mc addrs to CAM */
2155
2156                 /* Update adapter filters */
2157
2158                 if (dfx_ctl_update_filters(bp) != DFX_K_SUCCESS)
2159                         {
2160                         DBG_printk("%s: Could not update adapter filters!\n", dev->name);
2161                         }
2162                 else
2163                         {
2164                         DBG_printk("%s: Adapter filters updated!\n", dev->name);
2165                         }
2166                 }
2167
2168         /* Update adapter CAM with new unicast address */
2169
2170         if (dfx_ctl_update_cam(bp) != DFX_K_SUCCESS)
2171                 {
2172                 DBG_printk("%s: Could not set new MAC address!\n", dev->name);
2173                 }
2174         else
2175                 {
2176                 DBG_printk("%s: Adapter CAM updated with new MAC address\n", dev->name);
2177                 }
2178         return(0);                      /* always return zero */
2179         }
2180
2181 \f
2182 /*
2183  * ======================
2184  * = dfx_ctl_update_cam =
2185  * ======================
2186  *
2187  * Overview:
2188  *   Procedure to update adapter CAM (Content Addressable Memory)
2189  *   with desired unicast and multicast address entries.
2190  *
2191  * Returns:
2192  *   Condition code
2193  *
2194  * Arguments:
2195  *   bp - pointer to board information
2196  *
2197  * Functional Description:
2198  *   Updates adapter CAM with current contents of board structure
2199  *   unicast and multicast address tables.  Since there are only 62
2200  *   free entries in CAM, this routine ensures that the command
2201  *   request buffer is not overrun.
2202  *
2203  * Return Codes:
2204  *   DFX_K_SUCCESS - Request succeeded
2205  *   DFX_K_FAILURE - Request failed
2206  *
2207  * Assumptions:
2208  *   All addresses being added (unicast and multicast) are in canonical
2209  *   order.
2210  *
2211  * Side Effects:
2212  *   On-board adapter CAM is updated.
2213  */
2214
2215 static int dfx_ctl_update_cam(DFX_board_t *bp)
2216         {
2217         int                     i;                              /* used as index */
2218         PI_LAN_ADDR     *p_addr;                /* pointer to CAM entry */
2219
2220         /*
2221          * Fill in command request information
2222          *
2223          * Note: Even though both the unicast and multicast address
2224          *       table entries are stored as contiguous 6 byte entries,
2225          *               the firmware address filter set command expects each
2226          *               entry to be two longwords (8 bytes total).  We must be
2227          *               careful to only copy the six bytes of each unicast and
2228          *               multicast table entry into each command entry.  This
2229          *               is also why we must first clear the entire command
2230          *               request buffer.
2231          */
2232
2233         memset(bp->cmd_req_virt, 0, PI_CMD_REQ_K_SIZE_MAX);     /* first clear buffer */
2234         bp->cmd_req_virt->cmd_type = PI_CMD_K_ADDR_FILTER_SET;
2235         p_addr = &bp->cmd_req_virt->addr_filter_set.entry[0];
2236
2237         /* Now add unicast addresses to command request buffer, if any */
2238
2239         for (i=0; i < (int)bp->uc_count; i++)
2240                 {
2241                 if (i < PI_CMD_ADDR_FILTER_K_SIZE)
2242                         {
2243                         memcpy(p_addr, &bp->uc_table[i*FDDI_K_ALEN], FDDI_K_ALEN);
2244                         p_addr++;                       /* point to next command entry */
2245                         }
2246                 }
2247
2248         /* Now add multicast addresses to command request buffer, if any */
2249
2250         for (i=0; i < (int)bp->mc_count; i++)
2251                 {
2252                 if ((i + bp->uc_count) < PI_CMD_ADDR_FILTER_K_SIZE)
2253                         {
2254                         memcpy(p_addr, &bp->mc_table[i*FDDI_K_ALEN], FDDI_K_ALEN);
2255                         p_addr++;                       /* point to next command entry */
2256                         }
2257                 }
2258
2259         /* Issue command to update adapter CAM, then return */
2260
2261         if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS)
2262                 return(DFX_K_FAILURE);
2263         return(DFX_K_SUCCESS);
2264         }
2265
2266 \f
2267 /*
2268  * ==========================
2269  * = dfx_ctl_update_filters =
2270  * ==========================
2271  *
2272  * Overview:
2273  *   Procedure to update adapter filters with desired
2274  *   filter settings.
2275  *
2276  * Returns:
2277  *   Condition code
2278  *
2279  * Arguments:
2280  *   bp - pointer to board information
2281  *
2282  * Functional Description:
2283  *   Enables or disables filter using current filter settings.
2284  *
2285  * Return Codes:
2286  *   DFX_K_SUCCESS - Request succeeded.
2287  *   DFX_K_FAILURE - Request failed.
2288  *
2289  * Assumptions:
2290  *   We must always pass up packets destined to the broadcast
2291  *   address (FF-FF-FF-FF-FF-FF), so we'll always keep the
2292  *   broadcast filter enabled.
2293  *
2294  * Side Effects:
2295  *   On-board adapter filters are updated.
2296  */
2297
2298 static int dfx_ctl_update_filters(DFX_board_t *bp)
2299         {
2300         int     i = 0;                                  /* used as index */
2301
2302         /* Fill in command request information */
2303
2304         bp->cmd_req_virt->cmd_type = PI_CMD_K_FILTERS_SET;
2305
2306         /* Initialize Broadcast filter - * ALWAYS ENABLED * */
2307
2308         bp->cmd_req_virt->filter_set.item[i].item_code  = PI_ITEM_K_BROADCAST;
2309         bp->cmd_req_virt->filter_set.item[i++].value    = PI_FSTATE_K_PASS;
2310
2311         /* Initialize LLC Individual/Group Promiscuous filter */
2312
2313         bp->cmd_req_virt->filter_set.item[i].item_code  = PI_ITEM_K_IND_GROUP_PROM;
2314         bp->cmd_req_virt->filter_set.item[i++].value    = bp->ind_group_prom;
2315
2316         /* Initialize LLC Group Promiscuous filter */
2317
2318         bp->cmd_req_virt->filter_set.item[i].item_code  = PI_ITEM_K_GROUP_PROM;
2319         bp->cmd_req_virt->filter_set.item[i++].value    = bp->group_prom;
2320
2321         /* Terminate the item code list */
2322
2323         bp->cmd_req_virt->filter_set.item[i].item_code  = PI_ITEM_K_EOL;
2324
2325         /* Issue command to update adapter filters, then return */
2326
2327         if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS)
2328                 return(DFX_K_FAILURE);
2329         return(DFX_K_SUCCESS);
2330         }
2331
2332 \f
2333 /*
2334  * ======================
2335  * = dfx_hw_dma_cmd_req =
2336  * ======================
2337  *
2338  * Overview:
2339  *   Sends PDQ DMA command to adapter firmware
2340  *
2341  * Returns:
2342  *   Condition code
2343  *
2344  * Arguments:
2345  *   bp - pointer to board information
2346  *
2347  * Functional Description:
2348  *   The command request and response buffers are posted to the adapter in the manner
2349  *   described in the PDQ Port Specification:
2350  *
2351  *              1. Command Response Buffer is posted to adapter.
2352  *              2. Command Request Buffer is posted to adapter.
2353  *              3. Command Request consumer index is polled until it indicates that request
2354  *         buffer has been DMA'd to adapter.
2355  *              4. Command Response consumer index is polled until it indicates that response
2356  *         buffer has been DMA'd from adapter.
2357  *
2358  *   This ordering ensures that a response buffer is already available for the firmware
2359  *   to use once it's done processing the request buffer.
2360  *
2361  * Return Codes:
2362  *   DFX_K_SUCCESS        - DMA command succeeded
2363  *       DFX_K_OUTSTATE   - Adapter is NOT in proper state
2364  *   DFX_K_HW_TIMEOUT - DMA command timed out
2365  *
2366  * Assumptions:
2367  *   Command request buffer has already been filled with desired DMA command.
2368  *
2369  * Side Effects:
2370  *   None
2371  */
2372
2373 static int dfx_hw_dma_cmd_req(DFX_board_t *bp)
2374         {
2375         int status;                     /* adapter status */
2376         int timeout_cnt;        /* used in for loops */
2377
2378         /* Make sure the adapter is in a state that we can issue the DMA command in */
2379
2380         status = dfx_hw_adap_state_rd(bp);
2381         if ((status == PI_STATE_K_RESET)                ||
2382                 (status == PI_STATE_K_HALTED)           ||
2383                 (status == PI_STATE_K_DMA_UNAVAIL)      ||
2384                 (status == PI_STATE_K_UPGRADE))
2385                 return(DFX_K_OUTSTATE);
2386
2387         /* Put response buffer on the command response queue */
2388
2389         bp->descr_block_virt->cmd_rsp[bp->cmd_rsp_reg.index.prod].long_0 = (u32) (PI_RCV_DESCR_M_SOP |
2390                         ((PI_CMD_RSP_K_SIZE_MAX / PI_ALIGN_K_CMD_RSP_BUFF) << PI_RCV_DESCR_V_SEG_LEN));
2391         bp->descr_block_virt->cmd_rsp[bp->cmd_rsp_reg.index.prod].long_1 = bp->cmd_rsp_phys;
2392
2393         /* Bump (and wrap) the producer index and write out to register */
2394
2395         bp->cmd_rsp_reg.index.prod += 1;
2396         bp->cmd_rsp_reg.index.prod &= PI_CMD_RSP_K_NUM_ENTRIES-1;
2397         dfx_port_write_long(bp, PI_PDQ_K_REG_CMD_RSP_PROD, bp->cmd_rsp_reg.lword);
2398
2399         /* Put request buffer on the command request queue */
2400
2401         bp->descr_block_virt->cmd_req[bp->cmd_req_reg.index.prod].long_0 = (u32) (PI_XMT_DESCR_M_SOP |
2402                         PI_XMT_DESCR_M_EOP | (PI_CMD_REQ_K_SIZE_MAX << PI_XMT_DESCR_V_SEG_LEN));
2403         bp->descr_block_virt->cmd_req[bp->cmd_req_reg.index.prod].long_1 = bp->cmd_req_phys;
2404
2405         /* Bump (and wrap) the producer index and write out to register */
2406
2407         bp->cmd_req_reg.index.prod += 1;
2408         bp->cmd_req_reg.index.prod &= PI_CMD_REQ_K_NUM_ENTRIES-1;
2409         dfx_port_write_long(bp, PI_PDQ_K_REG_CMD_REQ_PROD, bp->cmd_req_reg.lword);
2410
2411         /*
2412          * Here we wait for the command request consumer index to be equal
2413          * to the producer, indicating that the adapter has DMAed the request.
2414          */
2415
2416         for (timeout_cnt = 20000; timeout_cnt > 0; timeout_cnt--)
2417                 {
2418                 if (bp->cmd_req_reg.index.prod == (u8)(bp->cons_block_virt->cmd_req))
2419                         break;
2420                 udelay(100);                    /* wait for 100 microseconds */
2421                 }
2422         if (timeout_cnt == 0)
2423                 return(DFX_K_HW_TIMEOUT);
2424
2425         /* Bump (and wrap) the completion index and write out to register */
2426
2427         bp->cmd_req_reg.index.comp += 1;
2428         bp->cmd_req_reg.index.comp &= PI_CMD_REQ_K_NUM_ENTRIES-1;
2429         dfx_port_write_long(bp, PI_PDQ_K_REG_CMD_REQ_PROD, bp->cmd_req_reg.lword);
2430
2431         /*
2432          * Here we wait for the command response consumer index to be equal
2433          * to the producer, indicating that the adapter has DMAed the response.
2434          */
2435
2436         for (timeout_cnt = 20000; timeout_cnt > 0; timeout_cnt--)
2437                 {
2438                 if (bp->cmd_rsp_reg.index.prod == (u8)(bp->cons_block_virt->cmd_rsp))
2439                         break;
2440                 udelay(100);                    /* wait for 100 microseconds */
2441                 }
2442         if (timeout_cnt == 0)
2443                 return(DFX_K_HW_TIMEOUT);
2444
2445         /* Bump (and wrap) the completion index and write out to register */
2446
2447         bp->cmd_rsp_reg.index.comp += 1;
2448         bp->cmd_rsp_reg.index.comp &= PI_CMD_RSP_K_NUM_ENTRIES-1;
2449         dfx_port_write_long(bp, PI_PDQ_K_REG_CMD_RSP_PROD, bp->cmd_rsp_reg.lword);
2450         return(DFX_K_SUCCESS);
2451         }
2452
2453 \f
2454 /*
2455  * ========================
2456  * = dfx_hw_port_ctrl_req =
2457  * ========================
2458  *
2459  * Overview:
2460  *   Sends PDQ port control command to adapter firmware
2461  *
2462  * Returns:
2463  *   Host data register value in host_data if ptr is not NULL
2464  *
2465  * Arguments:
2466  *   bp                 - pointer to board information
2467  *       command        - port control command
2468  *       data_a         - port data A register value
2469  *       data_b         - port data B register value
2470  *       host_data      - ptr to host data register value
2471  *
2472  * Functional Description:
2473  *   Send generic port control command to adapter by writing
2474  *   to various PDQ port registers, then polling for completion.
2475  *
2476  * Return Codes:
2477  *   DFX_K_SUCCESS        - port control command succeeded
2478  *   DFX_K_HW_TIMEOUT - port control command timed out
2479  *
2480  * Assumptions:
2481  *   None
2482  *
2483  * Side Effects:
2484  *   None
2485  */
2486
2487 static int dfx_hw_port_ctrl_req(
2488         DFX_board_t     *bp,
2489         PI_UINT32       command,
2490         PI_UINT32       data_a,
2491         PI_UINT32       data_b,
2492         PI_UINT32       *host_data
2493         )
2494
2495         {
2496         PI_UINT32       port_cmd;               /* Port Control command register value */
2497         int                     timeout_cnt;    /* used in for loops */
2498
2499         /* Set Command Error bit in command longword */
2500
2501         port_cmd = (PI_UINT32) (command | PI_PCTRL_M_CMD_ERROR);
2502
2503         /* Issue port command to the adapter */
2504
2505         dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_DATA_A, data_a);
2506         dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_DATA_B, data_b);
2507         dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_CTRL, port_cmd);
2508
2509         /* Now wait for command to complete */
2510
2511         if (command == PI_PCTRL_M_BLAST_FLASH)
2512                 timeout_cnt = 600000;   /* set command timeout count to 60 seconds */
2513         else
2514                 timeout_cnt = 20000;    /* set command timeout count to 2 seconds */
2515
2516         for (; timeout_cnt > 0; timeout_cnt--)
2517                 {
2518                 dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_CTRL, &port_cmd);
2519                 if (!(port_cmd & PI_PCTRL_M_CMD_ERROR))
2520                         break;
2521                 udelay(100);                    /* wait for 100 microseconds */
2522                 }
2523         if (timeout_cnt == 0)
2524                 return(DFX_K_HW_TIMEOUT);
2525
2526         /*
2527          * If the address of host_data is non-zero, assume caller has supplied a
2528          * non NULL pointer, and return the contents of the HOST_DATA register in
2529          * it.
2530          */
2531
2532         if (host_data != NULL)
2533                 dfx_port_read_long(bp, PI_PDQ_K_REG_HOST_DATA, host_data);
2534         return(DFX_K_SUCCESS);
2535         }
2536
2537 \f
2538 /*
2539  * =====================
2540  * = dfx_hw_adap_reset =
2541  * =====================
2542  *
2543  * Overview:
2544  *   Resets adapter
2545  *
2546  * Returns:
2547  *   None
2548  *
2549  * Arguments:
2550  *   bp   - pointer to board information
2551  *   type - type of reset to perform
2552  *
2553  * Functional Description:
2554  *   Issue soft reset to adapter by writing to PDQ Port Reset
2555  *   register.  Use incoming reset type to tell adapter what
2556  *   kind of reset operation to perform.
2557  *
2558  * Return Codes:
2559  *   None
2560  *
2561  * Assumptions:
2562  *   This routine merely issues a soft reset to the adapter.
2563  *   It is expected that after this routine returns, the caller
2564  *   will appropriately poll the Port Status register for the
2565  *   adapter to enter the proper state.
2566  *
2567  * Side Effects:
2568  *   Internal adapter registers are cleared.
2569  */
2570
2571 static void dfx_hw_adap_reset(
2572         DFX_board_t     *bp,
2573         PI_UINT32       type
2574         )
2575
2576         {
2577         /* Set Reset type and assert reset */
2578
2579         dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_DATA_A, type);        /* tell adapter type of reset */
2580         dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_RESET, PI_RESET_M_ASSERT_RESET);
2581
2582         /* Wait for at least 1 Microsecond according to the spec. We wait 20 just to be safe */
2583
2584         udelay(20);
2585
2586         /* Deassert reset */
2587
2588         dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_RESET, 0);
2589         }
2590
2591 \f
2592 /*
2593  * ========================
2594  * = dfx_hw_adap_state_rd =
2595  * ========================
2596  *
2597  * Overview:
2598  *   Returns current adapter state
2599  *
2600  * Returns:
2601  *   Adapter state per PDQ Port Specification
2602  *
2603  * Arguments:
2604  *   bp - pointer to board information
2605  *
2606  * Functional Description:
2607  *   Reads PDQ Port Status register and returns adapter state.
2608  *
2609  * Return Codes:
2610  *   None
2611  *
2612  * Assumptions:
2613  *   None
2614  *
2615  * Side Effects:
2616  *   None
2617  */
2618
2619 static int dfx_hw_adap_state_rd(DFX_board_t *bp)
2620         {
2621         PI_UINT32 port_status;          /* Port Status register value */
2622
2623         dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_STATUS, &port_status);
2624         return((port_status & PI_PSTATUS_M_STATE) >> PI_PSTATUS_V_STATE);
2625         }
2626
2627 \f
2628 /*
2629  * =====================
2630  * = dfx_hw_dma_uninit =
2631  * =====================
2632  *
2633  * Overview:
2634  *   Brings adapter to DMA_UNAVAILABLE state
2635  *
2636  * Returns:
2637  *   Condition code
2638  *
2639  * Arguments:
2640  *   bp   - pointer to board information
2641  *   type - type of reset to perform
2642  *
2643  * Functional Description:
2644  *   Bring adapter to DMA_UNAVAILABLE state by performing the following:
2645  *              1. Set reset type bit in Port Data A Register then reset adapter.
2646  *              2. Check that adapter is in DMA_UNAVAILABLE state.
2647  *
2648  * Return Codes:
2649  *   DFX_K_SUCCESS        - adapter is in DMA_UNAVAILABLE state
2650  *   DFX_K_HW_TIMEOUT - adapter did not reset properly
2651  *
2652  * Assumptions:
2653  *   None
2654  *
2655  * Side Effects:
2656  *   Internal adapter registers are cleared.
2657  */
2658
2659 static int dfx_hw_dma_uninit(DFX_board_t *bp, PI_UINT32 type)
2660         {
2661         int timeout_cnt;        /* used in for loops */
2662
2663         /* Set reset type bit and reset adapter */
2664
2665         dfx_hw_adap_reset(bp, type);
2666
2667         /* Now wait for adapter to enter DMA_UNAVAILABLE state */
2668
2669         for (timeout_cnt = 100000; timeout_cnt > 0; timeout_cnt--)
2670                 {
2671                 if (dfx_hw_adap_state_rd(bp) == PI_STATE_K_DMA_UNAVAIL)
2672                         break;
2673                 udelay(100);                                    /* wait for 100 microseconds */
2674                 }
2675         if (timeout_cnt == 0)
2676                 return(DFX_K_HW_TIMEOUT);
2677         return(DFX_K_SUCCESS);
2678         }
2679 \f
2680 /*
2681  *      Align an sk_buff to a boundary power of 2
2682  *
2683  */
2684
2685 static void my_skb_align(struct sk_buff *skb, int n)
2686 {
2687         unsigned long x = (unsigned long)skb->data;
2688         unsigned long v;
2689
2690         v = ALIGN(x, n);        /* Where we want to be */
2691
2692         skb_reserve(skb, v - x);
2693 }
2694
2695 \f
2696 /*
2697  * ================
2698  * = dfx_rcv_init =
2699  * ================
2700  *
2701  * Overview:
2702  *   Produces buffers to adapter LLC Host receive descriptor block
2703  *
2704  * Returns:
2705  *   None
2706  *
2707  * Arguments:
2708  *   bp - pointer to board information
2709  *   get_buffers - non-zero if buffers to be allocated
2710  *
2711  * Functional Description:
2712  *   This routine can be called during dfx_adap_init() or during an adapter
2713  *       reset.  It initializes the descriptor block and produces all allocated
2714  *   LLC Host queue receive buffers.
2715  *
2716  * Return Codes:
2717  *   Return 0 on success or -ENOMEM if buffer allocation failed (when using
2718  *   dynamic buffer allocation). If the buffer allocation failed, the
2719  *   already allocated buffers will not be released and the caller should do
2720  *   this.
2721  *
2722  * Assumptions:
2723  *   The PDQ has been reset and the adapter and driver maintained Type 2
2724  *   register indices are cleared.
2725  *
2726  * Side Effects:
2727  *   Receive buffers are posted to the adapter LLC queue and the adapter
2728  *   is notified.
2729  */
2730
2731 static int dfx_rcv_init(DFX_board_t *bp, int get_buffers)
2732         {
2733         int     i, j;                                   /* used in for loop */
2734
2735         /*
2736          *  Since each receive buffer is a single fragment of same length, initialize
2737          *  first longword in each receive descriptor for entire LLC Host descriptor
2738          *  block.  Also initialize second longword in each receive descriptor with
2739          *  physical address of receive buffer.  We'll always allocate receive
2740          *  buffers in powers of 2 so that we can easily fill the 256 entry descriptor
2741          *  block and produce new receive buffers by simply updating the receive
2742          *  producer index.
2743          *
2744          *      Assumptions:
2745          *              To support all shipping versions of PDQ, the receive buffer size
2746          *              must be mod 128 in length and the physical address must be 128 byte
2747          *              aligned.  In other words, bits 0-6 of the length and address must
2748          *              be zero for the following descriptor field entries to be correct on
2749          *              all PDQ-based boards.  We guaranteed both requirements during
2750          *              driver initialization when we allocated memory for the receive buffers.
2751          */
2752
2753         if (get_buffers) {
2754 #ifdef DYNAMIC_BUFFERS
2755         for (i = 0; i < (int)(bp->rcv_bufs_to_post); i++)
2756                 for (j = 0; (i + j) < (int)PI_RCV_DATA_K_NUM_ENTRIES; j += bp->rcv_bufs_to_post)
2757                 {
2758                         struct sk_buff *newskb = __dev_alloc_skb(NEW_SKB_SIZE, GFP_NOIO);
2759                         if (!newskb)
2760                                 return -ENOMEM;
2761                         bp->descr_block_virt->rcv_data[i+j].long_0 = (u32) (PI_RCV_DESCR_M_SOP |
2762                                 ((PI_RCV_DATA_K_SIZE_MAX / PI_ALIGN_K_RCV_DATA_BUFF) << PI_RCV_DESCR_V_SEG_LEN));
2763                         /*
2764                          * align to 128 bytes for compatibility with
2765                          * the old EISA boards.
2766                          */
2767
2768                         my_skb_align(newskb, 128);
2769                         bp->descr_block_virt->rcv_data[i + j].long_1 =
2770                                 (u32)pci_map_single(bp->pci_dev, newskb->data,
2771                                                     NEW_SKB_SIZE,
2772                                                     PCI_DMA_FROMDEVICE);
2773                         /*
2774                          * p_rcv_buff_va is only used inside the
2775                          * kernel so we put the skb pointer here.
2776                          */
2777                         bp->p_rcv_buff_va[i+j] = (char *) newskb;
2778                 }
2779 #else
2780         for (i=0; i < (int)(bp->rcv_bufs_to_post); i++)
2781                 for (j=0; (i + j) < (int)PI_RCV_DATA_K_NUM_ENTRIES; j += bp->rcv_bufs_to_post)
2782                         {
2783                         bp->descr_block_virt->rcv_data[i+j].long_0 = (u32) (PI_RCV_DESCR_M_SOP |
2784                                 ((PI_RCV_DATA_K_SIZE_MAX / PI_ALIGN_K_RCV_DATA_BUFF) << PI_RCV_DESCR_V_SEG_LEN));
2785                         bp->descr_block_virt->rcv_data[i+j].long_1 = (u32) (bp->rcv_block_phys + (i * PI_RCV_DATA_K_SIZE_MAX));
2786                         bp->p_rcv_buff_va[i+j] = (char *) (bp->rcv_block_virt + (i * PI_RCV_DATA_K_SIZE_MAX));
2787                         }
2788 #endif
2789         }
2790
2791         /* Update receive producer and Type 2 register */
2792
2793         bp->rcv_xmt_reg.index.rcv_prod = bp->rcv_bufs_to_post;
2794         dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_2_PROD, bp->rcv_xmt_reg.lword);
2795         return 0;
2796         }
2797
2798 \f
2799 /*
2800  * =========================
2801  * = dfx_rcv_queue_process =
2802  * =========================
2803  *
2804  * Overview:
2805  *   Process received LLC frames.
2806  *
2807  * Returns:
2808  *   None
2809  *
2810  * Arguments:
2811  *   bp - pointer to board information
2812  *
2813  * Functional Description:
2814  *   Received LLC frames are processed until there are no more consumed frames.
2815  *   Once all frames are processed, the receive buffers are returned to the
2816  *   adapter.  Note that this algorithm fixes the length of time that can be spent
2817  *   in this routine, because there are a fixed number of receive buffers to
2818  *   process and buffers are not produced until this routine exits and returns
2819  *   to the ISR.
2820  *
2821  * Return Codes:
2822  *   None
2823  *
2824  * Assumptions:
2825  *   None
2826  *
2827  * Side Effects:
2828  *   None
2829  */
2830
2831 static void dfx_rcv_queue_process(
2832         DFX_board_t *bp
2833         )
2834
2835         {
2836         PI_TYPE_2_CONSUMER      *p_type_2_cons;         /* ptr to rcv/xmt consumer block register */
2837         char                            *p_buff;                        /* ptr to start of packet receive buffer (FMC descriptor) */
2838         u32                                     descr, pkt_len;         /* FMC descriptor field and packet length */
2839         struct sk_buff          *skb;                           /* pointer to a sk_buff to hold incoming packet data */
2840
2841         /* Service all consumed LLC receive frames */
2842
2843         p_type_2_cons = (PI_TYPE_2_CONSUMER *)(&bp->cons_block_virt->xmt_rcv_data);
2844         while (bp->rcv_xmt_reg.index.rcv_comp != p_type_2_cons->index.rcv_cons)
2845                 {
2846                 /* Process any errors */
2847
2848                 int entry;
2849
2850                 entry = bp->rcv_xmt_reg.index.rcv_comp;
2851 #ifdef DYNAMIC_BUFFERS
2852                 p_buff = (char *) (((struct sk_buff *)bp->p_rcv_buff_va[entry])->data);
2853 #else
2854                 p_buff = (char *) bp->p_rcv_buff_va[entry];
2855 #endif
2856                 memcpy(&descr, p_buff + RCV_BUFF_K_DESCR, sizeof(u32));
2857
2858                 if (descr & PI_FMC_DESCR_M_RCC_FLUSH)
2859                         {
2860                         if (descr & PI_FMC_DESCR_M_RCC_CRC)
2861                                 bp->rcv_crc_errors++;
2862                         else
2863                                 bp->rcv_frame_status_errors++;
2864                         }
2865                 else
2866                 {
2867                         int rx_in_place = 0;
2868
2869                         /* The frame was received without errors - verify packet length */
2870
2871                         pkt_len = (u32)((descr & PI_FMC_DESCR_M_LEN) >> PI_FMC_DESCR_V_LEN);
2872                         pkt_len -= 4;                           /* subtract 4 byte CRC */
2873                         if (!IN_RANGE(pkt_len, FDDI_K_LLC_ZLEN, FDDI_K_LLC_LEN))
2874                                 bp->rcv_length_errors++;
2875                         else{
2876 #ifdef DYNAMIC_BUFFERS
2877                                 if (pkt_len > SKBUFF_RX_COPYBREAK) {
2878                                         struct sk_buff *newskb;
2879
2880                                         newskb = dev_alloc_skb(NEW_SKB_SIZE);
2881                                         if (newskb){
2882                                                 rx_in_place = 1;
2883
2884                                                 my_skb_align(newskb, 128);
2885                                                 skb = (struct sk_buff *)bp->p_rcv_buff_va[entry];
2886                                                 pci_unmap_single(bp->pci_dev,
2887                                                         bp->descr_block_virt->rcv_data[entry].long_1,
2888                                                         NEW_SKB_SIZE,
2889                                                         PCI_DMA_FROMDEVICE);
2890                                                 skb_reserve(skb, RCV_BUFF_K_PADDING);
2891                                                 bp->p_rcv_buff_va[entry] = (char *)newskb;
2892                                                 bp->descr_block_virt->rcv_data[entry].long_1 =
2893                                                         (u32)pci_map_single(bp->pci_dev,
2894                                                                 newskb->data,
2895                                                                 NEW_SKB_SIZE,
2896                                                                 PCI_DMA_FROMDEVICE);
2897                                         } else
2898                                                 skb = NULL;
2899                                 } else
2900 #endif
2901                                         skb = dev_alloc_skb(pkt_len+3); /* alloc new buffer to pass up, add room for PRH */
2902                                 if (skb == NULL)
2903                                         {
2904                                         printk("%s: Could not allocate receive buffer.  Dropping packet.\n", bp->dev->name);
2905                                         bp->rcv_discards++;
2906                                         break;
2907                                         }
2908                                 else {
2909 #ifndef DYNAMIC_BUFFERS
2910                                         if (! rx_in_place)
2911 #endif
2912                                         {
2913                                                 /* Receive buffer allocated, pass receive packet up */
2914
2915                                                 memcpy(skb->data, p_buff + RCV_BUFF_K_PADDING, pkt_len+3);
2916                                         }
2917
2918                                         skb_reserve(skb,3);             /* adjust data field so that it points to FC byte */
2919                                         skb_put(skb, pkt_len);          /* pass up packet length, NOT including CRC */
2920                                         skb->dev = bp->dev;             /* pass up device pointer */
2921
2922                                         skb->protocol = fddi_type_trans(skb, bp->dev);
2923                                         bp->rcv_total_bytes += skb->len;
2924                                         netif_rx(skb);
2925
2926                                         /* Update the rcv counters */
2927                                         bp->dev->last_rx = jiffies;
2928                                         bp->rcv_total_frames++;
2929                                         if (*(p_buff + RCV_BUFF_K_DA) & 0x01)
2930                                                 bp->rcv_multicast_frames++;
2931                                 }
2932                         }
2933                         }
2934
2935                 /*
2936                  * Advance the producer (for recycling) and advance the completion
2937                  * (for servicing received frames).  Note that it is okay to
2938                  * advance the producer without checking that it passes the
2939                  * completion index because they are both advanced at the same
2940                  * rate.
2941                  */
2942
2943                 bp->rcv_xmt_reg.index.rcv_prod += 1;
2944                 bp->rcv_xmt_reg.index.rcv_comp += 1;
2945                 }
2946         }
2947
2948 \f
2949 /*
2950  * =====================
2951  * = dfx_xmt_queue_pkt =
2952  * =====================
2953  *
2954  * Overview:
2955  *   Queues packets for transmission
2956  *
2957  * Returns:
2958  *   Condition code
2959  *
2960  * Arguments:
2961  *   skb - pointer to sk_buff to queue for transmission
2962  *   dev - pointer to device information
2963  *
2964  * Functional Description:
2965  *   Here we assume that an incoming skb transmit request
2966  *   is contained in a single physically contiguous buffer
2967  *   in which the virtual address of the start of packet
2968  *   (skb->data) can be converted to a physical address
2969  *   by using pci_map_single().
2970  *
2971  *   Since the adapter architecture requires a three byte
2972  *   packet request header to prepend the start of packet,
2973  *   we'll write the three byte field immediately prior to
2974  *   the FC byte.  This assumption is valid because we've
2975  *   ensured that dev->hard_header_len includes three pad
2976  *   bytes.  By posting a single fragment to the adapter,
2977  *   we'll reduce the number of descriptor fetches and
2978  *   bus traffic needed to send the request.
2979  *
2980  *   Also, we can't free the skb until after it's been DMA'd
2981  *   out by the adapter, so we'll queue it in the driver and
2982  *   return it in dfx_xmt_done.
2983  *
2984  * Return Codes:
2985  *   0 - driver queued packet, link is unavailable, or skbuff was bad
2986  *       1 - caller should requeue the sk_buff for later transmission
2987  *
2988  * Assumptions:
2989  *       First and foremost, we assume the incoming skb pointer
2990  *   is NOT NULL and is pointing to a valid sk_buff structure.
2991  *
2992  *   The outgoing packet is complete, starting with the
2993  *   frame control byte including the last byte of data,
2994  *   but NOT including the 4 byte CRC.  We'll let the
2995  *   adapter hardware generate and append the CRC.
2996  *
2997  *   The entire packet is stored in one physically
2998  *   contiguous buffer which is not cached and whose
2999  *   32-bit physical address can be determined.
3000  *
3001  *   It's vital that this routine is NOT reentered for the
3002  *   same board and that the OS is not in another section of
3003  *   code (eg. dfx_int_common) for the same board on a
3004  *   different thread.
3005  *
3006  * Side Effects:
3007  *   None
3008  */
3009
3010 static int dfx_xmt_queue_pkt(
3011         struct sk_buff  *skb,
3012         struct net_device       *dev
3013         )
3014
3015         {
3016         DFX_board_t             *bp = dev->priv;
3017         u8                      prod;                           /* local transmit producer index */
3018         PI_XMT_DESCR            *p_xmt_descr;           /* ptr to transmit descriptor block entry */
3019         XMT_DRIVER_DESCR        *p_xmt_drv_descr;       /* ptr to transmit driver descriptor */
3020         unsigned long           flags;
3021
3022         netif_stop_queue(dev);
3023
3024         /*
3025          * Verify that incoming transmit request is OK
3026          *
3027          * Note: The packet size check is consistent with other
3028          *               Linux device drivers, although the correct packet
3029          *               size should be verified before calling the
3030          *               transmit routine.
3031          */
3032
3033         if (!IN_RANGE(skb->len, FDDI_K_LLC_ZLEN, FDDI_K_LLC_LEN))
3034         {
3035                 printk("%s: Invalid packet length - %u bytes\n",
3036                         dev->name, skb->len);
3037                 bp->xmt_length_errors++;                /* bump error counter */
3038                 netif_wake_queue(dev);
3039                 dev_kfree_skb(skb);
3040                 return(0);                              /* return "success" */
3041         }
3042         /*
3043          * See if adapter link is available, if not, free buffer
3044          *
3045          * Note: If the link isn't available, free buffer and return 0
3046          *               rather than tell the upper layer to requeue the packet.
3047          *               The methodology here is that by the time the link
3048          *               becomes available, the packet to be sent will be
3049          *               fairly stale.  By simply dropping the packet, the
3050          *               higher layer protocols will eventually time out
3051          *               waiting for response packets which it won't receive.
3052          */
3053
3054         if (bp->link_available == PI_K_FALSE)
3055                 {
3056                 if (dfx_hw_adap_state_rd(bp) == PI_STATE_K_LINK_AVAIL)  /* is link really available? */
3057                         bp->link_available = PI_K_TRUE;         /* if so, set flag and continue */
3058                 else
3059                         {
3060                         bp->xmt_discards++;                                     /* bump error counter */
3061                         dev_kfree_skb(skb);             /* free sk_buff now */
3062                         netif_wake_queue(dev);
3063                         return(0);                                                      /* return "success" */
3064                         }
3065                 }
3066
3067         spin_lock_irqsave(&bp->lock, flags);
3068
3069         /* Get the current producer and the next free xmt data descriptor */
3070
3071         prod            = bp->rcv_xmt_reg.index.xmt_prod;
3072         p_xmt_descr = &(bp->descr_block_virt->xmt_data[prod]);
3073
3074         /*
3075          * Get pointer to auxiliary queue entry to contain information
3076          * for this packet.
3077          *
3078          * Note: The current xmt producer index will become the
3079          *       current xmt completion index when we complete this
3080          *       packet later on.  So, we'll get the pointer to the
3081          *       next auxiliary queue entry now before we bump the
3082          *       producer index.
3083          */
3084
3085         p_xmt_drv_descr = &(bp->xmt_drv_descr_blk[prod++]);     /* also bump producer index */
3086
3087         /* Write the three PRH bytes immediately before the FC byte */
3088
3089         skb_push(skb,3);
3090         skb->data[0] = DFX_PRH0_BYTE;   /* these byte values are defined */
3091         skb->data[1] = DFX_PRH1_BYTE;   /* in the Motorola FDDI MAC chip */
3092         skb->data[2] = DFX_PRH2_BYTE;   /* specification */
3093
3094         /*
3095          * Write the descriptor with buffer info and bump producer
3096          *
3097          * Note: Since we need to start DMA from the packet request
3098          *               header, we'll add 3 bytes to the DMA buffer length,
3099          *               and we'll determine the physical address of the
3100          *               buffer from the PRH, not skb->data.
3101          *
3102          * Assumptions:
3103          *               1. Packet starts with the frame control (FC) byte
3104          *                  at skb->data.
3105          *               2. The 4-byte CRC is not appended to the buffer or
3106          *                      included in the length.
3107          *               3. Packet length (skb->len) is from FC to end of
3108          *                      data, inclusive.
3109          *               4. The packet length does not exceed the maximum
3110          *                      FDDI LLC frame length of 4491 bytes.
3111          *               5. The entire packet is contained in a physically
3112          *                      contiguous, non-cached, locked memory space
3113          *                      comprised of a single buffer pointed to by
3114          *                      skb->data.
3115          *               6. The physical address of the start of packet
3116          *                      can be determined from the virtual address
3117          *                      by using pci_map_single() and is only 32-bits
3118          *                      wide.
3119          */
3120
3121         p_xmt_descr->long_0     = (u32) (PI_XMT_DESCR_M_SOP | PI_XMT_DESCR_M_EOP | ((skb->len) << PI_XMT_DESCR_V_SEG_LEN));
3122         p_xmt_descr->long_1 = (u32)pci_map_single(bp->pci_dev, skb->data,
3123                                                   skb->len, PCI_DMA_TODEVICE);
3124
3125         /*
3126          * Verify that descriptor is actually available
3127          *
3128          * Note: If descriptor isn't available, return 1 which tells
3129          *       the upper layer to requeue the packet for later
3130          *       transmission.
3131          *
3132          *       We need to ensure that the producer never reaches the
3133          *       completion, except to indicate that the queue is empty.
3134          */
3135
3136         if (prod == bp->rcv_xmt_reg.index.xmt_comp)
3137         {
3138                 skb_pull(skb,3);
3139                 spin_unlock_irqrestore(&bp->lock, flags);
3140                 return(1);                      /* requeue packet for later */
3141         }
3142
3143         /*
3144          * Save info for this packet for xmt done indication routine
3145          *
3146          * Normally, we'd save the producer index in the p_xmt_drv_descr
3147          * structure so that we'd have it handy when we complete this
3148          * packet later (in dfx_xmt_done).  However, since the current
3149          * transmit architecture guarantees a single fragment for the
3150          * entire packet, we can simply bump the completion index by
3151          * one (1) for each completed packet.
3152          *
3153          * Note: If this assumption changes and we're presented with
3154          *       an inconsistent number of transmit fragments for packet
3155          *       data, we'll need to modify this code to save the current
3156          *       transmit producer index.
3157          */
3158
3159         p_xmt_drv_descr->p_skb = skb;
3160
3161         /* Update Type 2 register */
3162
3163         bp->rcv_xmt_reg.index.xmt_prod = prod;
3164         dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_2_PROD, bp->rcv_xmt_reg.lword);
3165         spin_unlock_irqrestore(&bp->lock, flags);
3166         netif_wake_queue(dev);
3167         return(0);                                                      /* packet queued to adapter */
3168         }
3169
3170 \f
3171 /*
3172  * ================
3173  * = dfx_xmt_done =
3174  * ================
3175  *
3176  * Overview:
3177  *   Processes all frames that have been transmitted.
3178  *
3179  * Returns:
3180  *   None
3181  *
3182  * Arguments:
3183  *   bp - pointer to board information
3184  *
3185  * Functional Description:
3186  *   For all consumed transmit descriptors that have not
3187  *   yet been completed, we'll free the skb we were holding
3188  *   onto using dev_kfree_skb and bump the appropriate
3189  *   counters.
3190  *
3191  * Return Codes:
3192  *   None
3193  *
3194  * Assumptions:
3195  *   The Type 2 register is not updated in this routine.  It is
3196  *   assumed that it will be updated in the ISR when dfx_xmt_done
3197  *   returns.
3198  *
3199  * Side Effects:
3200  *   None
3201  */
3202
3203 static int dfx_xmt_done(DFX_board_t *bp)
3204         {
3205         XMT_DRIVER_DESCR        *p_xmt_drv_descr;       /* ptr to transmit driver descriptor */
3206         PI_TYPE_2_CONSUMER      *p_type_2_cons;         /* ptr to rcv/xmt consumer block register */
3207         u8                      comp;                   /* local transmit completion index */
3208         int                     freed = 0;              /* buffers freed */
3209
3210         /* Service all consumed transmit frames */
3211
3212         p_type_2_cons = (PI_TYPE_2_CONSUMER *)(&bp->cons_block_virt->xmt_rcv_data);
3213         while (bp->rcv_xmt_reg.index.xmt_comp != p_type_2_cons->index.xmt_cons)
3214                 {
3215                 /* Get pointer to the transmit driver descriptor block information */
3216
3217                 p_xmt_drv_descr = &(bp->xmt_drv_descr_blk[bp->rcv_xmt_reg.index.xmt_comp]);
3218
3219                 /* Increment transmit counters */
3220
3221                 bp->xmt_total_frames++;
3222                 bp->xmt_total_bytes += p_xmt_drv_descr->p_skb->len;
3223
3224                 /* Return skb to operating system */
3225                 comp = bp->rcv_xmt_reg.index.xmt_comp;
3226                 pci_unmap_single(bp->pci_dev,
3227                                  bp->descr_block_virt->xmt_data[comp].long_1,
3228                                  p_xmt_drv_descr->p_skb->len,
3229                                  PCI_DMA_TODEVICE);
3230                 dev_kfree_skb_irq(p_xmt_drv_descr->p_skb);
3231
3232                 /*
3233                  * Move to start of next packet by updating completion index
3234                  *
3235                  * Here we assume that a transmit packet request is always
3236                  * serviced by posting one fragment.  We can therefore
3237                  * simplify the completion code by incrementing the
3238                  * completion index by one.  This code will need to be
3239                  * modified if this assumption changes.  See comments
3240                  * in dfx_xmt_queue_pkt for more details.
3241                  */
3242
3243                 bp->rcv_xmt_reg.index.xmt_comp += 1;
3244                 freed++;
3245                 }
3246         return freed;
3247         }
3248
3249 \f
3250 /*
3251  * =================
3252  * = dfx_rcv_flush =
3253  * =================
3254  *
3255  * Overview:
3256  *   Remove all skb's in the receive ring.
3257  *
3258  * Returns:
3259  *   None
3260  *
3261  * Arguments:
3262  *   bp - pointer to board information
3263  *
3264  * Functional Description:
3265  *   Free's all the dynamically allocated skb's that are
3266  *   currently attached to the device receive ring. This
3267  *   function is typically only used when the device is
3268  *   initialized or reinitialized.
3269  *
3270  * Return Codes:
3271  *   None
3272  *
3273  * Side Effects:
3274  *   None
3275  */
3276 #ifdef DYNAMIC_BUFFERS
3277 static void dfx_rcv_flush( DFX_board_t *bp )
3278         {
3279         int i, j;
3280
3281         for (i = 0; i < (int)(bp->rcv_bufs_to_post); i++)
3282                 for (j = 0; (i + j) < (int)PI_RCV_DATA_K_NUM_ENTRIES; j += bp->rcv_bufs_to_post)
3283                 {
3284                         struct sk_buff *skb;
3285                         skb = (struct sk_buff *)bp->p_rcv_buff_va[i+j];
3286                         if (skb)
3287                                 dev_kfree_skb(skb);
3288                         bp->p_rcv_buff_va[i+j] = NULL;
3289                 }
3290
3291         }
3292 #else
3293 static inline void dfx_rcv_flush( DFX_board_t *bp )
3294 {
3295 }
3296 #endif /* DYNAMIC_BUFFERS */
3297
3298 /*
3299  * =================
3300  * = dfx_xmt_flush =
3301  * =================
3302  *
3303  * Overview:
3304  *   Processes all frames whether they've been transmitted
3305  *   or not.
3306  *
3307  * Returns:
3308  *   None
3309  *
3310  * Arguments:
3311  *   bp - pointer to board information
3312  *
3313  * Functional Description:
3314  *   For all produced transmit descriptors that have not
3315  *   yet been completed, we'll free the skb we were holding
3316  *   onto using dev_kfree_skb and bump the appropriate
3317  *   counters.  Of course, it's possible that some of
3318  *   these transmit requests actually did go out, but we
3319  *   won't make that distinction here.  Finally, we'll
3320  *   update the consumer index to match the producer.
3321  *
3322  * Return Codes:
3323  *   None
3324  *
3325  * Assumptions:
3326  *   This routine does NOT update the Type 2 register.  It
3327  *   is assumed that this routine is being called during a
3328  *   transmit flush interrupt, or a shutdown or close routine.
3329  *
3330  * Side Effects:
3331  *   None
3332  */
3333
3334 static void dfx_xmt_flush( DFX_board_t *bp )
3335         {
3336         u32                     prod_cons;              /* rcv/xmt consumer block longword */
3337         XMT_DRIVER_DESCR        *p_xmt_drv_descr;       /* ptr to transmit driver descriptor */
3338         u8                      comp;                   /* local transmit completion index */
3339
3340         /* Flush all outstanding transmit frames */
3341
3342         while (bp->rcv_xmt_reg.index.xmt_comp != bp->rcv_xmt_reg.index.xmt_prod)
3343                 {
3344                 /* Get pointer to the transmit driver descriptor block information */
3345
3346                 p_xmt_drv_descr = &(bp->xmt_drv_descr_blk[bp->rcv_xmt_reg.index.xmt_comp]);
3347
3348                 /* Return skb to operating system */
3349                 comp = bp->rcv_xmt_reg.index.xmt_comp;
3350                 pci_unmap_single(bp->pci_dev,
3351                                  bp->descr_block_virt->xmt_data[comp].long_1,
3352                                  p_xmt_drv_descr->p_skb->len,
3353                                  PCI_DMA_TODEVICE);
3354                 dev_kfree_skb(p_xmt_drv_descr->p_skb);
3355
3356                 /* Increment transmit error counter */
3357
3358                 bp->xmt_discards++;
3359
3360                 /*
3361                  * Move to start of next packet by updating completion index
3362                  *
3363                  * Here we assume that a transmit packet request is always
3364                  * serviced by posting one fragment.  We can therefore
3365                  * simplify the completion code by incrementing the
3366                  * completion index by one.  This code will need to be
3367                  * modified if this assumption changes.  See comments
3368                  * in dfx_xmt_queue_pkt for more details.
3369                  */
3370
3371                 bp->rcv_xmt_reg.index.xmt_comp += 1;
3372                 }
3373
3374         /* Update the transmit consumer index in the consumer block */
3375
3376         prod_cons = (u32)(bp->cons_block_virt->xmt_rcv_data & ~PI_CONS_M_XMT_INDEX);
3377         prod_cons |= (u32)(bp->rcv_xmt_reg.index.xmt_prod << PI_CONS_V_XMT_INDEX);
3378         bp->cons_block_virt->xmt_rcv_data = prod_cons;
3379         }
3380
3381 static void __devexit dfx_remove_one_pci_or_eisa(struct pci_dev *pdev, struct net_device *dev)
3382 {
3383         DFX_board_t     *bp = dev->priv;
3384         int             alloc_size;             /* total buffer size used */
3385
3386         unregister_netdev(dev);
3387         release_region(dev->base_addr,  pdev ? PFI_K_CSR_IO_LEN : PI_ESIC_K_CSR_IO_LEN );
3388
3389         alloc_size = sizeof(PI_DESCR_BLOCK) +
3390                      PI_CMD_REQ_K_SIZE_MAX + PI_CMD_RSP_K_SIZE_MAX +
3391 #ifndef DYNAMIC_BUFFERS
3392                      (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX) +
3393 #endif
3394                      sizeof(PI_CONSUMER_BLOCK) +
3395                      (PI_ALIGN_K_DESC_BLK - 1);
3396         if (bp->kmalloced)
3397                 pci_free_consistent(pdev, alloc_size, bp->kmalloced,
3398                                     bp->kmalloced_dma);
3399         free_netdev(dev);
3400 }
3401
3402 static void __devexit dfx_remove_one (struct pci_dev *pdev)
3403 {
3404         struct net_device *dev = pci_get_drvdata(pdev);
3405
3406         dfx_remove_one_pci_or_eisa(pdev, dev);
3407         pci_set_drvdata(pdev, NULL);
3408 }
3409
3410 static struct pci_device_id dfx_pci_tbl[] = {
3411         { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_FDDI, PCI_ANY_ID, PCI_ANY_ID, },
3412         { 0, }
3413 };
3414 MODULE_DEVICE_TABLE(pci, dfx_pci_tbl);
3415
3416 static struct pci_driver dfx_driver = {
3417         .name           = "defxx",
3418         .probe          = dfx_init_one,
3419         .remove         = __devexit_p(dfx_remove_one),
3420         .id_table       = dfx_pci_tbl,
3421 };
3422
3423 static int dfx_have_pci;
3424 static int dfx_have_eisa;
3425
3426
3427 static void __exit dfx_eisa_cleanup(void)
3428 {
3429         struct net_device *dev = root_dfx_eisa_dev;
3430
3431         while (dev)
3432         {
3433                 struct net_device *tmp;
3434                 DFX_board_t *bp;
3435
3436                 bp = (DFX_board_t*)dev->priv;
3437                 tmp = bp->next;
3438                 dfx_remove_one_pci_or_eisa(NULL, dev);
3439                 dev = tmp;
3440         }
3441 }
3442
3443 static int __init dfx_init(void)
3444 {
3445         int rc_pci, rc_eisa;
3446
3447         rc_pci = pci_module_init(&dfx_driver);
3448         if (rc_pci >= 0) dfx_have_pci = 1;
3449
3450         rc_eisa = dfx_eisa_init();
3451         if (rc_eisa >= 0) dfx_have_eisa = 1;
3452
3453         return ((rc_eisa < 0) ? 0 : rc_eisa)  + ((rc_pci < 0) ? 0 : rc_pci);
3454 }
3455
3456 static void __exit dfx_cleanup(void)
3457 {
3458         if (dfx_have_pci)
3459                 pci_unregister_driver(&dfx_driver);
3460         if (dfx_have_eisa)
3461                 dfx_eisa_cleanup();
3462
3463 }
3464
3465 module_init(dfx_init);
3466 module_exit(dfx_cleanup);
3467 MODULE_AUTHOR("Lawrence V. Stefani");
3468 MODULE_DESCRIPTION("DEC FDDIcontroller EISA/PCI (DEFEA/DEFPA) driver "
3469                    DRV_VERSION " " DRV_RELDATE);
3470 MODULE_LICENSE("GPL");
3471
3472 \f
3473 /*
3474  * Local variables:
3475  * kernel-compile-command: "gcc -D__KERNEL__ -I/root/linux/include -Wall -Wstrict-prototypes -O2 -pipe -fomit-frame-pointer -fno-strength-reduce -m486 -malign-loops=2 -malign-jumps=2 -malign-functions=2 -c defxx.c"
3476  * End:
3477  */