2 * ahci.c - AHCI SATA support
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <linux/dmi.h>
45 #include <scsi/scsi_host.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <linux/libata.h>
49 #define DRV_NAME "ahci"
50 #define DRV_VERSION "3.0"
52 static int ahci_skip_host_reset;
53 module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
54 MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
56 static int ahci_enable_alpm(struct ata_port *ap,
58 static void ahci_disable_alpm(struct ata_port *ap);
63 AHCI_MAX_SG = 168, /* hardware max is 64K */
64 AHCI_DMA_BOUNDARY = 0xffffffff,
67 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
69 AHCI_CMD_TBL_CDB = 0x40,
70 AHCI_CMD_TBL_HDR_SZ = 0x80,
71 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
72 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
73 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
75 AHCI_IRQ_ON_SG = (1 << 31),
76 AHCI_CMD_ATAPI = (1 << 5),
77 AHCI_CMD_WRITE = (1 << 6),
78 AHCI_CMD_PREFETCH = (1 << 7),
79 AHCI_CMD_RESET = (1 << 8),
80 AHCI_CMD_CLR_BUSY = (1 << 10),
82 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
83 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
84 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
87 board_ahci_vt8251 = 1,
88 board_ahci_ign_iferr = 2,
93 /* global controller registers */
94 HOST_CAP = 0x00, /* host capabilities */
95 HOST_CTL = 0x04, /* global host control */
96 HOST_IRQ_STAT = 0x08, /* interrupt status */
97 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
98 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
101 HOST_RESET = (1 << 0), /* reset controller; self-clear */
102 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
103 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
106 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
107 HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */
108 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
109 HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */
110 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
111 HOST_CAP_SNTF = (1 << 29), /* SNotification register */
112 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
113 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
115 /* registers for each SATA port */
116 PORT_LST_ADDR = 0x00, /* command list DMA addr */
117 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
118 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
119 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
120 PORT_IRQ_STAT = 0x10, /* interrupt status */
121 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
122 PORT_CMD = 0x18, /* port command */
123 PORT_TFDATA = 0x20, /* taskfile data */
124 PORT_SIG = 0x24, /* device TF signature */
125 PORT_CMD_ISSUE = 0x38, /* command issue */
126 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
127 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
128 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
129 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
130 PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
132 /* PORT_IRQ_{STAT,MASK} bits */
133 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
134 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
135 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
136 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
137 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
138 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
139 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
140 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
142 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
143 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
144 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
145 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
146 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
147 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
148 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
149 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
150 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
152 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
158 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
160 PORT_IRQ_HBUS_DATA_ERR,
161 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
162 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
163 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
166 PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */
167 PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */
168 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
169 PORT_CMD_PMP = (1 << 17), /* PMP attached */
170 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
171 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
172 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
173 PORT_CMD_CLO = (1 << 3), /* Command list override */
174 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
175 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
176 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
178 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
179 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
180 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
181 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
183 /* hpriv->flags bits */
184 AHCI_HFLAG_NO_NCQ = (1 << 0),
185 AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */
186 AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */
187 AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */
188 AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */
189 AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */
190 AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */
191 AHCI_HFLAG_NO_HOTPLUG = (1 << 7), /* ignore PxSERR.DIAG.N */
192 AHCI_HFLAG_SECT255 = (1 << 8), /* max 255 sectors */
196 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
197 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
198 ATA_FLAG_ACPI_SATA | ATA_FLAG_AN |
201 ICH_MAP = 0x90, /* ICH MAP register */
204 struct ahci_cmd_hdr {
219 struct ahci_host_priv {
220 unsigned int flags; /* AHCI_HFLAG_* */
221 u32 cap; /* cap to use */
222 u32 port_map; /* port map to use */
223 u32 saved_cap; /* saved initial cap */
224 u32 saved_port_map; /* saved initial port_map */
227 struct ahci_port_priv {
228 struct ata_link *active_link;
229 struct ahci_cmd_hdr *cmd_slot;
230 dma_addr_t cmd_slot_dma;
232 dma_addr_t cmd_tbl_dma;
234 dma_addr_t rx_fis_dma;
235 /* for NCQ spurious interrupt analysis */
236 unsigned int ncq_saw_d2h:1;
237 unsigned int ncq_saw_dmas:1;
238 unsigned int ncq_saw_sdb:1;
239 u32 intr_mask; /* interrupts to enable */
242 static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
243 static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
244 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
245 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
246 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
247 static int ahci_port_start(struct ata_port *ap);
248 static void ahci_port_stop(struct ata_port *ap);
249 static void ahci_qc_prep(struct ata_queued_cmd *qc);
250 static void ahci_freeze(struct ata_port *ap);
251 static void ahci_thaw(struct ata_port *ap);
252 static void ahci_pmp_attach(struct ata_port *ap);
253 static void ahci_pmp_detach(struct ata_port *ap);
254 static int ahci_softreset(struct ata_link *link, unsigned int *class,
255 unsigned long deadline);
256 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
257 unsigned long deadline);
258 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
259 unsigned long deadline);
260 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
261 unsigned long deadline);
262 static void ahci_postreset(struct ata_link *link, unsigned int *class);
263 static int ahci_pmp_softreset(struct ata_link *link, unsigned int *class,
264 unsigned long deadline);
265 static void ahci_error_handler(struct ata_port *ap);
266 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
267 static int ahci_port_resume(struct ata_port *ap);
268 static void ahci_dev_config(struct ata_device *dev);
269 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl);
270 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
273 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
274 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
275 static int ahci_pci_device_resume(struct pci_dev *pdev);
278 static struct class_device_attribute *ahci_shost_attrs[] = {
279 &class_device_attr_link_power_management_policy,
283 static struct scsi_host_template ahci_sht = {
284 ATA_NCQ_SHT(DRV_NAME),
285 .can_queue = AHCI_MAX_CMDS - 1,
286 .sg_tablesize = AHCI_MAX_SG,
287 .dma_boundary = AHCI_DMA_BOUNDARY,
288 .shost_attrs = ahci_shost_attrs,
291 static struct ata_port_operations ahci_ops = {
292 .inherits = &sata_pmp_port_ops,
294 .qc_defer = sata_pmp_qc_defer_cmd_switch,
295 .qc_prep = ahci_qc_prep,
296 .qc_issue = ahci_qc_issue,
297 .qc_fill_rtf = ahci_qc_fill_rtf,
299 .freeze = ahci_freeze,
301 .softreset = ahci_softreset,
302 .hardreset = ahci_hardreset,
303 .postreset = ahci_postreset,
304 .pmp_softreset = ahci_pmp_softreset,
305 .error_handler = ahci_error_handler,
306 .post_internal_cmd = ahci_post_internal_cmd,
307 .dev_config = ahci_dev_config,
309 .scr_read = ahci_scr_read,
310 .scr_write = ahci_scr_write,
311 .pmp_attach = ahci_pmp_attach,
312 .pmp_detach = ahci_pmp_detach,
314 .enable_pm = ahci_enable_alpm,
315 .disable_pm = ahci_disable_alpm,
317 .port_suspend = ahci_port_suspend,
318 .port_resume = ahci_port_resume,
320 .port_start = ahci_port_start,
321 .port_stop = ahci_port_stop,
324 static struct ata_port_operations ahci_vt8251_ops = {
325 .inherits = &ahci_ops,
326 .hardreset = ahci_vt8251_hardreset,
329 static struct ata_port_operations ahci_p5wdh_ops = {
330 .inherits = &ahci_ops,
331 .hardreset = ahci_p5wdh_hardreset,
334 #define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
336 static const struct ata_port_info ahci_port_info[] = {
339 .flags = AHCI_FLAG_COMMON,
340 .pio_mask = 0x1f, /* pio0-4 */
341 .udma_mask = ATA_UDMA6,
342 .port_ops = &ahci_ops,
344 /* board_ahci_vt8251 */
346 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
347 .flags = AHCI_FLAG_COMMON,
348 .pio_mask = 0x1f, /* pio0-4 */
349 .udma_mask = ATA_UDMA6,
350 .port_ops = &ahci_vt8251_ops,
352 /* board_ahci_ign_iferr */
354 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
355 .flags = AHCI_FLAG_COMMON,
356 .pio_mask = 0x1f, /* pio0-4 */
357 .udma_mask = ATA_UDMA6,
358 .port_ops = &ahci_ops,
360 /* board_ahci_sb600 */
362 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
363 AHCI_HFLAG_32BIT_ONLY |
364 AHCI_HFLAG_SECT255 | AHCI_HFLAG_NO_PMP),
365 .flags = AHCI_FLAG_COMMON,
366 .pio_mask = 0x1f, /* pio0-4 */
367 .udma_mask = ATA_UDMA6,
368 .port_ops = &ahci_ops,
372 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
374 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
375 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
376 .pio_mask = 0x1f, /* pio0-4 */
377 .udma_mask = ATA_UDMA6,
378 .port_ops = &ahci_ops,
380 /* board_ahci_sb700 */
382 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
384 .flags = AHCI_FLAG_COMMON,
385 .pio_mask = 0x1f, /* pio0-4 */
386 .udma_mask = ATA_UDMA6,
387 .port_ops = &ahci_ops,
391 static const struct pci_device_id ahci_pci_tbl[] = {
393 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
394 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
395 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
396 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
397 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
398 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
399 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
400 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
401 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
402 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
403 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
404 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */
405 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
406 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
407 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
408 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
409 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
410 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
411 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
412 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
413 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
414 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
415 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
416 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
417 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
418 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
419 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
420 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
421 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
422 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
423 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
425 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
426 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
427 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
430 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
431 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
432 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
433 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
434 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
435 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
436 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
439 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
440 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
443 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */
444 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */
445 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */
446 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */
447 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci }, /* MCP65 */
448 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci }, /* MCP65 */
449 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci }, /* MCP65 */
450 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci }, /* MCP65 */
451 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */
452 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */
453 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */
454 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */
455 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
456 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
457 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
458 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
459 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
460 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
461 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
462 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
463 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci }, /* MCP73 */
464 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci }, /* MCP73 */
465 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci }, /* MCP73 */
466 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci }, /* MCP73 */
467 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci }, /* MCP73 */
468 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci }, /* MCP73 */
469 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci }, /* MCP73 */
470 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci }, /* MCP73 */
471 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci }, /* MCP73 */
472 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci }, /* MCP73 */
473 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci }, /* MCP73 */
474 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci }, /* MCP73 */
475 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */
476 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */
477 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */
478 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */
479 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */
480 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */
481 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */
482 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */
483 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */
484 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */
485 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */
486 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */
487 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci }, /* MCP79 */
488 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci }, /* MCP79 */
489 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci }, /* MCP79 */
490 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci }, /* MCP79 */
491 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci }, /* MCP79 */
492 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci }, /* MCP79 */
493 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci }, /* MCP79 */
494 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci }, /* MCP79 */
495 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci }, /* MCP79 */
496 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci }, /* MCP79 */
497 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci }, /* MCP79 */
498 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci }, /* MCP79 */
499 { PCI_VDEVICE(NVIDIA, 0x0bc8), board_ahci }, /* MCP7B */
500 { PCI_VDEVICE(NVIDIA, 0x0bc9), board_ahci }, /* MCP7B */
501 { PCI_VDEVICE(NVIDIA, 0x0bca), board_ahci }, /* MCP7B */
502 { PCI_VDEVICE(NVIDIA, 0x0bcb), board_ahci }, /* MCP7B */
503 { PCI_VDEVICE(NVIDIA, 0x0bcc), board_ahci }, /* MCP7B */
504 { PCI_VDEVICE(NVIDIA, 0x0bcd), board_ahci }, /* MCP7B */
505 { PCI_VDEVICE(NVIDIA, 0x0bce), board_ahci }, /* MCP7B */
506 { PCI_VDEVICE(NVIDIA, 0x0bcf), board_ahci }, /* MCP7B */
507 { PCI_VDEVICE(NVIDIA, 0x0bd0), board_ahci }, /* MCP7B */
508 { PCI_VDEVICE(NVIDIA, 0x0bd1), board_ahci }, /* MCP7B */
509 { PCI_VDEVICE(NVIDIA, 0x0bd2), board_ahci }, /* MCP7B */
510 { PCI_VDEVICE(NVIDIA, 0x0bd3), board_ahci }, /* MCP7B */
513 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
514 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */
515 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
518 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
519 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
521 /* Generic, PCI class code for AHCI */
522 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
523 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
525 { } /* terminate list */
529 static struct pci_driver ahci_pci_driver = {
531 .id_table = ahci_pci_tbl,
532 .probe = ahci_init_one,
533 .remove = ata_pci_remove_one,
535 .suspend = ahci_pci_device_suspend,
536 .resume = ahci_pci_device_resume,
541 static inline int ahci_nr_ports(u32 cap)
543 return (cap & 0x1f) + 1;
546 static inline void __iomem *__ahci_port_base(struct ata_host *host,
547 unsigned int port_no)
549 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
551 return mmio + 0x100 + (port_no * 0x80);
554 static inline void __iomem *ahci_port_base(struct ata_port *ap)
556 return __ahci_port_base(ap->host, ap->port_no);
559 static void ahci_enable_ahci(void __iomem *mmio)
563 /* turn on AHCI_EN */
564 tmp = readl(mmio + HOST_CTL);
565 if (!(tmp & HOST_AHCI_EN)) {
567 writel(tmp, mmio + HOST_CTL);
568 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
569 WARN_ON(!(tmp & HOST_AHCI_EN));
574 * ahci_save_initial_config - Save and fixup initial config values
575 * @pdev: target PCI device
576 * @hpriv: host private area to store config values
578 * Some registers containing configuration info might be setup by
579 * BIOS and might be cleared on reset. This function saves the
580 * initial values of those registers into @hpriv such that they
581 * can be restored after controller reset.
583 * If inconsistent, config values are fixed up by this function.
588 static void ahci_save_initial_config(struct pci_dev *pdev,
589 struct ahci_host_priv *hpriv)
591 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
596 /* make sure AHCI mode is enabled before accessing CAP */
597 ahci_enable_ahci(mmio);
599 /* Values prefixed with saved_ are written back to host after
600 * reset. Values without are used for driver operation.
602 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
603 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
605 /* some chips have errata preventing 64bit use */
606 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
607 dev_printk(KERN_INFO, &pdev->dev,
608 "controller can't do 64bit DMA, forcing 32bit\n");
612 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
613 dev_printk(KERN_INFO, &pdev->dev,
614 "controller can't do NCQ, turning off CAP_NCQ\n");
615 cap &= ~HOST_CAP_NCQ;
618 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
619 dev_printk(KERN_INFO, &pdev->dev,
620 "controller can't do PMP, turning off CAP_PMP\n");
621 cap &= ~HOST_CAP_PMP;
625 * Temporary Marvell 6145 hack: PATA port presence
626 * is asserted through the standard AHCI port
627 * presence register, as bit 4 (counting from 0)
629 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
630 if (pdev->device == 0x6121)
634 dev_printk(KERN_ERR, &pdev->dev,
635 "MV_AHCI HACK: port_map %x -> %x\n",
642 /* cross check port_map and cap.n_ports */
646 for (i = 0; i < AHCI_MAX_PORTS; i++)
647 if (port_map & (1 << i))
650 /* If PI has more ports than n_ports, whine, clear
651 * port_map and let it be generated from n_ports.
653 if (map_ports > ahci_nr_ports(cap)) {
654 dev_printk(KERN_WARNING, &pdev->dev,
655 "implemented port map (0x%x) contains more "
656 "ports than nr_ports (%u), using nr_ports\n",
657 port_map, ahci_nr_ports(cap));
662 /* fabricate port_map from cap.nr_ports */
664 port_map = (1 << ahci_nr_ports(cap)) - 1;
665 dev_printk(KERN_WARNING, &pdev->dev,
666 "forcing PORTS_IMPL to 0x%x\n", port_map);
668 /* write the fixed up value to the PI register */
669 hpriv->saved_port_map = port_map;
672 /* record values to use during operation */
674 hpriv->port_map = port_map;
678 * ahci_restore_initial_config - Restore initial config
679 * @host: target ATA host
681 * Restore initial config stored by ahci_save_initial_config().
686 static void ahci_restore_initial_config(struct ata_host *host)
688 struct ahci_host_priv *hpriv = host->private_data;
689 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
691 writel(hpriv->saved_cap, mmio + HOST_CAP);
692 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
693 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
696 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
698 static const int offset[] = {
699 [SCR_STATUS] = PORT_SCR_STAT,
700 [SCR_CONTROL] = PORT_SCR_CTL,
701 [SCR_ERROR] = PORT_SCR_ERR,
702 [SCR_ACTIVE] = PORT_SCR_ACT,
703 [SCR_NOTIFICATION] = PORT_SCR_NTF,
705 struct ahci_host_priv *hpriv = ap->host->private_data;
707 if (sc_reg < ARRAY_SIZE(offset) &&
708 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
709 return offset[sc_reg];
713 static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
715 void __iomem *port_mmio = ahci_port_base(ap);
716 int offset = ahci_scr_offset(ap, sc_reg);
719 *val = readl(port_mmio + offset);
725 static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
727 void __iomem *port_mmio = ahci_port_base(ap);
728 int offset = ahci_scr_offset(ap, sc_reg);
731 writel(val, port_mmio + offset);
737 static void ahci_start_engine(struct ata_port *ap)
739 void __iomem *port_mmio = ahci_port_base(ap);
743 tmp = readl(port_mmio + PORT_CMD);
744 tmp |= PORT_CMD_START;
745 writel(tmp, port_mmio + PORT_CMD);
746 readl(port_mmio + PORT_CMD); /* flush */
749 static int ahci_stop_engine(struct ata_port *ap)
751 void __iomem *port_mmio = ahci_port_base(ap);
754 tmp = readl(port_mmio + PORT_CMD);
756 /* check if the HBA is idle */
757 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
760 /* setting HBA to idle */
761 tmp &= ~PORT_CMD_START;
762 writel(tmp, port_mmio + PORT_CMD);
764 /* wait for engine to stop. This could be as long as 500 msec */
765 tmp = ata_wait_register(port_mmio + PORT_CMD,
766 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
767 if (tmp & PORT_CMD_LIST_ON)
773 static void ahci_start_fis_rx(struct ata_port *ap)
775 void __iomem *port_mmio = ahci_port_base(ap);
776 struct ahci_host_priv *hpriv = ap->host->private_data;
777 struct ahci_port_priv *pp = ap->private_data;
780 /* set FIS registers */
781 if (hpriv->cap & HOST_CAP_64)
782 writel((pp->cmd_slot_dma >> 16) >> 16,
783 port_mmio + PORT_LST_ADDR_HI);
784 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
786 if (hpriv->cap & HOST_CAP_64)
787 writel((pp->rx_fis_dma >> 16) >> 16,
788 port_mmio + PORT_FIS_ADDR_HI);
789 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
791 /* enable FIS reception */
792 tmp = readl(port_mmio + PORT_CMD);
793 tmp |= PORT_CMD_FIS_RX;
794 writel(tmp, port_mmio + PORT_CMD);
797 readl(port_mmio + PORT_CMD);
800 static int ahci_stop_fis_rx(struct ata_port *ap)
802 void __iomem *port_mmio = ahci_port_base(ap);
805 /* disable FIS reception */
806 tmp = readl(port_mmio + PORT_CMD);
807 tmp &= ~PORT_CMD_FIS_RX;
808 writel(tmp, port_mmio + PORT_CMD);
810 /* wait for completion, spec says 500ms, give it 1000 */
811 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
812 PORT_CMD_FIS_ON, 10, 1000);
813 if (tmp & PORT_CMD_FIS_ON)
819 static void ahci_power_up(struct ata_port *ap)
821 struct ahci_host_priv *hpriv = ap->host->private_data;
822 void __iomem *port_mmio = ahci_port_base(ap);
825 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
828 if (hpriv->cap & HOST_CAP_SSS) {
829 cmd |= PORT_CMD_SPIN_UP;
830 writel(cmd, port_mmio + PORT_CMD);
834 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
837 static void ahci_disable_alpm(struct ata_port *ap)
839 struct ahci_host_priv *hpriv = ap->host->private_data;
840 void __iomem *port_mmio = ahci_port_base(ap);
842 struct ahci_port_priv *pp = ap->private_data;
844 /* IPM bits should be disabled by libata-core */
845 /* get the existing command bits */
846 cmd = readl(port_mmio + PORT_CMD);
848 /* disable ALPM and ASP */
849 cmd &= ~PORT_CMD_ASP;
850 cmd &= ~PORT_CMD_ALPE;
852 /* force the interface back to active */
853 cmd |= PORT_CMD_ICC_ACTIVE;
855 /* write out new cmd value */
856 writel(cmd, port_mmio + PORT_CMD);
857 cmd = readl(port_mmio + PORT_CMD);
859 /* wait 10ms to be sure we've come out of any low power state */
862 /* clear out any PhyRdy stuff from interrupt status */
863 writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT);
865 /* go ahead and clean out PhyRdy Change from Serror too */
866 ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18)));
869 * Clear flag to indicate that we should ignore all PhyRdy
872 hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG;
875 * Enable interrupts on Phy Ready.
877 pp->intr_mask |= PORT_IRQ_PHYRDY;
878 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
881 * don't change the link pm policy - we can be called
882 * just to turn of link pm temporarily
886 static int ahci_enable_alpm(struct ata_port *ap,
889 struct ahci_host_priv *hpriv = ap->host->private_data;
890 void __iomem *port_mmio = ahci_port_base(ap);
892 struct ahci_port_priv *pp = ap->private_data;
895 /* Make sure the host is capable of link power management */
896 if (!(hpriv->cap & HOST_CAP_ALPM))
900 case MAX_PERFORMANCE:
903 * if we came here with NOT_AVAILABLE,
904 * it just means this is the first time we
905 * have tried to enable - default to max performance,
906 * and let the user go to lower power modes on request.
908 ahci_disable_alpm(ap);
911 /* configure HBA to enter SLUMBER */
915 /* configure HBA to enter PARTIAL */
923 * Disable interrupts on Phy Ready. This keeps us from
924 * getting woken up due to spurious phy ready interrupts
925 * TBD - Hot plug should be done via polling now, is
926 * that even supported?
928 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
929 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
932 * Set a flag to indicate that we should ignore all PhyRdy
933 * state changes since these can happen now whenever we
936 hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG;
938 /* get the existing command bits */
939 cmd = readl(port_mmio + PORT_CMD);
942 * Set ASP based on Policy
947 * Setting this bit will instruct the HBA to aggressively
948 * enter a lower power link state when it's appropriate and
949 * based on the value set above for ASP
951 cmd |= PORT_CMD_ALPE;
953 /* write out new cmd value */
954 writel(cmd, port_mmio + PORT_CMD);
955 cmd = readl(port_mmio + PORT_CMD);
957 /* IPM bits should be set by libata-core */
962 static void ahci_power_down(struct ata_port *ap)
964 struct ahci_host_priv *hpriv = ap->host->private_data;
965 void __iomem *port_mmio = ahci_port_base(ap);
968 if (!(hpriv->cap & HOST_CAP_SSS))
971 /* put device into listen mode, first set PxSCTL.DET to 0 */
972 scontrol = readl(port_mmio + PORT_SCR_CTL);
974 writel(scontrol, port_mmio + PORT_SCR_CTL);
976 /* then set PxCMD.SUD to 0 */
977 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
978 cmd &= ~PORT_CMD_SPIN_UP;
979 writel(cmd, port_mmio + PORT_CMD);
983 static void ahci_start_port(struct ata_port *ap)
985 /* enable FIS reception */
986 ahci_start_fis_rx(ap);
989 ahci_start_engine(ap);
992 static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
997 rc = ahci_stop_engine(ap);
999 *emsg = "failed to stop engine";
1003 /* disable FIS reception */
1004 rc = ahci_stop_fis_rx(ap);
1006 *emsg = "failed stop FIS RX";
1013 static int ahci_reset_controller(struct ata_host *host)
1015 struct pci_dev *pdev = to_pci_dev(host->dev);
1016 struct ahci_host_priv *hpriv = host->private_data;
1017 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1020 /* we must be in AHCI mode, before using anything
1021 * AHCI-specific, such as HOST_RESET.
1023 ahci_enable_ahci(mmio);
1025 /* global controller reset */
1026 if (!ahci_skip_host_reset) {
1027 tmp = readl(mmio + HOST_CTL);
1028 if ((tmp & HOST_RESET) == 0) {
1029 writel(tmp | HOST_RESET, mmio + HOST_CTL);
1030 readl(mmio + HOST_CTL); /* flush */
1033 /* reset must complete within 1 second, or
1034 * the hardware should be considered fried.
1038 tmp = readl(mmio + HOST_CTL);
1039 if (tmp & HOST_RESET) {
1040 dev_printk(KERN_ERR, host->dev,
1041 "controller reset failed (0x%x)\n", tmp);
1045 /* turn on AHCI mode */
1046 ahci_enable_ahci(mmio);
1048 /* Some registers might be cleared on reset. Restore
1051 ahci_restore_initial_config(host);
1053 dev_printk(KERN_INFO, host->dev,
1054 "skipping global host reset\n");
1056 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
1060 pci_read_config_word(pdev, 0x92, &tmp16);
1061 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1062 tmp16 |= hpriv->port_map;
1063 pci_write_config_word(pdev, 0x92, tmp16);
1070 static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap,
1071 int port_no, void __iomem *mmio,
1072 void __iomem *port_mmio)
1074 const char *emsg = NULL;
1078 /* make sure port is not active */
1079 rc = ahci_deinit_port(ap, &emsg);
1081 dev_printk(KERN_WARNING, &pdev->dev,
1082 "%s (%d)\n", emsg, rc);
1085 tmp = readl(port_mmio + PORT_SCR_ERR);
1086 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1087 writel(tmp, port_mmio + PORT_SCR_ERR);
1089 /* clear port IRQ */
1090 tmp = readl(port_mmio + PORT_IRQ_STAT);
1091 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1093 writel(tmp, port_mmio + PORT_IRQ_STAT);
1095 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1098 static void ahci_init_controller(struct ata_host *host)
1100 struct ahci_host_priv *hpriv = host->private_data;
1101 struct pci_dev *pdev = to_pci_dev(host->dev);
1102 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1104 void __iomem *port_mmio;
1108 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
1109 if (pdev->device == 0x6121)
1113 port_mmio = __ahci_port_base(host, mv);
1115 writel(0, port_mmio + PORT_IRQ_MASK);
1117 /* clear port IRQ */
1118 tmp = readl(port_mmio + PORT_IRQ_STAT);
1119 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1121 writel(tmp, port_mmio + PORT_IRQ_STAT);
1124 for (i = 0; i < host->n_ports; i++) {
1125 struct ata_port *ap = host->ports[i];
1127 port_mmio = ahci_port_base(ap);
1128 if (ata_port_is_dummy(ap))
1131 ahci_port_init(pdev, ap, i, mmio, port_mmio);
1134 tmp = readl(mmio + HOST_CTL);
1135 VPRINTK("HOST_CTL 0x%x\n", tmp);
1136 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1137 tmp = readl(mmio + HOST_CTL);
1138 VPRINTK("HOST_CTL 0x%x\n", tmp);
1141 static void ahci_dev_config(struct ata_device *dev)
1143 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1145 if (hpriv->flags & AHCI_HFLAG_SECT255) {
1146 dev->max_sectors = 255;
1147 ata_dev_printk(dev, KERN_INFO,
1148 "SB600 AHCI: limiting to 255 sectors per cmd\n");
1152 static unsigned int ahci_dev_classify(struct ata_port *ap)
1154 void __iomem *port_mmio = ahci_port_base(ap);
1155 struct ata_taskfile tf;
1158 tmp = readl(port_mmio + PORT_SIG);
1159 tf.lbah = (tmp >> 24) & 0xff;
1160 tf.lbam = (tmp >> 16) & 0xff;
1161 tf.lbal = (tmp >> 8) & 0xff;
1162 tf.nsect = (tmp) & 0xff;
1164 return ata_dev_classify(&tf);
1167 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1170 dma_addr_t cmd_tbl_dma;
1172 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1174 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1175 pp->cmd_slot[tag].status = 0;
1176 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1177 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1180 static int ahci_kick_engine(struct ata_port *ap, int force_restart)
1182 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
1183 struct ahci_host_priv *hpriv = ap->host->private_data;
1184 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1188 /* do we need to kick the port? */
1189 busy = status & (ATA_BUSY | ATA_DRQ);
1190 if (!busy && !force_restart)
1194 rc = ahci_stop_engine(ap);
1198 /* need to do CLO? */
1204 if (!(hpriv->cap & HOST_CAP_CLO)) {
1210 tmp = readl(port_mmio + PORT_CMD);
1211 tmp |= PORT_CMD_CLO;
1212 writel(tmp, port_mmio + PORT_CMD);
1215 tmp = ata_wait_register(port_mmio + PORT_CMD,
1216 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1217 if (tmp & PORT_CMD_CLO)
1220 /* restart engine */
1222 ahci_start_engine(ap);
1226 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1227 struct ata_taskfile *tf, int is_cmd, u16 flags,
1228 unsigned long timeout_msec)
1230 const u32 cmd_fis_len = 5; /* five dwords */
1231 struct ahci_port_priv *pp = ap->private_data;
1232 void __iomem *port_mmio = ahci_port_base(ap);
1233 u8 *fis = pp->cmd_tbl;
1236 /* prep the command */
1237 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1238 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1241 writel(1, port_mmio + PORT_CMD_ISSUE);
1244 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
1247 ahci_kick_engine(ap, 1);
1251 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1256 static int ahci_check_ready(struct ata_link *link)
1258 void __iomem *mmio = link->ap->ioaddr.cmd_addr;
1259 u8 status = readl(mmio + PORT_TFDATA) & 0xFF;
1261 if (!(status & ATA_BUSY))
1266 static int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1267 int pmp, unsigned long deadline)
1269 struct ata_port *ap = link->ap;
1270 const char *reason = NULL;
1271 unsigned long now, msecs;
1272 struct ata_taskfile tf;
1277 if (ata_link_offline(link)) {
1278 DPRINTK("PHY reports no device\n");
1279 *class = ATA_DEV_NONE;
1283 /* prepare for SRST (AHCI-1.1 10.4.1) */
1284 rc = ahci_kick_engine(ap, 1);
1285 if (rc && rc != -EOPNOTSUPP)
1286 ata_link_printk(link, KERN_WARNING,
1287 "failed to reset engine (errno=%d)\n", rc);
1289 ata_tf_init(link->device, &tf);
1291 /* issue the first D2H Register FIS */
1294 if (time_after(now, deadline))
1295 msecs = jiffies_to_msecs(deadline - now);
1298 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1299 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1301 reason = "1st FIS failed";
1305 /* spec says at least 5us, but be generous and sleep for 1ms */
1308 /* issue the second D2H Register FIS */
1309 tf.ctl &= ~ATA_SRST;
1310 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1312 /* wait for link to become ready */
1313 rc = ata_wait_after_reset(link, deadline, ahci_check_ready);
1314 /* link occupied, -ENODEV too is an error */
1316 reason = "device not ready";
1319 *class = ahci_dev_classify(ap);
1321 DPRINTK("EXIT, class=%u\n", *class);
1325 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
1329 static int ahci_softreset(struct ata_link *link, unsigned int *class,
1330 unsigned long deadline)
1334 if (link->ap->flags & ATA_FLAG_PMP)
1335 pmp = SATA_PMP_CTRL_PORT;
1337 return ahci_do_softreset(link, class, pmp, deadline);
1340 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1341 unsigned long deadline)
1343 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1344 struct ata_port *ap = link->ap;
1345 struct ahci_port_priv *pp = ap->private_data;
1346 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1347 struct ata_taskfile tf;
1353 ahci_stop_engine(ap);
1355 /* clear D2H reception area to properly wait for D2H FIS */
1356 ata_tf_init(link->device, &tf);
1358 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1360 rc = sata_link_hardreset(link, timing, deadline, &online,
1363 ahci_start_engine(ap);
1366 *class = ahci_dev_classify(ap);
1368 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1372 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
1373 unsigned long deadline)
1375 struct ata_port *ap = link->ap;
1381 ahci_stop_engine(ap);
1383 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
1384 deadline, &online, NULL);
1386 ahci_start_engine(ap);
1388 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1390 /* vt8251 doesn't clear BSY on signature FIS reception,
1391 * request follow-up softreset.
1393 return online ? -EAGAIN : rc;
1396 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
1397 unsigned long deadline)
1399 struct ata_port *ap = link->ap;
1400 struct ahci_port_priv *pp = ap->private_data;
1401 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1402 struct ata_taskfile tf;
1406 ahci_stop_engine(ap);
1408 /* clear D2H reception area to properly wait for D2H FIS */
1409 ata_tf_init(link->device, &tf);
1411 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1413 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
1414 deadline, &online, NULL);
1416 ahci_start_engine(ap);
1418 /* The pseudo configuration device on SIMG4726 attached to
1419 * ASUS P5W-DH Deluxe doesn't send signature FIS after
1420 * hardreset if no device is attached to the first downstream
1421 * port && the pseudo device locks up on SRST w/ PMP==0. To
1422 * work around this, wait for !BSY only briefly. If BSY isn't
1423 * cleared, perform CLO and proceed to IDENTIFY (achieved by
1424 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
1426 * Wait for two seconds. Devices attached to downstream port
1427 * which can't process the following IDENTIFY after this will
1428 * have to be reset again. For most cases, this should
1429 * suffice while making probing snappish enough.
1432 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
1435 ahci_kick_engine(ap, 0);
1440 static void ahci_postreset(struct ata_link *link, unsigned int *class)
1442 struct ata_port *ap = link->ap;
1443 void __iomem *port_mmio = ahci_port_base(ap);
1446 ata_std_postreset(link, class);
1448 /* Make sure port's ATAPI bit is set appropriately */
1449 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1450 if (*class == ATA_DEV_ATAPI)
1451 new_tmp |= PORT_CMD_ATAPI;
1453 new_tmp &= ~PORT_CMD_ATAPI;
1454 if (new_tmp != tmp) {
1455 writel(new_tmp, port_mmio + PORT_CMD);
1456 readl(port_mmio + PORT_CMD); /* flush */
1460 static int ahci_pmp_softreset(struct ata_link *link, unsigned int *class,
1461 unsigned long deadline)
1463 return ahci_do_softreset(link, class, link->pmp, deadline);
1466 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1468 struct scatterlist *sg;
1469 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1475 * Next, the S/G list.
1477 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1478 dma_addr_t addr = sg_dma_address(sg);
1479 u32 sg_len = sg_dma_len(sg);
1481 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1482 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1483 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1489 static void ahci_qc_prep(struct ata_queued_cmd *qc)
1491 struct ata_port *ap = qc->ap;
1492 struct ahci_port_priv *pp = ap->private_data;
1493 int is_atapi = ata_is_atapi(qc->tf.protocol);
1496 const u32 cmd_fis_len = 5; /* five dwords */
1497 unsigned int n_elem;
1500 * Fill in command table information. First, the header,
1501 * a SATA Register - Host to Device command FIS.
1503 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1505 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1507 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1508 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1512 if (qc->flags & ATA_QCFLAG_DMAMAP)
1513 n_elem = ahci_fill_sg(qc, cmd_tbl);
1516 * Fill in command slot information.
1518 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1519 if (qc->tf.flags & ATA_TFLAG_WRITE)
1520 opts |= AHCI_CMD_WRITE;
1522 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1524 ahci_fill_cmd_slot(pp, qc->tag, opts);
1527 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1529 struct ahci_host_priv *hpriv = ap->host->private_data;
1530 struct ahci_port_priv *pp = ap->private_data;
1531 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1532 struct ata_link *link = NULL;
1533 struct ata_queued_cmd *active_qc;
1534 struct ata_eh_info *active_ehi;
1537 /* determine active link */
1538 ata_port_for_each_link(link, ap)
1539 if (ata_link_active(link))
1544 active_qc = ata_qc_from_tag(ap, link->active_tag);
1545 active_ehi = &link->eh_info;
1547 /* record irq stat */
1548 ata_ehi_clear_desc(host_ehi);
1549 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1551 /* AHCI needs SError cleared; otherwise, it might lock up */
1552 ahci_scr_read(ap, SCR_ERROR, &serror);
1553 ahci_scr_write(ap, SCR_ERROR, serror);
1554 host_ehi->serror |= serror;
1556 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1557 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1558 irq_stat &= ~PORT_IRQ_IF_ERR;
1560 if (irq_stat & PORT_IRQ_TF_ERR) {
1561 /* If qc is active, charge it; otherwise, the active
1562 * link. There's no active qc on NCQ errors. It will
1563 * be determined by EH by reading log page 10h.
1566 active_qc->err_mask |= AC_ERR_DEV;
1568 active_ehi->err_mask |= AC_ERR_DEV;
1570 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1571 host_ehi->serror &= ~SERR_INTERNAL;
1574 if (irq_stat & PORT_IRQ_UNK_FIS) {
1575 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1577 active_ehi->err_mask |= AC_ERR_HSM;
1578 active_ehi->action |= ATA_EH_RESET;
1579 ata_ehi_push_desc(active_ehi,
1580 "unknown FIS %08x %08x %08x %08x" ,
1581 unk[0], unk[1], unk[2], unk[3]);
1584 if (ap->nr_pmp_links && (irq_stat & PORT_IRQ_BAD_PMP)) {
1585 active_ehi->err_mask |= AC_ERR_HSM;
1586 active_ehi->action |= ATA_EH_RESET;
1587 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1590 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1591 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1592 host_ehi->action |= ATA_EH_RESET;
1593 ata_ehi_push_desc(host_ehi, "host bus error");
1596 if (irq_stat & PORT_IRQ_IF_ERR) {
1597 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1598 host_ehi->action |= ATA_EH_RESET;
1599 ata_ehi_push_desc(host_ehi, "interface fatal error");
1602 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1603 ata_ehi_hotplugged(host_ehi);
1604 ata_ehi_push_desc(host_ehi, "%s",
1605 irq_stat & PORT_IRQ_CONNECT ?
1606 "connection status changed" : "PHY RDY changed");
1609 /* okay, let's hand over to EH */
1611 if (irq_stat & PORT_IRQ_FREEZE)
1612 ata_port_freeze(ap);
1617 static void ahci_port_intr(struct ata_port *ap)
1619 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
1620 struct ata_eh_info *ehi = &ap->link.eh_info;
1621 struct ahci_port_priv *pp = ap->private_data;
1622 struct ahci_host_priv *hpriv = ap->host->private_data;
1623 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
1624 u32 status, qc_active;
1627 status = readl(port_mmio + PORT_IRQ_STAT);
1628 writel(status, port_mmio + PORT_IRQ_STAT);
1630 /* ignore BAD_PMP while resetting */
1631 if (unlikely(resetting))
1632 status &= ~PORT_IRQ_BAD_PMP;
1634 /* If we are getting PhyRdy, this is
1635 * just a power state change, we should
1636 * clear out this, plus the PhyRdy/Comm
1637 * Wake bits from Serror
1639 if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) &&
1640 (status & PORT_IRQ_PHYRDY)) {
1641 status &= ~PORT_IRQ_PHYRDY;
1642 ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18)));
1645 if (unlikely(status & PORT_IRQ_ERROR)) {
1646 ahci_error_intr(ap, status);
1650 if (status & PORT_IRQ_SDB_FIS) {
1651 /* If SNotification is available, leave notification
1652 * handling to sata_async_notification(). If not,
1653 * emulate it by snooping SDB FIS RX area.
1655 * Snooping FIS RX area is probably cheaper than
1656 * poking SNotification but some constrollers which
1657 * implement SNotification, ICH9 for example, don't
1658 * store AN SDB FIS into receive area.
1660 if (hpriv->cap & HOST_CAP_SNTF)
1661 sata_async_notification(ap);
1663 /* If the 'N' bit in word 0 of the FIS is set,
1664 * we just received asynchronous notification.
1665 * Tell libata about it.
1667 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1668 u32 f0 = le32_to_cpu(f[0]);
1671 sata_async_notification(ap);
1675 /* pp->active_link is valid iff any command is in flight */
1676 if (ap->qc_active && pp->active_link->sactive)
1677 qc_active = readl(port_mmio + PORT_SCR_ACT);
1679 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1681 rc = ata_qc_complete_multiple(ap, qc_active);
1683 /* while resetting, invalid completions are expected */
1684 if (unlikely(rc < 0 && !resetting)) {
1685 ehi->err_mask |= AC_ERR_HSM;
1686 ehi->action |= ATA_EH_RESET;
1687 ata_port_freeze(ap);
1691 static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1693 struct ata_host *host = dev_instance;
1694 struct ahci_host_priv *hpriv;
1695 unsigned int i, handled = 0;
1697 u32 irq_stat, irq_ack = 0;
1701 hpriv = host->private_data;
1702 mmio = host->iomap[AHCI_PCI_BAR];
1704 /* sigh. 0xffffffff is a valid return from h/w */
1705 irq_stat = readl(mmio + HOST_IRQ_STAT);
1706 irq_stat &= hpriv->port_map;
1710 spin_lock(&host->lock);
1712 for (i = 0; i < host->n_ports; i++) {
1713 struct ata_port *ap;
1715 if (!(irq_stat & (1 << i)))
1718 ap = host->ports[i];
1721 VPRINTK("port %u\n", i);
1723 VPRINTK("port %u (no irq)\n", i);
1724 if (ata_ratelimit())
1725 dev_printk(KERN_WARNING, host->dev,
1726 "interrupt on disabled port %u\n", i);
1729 irq_ack |= (1 << i);
1733 writel(irq_ack, mmio + HOST_IRQ_STAT);
1737 spin_unlock(&host->lock);
1741 return IRQ_RETVAL(handled);
1744 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1746 struct ata_port *ap = qc->ap;
1747 void __iomem *port_mmio = ahci_port_base(ap);
1748 struct ahci_port_priv *pp = ap->private_data;
1750 /* Keep track of the currently active link. It will be used
1751 * in completion path to determine whether NCQ phase is in
1754 pp->active_link = qc->dev->link;
1756 if (qc->tf.protocol == ATA_PROT_NCQ)
1757 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1758 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1759 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1764 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
1766 struct ahci_port_priv *pp = qc->ap->private_data;
1767 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1769 ata_tf_from_fis(d2h_fis, &qc->result_tf);
1773 static void ahci_freeze(struct ata_port *ap)
1775 void __iomem *port_mmio = ahci_port_base(ap);
1778 writel(0, port_mmio + PORT_IRQ_MASK);
1781 static void ahci_thaw(struct ata_port *ap)
1783 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1784 void __iomem *port_mmio = ahci_port_base(ap);
1786 struct ahci_port_priv *pp = ap->private_data;
1789 tmp = readl(port_mmio + PORT_IRQ_STAT);
1790 writel(tmp, port_mmio + PORT_IRQ_STAT);
1791 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
1793 /* turn IRQ back on */
1794 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1797 static void ahci_error_handler(struct ata_port *ap)
1799 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1800 /* restart engine */
1801 ahci_stop_engine(ap);
1802 ahci_start_engine(ap);
1805 sata_pmp_error_handler(ap);
1808 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1810 struct ata_port *ap = qc->ap;
1812 /* make DMA engine forget about the failed command */
1813 if (qc->flags & ATA_QCFLAG_FAILED)
1814 ahci_kick_engine(ap, 1);
1817 static void ahci_pmp_attach(struct ata_port *ap)
1819 void __iomem *port_mmio = ahci_port_base(ap);
1820 struct ahci_port_priv *pp = ap->private_data;
1823 cmd = readl(port_mmio + PORT_CMD);
1824 cmd |= PORT_CMD_PMP;
1825 writel(cmd, port_mmio + PORT_CMD);
1827 pp->intr_mask |= PORT_IRQ_BAD_PMP;
1828 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1831 static void ahci_pmp_detach(struct ata_port *ap)
1833 void __iomem *port_mmio = ahci_port_base(ap);
1834 struct ahci_port_priv *pp = ap->private_data;
1837 cmd = readl(port_mmio + PORT_CMD);
1838 cmd &= ~PORT_CMD_PMP;
1839 writel(cmd, port_mmio + PORT_CMD);
1841 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
1842 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1845 static int ahci_port_resume(struct ata_port *ap)
1848 ahci_start_port(ap);
1850 if (ap->nr_pmp_links)
1851 ahci_pmp_attach(ap);
1853 ahci_pmp_detach(ap);
1859 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
1861 const char *emsg = NULL;
1864 rc = ahci_deinit_port(ap, &emsg);
1866 ahci_power_down(ap);
1868 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
1869 ahci_start_port(ap);
1875 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1877 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1878 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1881 if (mesg.event & PM_EVENT_SLEEP) {
1882 /* AHCI spec rev1.1 section 8.3.3:
1883 * Software must disable interrupts prior to requesting a
1884 * transition of the HBA to D3 state.
1886 ctl = readl(mmio + HOST_CTL);
1887 ctl &= ~HOST_IRQ_EN;
1888 writel(ctl, mmio + HOST_CTL);
1889 readl(mmio + HOST_CTL); /* flush */
1892 return ata_pci_device_suspend(pdev, mesg);
1895 static int ahci_pci_device_resume(struct pci_dev *pdev)
1897 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1900 rc = ata_pci_device_do_resume(pdev);
1904 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
1905 rc = ahci_reset_controller(host);
1909 ahci_init_controller(host);
1912 ata_host_resume(host);
1918 static int ahci_port_start(struct ata_port *ap)
1920 struct device *dev = ap->host->dev;
1921 struct ahci_port_priv *pp;
1925 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1929 mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
1933 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
1936 * First item in chunk of DMA memory: 32-slot command table,
1937 * 32 bytes each in size
1940 pp->cmd_slot_dma = mem_dma;
1942 mem += AHCI_CMD_SLOT_SZ;
1943 mem_dma += AHCI_CMD_SLOT_SZ;
1946 * Second item: Received-FIS area
1949 pp->rx_fis_dma = mem_dma;
1951 mem += AHCI_RX_FIS_SZ;
1952 mem_dma += AHCI_RX_FIS_SZ;
1955 * Third item: data area for storing a single command
1956 * and its scatter-gather table
1959 pp->cmd_tbl_dma = mem_dma;
1962 * Save off initial list of interrupts to be enabled.
1963 * This could be changed later
1965 pp->intr_mask = DEF_PORT_IRQ;
1967 ap->private_data = pp;
1969 /* engage engines, captain */
1970 return ahci_port_resume(ap);
1973 static void ahci_port_stop(struct ata_port *ap)
1975 const char *emsg = NULL;
1978 /* de-initialize port */
1979 rc = ahci_deinit_port(ap, &emsg);
1981 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
1984 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
1989 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1990 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1992 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1994 dev_printk(KERN_ERR, &pdev->dev,
1995 "64-bit DMA enable failed\n");
2000 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2002 dev_printk(KERN_ERR, &pdev->dev,
2003 "32-bit DMA enable failed\n");
2006 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2008 dev_printk(KERN_ERR, &pdev->dev,
2009 "32-bit consistent DMA enable failed\n");
2016 static void ahci_print_info(struct ata_host *host)
2018 struct ahci_host_priv *hpriv = host->private_data;
2019 struct pci_dev *pdev = to_pci_dev(host->dev);
2020 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
2021 u32 vers, cap, impl, speed;
2022 const char *speed_s;
2026 vers = readl(mmio + HOST_VERSION);
2028 impl = hpriv->port_map;
2030 speed = (cap >> 20) & 0xf;
2033 else if (speed == 2)
2038 pci_read_config_word(pdev, 0x0a, &cc);
2039 if (cc == PCI_CLASS_STORAGE_IDE)
2041 else if (cc == PCI_CLASS_STORAGE_SATA)
2043 else if (cc == PCI_CLASS_STORAGE_RAID)
2048 dev_printk(KERN_INFO, &pdev->dev,
2049 "AHCI %02x%02x.%02x%02x "
2050 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2053 (vers >> 24) & 0xff,
2054 (vers >> 16) & 0xff,
2058 ((cap >> 8) & 0x1f) + 1,
2064 dev_printk(KERN_INFO, &pdev->dev,
2070 cap & (1 << 31) ? "64bit " : "",
2071 cap & (1 << 30) ? "ncq " : "",
2072 cap & (1 << 29) ? "sntf " : "",
2073 cap & (1 << 28) ? "ilck " : "",
2074 cap & (1 << 27) ? "stag " : "",
2075 cap & (1 << 26) ? "pm " : "",
2076 cap & (1 << 25) ? "led " : "",
2078 cap & (1 << 24) ? "clo " : "",
2079 cap & (1 << 19) ? "nz " : "",
2080 cap & (1 << 18) ? "only " : "",
2081 cap & (1 << 17) ? "pmp " : "",
2082 cap & (1 << 15) ? "pio " : "",
2083 cap & (1 << 14) ? "slum " : "",
2084 cap & (1 << 13) ? "part " : ""
2088 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
2089 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
2090 * support PMP and the 4726 either directly exports the device
2091 * attached to the first downstream port or acts as a hardware storage
2092 * controller and emulate a single ATA device (can be RAID 0/1 or some
2093 * other configuration).
2095 * When there's no device attached to the first downstream port of the
2096 * 4726, "Config Disk" appears, which is a pseudo ATA device to
2097 * configure the 4726. However, ATA emulation of the device is very
2098 * lame. It doesn't send signature D2H Reg FIS after the initial
2099 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
2101 * The following function works around the problem by always using
2102 * hardreset on the port and not depending on receiving signature FIS
2103 * afterward. If signature FIS isn't received soon, ATA class is
2104 * assumed without follow-up softreset.
2106 static void ahci_p5wdh_workaround(struct ata_host *host)
2108 static struct dmi_system_id sysids[] = {
2110 .ident = "P5W DH Deluxe",
2112 DMI_MATCH(DMI_SYS_VENDOR,
2113 "ASUSTEK COMPUTER INC"),
2114 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
2119 struct pci_dev *pdev = to_pci_dev(host->dev);
2121 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
2122 dmi_check_system(sysids)) {
2123 struct ata_port *ap = host->ports[1];
2125 dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH "
2126 "Deluxe on-board SIMG4726 workaround\n");
2128 ap->ops = &ahci_p5wdh_ops;
2129 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
2133 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2135 static int printed_version;
2136 struct ata_port_info pi = ahci_port_info[ent->driver_data];
2137 const struct ata_port_info *ppi[] = { &pi, NULL };
2138 struct device *dev = &pdev->dev;
2139 struct ahci_host_priv *hpriv;
2140 struct ata_host *host;
2145 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
2147 if (!printed_version++)
2148 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
2150 /* acquire resources */
2151 rc = pcim_enable_device(pdev);
2155 /* AHCI controllers often implement SFF compatible interface.
2156 * Grab all PCI BARs just in case.
2158 rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
2160 pcim_pin_device(pdev);
2164 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
2165 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
2168 /* ICH6s share the same PCI ID for both piix and ahci
2169 * modes. Enabling ahci mode while MAP indicates
2170 * combined mode is a bad idea. Yield to ata_piix.
2172 pci_read_config_byte(pdev, ICH_MAP, &map);
2174 dev_printk(KERN_INFO, &pdev->dev, "controller is in "
2175 "combined mode, can't enable AHCI mode\n");
2180 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
2183 hpriv->flags |= (unsigned long)pi.private_data;
2185 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
2188 /* save initial config */
2189 ahci_save_initial_config(pdev, hpriv);
2192 if (hpriv->cap & HOST_CAP_NCQ)
2193 pi.flags |= ATA_FLAG_NCQ;
2195 if (hpriv->cap & HOST_CAP_PMP)
2196 pi.flags |= ATA_FLAG_PMP;
2198 /* CAP.NP sometimes indicate the index of the last enabled
2199 * port, at other times, that of the last possible port, so
2200 * determining the maximum port number requires looking at
2201 * both CAP.NP and port_map.
2203 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
2205 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
2208 host->iomap = pcim_iomap_table(pdev);
2209 host->private_data = hpriv;
2211 for (i = 0; i < host->n_ports; i++) {
2212 struct ata_port *ap = host->ports[i];
2213 void __iomem *port_mmio = ahci_port_base(ap);
2215 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
2216 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
2217 0x100 + ap->port_no * 0x80, "port");
2219 /* set initial link pm policy */
2220 ap->pm_policy = NOT_AVAILABLE;
2222 /* standard SATA port setup */
2223 if (hpriv->port_map & (1 << i))
2224 ap->ioaddr.cmd_addr = port_mmio;
2226 /* disabled/not-implemented port */
2228 ap->ops = &ata_dummy_port_ops;
2231 /* apply workaround for ASUS P5W DH Deluxe mainboard */
2232 ahci_p5wdh_workaround(host);
2234 /* initialize adapter */
2235 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
2239 rc = ahci_reset_controller(host);
2243 ahci_init_controller(host);
2244 ahci_print_info(host);
2246 pci_set_master(pdev);
2247 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
2251 static int __init ahci_init(void)
2253 return pci_register_driver(&ahci_pci_driver);
2256 static void __exit ahci_exit(void)
2258 pci_unregister_driver(&ahci_pci_driver);
2262 MODULE_AUTHOR("Jeff Garzik");
2263 MODULE_DESCRIPTION("AHCI SATA low-level driver");
2264 MODULE_LICENSE("GPL");
2265 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
2266 MODULE_VERSION(DRV_VERSION);
2268 module_init(ahci_init);
2269 module_exit(ahci_exit);