Merge git://git.infradead.org/iommu-2.6
[linux-2.6] / arch / powerpc / boot / dts / mpc8572ds_camp_core0.dts
1 /*
2  * MPC8572 DS Core0 Device Tree Source in CAMP mode.
3  *
4  * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
5  * can be shared, all the other devices must be assigned to one core only.
6  * This dts file allows core0 to have memory, l2, i2c, dma1, global-util, eth0,
7  * eth1, crypto, pci0, pci1.
8  *
9  * Copyright 2007-2009 Freescale Semiconductor Inc.
10  *
11  * This program is free software; you can redistribute  it and/or modify it
12  * under  the terms of  the GNU General  Public License as published by the
13  * Free Software Foundation;  either version 2 of the  License, or (at your
14  * option) any later version.
15  */
16
17 /dts-v1/;
18 / {
19         model = "fsl,MPC8572DS";
20         compatible = "fsl,MPC8572DS", "fsl,MPC8572DS-CAMP";
21         #address-cells = <1>;
22         #size-cells = <1>;
23
24         aliases {
25                 ethernet0 = &enet0;
26                 ethernet1 = &enet1;
27                 serial0 = &serial0;
28                 pci0 = &pci0;
29                 pci1 = &pci1;
30         };
31
32         cpus {
33                 #address-cells = <1>;
34                 #size-cells = <0>;
35
36                 PowerPC,8572@0 {
37                         device_type = "cpu";
38                         reg = <0x0>;
39                         d-cache-line-size = <32>;       // 32 bytes
40                         i-cache-line-size = <32>;       // 32 bytes
41                         d-cache-size = <0x8000>;                // L1, 32K
42                         i-cache-size = <0x8000>;                // L1, 32K
43                         timebase-frequency = <0>;
44                         bus-frequency = <0>;
45                         clock-frequency = <0>;
46                         next-level-cache = <&L2>;
47                 };
48
49         };
50
51         memory {
52                 device_type = "memory";
53                 reg = <0x0 0x0>;        // Filled by U-Boot
54         };
55
56         soc8572@ffe00000 {
57                 #address-cells = <1>;
58                 #size-cells = <1>;
59                 device_type = "soc";
60                 compatible = "simple-bus";
61                 ranges = <0x0 0xffe00000 0x100000>;
62                 reg = <0xffe00000 0x1000>;      // CCSRBAR & soc regs, remove once parse code for immrbase fixed
63                 bus-frequency = <0>;            // Filled out by uboot.
64
65                 memory-controller@2000 {
66                         compatible = "fsl,mpc8572-memory-controller";
67                         reg = <0x2000 0x1000>;
68                         interrupt-parent = <&mpic>;
69                         interrupts = <18 2>;
70                 };
71
72                 memory-controller@6000 {
73                         compatible = "fsl,mpc8572-memory-controller";
74                         reg = <0x6000 0x1000>;
75                         interrupt-parent = <&mpic>;
76                         interrupts = <18 2>;
77                 };
78
79                 L2: l2-cache-controller@20000 {
80                         compatible = "fsl,mpc8572-l2-cache-controller";
81                         reg = <0x20000 0x1000>;
82                         cache-line-size = <32>; // 32 bytes
83                         cache-size = <0x80000>; // L2, 512K
84                         interrupt-parent = <&mpic>;
85                         interrupts = <16 2>;
86                 };
87
88                 i2c@3000 {
89                         #address-cells = <1>;
90                         #size-cells = <0>;
91                         cell-index = <0>;
92                         compatible = "fsl-i2c";
93                         reg = <0x3000 0x100>;
94                         interrupts = <43 2>;
95                         interrupt-parent = <&mpic>;
96                         dfsrr;
97                 };
98
99                 i2c@3100 {
100                         #address-cells = <1>;
101                         #size-cells = <0>;
102                         cell-index = <1>;
103                         compatible = "fsl-i2c";
104                         reg = <0x3100 0x100>;
105                         interrupts = <43 2>;
106                         interrupt-parent = <&mpic>;
107                         dfsrr;
108                 };
109
110                 dma@21300 {
111                         #address-cells = <1>;
112                         #size-cells = <1>;
113                         compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
114                         reg = <0x21300 0x4>;
115                         ranges = <0x0 0x21100 0x200>;
116                         cell-index = <0>;
117                         dma-channel@0 {
118                                 compatible = "fsl,mpc8572-dma-channel",
119                                                 "fsl,eloplus-dma-channel";
120                                 reg = <0x0 0x80>;
121                                 cell-index = <0>;
122                                 interrupt-parent = <&mpic>;
123                                 interrupts = <20 2>;
124                         };
125                         dma-channel@80 {
126                                 compatible = "fsl,mpc8572-dma-channel",
127                                                 "fsl,eloplus-dma-channel";
128                                 reg = <0x80 0x80>;
129                                 cell-index = <1>;
130                                 interrupt-parent = <&mpic>;
131                                 interrupts = <21 2>;
132                         };
133                         dma-channel@100 {
134                                 compatible = "fsl,mpc8572-dma-channel",
135                                                 "fsl,eloplus-dma-channel";
136                                 reg = <0x100 0x80>;
137                                 cell-index = <2>;
138                                 interrupt-parent = <&mpic>;
139                                 interrupts = <22 2>;
140                         };
141                         dma-channel@180 {
142                                 compatible = "fsl,mpc8572-dma-channel",
143                                                 "fsl,eloplus-dma-channel";
144                                 reg = <0x180 0x80>;
145                                 cell-index = <3>;
146                                 interrupt-parent = <&mpic>;
147                                 interrupts = <23 2>;
148                         };
149                 };
150
151                 enet0: ethernet@24000 {
152                         #address-cells = <1>;
153                         #size-cells = <1>;
154                         cell-index = <0>;
155                         device_type = "network";
156                         model = "eTSEC";
157                         compatible = "gianfar";
158                         reg = <0x24000 0x1000>;
159                         ranges = <0x0 0x24000 0x1000>;
160                         local-mac-address = [ 00 00 00 00 00 00 ];
161                         interrupts = <29 2 30 2 34 2>;
162                         interrupt-parent = <&mpic>;
163                         phy-handle = <&phy0>;
164                         phy-connection-type = "rgmii-id";
165
166                         mdio@520 {
167                                 #address-cells = <1>;
168                                 #size-cells = <0>;
169                                 compatible = "fsl,gianfar-mdio";
170                                 reg = <0x520 0x20>;
171
172                                 phy0: ethernet-phy@0 {
173                                         interrupt-parent = <&mpic>;
174                                         interrupts = <10 1>;
175                                         reg = <0x0>;
176                                 };
177                                 phy1: ethernet-phy@1 {
178                                         interrupt-parent = <&mpic>;
179                                         interrupts = <10 1>;
180                                         reg = <0x1>;
181                                 };
182                         };
183                 };
184
185                 enet1: ethernet@25000 {
186                         cell-index = <1>;
187                         device_type = "network";
188                         model = "eTSEC";
189                         compatible = "gianfar";
190                         reg = <0x25000 0x1000>;
191                         local-mac-address = [ 00 00 00 00 00 00 ];
192                         interrupts = <35 2 36 2 40 2>;
193                         interrupt-parent = <&mpic>;
194                         phy-handle = <&phy1>;
195                         phy-connection-type = "rgmii-id";
196                 };
197
198                 serial0: serial@4500 {
199                         cell-index = <0>;
200                         device_type = "serial";
201                         compatible = "ns16550";
202                         reg = <0x4500 0x100>;
203                         clock-frequency = <0>;
204                 };
205
206                 global-utilities@e0000 {        //global utilities block
207                         compatible = "fsl,mpc8572-guts";
208                         reg = <0xe0000 0x1000>;
209                         fsl,has-rstcr;
210                 };
211
212                 crypto@30000 {
213                         compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
214                                      "fsl,sec2.1", "fsl,sec2.0";
215                         reg = <0x30000 0x10000>;
216                         interrupts = <45 2 58 2>;
217                         interrupt-parent = <&mpic>;
218                         fsl,num-channels = <4>;
219                         fsl,channel-fifo-len = <24>;
220                         fsl,exec-units-mask = <0x9fe>;
221                         fsl,descriptor-types-mask = <0x3ab0ebf>;
222                 };
223
224                 mpic: pic@40000 {
225                         interrupt-controller;
226                         #address-cells = <0>;
227                         #interrupt-cells = <2>;
228                         reg = <0x40000 0x40000>;
229                         compatible = "chrp,open-pic";
230                         device_type = "open-pic";
231                         protected-sources = <
232                         31 32 33 37 38 39       /* enet2 enet3 */
233                         76 77 78 79 26 42       /* dma2 pci2 serial*/
234                         0xe0 0xe1 0xe2 0xe3     /* msi */
235                         0xe4 0xe5 0xe6 0xe7
236                         >;
237                 };
238         };
239
240         pci0: pcie@ffe08000 {
241                 cell-index = <0>;
242                 compatible = "fsl,mpc8548-pcie";
243                 device_type = "pci";
244                 #interrupt-cells = <1>;
245                 #size-cells = <2>;
246                 #address-cells = <3>;
247                 reg = <0xffe08000 0x1000>;
248                 bus-range = <0 255>;
249                 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
250                           0x1000000 0x0 0x0 0xffc00000 0x0 0x10000>;
251                 clock-frequency = <33333333>;
252                 interrupt-parent = <&mpic>;
253                 interrupts = <24 2>;
254                 interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
255                 interrupt-map = <
256                         /* IDSEL 0x11 func 0 - PCI slot 1 */
257                         0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
258                         0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
259                         0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
260                         0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
261
262                         /* IDSEL 0x11 func 1 - PCI slot 1 */
263                         0x8900 0x0 0x0 0x1 &mpic 0x2 0x1
264                         0x8900 0x0 0x0 0x2 &mpic 0x3 0x1
265                         0x8900 0x0 0x0 0x3 &mpic 0x4 0x1
266                         0x8900 0x0 0x0 0x4 &mpic 0x1 0x1
267
268                         /* IDSEL 0x11 func 2 - PCI slot 1 */
269                         0x8a00 0x0 0x0 0x1 &mpic 0x2 0x1
270                         0x8a00 0x0 0x0 0x2 &mpic 0x3 0x1
271                         0x8a00 0x0 0x0 0x3 &mpic 0x4 0x1
272                         0x8a00 0x0 0x0 0x4 &mpic 0x1 0x1
273
274                         /* IDSEL 0x11 func 3 - PCI slot 1 */
275                         0x8b00 0x0 0x0 0x1 &mpic 0x2 0x1
276                         0x8b00 0x0 0x0 0x2 &mpic 0x3 0x1
277                         0x8b00 0x0 0x0 0x3 &mpic 0x4 0x1
278                         0x8b00 0x0 0x0 0x4 &mpic 0x1 0x1
279
280                         /* IDSEL 0x11 func 4 - PCI slot 1 */
281                         0x8c00 0x0 0x0 0x1 &mpic 0x2 0x1
282                         0x8c00 0x0 0x0 0x2 &mpic 0x3 0x1
283                         0x8c00 0x0 0x0 0x3 &mpic 0x4 0x1
284                         0x8c00 0x0 0x0 0x4 &mpic 0x1 0x1
285
286                         /* IDSEL 0x11 func 5 - PCI slot 1 */
287                         0x8d00 0x0 0x0 0x1 &mpic 0x2 0x1
288                         0x8d00 0x0 0x0 0x2 &mpic 0x3 0x1
289                         0x8d00 0x0 0x0 0x3 &mpic 0x4 0x1
290                         0x8d00 0x0 0x0 0x4 &mpic 0x1 0x1
291
292                         /* IDSEL 0x11 func 6 - PCI slot 1 */
293                         0x8e00 0x0 0x0 0x1 &mpic 0x2 0x1
294                         0x8e00 0x0 0x0 0x2 &mpic 0x3 0x1
295                         0x8e00 0x0 0x0 0x3 &mpic 0x4 0x1
296                         0x8e00 0x0 0x0 0x4 &mpic 0x1 0x1
297
298                         /* IDSEL 0x11 func 7 - PCI slot 1 */
299                         0x8f00 0x0 0x0 0x1 &mpic 0x2 0x1
300                         0x8f00 0x0 0x0 0x2 &mpic 0x3 0x1
301                         0x8f00 0x0 0x0 0x3 &mpic 0x4 0x1
302                         0x8f00 0x0 0x0 0x4 &mpic 0x1 0x1
303
304                         /* IDSEL 0x12 func 0 - PCI slot 2 */
305                         0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
306                         0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
307                         0x9000 0x0 0x0 0x3 &mpic 0x1 0x1
308                         0x9000 0x0 0x0 0x4 &mpic 0x2 0x1
309
310                         /* IDSEL 0x12 func 1 - PCI slot 2 */
311                         0x9100 0x0 0x0 0x1 &mpic 0x3 0x1
312                         0x9100 0x0 0x0 0x2 &mpic 0x4 0x1
313                         0x9100 0x0 0x0 0x3 &mpic 0x1 0x1
314                         0x9100 0x0 0x0 0x4 &mpic 0x2 0x1
315
316                         /* IDSEL 0x12 func 2 - PCI slot 2 */
317                         0x9200 0x0 0x0 0x1 &mpic 0x3 0x1
318                         0x9200 0x0 0x0 0x2 &mpic 0x4 0x1
319                         0x9200 0x0 0x0 0x3 &mpic 0x1 0x1
320                         0x9200 0x0 0x0 0x4 &mpic 0x2 0x1
321
322                         /* IDSEL 0x12 func 3 - PCI slot 2 */
323                         0x9300 0x0 0x0 0x1 &mpic 0x3 0x1
324                         0x9300 0x0 0x0 0x2 &mpic 0x4 0x1
325                         0x9300 0x0 0x0 0x3 &mpic 0x1 0x1
326                         0x9300 0x0 0x0 0x4 &mpic 0x2 0x1
327
328                         /* IDSEL 0x12 func 4 - PCI slot 2 */
329                         0x9400 0x0 0x0 0x1 &mpic 0x3 0x1
330                         0x9400 0x0 0x0 0x2 &mpic 0x4 0x1
331                         0x9400 0x0 0x0 0x3 &mpic 0x1 0x1
332                         0x9400 0x0 0x0 0x4 &mpic 0x2 0x1
333
334                         /* IDSEL 0x12 func 5 - PCI slot 2 */
335                         0x9500 0x0 0x0 0x1 &mpic 0x3 0x1
336                         0x9500 0x0 0x0 0x2 &mpic 0x4 0x1
337                         0x9500 0x0 0x0 0x3 &mpic 0x1 0x1
338                         0x9500 0x0 0x0 0x4 &mpic 0x2 0x1
339
340                         /* IDSEL 0x12 func 6 - PCI slot 2 */
341                         0x9600 0x0 0x0 0x1 &mpic 0x3 0x1
342                         0x9600 0x0 0x0 0x2 &mpic 0x4 0x1
343                         0x9600 0x0 0x0 0x3 &mpic 0x1 0x1
344                         0x9600 0x0 0x0 0x4 &mpic 0x2 0x1
345
346                         /* IDSEL 0x12 func 7 - PCI slot 2 */
347                         0x9700 0x0 0x0 0x1 &mpic 0x3 0x1
348                         0x9700 0x0 0x0 0x2 &mpic 0x4 0x1
349                         0x9700 0x0 0x0 0x3 &mpic 0x1 0x1
350                         0x9700 0x0 0x0 0x4 &mpic 0x2 0x1
351
352                         // IDSEL 0x1c  USB
353                         0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
354                         0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
355                         0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
356                         0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
357
358                         // IDSEL 0x1d  Audio
359                         0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
360
361                         // IDSEL 0x1e Legacy
362                         0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
363                         0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
364
365                         // IDSEL 0x1f IDE/SATA
366                         0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
367                         0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
368
369                         >;
370
371                 pcie@0 {
372                         reg = <0x0 0x0 0x0 0x0 0x0>;
373                         #size-cells = <2>;
374                         #address-cells = <3>;
375                         device_type = "pci";
376                         ranges = <0x2000000 0x0 0x80000000
377                                   0x2000000 0x0 0x80000000
378                                   0x0 0x20000000
379
380                                   0x1000000 0x0 0x0
381                                   0x1000000 0x0 0x0
382                                   0x0 0x10000>;
383                         uli1575@0 {
384                                 reg = <0x0 0x0 0x0 0x0 0x0>;
385                                 #size-cells = <2>;
386                                 #address-cells = <3>;
387                                 ranges = <0x2000000 0x0 0x80000000
388                                           0x2000000 0x0 0x80000000
389                                           0x0 0x20000000
390
391                                           0x1000000 0x0 0x0
392                                           0x1000000 0x0 0x0
393                                           0x0 0x10000>;
394                                 isa@1e {
395                                         device_type = "isa";
396                                         #interrupt-cells = <2>;
397                                         #size-cells = <1>;
398                                         #address-cells = <2>;
399                                         reg = <0xf000 0x0 0x0 0x0 0x0>;
400                                         ranges = <0x1 0x0 0x1000000 0x0 0x0
401                                                   0x1000>;
402                                         interrupt-parent = <&i8259>;
403
404                                         i8259: interrupt-controller@20 {
405                                                 reg = <0x1 0x20 0x2
406                                                        0x1 0xa0 0x2
407                                                        0x1 0x4d0 0x2>;
408                                                 interrupt-controller;
409                                                 device_type = "interrupt-controller";
410                                                 #address-cells = <0>;
411                                                 #interrupt-cells = <2>;
412                                                 compatible = "chrp,iic";
413                                                 interrupts = <9 2>;
414                                                 interrupt-parent = <&mpic>;
415                                         };
416
417                                         i8042@60 {
418                                                 #size-cells = <0>;
419                                                 #address-cells = <1>;
420                                                 reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
421                                                 interrupts = <1 3 12 3>;
422                                                 interrupt-parent =
423                                                         <&i8259>;
424
425                                                 keyboard@0 {
426                                                         reg = <0x0>;
427                                                         compatible = "pnpPNP,303";
428                                                 };
429
430                                                 mouse@1 {
431                                                         reg = <0x1>;
432                                                         compatible = "pnpPNP,f03";
433                                                 };
434                                         };
435
436                                         rtc@70 {
437                                                 compatible = "pnpPNP,b00";
438                                                 reg = <0x1 0x70 0x2>;
439                                         };
440
441                                         gpio@400 {
442                                                 reg = <0x1 0x400 0x80>;
443                                         };
444                                 };
445                         };
446                 };
447
448         };
449
450         pci1: pcie@ffe09000 {
451                 cell-index = <1>;
452                 compatible = "fsl,mpc8548-pcie";
453                 device_type = "pci";
454                 #interrupt-cells = <1>;
455                 #size-cells = <2>;
456                 #address-cells = <3>;
457                 reg = <0xffe09000 0x1000>;
458                 bus-range = <0 255>;
459                 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
460                           0x1000000 0x0 0x0 0xffc10000 0x0 0x10000>;
461                 clock-frequency = <33333333>;
462                 interrupt-parent = <&mpic>;
463                 interrupts = <25 2>;
464                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
465                 interrupt-map = <
466                         /* IDSEL 0x0 */
467                         0000 0x0 0x0 0x1 &mpic 0x4 0x1
468                         0000 0x0 0x0 0x2 &mpic 0x5 0x1
469                         0000 0x0 0x0 0x3 &mpic 0x6 0x1
470                         0000 0x0 0x0 0x4 &mpic 0x7 0x1
471                         >;
472                 pcie@0 {
473                         reg = <0x0 0x0 0x0 0x0 0x0>;
474                         #size-cells = <2>;
475                         #address-cells = <3>;
476                         device_type = "pci";
477                         ranges = <0x2000000 0x0 0xa0000000
478                                   0x2000000 0x0 0xa0000000
479                                   0x0 0x20000000
480
481                                   0x1000000 0x0 0x0
482                                   0x1000000 0x0 0x0
483                                   0x0 0x10000>;
484                 };
485         };
486 };