Merge git://git.infradead.org/iommu-2.6
[linux-2.6] / arch / powerpc / boot / dts / virtex440-ml507.dts
1 /*
2  * This file supports the Xilinx ML507 board with the 440 processor.
3  * A reference design for the FPGA is provided at http://git.xilinx.com.
4  *
5  * (C) Copyright 2008 Xilinx, Inc.
6  *
7  * This file is licensed under the terms of the GNU General Public License
8  * version 2. This program is licensed "as is" without any warranty of any
9  * kind, whether express or implied.
10  *
11  * ---
12  *
13  * Device Tree Generator version: 1.1
14  *
15  * CAUTION: This file is automatically generated by libgen.
16  * Version: Xilinx EDK 10.1.03 EDK_K_SP3.6
17  *
18  * XPS project directory: ml507_ppc440_emb_ref
19  */
20
21 /dts-v1/;
22
23 / {
24         #address-cells = <1>;
25         #size-cells = <1>;
26         compatible = "xlnx,virtex440";
27         dcr-parent = <&ppc440_0>;
28         model = "testing";
29         DDR2_SDRAM: memory@0 {
30                 device_type = "memory";
31                 reg = < 0 0x10000000 >;
32         } ;
33         chosen {
34                 bootargs = "console=ttyS0 root=/dev/ram";
35                 linux,stdout-path = &RS232_Uart_1;
36         } ;
37         cpus {
38                 #address-cells = <1>;
39                 #cpus = <1>;
40                 #size-cells = <0>;
41                 ppc440_0: cpu@0 {
42                         clock-frequency = <400000000>;
43                         compatible = "PowerPC,440", "ibm,ppc440";
44                         d-cache-line-size = <0x20>;
45                         d-cache-size = <0x8000>;
46                         dcr-access-method = "native";
47                         dcr-controller ;
48                         device_type = "cpu";
49                         i-cache-line-size = <0x20>;
50                         i-cache-size = <0x8000>;
51                         model = "PowerPC,440";
52                         reg = <0>;
53                         timebase-frequency = <400000000>;
54                         xlnx,apu-control = <1>;
55                         xlnx,apu-udi-0 = <0>;
56                         xlnx,apu-udi-1 = <0>;
57                         xlnx,apu-udi-10 = <0>;
58                         xlnx,apu-udi-11 = <0>;
59                         xlnx,apu-udi-12 = <0>;
60                         xlnx,apu-udi-13 = <0>;
61                         xlnx,apu-udi-14 = <0>;
62                         xlnx,apu-udi-15 = <0>;
63                         xlnx,apu-udi-2 = <0>;
64                         xlnx,apu-udi-3 = <0>;
65                         xlnx,apu-udi-4 = <0>;
66                         xlnx,apu-udi-5 = <0>;
67                         xlnx,apu-udi-6 = <0>;
68                         xlnx,apu-udi-7 = <0>;
69                         xlnx,apu-udi-8 = <0>;
70                         xlnx,apu-udi-9 = <0>;
71                         xlnx,dcr-autolock-enable = <1>;
72                         xlnx,dcu-rd-ld-cache-plb-prio = <0>;
73                         xlnx,dcu-rd-noncache-plb-prio = <0>;
74                         xlnx,dcu-rd-touch-plb-prio = <0>;
75                         xlnx,dcu-rd-urgent-plb-prio = <0>;
76                         xlnx,dcu-wr-flush-plb-prio = <0>;
77                         xlnx,dcu-wr-store-plb-prio = <0>;
78                         xlnx,dcu-wr-urgent-plb-prio = <0>;
79                         xlnx,dma0-control = <0>;
80                         xlnx,dma0-plb-prio = <0>;
81                         xlnx,dma0-rxchannelctrl = <0x1010000>;
82                         xlnx,dma0-rxirqtimer = <0x3ff>;
83                         xlnx,dma0-txchannelctrl = <0x1010000>;
84                         xlnx,dma0-txirqtimer = <0x3ff>;
85                         xlnx,dma1-control = <0>;
86                         xlnx,dma1-plb-prio = <0>;
87                         xlnx,dma1-rxchannelctrl = <0x1010000>;
88                         xlnx,dma1-rxirqtimer = <0x3ff>;
89                         xlnx,dma1-txchannelctrl = <0x1010000>;
90                         xlnx,dma1-txirqtimer = <0x3ff>;
91                         xlnx,dma2-control = <0>;
92                         xlnx,dma2-plb-prio = <0>;
93                         xlnx,dma2-rxchannelctrl = <0x1010000>;
94                         xlnx,dma2-rxirqtimer = <0x3ff>;
95                         xlnx,dma2-txchannelctrl = <0x1010000>;
96                         xlnx,dma2-txirqtimer = <0x3ff>;
97                         xlnx,dma3-control = <0>;
98                         xlnx,dma3-plb-prio = <0>;
99                         xlnx,dma3-rxchannelctrl = <0x1010000>;
100                         xlnx,dma3-rxirqtimer = <0x3ff>;
101                         xlnx,dma3-txchannelctrl = <0x1010000>;
102                         xlnx,dma3-txirqtimer = <0x3ff>;
103                         xlnx,endian-reset = <0>;
104                         xlnx,generate-plb-timespecs = <1>;
105                         xlnx,icu-rd-fetch-plb-prio = <0>;
106                         xlnx,icu-rd-spec-plb-prio = <0>;
107                         xlnx,icu-rd-touch-plb-prio = <0>;
108                         xlnx,interconnect-imask = <0xffffffff>;
109                         xlnx,mplb-allow-lock-xfer = <1>;
110                         xlnx,mplb-arb-mode = <0>;
111                         xlnx,mplb-awidth = <0x20>;
112                         xlnx,mplb-counter = <0x500>;
113                         xlnx,mplb-dwidth = <0x80>;
114                         xlnx,mplb-max-burst = <8>;
115                         xlnx,mplb-native-dwidth = <0x80>;
116                         xlnx,mplb-p2p = <0>;
117                         xlnx,mplb-prio-dcur = <2>;
118                         xlnx,mplb-prio-dcuw = <3>;
119                         xlnx,mplb-prio-icu = <4>;
120                         xlnx,mplb-prio-splb0 = <1>;
121                         xlnx,mplb-prio-splb1 = <0>;
122                         xlnx,mplb-read-pipe-enable = <1>;
123                         xlnx,mplb-sync-tattribute = <0>;
124                         xlnx,mplb-wdog-enable = <1>;
125                         xlnx,mplb-write-pipe-enable = <1>;
126                         xlnx,mplb-write-post-enable = <1>;
127                         xlnx,num-dma = <1>;
128                         xlnx,pir = <0xf>;
129                         xlnx,ppc440mc-addr-base = <0>;
130                         xlnx,ppc440mc-addr-high = <0xfffffff>;
131                         xlnx,ppc440mc-arb-mode = <0>;
132                         xlnx,ppc440mc-bank-conflict-mask = <0xc00000>;
133                         xlnx,ppc440mc-control = <0xf810008f>;
134                         xlnx,ppc440mc-max-burst = <8>;
135                         xlnx,ppc440mc-prio-dcur = <2>;
136                         xlnx,ppc440mc-prio-dcuw = <3>;
137                         xlnx,ppc440mc-prio-icu = <4>;
138                         xlnx,ppc440mc-prio-splb0 = <1>;
139                         xlnx,ppc440mc-prio-splb1 = <0>;
140                         xlnx,ppc440mc-row-conflict-mask = <0x3ffe00>;
141                         xlnx,ppcdm-asyncmode = <0>;
142                         xlnx,ppcds-asyncmode = <0>;
143                         xlnx,user-reset = <0>;
144                         DMA0: sdma@80 {
145                                 compatible = "xlnx,ll-dma-1.00.a";
146                                 dcr-reg = < 0x80 0x11 >;
147                                 interrupt-parent = <&xps_intc_0>;
148                                 interrupts = < 10 2 11 2 >;
149                         } ;
150                 } ;
151         } ;
152         plb_v46_0: plb@0 {
153                 #address-cells = <1>;
154                 #size-cells = <1>;
155                 compatible = "xlnx,plb-v46-1.03.a", "simple-bus";
156                 ranges ;
157                 DIP_Switches_8Bit: gpio@81460000 {
158                         compatible = "xlnx,xps-gpio-1.00.a";
159                         interrupt-parent = <&xps_intc_0>;
160                         interrupts = < 7 2 >;
161                         reg = < 0x81460000 0x10000 >;
162                         xlnx,all-inputs = <1>;
163                         xlnx,all-inputs-2 = <0>;
164                         xlnx,dout-default = <0>;
165                         xlnx,dout-default-2 = <0>;
166                         xlnx,family = "virtex5";
167                         xlnx,gpio-width = <8>;
168                         xlnx,interrupt-present = <1>;
169                         xlnx,is-bidir = <1>;
170                         xlnx,is-bidir-2 = <1>;
171                         xlnx,is-dual = <0>;
172                         xlnx,tri-default = <0xffffffff>;
173                         xlnx,tri-default-2 = <0xffffffff>;
174                 } ;
175                 FLASH: flash@fc000000 {
176                         bank-width = <2>;
177                         compatible = "xlnx,xps-mch-emc-2.00.a", "cfi-flash";
178                         reg = < 0xfc000000 0x2000000 >;
179                         xlnx,family = "virtex5";
180                         xlnx,include-datawidth-matching-0 = <0x1>;
181                         xlnx,include-datawidth-matching-1 = <0x0>;
182                         xlnx,include-datawidth-matching-2 = <0x0>;
183                         xlnx,include-datawidth-matching-3 = <0x0>;
184                         xlnx,include-negedge-ioregs = <0x0>;
185                         xlnx,include-plb-ipif = <0x1>;
186                         xlnx,include-wrbuf = <0x1>;
187                         xlnx,max-mem-width = <0x10>;
188                         xlnx,mch-native-dwidth = <0x20>;
189                         xlnx,mch-plb-clk-period-ps = <0x2710>;
190                         xlnx,mch-splb-awidth = <0x20>;
191                         xlnx,mch0-accessbuf-depth = <0x10>;
192                         xlnx,mch0-protocol = <0x0>;
193                         xlnx,mch0-rddatabuf-depth = <0x10>;
194                         xlnx,mch1-accessbuf-depth = <0x10>;
195                         xlnx,mch1-protocol = <0x0>;
196                         xlnx,mch1-rddatabuf-depth = <0x10>;
197                         xlnx,mch2-accessbuf-depth = <0x10>;
198                         xlnx,mch2-protocol = <0x0>;
199                         xlnx,mch2-rddatabuf-depth = <0x10>;
200                         xlnx,mch3-accessbuf-depth = <0x10>;
201                         xlnx,mch3-protocol = <0x0>;
202                         xlnx,mch3-rddatabuf-depth = <0x10>;
203                         xlnx,mem0-width = <0x10>;
204                         xlnx,mem1-width = <0x20>;
205                         xlnx,mem2-width = <0x20>;
206                         xlnx,mem3-width = <0x20>;
207                         xlnx,num-banks-mem = <0x1>;
208                         xlnx,num-channels = <0x2>;
209                         xlnx,priority-mode = <0x0>;
210                         xlnx,synch-mem-0 = <0x0>;
211                         xlnx,synch-mem-1 = <0x0>;
212                         xlnx,synch-mem-2 = <0x0>;
213                         xlnx,synch-mem-3 = <0x0>;
214                         xlnx,synch-pipedelay-0 = <0x2>;
215                         xlnx,synch-pipedelay-1 = <0x2>;
216                         xlnx,synch-pipedelay-2 = <0x2>;
217                         xlnx,synch-pipedelay-3 = <0x2>;
218                         xlnx,tavdv-ps-mem-0 = <0x1adb0>;
219                         xlnx,tavdv-ps-mem-1 = <0x3a98>;
220                         xlnx,tavdv-ps-mem-2 = <0x3a98>;
221                         xlnx,tavdv-ps-mem-3 = <0x3a98>;
222                         xlnx,tcedv-ps-mem-0 = <0x1adb0>;
223                         xlnx,tcedv-ps-mem-1 = <0x3a98>;
224                         xlnx,tcedv-ps-mem-2 = <0x3a98>;
225                         xlnx,tcedv-ps-mem-3 = <0x3a98>;
226                         xlnx,thzce-ps-mem-0 = <0x88b8>;
227                         xlnx,thzce-ps-mem-1 = <0x1b58>;
228                         xlnx,thzce-ps-mem-2 = <0x1b58>;
229                         xlnx,thzce-ps-mem-3 = <0x1b58>;
230                         xlnx,thzoe-ps-mem-0 = <0x1b58>;
231                         xlnx,thzoe-ps-mem-1 = <0x1b58>;
232                         xlnx,thzoe-ps-mem-2 = <0x1b58>;
233                         xlnx,thzoe-ps-mem-3 = <0x1b58>;
234                         xlnx,tlzwe-ps-mem-0 = <0x88b8>;
235                         xlnx,tlzwe-ps-mem-1 = <0x0>;
236                         xlnx,tlzwe-ps-mem-2 = <0x0>;
237                         xlnx,tlzwe-ps-mem-3 = <0x0>;
238                         xlnx,twc-ps-mem-0 = <0x2af8>;
239                         xlnx,twc-ps-mem-1 = <0x3a98>;
240                         xlnx,twc-ps-mem-2 = <0x3a98>;
241                         xlnx,twc-ps-mem-3 = <0x3a98>;
242                         xlnx,twp-ps-mem-0 = <0x11170>;
243                         xlnx,twp-ps-mem-1 = <0x2ee0>;
244                         xlnx,twp-ps-mem-2 = <0x2ee0>;
245                         xlnx,twp-ps-mem-3 = <0x2ee0>;
246                         xlnx,xcl0-linesize = <0x4>;
247                         xlnx,xcl0-writexfer = <0x1>;
248                         xlnx,xcl1-linesize = <0x4>;
249                         xlnx,xcl1-writexfer = <0x1>;
250                         xlnx,xcl2-linesize = <0x4>;
251                         xlnx,xcl2-writexfer = <0x1>;
252                         xlnx,xcl3-linesize = <0x4>;
253                         xlnx,xcl3-writexfer = <0x1>;
254                 } ;
255                 Hard_Ethernet_MAC: xps-ll-temac@81c00000 {
256                         #address-cells = <1>;
257                         #size-cells = <1>;
258                         compatible = "xlnx,compound";
259                         ethernet@81c00000 {
260                                 compatible = "xlnx,xps-ll-temac-1.01.b";
261                                 device_type = "network";
262                                 interrupt-parent = <&xps_intc_0>;
263                                 interrupts = < 5 2 >;
264                                 llink-connected = <&DMA0>;
265                                 local-mac-address = [ 02 00 00 00 00 00 ];
266                                 reg = < 0x81c00000 0x40 >;
267                                 xlnx,bus2core-clk-ratio = <1>;
268                                 xlnx,phy-type = <1>;
269                                 xlnx,phyaddr = <1>;
270                                 xlnx,rxcsum = <1>;
271                                 xlnx,rxfifo = <0x1000>;
272                                 xlnx,temac-type = <0>;
273                                 xlnx,txcsum = <1>;
274                                 xlnx,txfifo = <0x1000>;
275                         } ;
276                 } ;
277                 IIC_EEPROM: i2c@81600000 {
278                         compatible = "xlnx,xps-iic-2.00.a";
279                         interrupt-parent = <&xps_intc_0>;
280                         interrupts = < 6 2 >;
281                         reg = < 0x81600000 0x10000 >;
282                         xlnx,clk-freq = <0x5f5e100>;
283                         xlnx,family = "virtex5";
284                         xlnx,gpo-width = <0x1>;
285                         xlnx,iic-freq = <0x186a0>;
286                         xlnx,scl-inertial-delay = <0x0>;
287                         xlnx,sda-inertial-delay = <0x0>;
288                         xlnx,ten-bit-adr = <0x0>;
289                 } ;
290                 LEDs_8Bit: gpio@81400000 {
291                         compatible = "xlnx,xps-gpio-1.00.a";
292                         reg = < 0x81400000 0x10000 >;
293                         xlnx,all-inputs = <0>;
294                         xlnx,all-inputs-2 = <0>;
295                         xlnx,dout-default = <0>;
296                         xlnx,dout-default-2 = <0>;
297                         xlnx,family = "virtex5";
298                         xlnx,gpio-width = <8>;
299                         xlnx,interrupt-present = <0>;
300                         xlnx,is-bidir = <1>;
301                         xlnx,is-bidir-2 = <1>;
302                         xlnx,is-dual = <0>;
303                         xlnx,tri-default = <0xffffffff>;
304                         xlnx,tri-default-2 = <0xffffffff>;
305                 } ;
306                 LEDs_Positions: gpio@81420000 {
307                         compatible = "xlnx,xps-gpio-1.00.a";
308                         reg = < 0x81420000 0x10000 >;
309                         xlnx,all-inputs = <0>;
310                         xlnx,all-inputs-2 = <0>;
311                         xlnx,dout-default = <0>;
312                         xlnx,dout-default-2 = <0>;
313                         xlnx,family = "virtex5";
314                         xlnx,gpio-width = <5>;
315                         xlnx,interrupt-present = <0>;
316                         xlnx,is-bidir = <1>;
317                         xlnx,is-bidir-2 = <1>;
318                         xlnx,is-dual = <0>;
319                         xlnx,tri-default = <0xffffffff>;
320                         xlnx,tri-default-2 = <0xffffffff>;
321                 } ;
322                 Push_Buttons_5Bit: gpio@81440000 {
323                         compatible = "xlnx,xps-gpio-1.00.a";
324                         interrupt-parent = <&xps_intc_0>;
325                         interrupts = < 8 2 >;
326                         reg = < 0x81440000 0x10000 >;
327                         xlnx,all-inputs = <1>;
328                         xlnx,all-inputs-2 = <0>;
329                         xlnx,dout-default = <0>;
330                         xlnx,dout-default-2 = <0>;
331                         xlnx,family = "virtex5";
332                         xlnx,gpio-width = <5>;
333                         xlnx,interrupt-present = <1>;
334                         xlnx,is-bidir = <1>;
335                         xlnx,is-bidir-2 = <1>;
336                         xlnx,is-dual = <0>;
337                         xlnx,tri-default = <0xffffffff>;
338                         xlnx,tri-default-2 = <0xffffffff>;
339                 } ;
340                 RS232_Uart_1: serial@83e00000 {
341                         clock-frequency = <100000000>;
342                         compatible = "xlnx,xps-uart16550-2.00.b", "ns16550";
343                         current-speed = <9600>;
344                         device_type = "serial";
345                         interrupt-parent = <&xps_intc_0>;
346                         interrupts = < 9 2 >;
347                         reg = < 0x83e00000 0x10000 >;
348                         reg-offset = <0x1003>;
349                         reg-shift = <2>;
350                         xlnx,family = "virtex5";
351                         xlnx,has-external-rclk = <0>;
352                         xlnx,has-external-xin = <0>;
353                         xlnx,is-a-16550 = <1>;
354                 } ;
355                 SysACE_CompactFlash: sysace@83600000 {
356                         compatible = "xlnx,xps-sysace-1.00.a";
357                         interrupt-parent = <&xps_intc_0>;
358                         interrupts = < 4 2 >;
359                         reg = < 0x83600000 0x10000 >;
360                         xlnx,family = "virtex5";
361                         xlnx,mem-width = <0x10>;
362                 } ;
363                 xps_bram_if_cntlr_1: xps-bram-if-cntlr@ffff0000 {
364                         compatible = "xlnx,xps-bram-if-cntlr-1.00.a";
365                         reg = < 0xffff0000 0x10000 >;
366                         xlnx,family = "virtex5";
367                 } ;
368                 xps_intc_0: interrupt-controller@81800000 {
369                         #interrupt-cells = <2>;
370                         compatible = "xlnx,xps-intc-1.00.a";
371                         interrupt-controller ;
372                         reg = < 0x81800000 0x10000 >;
373                         xlnx,num-intr-inputs = <0xc>;
374                 } ;
375                 xps_timebase_wdt_1: xps-timebase-wdt@83a00000 {
376                         compatible = "xlnx,xps-timebase-wdt-1.00.b";
377                         interrupt-parent = <&xps_intc_0>;
378                         interrupts = < 2 0 1 2 >;
379                         reg = < 0x83a00000 0x10000 >;
380                         xlnx,family = "virtex5";
381                         xlnx,wdt-enable-once = <0>;
382                         xlnx,wdt-interval = <0x1e>;
383                 } ;
384                 xps_timer_1: timer@83c00000 {
385                         compatible = "xlnx,xps-timer-1.00.a";
386                         interrupt-parent = <&xps_intc_0>;
387                         interrupts = < 3 2 >;
388                         reg = < 0x83c00000 0x10000 >;
389                         xlnx,count-width = <0x20>;
390                         xlnx,family = "virtex5";
391                         xlnx,gen0-assert = <1>;
392                         xlnx,gen1-assert = <1>;
393                         xlnx,one-timer-only = <1>;
394                         xlnx,trig0-assert = <1>;
395                         xlnx,trig1-assert = <1>;
396                 } ;
397         } ;
398 }  ;