2 * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor,
17 * Boston, MA 02110-1301, USA.
20 #include <linux/dma-mapping.h>
21 #include <linux/module.h>
22 #include <linux/platform_device.h>
23 #include <linux/serial.h>
24 #include <linux/gpio.h>
25 #include <mach/hardware.h>
26 #include <mach/irqs.h>
27 #include <mach/common.h>
28 #include <mach/imx-uart.h>
29 #include <mach/mx3_camera.h>
33 static struct resource uart0[] = {
35 .start = UART1_BASE_ADDR,
36 .end = UART1_BASE_ADDR + 0x0B5,
37 .flags = IORESOURCE_MEM,
39 .start = MXC_INT_UART1,
41 .flags = IORESOURCE_IRQ,
45 struct platform_device mxc_uart_device0 = {
49 .num_resources = ARRAY_SIZE(uart0),
52 static struct resource uart1[] = {
54 .start = UART2_BASE_ADDR,
55 .end = UART2_BASE_ADDR + 0x0B5,
56 .flags = IORESOURCE_MEM,
58 .start = MXC_INT_UART2,
60 .flags = IORESOURCE_IRQ,
64 struct platform_device mxc_uart_device1 = {
68 .num_resources = ARRAY_SIZE(uart1),
71 static struct resource uart2[] = {
73 .start = UART3_BASE_ADDR,
74 .end = UART3_BASE_ADDR + 0x0B5,
75 .flags = IORESOURCE_MEM,
77 .start = MXC_INT_UART3,
79 .flags = IORESOURCE_IRQ,
83 struct platform_device mxc_uart_device2 = {
87 .num_resources = ARRAY_SIZE(uart2),
90 #ifdef CONFIG_ARCH_MX31
91 static struct resource uart3[] = {
93 .start = UART4_BASE_ADDR,
94 .end = UART4_BASE_ADDR + 0x0B5,
95 .flags = IORESOURCE_MEM,
97 .start = MXC_INT_UART4,
99 .flags = IORESOURCE_IRQ,
103 struct platform_device mxc_uart_device3 = {
107 .num_resources = ARRAY_SIZE(uart3),
110 static struct resource uart4[] = {
112 .start = UART5_BASE_ADDR,
113 .end = UART5_BASE_ADDR + 0x0B5,
114 .flags = IORESOURCE_MEM,
116 .start = MXC_INT_UART5,
117 .end = MXC_INT_UART5,
118 .flags = IORESOURCE_IRQ,
122 struct platform_device mxc_uart_device4 = {
126 .num_resources = ARRAY_SIZE(uart4),
128 #endif /* CONFIG_ARCH_MX31 */
130 /* GPIO port description */
131 static struct mxc_gpio_port imx_gpio_ports[] = {
133 .chip.label = "gpio-0",
134 .base = IO_ADDRESS(GPIO1_BASE_ADDR),
135 .irq = MXC_INT_GPIO1,
136 .virtual_irq_start = MXC_GPIO_IRQ_START,
139 .chip.label = "gpio-1",
140 .base = IO_ADDRESS(GPIO2_BASE_ADDR),
141 .irq = MXC_INT_GPIO2,
142 .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
145 .chip.label = "gpio-2",
146 .base = IO_ADDRESS(GPIO3_BASE_ADDR),
147 .irq = MXC_INT_GPIO3,
148 .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
152 int __init mxc_register_gpios(void)
154 return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
157 static struct resource mxc_w1_master_resources[] = {
159 .start = OWIRE_BASE_ADDR,
160 .end = OWIRE_BASE_ADDR + SZ_4K - 1,
161 .flags = IORESOURCE_MEM,
165 struct platform_device mxc_w1_master_device = {
168 .num_resources = ARRAY_SIZE(mxc_w1_master_resources),
169 .resource = mxc_w1_master_resources,
172 static struct resource mxc_nand_resources[] = {
174 .start = 0, /* runtime dependent */
176 .flags = IORESOURCE_MEM
178 .start = MXC_INT_NANDFC,
179 .end = MXC_INT_NANDFC,
180 .flags = IORESOURCE_IRQ
184 struct platform_device mxc_nand_device = {
187 .num_resources = ARRAY_SIZE(mxc_nand_resources),
188 .resource = mxc_nand_resources,
191 static struct resource mxc_i2c0_resources[] = {
193 .start = I2C_BASE_ADDR,
194 .end = I2C_BASE_ADDR + SZ_4K - 1,
195 .flags = IORESOURCE_MEM,
198 .start = MXC_INT_I2C,
200 .flags = IORESOURCE_IRQ,
204 struct platform_device mxc_i2c_device0 = {
207 .num_resources = ARRAY_SIZE(mxc_i2c0_resources),
208 .resource = mxc_i2c0_resources,
211 static struct resource mxc_i2c1_resources[] = {
213 .start = I2C2_BASE_ADDR,
214 .end = I2C2_BASE_ADDR + SZ_4K - 1,
215 .flags = IORESOURCE_MEM,
218 .start = MXC_INT_I2C2,
220 .flags = IORESOURCE_IRQ,
224 struct platform_device mxc_i2c_device1 = {
227 .num_resources = ARRAY_SIZE(mxc_i2c1_resources),
228 .resource = mxc_i2c1_resources,
231 static struct resource mxc_i2c2_resources[] = {
233 .start = I2C3_BASE_ADDR,
234 .end = I2C3_BASE_ADDR + SZ_4K - 1,
235 .flags = IORESOURCE_MEM,
238 .start = MXC_INT_I2C3,
240 .flags = IORESOURCE_IRQ,
244 struct platform_device mxc_i2c_device2 = {
247 .num_resources = ARRAY_SIZE(mxc_i2c2_resources),
248 .resource = mxc_i2c2_resources,
251 #ifdef CONFIG_ARCH_MX31
252 static struct resource mxcsdhc0_resources[] = {
254 .start = MMC_SDHC1_BASE_ADDR,
255 .end = MMC_SDHC1_BASE_ADDR + SZ_16K - 1,
256 .flags = IORESOURCE_MEM,
258 .start = MXC_INT_MMC_SDHC1,
259 .end = MXC_INT_MMC_SDHC1,
260 .flags = IORESOURCE_IRQ,
264 static struct resource mxcsdhc1_resources[] = {
266 .start = MMC_SDHC2_BASE_ADDR,
267 .end = MMC_SDHC2_BASE_ADDR + SZ_16K - 1,
268 .flags = IORESOURCE_MEM,
270 .start = MXC_INT_MMC_SDHC2,
271 .end = MXC_INT_MMC_SDHC2,
272 .flags = IORESOURCE_IRQ,
276 struct platform_device mxcsdhc_device0 = {
279 .num_resources = ARRAY_SIZE(mxcsdhc0_resources),
280 .resource = mxcsdhc0_resources,
283 struct platform_device mxcsdhc_device1 = {
286 .num_resources = ARRAY_SIZE(mxcsdhc1_resources),
287 .resource = mxcsdhc1_resources,
290 static struct resource rnga_resources[] = {
292 .start = RNGA_BASE_ADDR,
293 .end = RNGA_BASE_ADDR + 0x28,
294 .flags = IORESOURCE_MEM,
298 struct platform_device mxc_rnga_device = {
302 .resource = rnga_resources,
304 #endif /* CONFIG_ARCH_MX31 */
306 /* i.MX31 Image Processing Unit */
308 /* The resource order is important! */
309 static struct resource mx3_ipu_rsrc[] = {
311 .start = IPU_CTRL_BASE_ADDR,
312 .end = IPU_CTRL_BASE_ADDR + 0x5F,
313 .flags = IORESOURCE_MEM,
315 .start = IPU_CTRL_BASE_ADDR + 0x88,
316 .end = IPU_CTRL_BASE_ADDR + 0xB3,
317 .flags = IORESOURCE_MEM,
319 .start = MXC_INT_IPU_SYN,
320 .end = MXC_INT_IPU_SYN,
321 .flags = IORESOURCE_IRQ,
323 .start = MXC_INT_IPU_ERR,
324 .end = MXC_INT_IPU_ERR,
325 .flags = IORESOURCE_IRQ,
329 struct platform_device mx3_ipu = {
332 .num_resources = ARRAY_SIZE(mx3_ipu_rsrc),
333 .resource = mx3_ipu_rsrc,
336 static struct resource fb_resources[] = {
338 .start = IPU_CTRL_BASE_ADDR + 0xB4,
339 .end = IPU_CTRL_BASE_ADDR + 0x1BF,
340 .flags = IORESOURCE_MEM,
344 struct platform_device mx3_fb = {
345 .name = "mx3_sdc_fb",
347 .num_resources = ARRAY_SIZE(fb_resources),
348 .resource = fb_resources,
350 .coherent_dma_mask = DMA_BIT_MASK(32),
354 static struct resource camera_resources[] = {
356 .start = IPU_CTRL_BASE_ADDR + 0x60,
357 .end = IPU_CTRL_BASE_ADDR + 0x87,
358 .flags = IORESOURCE_MEM,
362 struct platform_device mx3_camera = {
363 .name = "mx3-camera",
365 .num_resources = ARRAY_SIZE(camera_resources),
366 .resource = camera_resources,
368 .coherent_dma_mask = DMA_BIT_MASK(32),
372 static struct resource otg_resources[] = {
374 .start = OTG_BASE_ADDR,
375 .end = OTG_BASE_ADDR + 0x1ff,
376 .flags = IORESOURCE_MEM,
378 .start = MXC_INT_USB3,
380 .flags = IORESOURCE_IRQ,
384 static u64 otg_dmamask = DMA_BIT_MASK(32);
386 /* OTG gadget device */
387 struct platform_device mxc_otg_udc_device = {
388 .name = "fsl-usb2-udc",
391 .dma_mask = &otg_dmamask,
392 .coherent_dma_mask = DMA_BIT_MASK(32),
394 .resource = otg_resources,
395 .num_resources = ARRAY_SIZE(otg_resources),
398 #ifdef CONFIG_ARCH_MX35
399 static struct resource mxc_fec_resources[] = {
401 .start = MXC_FEC_BASE_ADDR,
402 .end = MXC_FEC_BASE_ADDR + 0xfff,
403 .flags = IORESOURCE_MEM
405 .start = MXC_INT_FEC,
407 .flags = IORESOURCE_IRQ
411 struct platform_device mxc_fec_device = {
414 .num_resources = ARRAY_SIZE(mxc_fec_resources),
415 .resource = mxc_fec_resources,
419 static int mx3_devices_init(void)
422 mxc_nand_resources[0].start = MX31_NFC_BASE_ADDR;
423 mxc_nand_resources[0].end = MX31_NFC_BASE_ADDR + 0xfff;
424 mxc_register_device(&mxc_rnga_device, NULL);
427 mxc_nand_resources[0].start = MX35_NFC_BASE_ADDR;
428 mxc_nand_resources[0].end = MX35_NFC_BASE_ADDR + 0xfff;
434 subsys_initcall(mx3_devices_init);