2 i2c-i801.c - Part of lm_sensors, Linux kernel modules for hardware
4 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
5 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 SUPPORTED DEVICES PCI ID
29 82801DB 24C3 (HW PEC supported, 32 byte buffer not supported)
30 82801EB 24D3 (HW PEC supported, 32 byte buffer not supported)
37 This driver supports several versions of Intel's I/O Controller Hubs (ICH).
38 For SMBus support, they are similar to the PIIX4 and are part
39 of Intel's '810' and other chipsets.
40 See the file Documentation/i2c/busses/i2c-i801 for details.
41 I2C Block Read and Process Call are not supported.
44 /* Note: we assume there can only be one I801, with one SMBus interface */
46 #include <linux/module.h>
47 #include <linux/pci.h>
48 #include <linux/kernel.h>
49 #include <linux/stddef.h>
50 #include <linux/delay.h>
51 #include <linux/ioport.h>
52 #include <linux/init.h>
53 #include <linux/i2c.h>
56 /* I801 SMBus address offsets */
57 #define SMBHSTSTS (0 + i801_smba)
58 #define SMBHSTCNT (2 + i801_smba)
59 #define SMBHSTCMD (3 + i801_smba)
60 #define SMBHSTADD (4 + i801_smba)
61 #define SMBHSTDAT0 (5 + i801_smba)
62 #define SMBHSTDAT1 (6 + i801_smba)
63 #define SMBBLKDAT (7 + i801_smba)
64 #define SMBPEC (8 + i801_smba) /* ICH4 only */
65 #define SMBAUXSTS (12 + i801_smba) /* ICH4 only */
66 #define SMBAUXCTL (13 + i801_smba) /* ICH4 only */
68 /* PCI Address Constants */
70 #define SMBHSTCFG 0x040
72 /* Host configuration bits for SMBHSTCFG */
73 #define SMBHSTCFG_HST_EN 1
74 #define SMBHSTCFG_SMB_SMI_EN 2
75 #define SMBHSTCFG_I2C_EN 4
77 /* Auxillary control register bits, ICH4+ only */
78 #define SMBAUXCTL_CRC 1
79 #define SMBAUXCTL_E32B 2
81 /* kill bit for SMBHSTCNT */
82 #define SMBHSTCNT_KILL 2
85 #define MAX_TIMEOUT 100
86 #define ENABLE_INT9 0 /* set to 0x01 to enable - untested */
88 /* I801 command constants */
89 #define I801_QUICK 0x00
90 #define I801_BYTE 0x04
91 #define I801_BYTE_DATA 0x08
92 #define I801_WORD_DATA 0x0C
93 #define I801_PROC_CALL 0x10 /* later chips only, unimplemented */
94 #define I801_BLOCK_DATA 0x14
95 #define I801_I2C_BLOCK_DATA 0x18 /* unimplemented */
96 #define I801_BLOCK_LAST 0x34
97 #define I801_I2C_BLOCK_LAST 0x38 /* unimplemented */
98 #define I801_START 0x40
99 #define I801_PEC_EN 0x80 /* ICH4 only */
101 /* I801 Hosts Status register bits */
102 #define SMBHSTSTS_BYTE_DONE 0x80
103 #define SMBHSTSTS_INUSE_STS 0x40
104 #define SMBHSTSTS_SMBALERT_STS 0x20
105 #define SMBHSTSTS_FAILED 0x10
106 #define SMBHSTSTS_BUS_ERR 0x08
107 #define SMBHSTSTS_DEV_ERR 0x04
108 #define SMBHSTSTS_INTR 0x02
109 #define SMBHSTSTS_HOST_BUSY 0x01
111 static unsigned long i801_smba;
112 static unsigned char i801_original_hstcfg;
113 static struct pci_driver i801_driver;
114 static struct pci_dev *I801_dev;
117 static int i801_transaction(void)
123 dev_dbg(&I801_dev->dev, "Transaction (pre): CNT=%02x, CMD=%02x, "
124 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
125 inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
128 /* Make sure the SMBus host is ready to start transmitting */
129 /* 0x1f = Failed, Bus_Err, Dev_Err, Intr, Host_Busy */
130 if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
131 dev_dbg(&I801_dev->dev, "SMBus busy (%02x). Resetting...\n",
133 outb_p(temp, SMBHSTSTS);
134 if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
135 dev_dbg(&I801_dev->dev, "Failed! (%02x)\n", temp);
138 dev_dbg(&I801_dev->dev, "Successful!\n");
142 outb_p(inb(SMBHSTCNT) | I801_START, SMBHSTCNT);
144 /* We will always wait for a fraction of a second! */
147 temp = inb_p(SMBHSTSTS);
148 } while ((temp & SMBHSTSTS_HOST_BUSY) && (timeout++ < MAX_TIMEOUT));
150 /* If the SMBus is still busy, we give up */
151 if (timeout >= MAX_TIMEOUT) {
152 dev_dbg(&I801_dev->dev, "SMBus Timeout!\n");
154 /* try to stop the current command */
155 dev_dbg(&I801_dev->dev, "Terminating the current operation\n");
156 outb_p(inb_p(SMBHSTCNT) | SMBHSTCNT_KILL, SMBHSTCNT);
158 outb_p(inb_p(SMBHSTCNT) & (~SMBHSTCNT_KILL), SMBHSTCNT);
161 if (temp & SMBHSTSTS_FAILED) {
163 dev_dbg(&I801_dev->dev, "Error: Failed bus transaction\n");
166 if (temp & SMBHSTSTS_BUS_ERR) {
168 dev_err(&I801_dev->dev, "Bus collision! SMBus may be locked "
169 "until next hard reset. (sorry!)\n");
170 /* Clock stops and slave is stuck in mid-transmission */
173 if (temp & SMBHSTSTS_DEV_ERR) {
175 dev_dbg(&I801_dev->dev, "Error: no response!\n");
178 if ((inb_p(SMBHSTSTS) & 0x1f) != 0x00)
179 outb_p(inb(SMBHSTSTS), SMBHSTSTS);
181 if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
182 dev_dbg(&I801_dev->dev, "Failed reset at end of transaction "
185 dev_dbg(&I801_dev->dev, "Transaction (post): CNT=%02x, CMD=%02x, "
186 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
187 inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
192 /* wait for INTR bit as advised by Intel */
193 static void i801_wait_hwpec(void)
200 temp = inb_p(SMBHSTSTS);
201 } while ((!(temp & SMBHSTSTS_INTR))
202 && (timeout++ < MAX_TIMEOUT));
204 if (timeout >= MAX_TIMEOUT) {
205 dev_dbg(&I801_dev->dev, "PEC Timeout!\n");
207 outb_p(temp, SMBHSTSTS);
210 /* All-inclusive block transaction function */
211 static int i801_block_transaction(union i2c_smbus_data *data, char read_write,
212 int command, int hwpec)
219 unsigned char hostc, errmask;
221 if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
222 if (read_write == I2C_SMBUS_WRITE) {
223 /* set I2C_EN bit in configuration register */
224 pci_read_config_byte(I801_dev, SMBHSTCFG, &hostc);
225 pci_write_config_byte(I801_dev, SMBHSTCFG,
226 hostc | SMBHSTCFG_I2C_EN);
228 dev_err(&I801_dev->dev,
229 "I2C_SMBUS_I2C_BLOCK_READ not DB!\n");
234 if (read_write == I2C_SMBUS_WRITE) {
235 len = data->block[0];
240 outb_p(len, SMBHSTDAT0);
241 outb_p(data->block[1], SMBBLKDAT);
243 len = 32; /* max for reads */
246 if(isich4 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
247 /* set 32 byte buffer */
250 for (i = 1; i <= len; i++) {
251 if (i == len && read_write == I2C_SMBUS_READ)
252 smbcmd = I801_BLOCK_LAST;
254 smbcmd = I801_BLOCK_DATA;
255 outb_p(smbcmd | ENABLE_INT9, SMBHSTCNT);
257 dev_dbg(&I801_dev->dev, "Block (pre %d): CNT=%02x, CMD=%02x, "
258 "ADD=%02x, DAT0=%02x, BLKDAT=%02x\n", i,
259 inb_p(SMBHSTCNT), inb_p(SMBHSTCMD), inb_p(SMBHSTADD),
260 inb_p(SMBHSTDAT0), inb_p(SMBBLKDAT));
262 /* Make sure the SMBus host is ready to start transmitting */
263 temp = inb_p(SMBHSTSTS);
265 /* Erronenous conditions before transaction:
266 * Byte_Done, Failed, Bus_Err, Dev_Err, Intr, Host_Busy */
269 /* Erronenous conditions during transaction:
270 * Failed, Bus_Err, Dev_Err, Intr */
273 if (temp & errmask) {
274 dev_dbg(&I801_dev->dev, "SMBus busy (%02x). "
275 "Resetting...\n", temp);
276 outb_p(temp, SMBHSTSTS);
277 if (((temp = inb_p(SMBHSTSTS)) & errmask) != 0x00) {
278 dev_err(&I801_dev->dev,
279 "Reset failed! (%02x)\n", temp);
284 /* if die in middle of block transaction, fail */
291 outb_p(inb(SMBHSTCNT) | I801_START, SMBHSTCNT);
293 /* We will always wait for a fraction of a second! */
297 temp = inb_p(SMBHSTSTS);
299 while ((!(temp & SMBHSTSTS_BYTE_DONE))
300 && (timeout++ < MAX_TIMEOUT));
302 /* If the SMBus is still busy, we give up */
303 if (timeout >= MAX_TIMEOUT) {
304 /* try to stop the current command */
305 dev_dbg(&I801_dev->dev, "Terminating the current "
307 outb_p(inb_p(SMBHSTCNT) | SMBHSTCNT_KILL, SMBHSTCNT);
309 outb_p(inb_p(SMBHSTCNT) & (~SMBHSTCNT_KILL),
312 dev_dbg(&I801_dev->dev, "SMBus Timeout!\n");
315 if (temp & SMBHSTSTS_FAILED) {
317 dev_dbg(&I801_dev->dev,
318 "Error: Failed bus transaction\n");
319 } else if (temp & SMBHSTSTS_BUS_ERR) {
321 dev_err(&I801_dev->dev, "Bus collision!\n");
322 } else if (temp & SMBHSTSTS_DEV_ERR) {
324 dev_dbg(&I801_dev->dev, "Error: no response!\n");
327 if (i == 1 && read_write == I2C_SMBUS_READ) {
328 len = inb_p(SMBHSTDAT0);
329 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
333 data->block[0] = len;
336 /* Retrieve/store value in SMBBLKDAT */
337 if (read_write == I2C_SMBUS_READ)
338 data->block[i] = inb_p(SMBBLKDAT);
339 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
340 outb_p(data->block[i+1], SMBBLKDAT);
341 if ((temp & 0x9e) != 0x00)
342 outb_p(temp, SMBHSTSTS); /* signals SMBBLKDAT ready */
344 if ((temp = (0x1e & inb_p(SMBHSTSTS))) != 0x00) {
345 dev_dbg(&I801_dev->dev,
346 "Bad status (%02x) at end of transaction\n",
349 dev_dbg(&I801_dev->dev, "Block (post %d): CNT=%02x, CMD=%02x, "
350 "ADD=%02x, DAT0=%02x, BLKDAT=%02x\n", i,
351 inb_p(SMBHSTCNT), inb_p(SMBHSTCMD), inb_p(SMBHSTADD),
352 inb_p(SMBHSTDAT0), inb_p(SMBBLKDAT));
363 if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
364 /* restore saved configuration register value */
365 pci_write_config_byte(I801_dev, SMBHSTCFG, hostc);
370 /* Return -1 on error. */
371 static s32 i801_access(struct i2c_adapter * adap, u16 addr,
372 unsigned short flags, char read_write, u8 command,
373 int size, union i2c_smbus_data * data)
379 hwpec = isich4 && (flags & I2C_CLIENT_PEC)
380 && size != I2C_SMBUS_QUICK
381 && size != I2C_SMBUS_I2C_BLOCK_DATA;
384 case I2C_SMBUS_QUICK:
385 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
390 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
392 if (read_write == I2C_SMBUS_WRITE)
393 outb_p(command, SMBHSTCMD);
396 case I2C_SMBUS_BYTE_DATA:
397 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
399 outb_p(command, SMBHSTCMD);
400 if (read_write == I2C_SMBUS_WRITE)
401 outb_p(data->byte, SMBHSTDAT0);
402 xact = I801_BYTE_DATA;
404 case I2C_SMBUS_WORD_DATA:
405 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
407 outb_p(command, SMBHSTCMD);
408 if (read_write == I2C_SMBUS_WRITE) {
409 outb_p(data->word & 0xff, SMBHSTDAT0);
410 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1);
412 xact = I801_WORD_DATA;
414 case I2C_SMBUS_BLOCK_DATA:
415 case I2C_SMBUS_I2C_BLOCK_DATA:
416 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
418 outb_p(command, SMBHSTCMD);
421 case I2C_SMBUS_PROC_CALL:
423 dev_err(&I801_dev->dev, "Unsupported transaction %d\n", size);
427 if (hwpec) /* enable/disable hardware PEC */
428 outb_p(inb_p(SMBAUXCTL) | SMBAUXCTL_CRC, SMBAUXCTL);
430 outb_p(inb_p(SMBAUXCTL) & (~SMBAUXCTL_CRC), SMBAUXCTL);
433 ret = i801_block_transaction(data, read_write, size, hwpec);
435 outb_p(xact | ENABLE_INT9, SMBHSTCNT);
436 ret = i801_transaction();
439 /* Some BIOSes don't like it when PEC is enabled at reboot or resume
440 time, so we forcibly disable it after every transaction. */
442 outb_p(inb_p(SMBAUXCTL) & (~SMBAUXCTL_CRC), SMBAUXCTL);
448 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
451 switch (xact & 0x7f) {
452 case I801_BYTE: /* Result put in SMBHSTDAT0 */
454 data->byte = inb_p(SMBHSTDAT0);
457 data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8);
464 static u32 i801_func(struct i2c_adapter *adapter)
466 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
467 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
468 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK
469 | (isich4 ? I2C_FUNC_SMBUS_HWPEC_CALC : 0);
472 static const struct i2c_algorithm smbus_algorithm = {
473 .smbus_xfer = i801_access,
474 .functionality = i801_func,
477 static struct i2c_adapter i801_adapter = {
478 .owner = THIS_MODULE,
479 .id = I2C_HW_SMBUS_I801,
480 .class = I2C_CLASS_HWMON,
481 .algo = &smbus_algorithm,
484 static struct pci_device_id i801_ids[] = {
485 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
486 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
487 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
488 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
489 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
490 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
491 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
492 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
493 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
494 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
495 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
496 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
500 MODULE_DEVICE_TABLE (pci, i801_ids);
502 static int __devinit i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
508 switch (dev->device) {
509 case PCI_DEVICE_ID_INTEL_82801DB_3:
510 case PCI_DEVICE_ID_INTEL_82801EB_3:
511 case PCI_DEVICE_ID_INTEL_ESB_4:
512 case PCI_DEVICE_ID_INTEL_ICH6_16:
513 case PCI_DEVICE_ID_INTEL_ICH7_17:
514 case PCI_DEVICE_ID_INTEL_ESB2_17:
515 case PCI_DEVICE_ID_INTEL_ICH8_5:
516 case PCI_DEVICE_ID_INTEL_ICH9_6:
523 err = pci_enable_device(dev);
525 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
530 /* Determine the address of the SMBus area */
531 i801_smba = pci_resource_start(dev, SMBBAR);
533 dev_err(&dev->dev, "SMBus base address uninitialized, "
539 err = pci_request_region(dev, SMBBAR, i801_driver.name);
541 dev_err(&dev->dev, "Failed to request SMBus region "
542 "0x%lx-0x%Lx\n", i801_smba,
543 (unsigned long long)pci_resource_end(dev, SMBBAR));
547 pci_read_config_byte(I801_dev, SMBHSTCFG, &temp);
548 i801_original_hstcfg = temp;
549 temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
550 if (!(temp & SMBHSTCFG_HST_EN)) {
551 dev_info(&dev->dev, "Enabling SMBus device\n");
552 temp |= SMBHSTCFG_HST_EN;
554 pci_write_config_byte(I801_dev, SMBHSTCFG, temp);
556 if (temp & SMBHSTCFG_SMB_SMI_EN)
557 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
559 dev_dbg(&dev->dev, "SMBus using PCI Interrupt\n");
561 /* set up the sysfs linkage to our parent device */
562 i801_adapter.dev.parent = &dev->dev;
564 snprintf(i801_adapter.name, sizeof(i801_adapter.name),
565 "SMBus I801 adapter at %04lx", i801_smba);
566 err = i2c_add_adapter(&i801_adapter);
568 dev_err(&dev->dev, "Failed to add SMBus adapter\n");
574 pci_release_region(dev, SMBBAR);
579 static void __devexit i801_remove(struct pci_dev *dev)
581 i2c_del_adapter(&i801_adapter);
582 pci_write_config_byte(I801_dev, SMBHSTCFG, i801_original_hstcfg);
583 pci_release_region(dev, SMBBAR);
585 * do not call pci_disable_device(dev) since it can cause hard hangs on
586 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
591 static int i801_suspend(struct pci_dev *dev, pm_message_t mesg)
594 pci_write_config_byte(dev, SMBHSTCFG, i801_original_hstcfg);
595 pci_set_power_state(dev, pci_choose_state(dev, mesg));
599 static int i801_resume(struct pci_dev *dev)
601 pci_set_power_state(dev, PCI_D0);
602 pci_restore_state(dev);
603 return pci_enable_device(dev);
606 #define i801_suspend NULL
607 #define i801_resume NULL
610 static struct pci_driver i801_driver = {
611 .name = "i801_smbus",
612 .id_table = i801_ids,
614 .remove = __devexit_p(i801_remove),
615 .suspend = i801_suspend,
616 .resume = i801_resume,
619 static int __init i2c_i801_init(void)
621 return pci_register_driver(&i801_driver);
624 static void __exit i2c_i801_exit(void)
626 pci_unregister_driver(&i801_driver);
629 MODULE_AUTHOR ("Frodo Looijaard <frodol@dds.nl>, "
630 "Philip Edelbrock <phil@netroedge.com>, "
631 "and Mark D. Studebaker <mdsxyz123@yahoo.com>");
632 MODULE_DESCRIPTION("I801 SMBus driver");
633 MODULE_LICENSE("GPL");
635 module_init(i2c_i801_init);
636 module_exit(i2c_i801_exit);