forcedeth: mgmt unit interface
[linux-2.6] / drivers / net / forcedeth.c
1 /*
2  * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
3  *
4  * Note: This driver is a cleanroom reimplementation based on reverse
5  *      engineered documentation written by Carl-Daniel Hailfinger
6  *      and Andrew de Quincey.
7  *
8  * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
9  * trademarks of NVIDIA Corporation in the United States and other
10  * countries.
11  *
12  * Copyright (C) 2003,4,5 Manfred Spraul
13  * Copyright (C) 2004 Andrew de Quincey (wol support)
14  * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
15  *              IRQ rate fixes, bigendian fixes, cleanups, verification)
16  * Copyright (c) 2004,2005,2006,2007,2008,2009 NVIDIA Corporation
17  *
18  * This program is free software; you can redistribute it and/or modify
19  * it under the terms of the GNU General Public License as published by
20  * the Free Software Foundation; either version 2 of the License, or
21  * (at your option) any later version.
22  *
23  * This program is distributed in the hope that it will be useful,
24  * but WITHOUT ANY WARRANTY; without even the implied warranty of
25  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
26  * GNU General Public License for more details.
27  *
28  * You should have received a copy of the GNU General Public License
29  * along with this program; if not, write to the Free Software
30  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
31  *
32  * Known bugs:
33  * We suspect that on some hardware no TX done interrupts are generated.
34  * This means recovery from netif_stop_queue only happens if the hw timer
35  * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
36  * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
37  * If your hardware reliably generates tx done interrupts, then you can remove
38  * DEV_NEED_TIMERIRQ from the driver_data flags.
39  * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
40  * superfluous timer interrupts from the nic.
41  */
42 #define FORCEDETH_VERSION               "0.62"
43 #define DRV_NAME                        "forcedeth"
44
45 #include <linux/module.h>
46 #include <linux/types.h>
47 #include <linux/pci.h>
48 #include <linux/interrupt.h>
49 #include <linux/netdevice.h>
50 #include <linux/etherdevice.h>
51 #include <linux/delay.h>
52 #include <linux/spinlock.h>
53 #include <linux/ethtool.h>
54 #include <linux/timer.h>
55 #include <linux/skbuff.h>
56 #include <linux/mii.h>
57 #include <linux/random.h>
58 #include <linux/init.h>
59 #include <linux/if_vlan.h>
60 #include <linux/dma-mapping.h>
61
62 #include <asm/irq.h>
63 #include <asm/io.h>
64 #include <asm/uaccess.h>
65 #include <asm/system.h>
66
67 #if 0
68 #define dprintk                 printk
69 #else
70 #define dprintk(x...)           do { } while (0)
71 #endif
72
73 #define TX_WORK_PER_LOOP  64
74 #define RX_WORK_PER_LOOP  64
75
76 /*
77  * Hardware access:
78  */
79
80 #define DEV_NEED_TIMERIRQ          0x000001  /* set the timer irq flag in the irq mask */
81 #define DEV_NEED_LINKTIMER         0x000002  /* poll link settings. Relies on the timer irq */
82 #define DEV_HAS_LARGEDESC          0x000004  /* device supports jumbo frames and needs packet format 2 */
83 #define DEV_HAS_HIGH_DMA           0x000008  /* device supports 64bit dma */
84 #define DEV_HAS_CHECKSUM           0x000010  /* device supports tx and rx checksum offloads */
85 #define DEV_HAS_VLAN               0x000020  /* device supports vlan tagging and striping */
86 #define DEV_HAS_MSI                0x000040  /* device supports MSI */
87 #define DEV_HAS_MSI_X              0x000080  /* device supports MSI-X */
88 #define DEV_HAS_POWER_CNTRL        0x000100  /* device supports power savings */
89 #define DEV_HAS_STATISTICS_V1      0x000200  /* device supports hw statistics version 1 */
90 #define DEV_HAS_STATISTICS_V2      0x000400  /* device supports hw statistics version 2 */
91 #define DEV_HAS_STATISTICS_V3      0x000800  /* device supports hw statistics version 3 */
92 #define DEV_HAS_TEST_EXTENDED      0x001000  /* device supports extended diagnostic test */
93 #define DEV_HAS_MGMT_UNIT          0x002000  /* device supports management unit */
94 #define DEV_HAS_CORRECT_MACADDR    0x004000  /* device supports correct mac address order */
95 #define DEV_HAS_COLLISION_FIX      0x008000  /* device supports tx collision fix */
96 #define DEV_HAS_PAUSEFRAME_TX_V1   0x010000  /* device supports tx pause frames version 1 */
97 #define DEV_HAS_PAUSEFRAME_TX_V2   0x020000  /* device supports tx pause frames version 2 */
98 #define DEV_HAS_PAUSEFRAME_TX_V3   0x040000  /* device supports tx pause frames version 3 */
99 #define DEV_NEED_TX_LIMIT          0x080000  /* device needs to limit tx */
100 #define DEV_HAS_GEAR_MODE          0x100000  /* device supports gear mode */
101
102 enum {
103         NvRegIrqStatus = 0x000,
104 #define NVREG_IRQSTAT_MIIEVENT  0x040
105 #define NVREG_IRQSTAT_MASK              0x81ff
106         NvRegIrqMask = 0x004,
107 #define NVREG_IRQ_RX_ERROR              0x0001
108 #define NVREG_IRQ_RX                    0x0002
109 #define NVREG_IRQ_RX_NOBUF              0x0004
110 #define NVREG_IRQ_TX_ERR                0x0008
111 #define NVREG_IRQ_TX_OK                 0x0010
112 #define NVREG_IRQ_TIMER                 0x0020
113 #define NVREG_IRQ_LINK                  0x0040
114 #define NVREG_IRQ_RX_FORCED             0x0080
115 #define NVREG_IRQ_TX_FORCED             0x0100
116 #define NVREG_IRQ_RECOVER_ERROR         0x8000
117 #define NVREG_IRQMASK_THROUGHPUT        0x00df
118 #define NVREG_IRQMASK_CPU               0x0060
119 #define NVREG_IRQ_TX_ALL                (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
120 #define NVREG_IRQ_RX_ALL                (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
121 #define NVREG_IRQ_OTHER                 (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
122
123 #define NVREG_IRQ_UNKNOWN       (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \
124                                         NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RX_FORCED| \
125                                         NVREG_IRQ_TX_FORCED|NVREG_IRQ_RECOVER_ERROR))
126
127         NvRegUnknownSetupReg6 = 0x008,
128 #define NVREG_UNKSETUP6_VAL             3
129
130 /*
131  * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
132  * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
133  */
134         NvRegPollingInterval = 0x00c,
135 #define NVREG_POLL_DEFAULT_THROUGHPUT   970 /* backup tx cleanup if loop max reached */
136 #define NVREG_POLL_DEFAULT_CPU  13
137         NvRegMSIMap0 = 0x020,
138         NvRegMSIMap1 = 0x024,
139         NvRegMSIIrqMask = 0x030,
140 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
141         NvRegMisc1 = 0x080,
142 #define NVREG_MISC1_PAUSE_TX    0x01
143 #define NVREG_MISC1_HD          0x02
144 #define NVREG_MISC1_FORCE       0x3b0f3c
145
146         NvRegMacReset = 0x34,
147 #define NVREG_MAC_RESET_ASSERT  0x0F3
148         NvRegTransmitterControl = 0x084,
149 #define NVREG_XMITCTL_START     0x01
150 #define NVREG_XMITCTL_MGMT_ST   0x40000000
151 #define NVREG_XMITCTL_SYNC_MASK         0x000f0000
152 #define NVREG_XMITCTL_SYNC_NOT_READY    0x0
153 #define NVREG_XMITCTL_SYNC_PHY_INIT     0x00040000
154 #define NVREG_XMITCTL_MGMT_SEMA_MASK    0x00000f00
155 #define NVREG_XMITCTL_MGMT_SEMA_FREE    0x0
156 #define NVREG_XMITCTL_HOST_SEMA_MASK    0x0000f000
157 #define NVREG_XMITCTL_HOST_SEMA_ACQ     0x0000f000
158 #define NVREG_XMITCTL_HOST_LOADED       0x00004000
159 #define NVREG_XMITCTL_TX_PATH_EN        0x01000000
160 #define NVREG_XMITCTL_DATA_START        0x00100000
161 #define NVREG_XMITCTL_DATA_READY        0x00010000
162 #define NVREG_XMITCTL_DATA_ERROR        0x00020000
163         NvRegTransmitterStatus = 0x088,
164 #define NVREG_XMITSTAT_BUSY     0x01
165
166         NvRegPacketFilterFlags = 0x8c,
167 #define NVREG_PFF_PAUSE_RX      0x08
168 #define NVREG_PFF_ALWAYS        0x7F0000
169 #define NVREG_PFF_PROMISC       0x80
170 #define NVREG_PFF_MYADDR        0x20
171 #define NVREG_PFF_LOOPBACK      0x10
172
173         NvRegOffloadConfig = 0x90,
174 #define NVREG_OFFLOAD_HOMEPHY   0x601
175 #define NVREG_OFFLOAD_NORMAL    RX_NIC_BUFSIZE
176         NvRegReceiverControl = 0x094,
177 #define NVREG_RCVCTL_START      0x01
178 #define NVREG_RCVCTL_RX_PATH_EN 0x01000000
179         NvRegReceiverStatus = 0x98,
180 #define NVREG_RCVSTAT_BUSY      0x01
181
182         NvRegSlotTime = 0x9c,
183 #define NVREG_SLOTTIME_LEGBF_ENABLED    0x80000000
184 #define NVREG_SLOTTIME_10_100_FULL      0x00007f00
185 #define NVREG_SLOTTIME_1000_FULL        0x0003ff00
186 #define NVREG_SLOTTIME_HALF             0x0000ff00
187 #define NVREG_SLOTTIME_DEFAULT          0x00007f00
188 #define NVREG_SLOTTIME_MASK             0x000000ff
189
190         NvRegTxDeferral = 0xA0,
191 #define NVREG_TX_DEFERRAL_DEFAULT               0x15050f
192 #define NVREG_TX_DEFERRAL_RGMII_10_100          0x16070f
193 #define NVREG_TX_DEFERRAL_RGMII_1000            0x14050f
194 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_10      0x16190f
195 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_100     0x16300f
196 #define NVREG_TX_DEFERRAL_MII_STRETCH           0x152000
197         NvRegRxDeferral = 0xA4,
198 #define NVREG_RX_DEFERRAL_DEFAULT       0x16
199         NvRegMacAddrA = 0xA8,
200         NvRegMacAddrB = 0xAC,
201         NvRegMulticastAddrA = 0xB0,
202 #define NVREG_MCASTADDRA_FORCE  0x01
203         NvRegMulticastAddrB = 0xB4,
204         NvRegMulticastMaskA = 0xB8,
205 #define NVREG_MCASTMASKA_NONE           0xffffffff
206         NvRegMulticastMaskB = 0xBC,
207 #define NVREG_MCASTMASKB_NONE           0xffff
208
209         NvRegPhyInterface = 0xC0,
210 #define PHY_RGMII               0x10000000
211         NvRegBackOffControl = 0xC4,
212 #define NVREG_BKOFFCTRL_DEFAULT                 0x70000000
213 #define NVREG_BKOFFCTRL_SEED_MASK               0x000003ff
214 #define NVREG_BKOFFCTRL_SELECT                  24
215 #define NVREG_BKOFFCTRL_GEAR                    12
216
217         NvRegTxRingPhysAddr = 0x100,
218         NvRegRxRingPhysAddr = 0x104,
219         NvRegRingSizes = 0x108,
220 #define NVREG_RINGSZ_TXSHIFT 0
221 #define NVREG_RINGSZ_RXSHIFT 16
222         NvRegTransmitPoll = 0x10c,
223 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
224         NvRegLinkSpeed = 0x110,
225 #define NVREG_LINKSPEED_FORCE 0x10000
226 #define NVREG_LINKSPEED_10      1000
227 #define NVREG_LINKSPEED_100     100
228 #define NVREG_LINKSPEED_1000    50
229 #define NVREG_LINKSPEED_MASK    (0xFFF)
230         NvRegUnknownSetupReg5 = 0x130,
231 #define NVREG_UNKSETUP5_BIT31   (1<<31)
232         NvRegTxWatermark = 0x13c,
233 #define NVREG_TX_WM_DESC1_DEFAULT       0x0200010
234 #define NVREG_TX_WM_DESC2_3_DEFAULT     0x1e08000
235 #define NVREG_TX_WM_DESC2_3_1000        0xfe08000
236         NvRegTxRxControl = 0x144,
237 #define NVREG_TXRXCTL_KICK      0x0001
238 #define NVREG_TXRXCTL_BIT1      0x0002
239 #define NVREG_TXRXCTL_BIT2      0x0004
240 #define NVREG_TXRXCTL_IDLE      0x0008
241 #define NVREG_TXRXCTL_RESET     0x0010
242 #define NVREG_TXRXCTL_RXCHECK   0x0400
243 #define NVREG_TXRXCTL_DESC_1    0
244 #define NVREG_TXRXCTL_DESC_2    0x002100
245 #define NVREG_TXRXCTL_DESC_3    0xc02200
246 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
247 #define NVREG_TXRXCTL_VLANINS   0x00080
248         NvRegTxRingPhysAddrHigh = 0x148,
249         NvRegRxRingPhysAddrHigh = 0x14C,
250         NvRegTxPauseFrame = 0x170,
251 #define NVREG_TX_PAUSEFRAME_DISABLE     0x0fff0080
252 #define NVREG_TX_PAUSEFRAME_ENABLE_V1   0x01800010
253 #define NVREG_TX_PAUSEFRAME_ENABLE_V2   0x056003f0
254 #define NVREG_TX_PAUSEFRAME_ENABLE_V3   0x09f00880
255         NvRegTxPauseFrameLimit = 0x174,
256 #define NVREG_TX_PAUSEFRAMELIMIT_ENABLE 0x00010000
257         NvRegMIIStatus = 0x180,
258 #define NVREG_MIISTAT_ERROR             0x0001
259 #define NVREG_MIISTAT_LINKCHANGE        0x0008
260 #define NVREG_MIISTAT_MASK_RW           0x0007
261 #define NVREG_MIISTAT_MASK_ALL          0x000f
262         NvRegMIIMask = 0x184,
263 #define NVREG_MII_LINKCHANGE            0x0008
264
265         NvRegAdapterControl = 0x188,
266 #define NVREG_ADAPTCTL_START    0x02
267 #define NVREG_ADAPTCTL_LINKUP   0x04
268 #define NVREG_ADAPTCTL_PHYVALID 0x40000
269 #define NVREG_ADAPTCTL_RUNNING  0x100000
270 #define NVREG_ADAPTCTL_PHYSHIFT 24
271         NvRegMIISpeed = 0x18c,
272 #define NVREG_MIISPEED_BIT8     (1<<8)
273 #define NVREG_MIIDELAY  5
274         NvRegMIIControl = 0x190,
275 #define NVREG_MIICTL_INUSE      0x08000
276 #define NVREG_MIICTL_WRITE      0x00400
277 #define NVREG_MIICTL_ADDRSHIFT  5
278         NvRegMIIData = 0x194,
279         NvRegTxUnicast = 0x1a0,
280         NvRegTxMulticast = 0x1a4,
281         NvRegTxBroadcast = 0x1a8,
282         NvRegWakeUpFlags = 0x200,
283 #define NVREG_WAKEUPFLAGS_VAL           0x7770
284 #define NVREG_WAKEUPFLAGS_BUSYSHIFT     24
285 #define NVREG_WAKEUPFLAGS_ENABLESHIFT   16
286 #define NVREG_WAKEUPFLAGS_D3SHIFT       12
287 #define NVREG_WAKEUPFLAGS_D2SHIFT       8
288 #define NVREG_WAKEUPFLAGS_D1SHIFT       4
289 #define NVREG_WAKEUPFLAGS_D0SHIFT       0
290 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT         0x01
291 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT      0x02
292 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE     0x04
293 #define NVREG_WAKEUPFLAGS_ENABLE        0x1111
294
295         NvRegMgmtUnitGetVersion = 0x204,
296 #define NVREG_MGMTUNITGETVERSION        0x01
297         NvRegMgmtUnitVersion = 0x208,
298 #define NVREG_MGMTUNITVERSION           0x08
299         NvRegPowerCap = 0x268,
300 #define NVREG_POWERCAP_D3SUPP   (1<<30)
301 #define NVREG_POWERCAP_D2SUPP   (1<<26)
302 #define NVREG_POWERCAP_D1SUPP   (1<<25)
303         NvRegPowerState = 0x26c,
304 #define NVREG_POWERSTATE_POWEREDUP      0x8000
305 #define NVREG_POWERSTATE_VALID          0x0100
306 #define NVREG_POWERSTATE_MASK           0x0003
307 #define NVREG_POWERSTATE_D0             0x0000
308 #define NVREG_POWERSTATE_D1             0x0001
309 #define NVREG_POWERSTATE_D2             0x0002
310 #define NVREG_POWERSTATE_D3             0x0003
311         NvRegMgmtUnitControl = 0x278,
312 #define NVREG_MGMTUNITCONTROL_INUSE     0x20000
313         NvRegTxCnt = 0x280,
314         NvRegTxZeroReXmt = 0x284,
315         NvRegTxOneReXmt = 0x288,
316         NvRegTxManyReXmt = 0x28c,
317         NvRegTxLateCol = 0x290,
318         NvRegTxUnderflow = 0x294,
319         NvRegTxLossCarrier = 0x298,
320         NvRegTxExcessDef = 0x29c,
321         NvRegTxRetryErr = 0x2a0,
322         NvRegRxFrameErr = 0x2a4,
323         NvRegRxExtraByte = 0x2a8,
324         NvRegRxLateCol = 0x2ac,
325         NvRegRxRunt = 0x2b0,
326         NvRegRxFrameTooLong = 0x2b4,
327         NvRegRxOverflow = 0x2b8,
328         NvRegRxFCSErr = 0x2bc,
329         NvRegRxFrameAlignErr = 0x2c0,
330         NvRegRxLenErr = 0x2c4,
331         NvRegRxUnicast = 0x2c8,
332         NvRegRxMulticast = 0x2cc,
333         NvRegRxBroadcast = 0x2d0,
334         NvRegTxDef = 0x2d4,
335         NvRegTxFrame = 0x2d8,
336         NvRegRxCnt = 0x2dc,
337         NvRegTxPause = 0x2e0,
338         NvRegRxPause = 0x2e4,
339         NvRegRxDropFrame = 0x2e8,
340         NvRegVlanControl = 0x300,
341 #define NVREG_VLANCONTROL_ENABLE        0x2000
342         NvRegMSIXMap0 = 0x3e0,
343         NvRegMSIXMap1 = 0x3e4,
344         NvRegMSIXIrqStatus = 0x3f0,
345
346         NvRegPowerState2 = 0x600,
347 #define NVREG_POWERSTATE2_POWERUP_MASK          0x0F15
348 #define NVREG_POWERSTATE2_POWERUP_REV_A3        0x0001
349 #define NVREG_POWERSTATE2_PHY_RESET             0x0004
350 };
351
352 /* Big endian: should work, but is untested */
353 struct ring_desc {
354         __le32 buf;
355         __le32 flaglen;
356 };
357
358 struct ring_desc_ex {
359         __le32 bufhigh;
360         __le32 buflow;
361         __le32 txvlan;
362         __le32 flaglen;
363 };
364
365 union ring_type {
366         struct ring_desc* orig;
367         struct ring_desc_ex* ex;
368 };
369
370 #define FLAG_MASK_V1 0xffff0000
371 #define FLAG_MASK_V2 0xffffc000
372 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
373 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
374
375 #define NV_TX_LASTPACKET        (1<<16)
376 #define NV_TX_RETRYERROR        (1<<19)
377 #define NV_TX_RETRYCOUNT_MASK   (0xF<<20)
378 #define NV_TX_FORCED_INTERRUPT  (1<<24)
379 #define NV_TX_DEFERRED          (1<<26)
380 #define NV_TX_CARRIERLOST       (1<<27)
381 #define NV_TX_LATECOLLISION     (1<<28)
382 #define NV_TX_UNDERFLOW         (1<<29)
383 #define NV_TX_ERROR             (1<<30)
384 #define NV_TX_VALID             (1<<31)
385
386 #define NV_TX2_LASTPACKET       (1<<29)
387 #define NV_TX2_RETRYERROR       (1<<18)
388 #define NV_TX2_RETRYCOUNT_MASK  (0xF<<19)
389 #define NV_TX2_FORCED_INTERRUPT (1<<30)
390 #define NV_TX2_DEFERRED         (1<<25)
391 #define NV_TX2_CARRIERLOST      (1<<26)
392 #define NV_TX2_LATECOLLISION    (1<<27)
393 #define NV_TX2_UNDERFLOW        (1<<28)
394 /* error and valid are the same for both */
395 #define NV_TX2_ERROR            (1<<30)
396 #define NV_TX2_VALID            (1<<31)
397 #define NV_TX2_TSO              (1<<28)
398 #define NV_TX2_TSO_SHIFT        14
399 #define NV_TX2_TSO_MAX_SHIFT    14
400 #define NV_TX2_TSO_MAX_SIZE     (1<<NV_TX2_TSO_MAX_SHIFT)
401 #define NV_TX2_CHECKSUM_L3      (1<<27)
402 #define NV_TX2_CHECKSUM_L4      (1<<26)
403
404 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
405
406 #define NV_RX_DESCRIPTORVALID   (1<<16)
407 #define NV_RX_MISSEDFRAME       (1<<17)
408 #define NV_RX_SUBSTRACT1        (1<<18)
409 #define NV_RX_ERROR1            (1<<23)
410 #define NV_RX_ERROR2            (1<<24)
411 #define NV_RX_ERROR3            (1<<25)
412 #define NV_RX_ERROR4            (1<<26)
413 #define NV_RX_CRCERR            (1<<27)
414 #define NV_RX_OVERFLOW          (1<<28)
415 #define NV_RX_FRAMINGERR        (1<<29)
416 #define NV_RX_ERROR             (1<<30)
417 #define NV_RX_AVAIL             (1<<31)
418 #define NV_RX_ERROR_MASK        (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3|NV_RX_ERROR4|NV_RX_CRCERR|NV_RX_OVERFLOW|NV_RX_FRAMINGERR)
419
420 #define NV_RX2_CHECKSUMMASK     (0x1C000000)
421 #define NV_RX2_CHECKSUM_IP      (0x10000000)
422 #define NV_RX2_CHECKSUM_IP_TCP  (0x14000000)
423 #define NV_RX2_CHECKSUM_IP_UDP  (0x18000000)
424 #define NV_RX2_DESCRIPTORVALID  (1<<29)
425 #define NV_RX2_SUBSTRACT1       (1<<25)
426 #define NV_RX2_ERROR1           (1<<18)
427 #define NV_RX2_ERROR2           (1<<19)
428 #define NV_RX2_ERROR3           (1<<20)
429 #define NV_RX2_ERROR4           (1<<21)
430 #define NV_RX2_CRCERR           (1<<22)
431 #define NV_RX2_OVERFLOW         (1<<23)
432 #define NV_RX2_FRAMINGERR       (1<<24)
433 /* error and avail are the same for both */
434 #define NV_RX2_ERROR            (1<<30)
435 #define NV_RX2_AVAIL            (1<<31)
436 #define NV_RX2_ERROR_MASK       (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3|NV_RX2_ERROR4|NV_RX2_CRCERR|NV_RX2_OVERFLOW|NV_RX2_FRAMINGERR)
437
438 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
439 #define NV_RX3_VLAN_TAG_MASK    (0x0000FFFF)
440
441 /* Miscelaneous hardware related defines: */
442 #define NV_PCI_REGSZ_VER1       0x270
443 #define NV_PCI_REGSZ_VER2       0x2d4
444 #define NV_PCI_REGSZ_VER3       0x604
445 #define NV_PCI_REGSZ_MAX        0x604
446
447 /* various timeout delays: all in usec */
448 #define NV_TXRX_RESET_DELAY     4
449 #define NV_TXSTOP_DELAY1        10
450 #define NV_TXSTOP_DELAY1MAX     500000
451 #define NV_TXSTOP_DELAY2        100
452 #define NV_RXSTOP_DELAY1        10
453 #define NV_RXSTOP_DELAY1MAX     500000
454 #define NV_RXSTOP_DELAY2        100
455 #define NV_SETUP5_DELAY         5
456 #define NV_SETUP5_DELAYMAX      50000
457 #define NV_POWERUP_DELAY        5
458 #define NV_POWERUP_DELAYMAX     5000
459 #define NV_MIIBUSY_DELAY        50
460 #define NV_MIIPHY_DELAY 10
461 #define NV_MIIPHY_DELAYMAX      10000
462 #define NV_MAC_RESET_DELAY      64
463
464 #define NV_WAKEUPPATTERNS       5
465 #define NV_WAKEUPMASKENTRIES    4
466
467 /* General driver defaults */
468 #define NV_WATCHDOG_TIMEO       (5*HZ)
469
470 #define RX_RING_DEFAULT         128
471 #define TX_RING_DEFAULT         256
472 #define RX_RING_MIN             128
473 #define TX_RING_MIN             64
474 #define RING_MAX_DESC_VER_1     1024
475 #define RING_MAX_DESC_VER_2_3   16384
476
477 /* rx/tx mac addr + type + vlan + align + slack*/
478 #define NV_RX_HEADERS           (64)
479 /* even more slack. */
480 #define NV_RX_ALLOC_PAD         (64)
481
482 /* maximum mtu size */
483 #define NV_PKTLIMIT_1   ETH_DATA_LEN    /* hard limit not known */
484 #define NV_PKTLIMIT_2   9100    /* Actual limit according to NVidia: 9202 */
485
486 #define OOM_REFILL      (1+HZ/20)
487 #define POLL_WAIT       (1+HZ/100)
488 #define LINK_TIMEOUT    (3*HZ)
489 #define STATS_INTERVAL  (10*HZ)
490
491 /*
492  * desc_ver values:
493  * The nic supports three different descriptor types:
494  * - DESC_VER_1: Original
495  * - DESC_VER_2: support for jumbo frames.
496  * - DESC_VER_3: 64-bit format.
497  */
498 #define DESC_VER_1      1
499 #define DESC_VER_2      2
500 #define DESC_VER_3      3
501
502 /* PHY defines */
503 #define PHY_OUI_MARVELL         0x5043
504 #define PHY_OUI_CICADA          0x03f1
505 #define PHY_OUI_VITESSE         0x01c1
506 #define PHY_OUI_REALTEK         0x0732
507 #define PHY_OUI_REALTEK2        0x0020
508 #define PHYID1_OUI_MASK 0x03ff
509 #define PHYID1_OUI_SHFT 6
510 #define PHYID2_OUI_MASK 0xfc00
511 #define PHYID2_OUI_SHFT 10
512 #define PHYID2_MODEL_MASK               0x03f0
513 #define PHY_MODEL_REALTEK_8211          0x0110
514 #define PHY_REV_MASK                    0x0001
515 #define PHY_REV_REALTEK_8211B           0x0000
516 #define PHY_REV_REALTEK_8211C           0x0001
517 #define PHY_MODEL_REALTEK_8201          0x0200
518 #define PHY_MODEL_MARVELL_E3016         0x0220
519 #define PHY_MARVELL_E3016_INITMASK      0x0300
520 #define PHY_CICADA_INIT1        0x0f000
521 #define PHY_CICADA_INIT2        0x0e00
522 #define PHY_CICADA_INIT3        0x01000
523 #define PHY_CICADA_INIT4        0x0200
524 #define PHY_CICADA_INIT5        0x0004
525 #define PHY_CICADA_INIT6        0x02000
526 #define PHY_VITESSE_INIT_REG1   0x1f
527 #define PHY_VITESSE_INIT_REG2   0x10
528 #define PHY_VITESSE_INIT_REG3   0x11
529 #define PHY_VITESSE_INIT_REG4   0x12
530 #define PHY_VITESSE_INIT_MSK1   0xc
531 #define PHY_VITESSE_INIT_MSK2   0x0180
532 #define PHY_VITESSE_INIT1       0x52b5
533 #define PHY_VITESSE_INIT2       0xaf8a
534 #define PHY_VITESSE_INIT3       0x8
535 #define PHY_VITESSE_INIT4       0x8f8a
536 #define PHY_VITESSE_INIT5       0xaf86
537 #define PHY_VITESSE_INIT6       0x8f86
538 #define PHY_VITESSE_INIT7       0xaf82
539 #define PHY_VITESSE_INIT8       0x0100
540 #define PHY_VITESSE_INIT9       0x8f82
541 #define PHY_VITESSE_INIT10      0x0
542 #define PHY_REALTEK_INIT_REG1   0x1f
543 #define PHY_REALTEK_INIT_REG2   0x19
544 #define PHY_REALTEK_INIT_REG3   0x13
545 #define PHY_REALTEK_INIT_REG4   0x14
546 #define PHY_REALTEK_INIT_REG5   0x18
547 #define PHY_REALTEK_INIT_REG6   0x11
548 #define PHY_REALTEK_INIT_REG7   0x01
549 #define PHY_REALTEK_INIT1       0x0000
550 #define PHY_REALTEK_INIT2       0x8e00
551 #define PHY_REALTEK_INIT3       0x0001
552 #define PHY_REALTEK_INIT4       0xad17
553 #define PHY_REALTEK_INIT5       0xfb54
554 #define PHY_REALTEK_INIT6       0xf5c7
555 #define PHY_REALTEK_INIT7       0x1000
556 #define PHY_REALTEK_INIT8       0x0003
557 #define PHY_REALTEK_INIT9       0x0008
558 #define PHY_REALTEK_INIT10      0x0005
559 #define PHY_REALTEK_INIT11      0x0200
560 #define PHY_REALTEK_INIT_MSK1   0x0003
561
562 #define PHY_GIGABIT     0x0100
563
564 #define PHY_TIMEOUT     0x1
565 #define PHY_ERROR       0x2
566
567 #define PHY_100 0x1
568 #define PHY_1000        0x2
569 #define PHY_HALF        0x100
570
571 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
572 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
573 #define NV_PAUSEFRAME_RX_ENABLE  0x0004
574 #define NV_PAUSEFRAME_TX_ENABLE  0x0008
575 #define NV_PAUSEFRAME_RX_REQ     0x0010
576 #define NV_PAUSEFRAME_TX_REQ     0x0020
577 #define NV_PAUSEFRAME_AUTONEG    0x0040
578
579 /* MSI/MSI-X defines */
580 #define NV_MSI_X_MAX_VECTORS  8
581 #define NV_MSI_X_VECTORS_MASK 0x000f
582 #define NV_MSI_CAPABLE        0x0010
583 #define NV_MSI_X_CAPABLE      0x0020
584 #define NV_MSI_ENABLED        0x0040
585 #define NV_MSI_X_ENABLED      0x0080
586
587 #define NV_MSI_X_VECTOR_ALL   0x0
588 #define NV_MSI_X_VECTOR_RX    0x0
589 #define NV_MSI_X_VECTOR_TX    0x1
590 #define NV_MSI_X_VECTOR_OTHER 0x2
591
592 #define NV_RESTART_TX         0x1
593 #define NV_RESTART_RX         0x2
594
595 #define NV_TX_LIMIT_COUNT     16
596
597 /* statistics */
598 struct nv_ethtool_str {
599         char name[ETH_GSTRING_LEN];
600 };
601
602 static const struct nv_ethtool_str nv_estats_str[] = {
603         { "tx_bytes" },
604         { "tx_zero_rexmt" },
605         { "tx_one_rexmt" },
606         { "tx_many_rexmt" },
607         { "tx_late_collision" },
608         { "tx_fifo_errors" },
609         { "tx_carrier_errors" },
610         { "tx_excess_deferral" },
611         { "tx_retry_error" },
612         { "rx_frame_error" },
613         { "rx_extra_byte" },
614         { "rx_late_collision" },
615         { "rx_runt" },
616         { "rx_frame_too_long" },
617         { "rx_over_errors" },
618         { "rx_crc_errors" },
619         { "rx_frame_align_error" },
620         { "rx_length_error" },
621         { "rx_unicast" },
622         { "rx_multicast" },
623         { "rx_broadcast" },
624         { "rx_packets" },
625         { "rx_errors_total" },
626         { "tx_errors_total" },
627
628         /* version 2 stats */
629         { "tx_deferral" },
630         { "tx_packets" },
631         { "rx_bytes" },
632         { "tx_pause" },
633         { "rx_pause" },
634         { "rx_drop_frame" },
635
636         /* version 3 stats */
637         { "tx_unicast" },
638         { "tx_multicast" },
639         { "tx_broadcast" }
640 };
641
642 struct nv_ethtool_stats {
643         u64 tx_bytes;
644         u64 tx_zero_rexmt;
645         u64 tx_one_rexmt;
646         u64 tx_many_rexmt;
647         u64 tx_late_collision;
648         u64 tx_fifo_errors;
649         u64 tx_carrier_errors;
650         u64 tx_excess_deferral;
651         u64 tx_retry_error;
652         u64 rx_frame_error;
653         u64 rx_extra_byte;
654         u64 rx_late_collision;
655         u64 rx_runt;
656         u64 rx_frame_too_long;
657         u64 rx_over_errors;
658         u64 rx_crc_errors;
659         u64 rx_frame_align_error;
660         u64 rx_length_error;
661         u64 rx_unicast;
662         u64 rx_multicast;
663         u64 rx_broadcast;
664         u64 rx_packets;
665         u64 rx_errors_total;
666         u64 tx_errors_total;
667
668         /* version 2 stats */
669         u64 tx_deferral;
670         u64 tx_packets;
671         u64 rx_bytes;
672         u64 tx_pause;
673         u64 rx_pause;
674         u64 rx_drop_frame;
675
676         /* version 3 stats */
677         u64 tx_unicast;
678         u64 tx_multicast;
679         u64 tx_broadcast;
680 };
681
682 #define NV_DEV_STATISTICS_V3_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64))
683 #define NV_DEV_STATISTICS_V2_COUNT (NV_DEV_STATISTICS_V3_COUNT - 3)
684 #define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6)
685
686 /* diagnostics */
687 #define NV_TEST_COUNT_BASE 3
688 #define NV_TEST_COUNT_EXTENDED 4
689
690 static const struct nv_ethtool_str nv_etests_str[] = {
691         { "link      (online/offline)" },
692         { "register  (offline)       " },
693         { "interrupt (offline)       " },
694         { "loopback  (offline)       " }
695 };
696
697 struct register_test {
698         __u32 reg;
699         __u32 mask;
700 };
701
702 static const struct register_test nv_registers_test[] = {
703         { NvRegUnknownSetupReg6, 0x01 },
704         { NvRegMisc1, 0x03c },
705         { NvRegOffloadConfig, 0x03ff },
706         { NvRegMulticastAddrA, 0xffffffff },
707         { NvRegTxWatermark, 0x0ff },
708         { NvRegWakeUpFlags, 0x07777 },
709         { 0,0 }
710 };
711
712 struct nv_skb_map {
713         struct sk_buff *skb;
714         dma_addr_t dma;
715         unsigned int dma_len;
716         struct ring_desc_ex *first_tx_desc;
717         struct nv_skb_map *next_tx_ctx;
718 };
719
720 /*
721  * SMP locking:
722  * All hardware access under netdev_priv(dev)->lock, except the performance
723  * critical parts:
724  * - rx is (pseudo-) lockless: it relies on the single-threading provided
725  *      by the arch code for interrupts.
726  * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
727  *      needs netdev_priv(dev)->lock :-(
728  * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
729  */
730
731 /* in dev: base, irq */
732 struct fe_priv {
733         spinlock_t lock;
734
735         struct net_device *dev;
736         struct napi_struct napi;
737
738         /* General data:
739          * Locking: spin_lock(&np->lock); */
740         struct nv_ethtool_stats estats;
741         int in_shutdown;
742         u32 linkspeed;
743         int duplex;
744         int autoneg;
745         int fixed_mode;
746         int phyaddr;
747         int wolenabled;
748         unsigned int phy_oui;
749         unsigned int phy_model;
750         unsigned int phy_rev;
751         u16 gigabit;
752         int intr_test;
753         int recover_error;
754
755         /* General data: RO fields */
756         dma_addr_t ring_addr;
757         struct pci_dev *pci_dev;
758         u32 orig_mac[2];
759         u32 irqmask;
760         u32 desc_ver;
761         u32 txrxctl_bits;
762         u32 vlanctl_bits;
763         u32 driver_data;
764         u32 device_id;
765         u32 register_size;
766         int rx_csum;
767         u32 mac_in_use;
768         int mgmt_version;
769         int mgmt_sema;
770
771         void __iomem *base;
772
773         /* rx specific fields.
774          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
775          */
776         union ring_type get_rx, put_rx, first_rx, last_rx;
777         struct nv_skb_map *get_rx_ctx, *put_rx_ctx;
778         struct nv_skb_map *first_rx_ctx, *last_rx_ctx;
779         struct nv_skb_map *rx_skb;
780
781         union ring_type rx_ring;
782         unsigned int rx_buf_sz;
783         unsigned int pkt_limit;
784         struct timer_list oom_kick;
785         struct timer_list nic_poll;
786         struct timer_list stats_poll;
787         u32 nic_poll_irq;
788         int rx_ring_size;
789
790         /* media detection workaround.
791          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
792          */
793         int need_linktimer;
794         unsigned long link_timeout;
795         /*
796          * tx specific fields.
797          */
798         union ring_type get_tx, put_tx, first_tx, last_tx;
799         struct nv_skb_map *get_tx_ctx, *put_tx_ctx;
800         struct nv_skb_map *first_tx_ctx, *last_tx_ctx;
801         struct nv_skb_map *tx_skb;
802
803         union ring_type tx_ring;
804         u32 tx_flags;
805         int tx_ring_size;
806         int tx_limit;
807         u32 tx_pkts_in_progress;
808         struct nv_skb_map *tx_change_owner;
809         struct nv_skb_map *tx_end_flip;
810         int tx_stop;
811
812         /* vlan fields */
813         struct vlan_group *vlangrp;
814
815         /* msi/msi-x fields */
816         u32 msi_flags;
817         struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
818
819         /* flow control */
820         u32 pause_flags;
821
822         /* power saved state */
823         u32 saved_config_space[NV_PCI_REGSZ_MAX/4];
824
825         /* for different msi-x irq type */
826         char name_rx[IFNAMSIZ + 3];       /* -rx    */
827         char name_tx[IFNAMSIZ + 3];       /* -tx    */
828         char name_other[IFNAMSIZ + 6];    /* -other */
829 };
830
831 /*
832  * Maximum number of loops until we assume that a bit in the irq mask
833  * is stuck. Overridable with module param.
834  */
835 static int max_interrupt_work = 15;
836
837 /*
838  * Optimization can be either throuput mode or cpu mode
839  *
840  * Throughput Mode: Every tx and rx packet will generate an interrupt.
841  * CPU Mode: Interrupts are controlled by a timer.
842  */
843 enum {
844         NV_OPTIMIZATION_MODE_THROUGHPUT,
845         NV_OPTIMIZATION_MODE_CPU
846 };
847 static int optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
848
849 /*
850  * Poll interval for timer irq
851  *
852  * This interval determines how frequent an interrupt is generated.
853  * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
854  * Min = 0, and Max = 65535
855  */
856 static int poll_interval = -1;
857
858 /*
859  * MSI interrupts
860  */
861 enum {
862         NV_MSI_INT_DISABLED,
863         NV_MSI_INT_ENABLED
864 };
865 static int msi = NV_MSI_INT_ENABLED;
866
867 /*
868  * MSIX interrupts
869  */
870 enum {
871         NV_MSIX_INT_DISABLED,
872         NV_MSIX_INT_ENABLED
873 };
874 static int msix = NV_MSIX_INT_ENABLED;
875
876 /*
877  * DMA 64bit
878  */
879 enum {
880         NV_DMA_64BIT_DISABLED,
881         NV_DMA_64BIT_ENABLED
882 };
883 static int dma_64bit = NV_DMA_64BIT_ENABLED;
884
885 /*
886  * Crossover Detection
887  * Realtek 8201 phy + some OEM boards do not work properly.
888  */
889 enum {
890         NV_CROSSOVER_DETECTION_DISABLED,
891         NV_CROSSOVER_DETECTION_ENABLED
892 };
893 static int phy_cross = NV_CROSSOVER_DETECTION_DISABLED;
894
895 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
896 {
897         return netdev_priv(dev);
898 }
899
900 static inline u8 __iomem *get_hwbase(struct net_device *dev)
901 {
902         return ((struct fe_priv *)netdev_priv(dev))->base;
903 }
904
905 static inline void pci_push(u8 __iomem *base)
906 {
907         /* force out pending posted writes */
908         readl(base);
909 }
910
911 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
912 {
913         return le32_to_cpu(prd->flaglen)
914                 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
915 }
916
917 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
918 {
919         return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
920 }
921
922 static bool nv_optimized(struct fe_priv *np)
923 {
924         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
925                 return false;
926         return true;
927 }
928
929 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
930                                 int delay, int delaymax, const char *msg)
931 {
932         u8 __iomem *base = get_hwbase(dev);
933
934         pci_push(base);
935         do {
936                 udelay(delay);
937                 delaymax -= delay;
938                 if (delaymax < 0) {
939                         if (msg)
940                                 printk(msg);
941                         return 1;
942                 }
943         } while ((readl(base + offset) & mask) != target);
944         return 0;
945 }
946
947 #define NV_SETUP_RX_RING 0x01
948 #define NV_SETUP_TX_RING 0x02
949
950 static inline u32 dma_low(dma_addr_t addr)
951 {
952         return addr;
953 }
954
955 static inline u32 dma_high(dma_addr_t addr)
956 {
957         return addr>>31>>1;     /* 0 if 32bit, shift down by 32 if 64bit */
958 }
959
960 static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
961 {
962         struct fe_priv *np = get_nvpriv(dev);
963         u8 __iomem *base = get_hwbase(dev);
964
965         if (!nv_optimized(np)) {
966                 if (rxtx_flags & NV_SETUP_RX_RING) {
967                         writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
968                 }
969                 if (rxtx_flags & NV_SETUP_TX_RING) {
970                         writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
971                 }
972         } else {
973                 if (rxtx_flags & NV_SETUP_RX_RING) {
974                         writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
975                         writel(dma_high(np->ring_addr), base + NvRegRxRingPhysAddrHigh);
976                 }
977                 if (rxtx_flags & NV_SETUP_TX_RING) {
978                         writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
979                         writel(dma_high(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddrHigh);
980                 }
981         }
982 }
983
984 static void free_rings(struct net_device *dev)
985 {
986         struct fe_priv *np = get_nvpriv(dev);
987
988         if (!nv_optimized(np)) {
989                 if (np->rx_ring.orig)
990                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
991                                             np->rx_ring.orig, np->ring_addr);
992         } else {
993                 if (np->rx_ring.ex)
994                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
995                                             np->rx_ring.ex, np->ring_addr);
996         }
997         if (np->rx_skb)
998                 kfree(np->rx_skb);
999         if (np->tx_skb)
1000                 kfree(np->tx_skb);
1001 }
1002
1003 static int using_multi_irqs(struct net_device *dev)
1004 {
1005         struct fe_priv *np = get_nvpriv(dev);
1006
1007         if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
1008             ((np->msi_flags & NV_MSI_X_ENABLED) &&
1009              ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
1010                 return 0;
1011         else
1012                 return 1;
1013 }
1014
1015 static void nv_enable_irq(struct net_device *dev)
1016 {
1017         struct fe_priv *np = get_nvpriv(dev);
1018
1019         if (!using_multi_irqs(dev)) {
1020                 if (np->msi_flags & NV_MSI_X_ENABLED)
1021                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1022                 else
1023                         enable_irq(np->pci_dev->irq);
1024         } else {
1025                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1026                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1027                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1028         }
1029 }
1030
1031 static void nv_disable_irq(struct net_device *dev)
1032 {
1033         struct fe_priv *np = get_nvpriv(dev);
1034
1035         if (!using_multi_irqs(dev)) {
1036                 if (np->msi_flags & NV_MSI_X_ENABLED)
1037                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1038                 else
1039                         disable_irq(np->pci_dev->irq);
1040         } else {
1041                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1042                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1043                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1044         }
1045 }
1046
1047 /* In MSIX mode, a write to irqmask behaves as XOR */
1048 static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
1049 {
1050         u8 __iomem *base = get_hwbase(dev);
1051
1052         writel(mask, base + NvRegIrqMask);
1053 }
1054
1055 static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
1056 {
1057         struct fe_priv *np = get_nvpriv(dev);
1058         u8 __iomem *base = get_hwbase(dev);
1059
1060         if (np->msi_flags & NV_MSI_X_ENABLED) {
1061                 writel(mask, base + NvRegIrqMask);
1062         } else {
1063                 if (np->msi_flags & NV_MSI_ENABLED)
1064                         writel(0, base + NvRegMSIIrqMask);
1065                 writel(0, base + NvRegIrqMask);
1066         }
1067 }
1068
1069 #define MII_READ        (-1)
1070 /* mii_rw: read/write a register on the PHY.
1071  *
1072  * Caller must guarantee serialization
1073  */
1074 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
1075 {
1076         u8 __iomem *base = get_hwbase(dev);
1077         u32 reg;
1078         int retval;
1079
1080         writel(NVREG_MIISTAT_MASK_RW, base + NvRegMIIStatus);
1081
1082         reg = readl(base + NvRegMIIControl);
1083         if (reg & NVREG_MIICTL_INUSE) {
1084                 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
1085                 udelay(NV_MIIBUSY_DELAY);
1086         }
1087
1088         reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
1089         if (value != MII_READ) {
1090                 writel(value, base + NvRegMIIData);
1091                 reg |= NVREG_MIICTL_WRITE;
1092         }
1093         writel(reg, base + NvRegMIIControl);
1094
1095         if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
1096                         NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
1097                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
1098                                 dev->name, miireg, addr);
1099                 retval = -1;
1100         } else if (value != MII_READ) {
1101                 /* it was a write operation - fewer failures are detectable */
1102                 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
1103                                 dev->name, value, miireg, addr);
1104                 retval = 0;
1105         } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
1106                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
1107                                 dev->name, miireg, addr);
1108                 retval = -1;
1109         } else {
1110                 retval = readl(base + NvRegMIIData);
1111                 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
1112                                 dev->name, miireg, addr, retval);
1113         }
1114
1115         return retval;
1116 }
1117
1118 static int phy_reset(struct net_device *dev, u32 bmcr_setup)
1119 {
1120         struct fe_priv *np = netdev_priv(dev);
1121         u32 miicontrol;
1122         unsigned int tries = 0;
1123
1124         miicontrol = BMCR_RESET | bmcr_setup;
1125         if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
1126                 return -1;
1127         }
1128
1129         /* wait for 500ms */
1130         msleep(500);
1131
1132         /* must wait till reset is deasserted */
1133         while (miicontrol & BMCR_RESET) {
1134                 msleep(10);
1135                 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1136                 /* FIXME: 100 tries seem excessive */
1137                 if (tries++ > 100)
1138                         return -1;
1139         }
1140         return 0;
1141 }
1142
1143 static int phy_init(struct net_device *dev)
1144 {
1145         struct fe_priv *np = get_nvpriv(dev);
1146         u8 __iomem *base = get_hwbase(dev);
1147         u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
1148
1149         /* phy errata for E3016 phy */
1150         if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
1151                 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1152                 reg &= ~PHY_MARVELL_E3016_INITMASK;
1153                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
1154                         printk(KERN_INFO "%s: phy write to errata reg failed.\n", pci_name(np->pci_dev));
1155                         return PHY_ERROR;
1156                 }
1157         }
1158         if (np->phy_oui == PHY_OUI_REALTEK) {
1159                 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1160                     np->phy_rev == PHY_REV_REALTEK_8211B) {
1161                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1162                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1163                                 return PHY_ERROR;
1164                         }
1165                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
1166                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1167                                 return PHY_ERROR;
1168                         }
1169                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1170                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1171                                 return PHY_ERROR;
1172                         }
1173                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
1174                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1175                                 return PHY_ERROR;
1176                         }
1177                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) {
1178                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1179                                 return PHY_ERROR;
1180                         }
1181                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) {
1182                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1183                                 return PHY_ERROR;
1184                         }
1185                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1186                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1187                                 return PHY_ERROR;
1188                         }
1189                 }
1190                 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1191                     np->phy_rev == PHY_REV_REALTEK_8211C) {
1192                         u32 powerstate = readl(base + NvRegPowerState2);
1193
1194                         /* need to perform hw phy reset */
1195                         powerstate |= NVREG_POWERSTATE2_PHY_RESET;
1196                         writel(powerstate, base + NvRegPowerState2);
1197                         msleep(25);
1198
1199                         powerstate &= ~NVREG_POWERSTATE2_PHY_RESET;
1200                         writel(powerstate, base + NvRegPowerState2);
1201                         msleep(25);
1202
1203                         reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1204                         reg |= PHY_REALTEK_INIT9;
1205                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg)) {
1206                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1207                                 return PHY_ERROR;
1208                         }
1209                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT10)) {
1210                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1211                                 return PHY_ERROR;
1212                         }
1213                         reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ);
1214                         if (!(reg & PHY_REALTEK_INIT11)) {
1215                                 reg |= PHY_REALTEK_INIT11;
1216                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg)) {
1217                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1218                                         return PHY_ERROR;
1219                                 }
1220                         }
1221                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1222                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1223                                 return PHY_ERROR;
1224                         }
1225                 }
1226                 if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1227                         if (np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_32 ||
1228                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_33 ||
1229                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_34 ||
1230                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_35 ||
1231                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_36 ||
1232                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_37 ||
1233                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_38 ||
1234                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_39) {
1235                                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1236                                 phy_reserved |= PHY_REALTEK_INIT7;
1237                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) {
1238                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1239                                         return PHY_ERROR;
1240                                 }
1241                         }
1242                 }
1243         }
1244
1245         /* set advertise register */
1246         reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1247         reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP);
1248         if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1249                 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
1250                 return PHY_ERROR;
1251         }
1252
1253         /* get phy interface type */
1254         phyinterface = readl(base + NvRegPhyInterface);
1255
1256         /* see if gigabit phy */
1257         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1258         if (mii_status & PHY_GIGABIT) {
1259                 np->gigabit = PHY_GIGABIT;
1260                 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
1261                 mii_control_1000 &= ~ADVERTISE_1000HALF;
1262                 if (phyinterface & PHY_RGMII)
1263                         mii_control_1000 |= ADVERTISE_1000FULL;
1264                 else
1265                         mii_control_1000 &= ~ADVERTISE_1000FULL;
1266
1267                 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
1268                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1269                         return PHY_ERROR;
1270                 }
1271         }
1272         else
1273                 np->gigabit = 0;
1274
1275         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1276         mii_control |= BMCR_ANENABLE;
1277
1278         if (np->phy_oui == PHY_OUI_REALTEK &&
1279             np->phy_model == PHY_MODEL_REALTEK_8211 &&
1280             np->phy_rev == PHY_REV_REALTEK_8211C) {
1281                 /* start autoneg since we already performed hw reset above */
1282                 mii_control |= BMCR_ANRESTART;
1283                 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1284                         printk(KERN_INFO "%s: phy init failed\n", pci_name(np->pci_dev));
1285                         return PHY_ERROR;
1286                 }
1287         } else {
1288                 /* reset the phy
1289                  * (certain phys need bmcr to be setup with reset)
1290                  */
1291                 if (phy_reset(dev, mii_control)) {
1292                         printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
1293                         return PHY_ERROR;
1294                 }
1295         }
1296
1297         /* phy vendor specific configuration */
1298         if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
1299                 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1300                 phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2);
1301                 phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4);
1302                 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
1303                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1304                         return PHY_ERROR;
1305                 }
1306                 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1307                 phy_reserved |= PHY_CICADA_INIT5;
1308                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
1309                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1310                         return PHY_ERROR;
1311                 }
1312         }
1313         if (np->phy_oui == PHY_OUI_CICADA) {
1314                 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1315                 phy_reserved |= PHY_CICADA_INIT6;
1316                 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
1317                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1318                         return PHY_ERROR;
1319                 }
1320         }
1321         if (np->phy_oui == PHY_OUI_VITESSE) {
1322                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1)) {
1323                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1324                         return PHY_ERROR;
1325                 }
1326                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2)) {
1327                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1328                         return PHY_ERROR;
1329                 }
1330                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1331                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1332                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1333                         return PHY_ERROR;
1334                 }
1335                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1336                 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1337                 phy_reserved |= PHY_VITESSE_INIT3;
1338                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1339                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1340                         return PHY_ERROR;
1341                 }
1342                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4)) {
1343                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1344                         return PHY_ERROR;
1345                 }
1346                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5)) {
1347                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1348                         return PHY_ERROR;
1349                 }
1350                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1351                 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1352                 phy_reserved |= PHY_VITESSE_INIT3;
1353                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1354                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1355                         return PHY_ERROR;
1356                 }
1357                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1358                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1359                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1360                         return PHY_ERROR;
1361                 }
1362                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6)) {
1363                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1364                         return PHY_ERROR;
1365                 }
1366                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7)) {
1367                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1368                         return PHY_ERROR;
1369                 }
1370                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1371                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1372                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1373                         return PHY_ERROR;
1374                 }
1375                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1376                 phy_reserved &= ~PHY_VITESSE_INIT_MSK2;
1377                 phy_reserved |= PHY_VITESSE_INIT8;
1378                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1379                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1380                         return PHY_ERROR;
1381                 }
1382                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9)) {
1383                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1384                         return PHY_ERROR;
1385                 }
1386                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10)) {
1387                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1388                         return PHY_ERROR;
1389                 }
1390         }
1391         if (np->phy_oui == PHY_OUI_REALTEK) {
1392                 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1393                     np->phy_rev == PHY_REV_REALTEK_8211B) {
1394                         /* reset could have cleared these out, set them back */
1395                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1396                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1397                                 return PHY_ERROR;
1398                         }
1399                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
1400                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1401                                 return PHY_ERROR;
1402                         }
1403                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1404                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1405                                 return PHY_ERROR;
1406                         }
1407                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
1408                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1409                                 return PHY_ERROR;
1410                         }
1411                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) {
1412                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1413                                 return PHY_ERROR;
1414                         }
1415                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) {
1416                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1417                                 return PHY_ERROR;
1418                         }
1419                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1420                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1421                                 return PHY_ERROR;
1422                         }
1423                 }
1424                 if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1425                         if (np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_32 ||
1426                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_33 ||
1427                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_34 ||
1428                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_35 ||
1429                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_36 ||
1430                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_37 ||
1431                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_38 ||
1432                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_39) {
1433                                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1434                                 phy_reserved |= PHY_REALTEK_INIT7;
1435                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) {
1436                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1437                                         return PHY_ERROR;
1438                                 }
1439                         }
1440                         if (phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
1441                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1442                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1443                                         return PHY_ERROR;
1444                                 }
1445                                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
1446                                 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
1447                                 phy_reserved |= PHY_REALTEK_INIT3;
1448                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved)) {
1449                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1450                                         return PHY_ERROR;
1451                                 }
1452                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1453                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1454                                         return PHY_ERROR;
1455                                 }
1456                         }
1457                 }
1458         }
1459
1460         /* some phys clear out pause advertisment on reset, set it back */
1461         mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
1462
1463         /* restart auto negotiation, power down phy */
1464         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1465         mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE | BMCR_PDOWN);
1466         if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1467                 return PHY_ERROR;
1468         }
1469
1470         return 0;
1471 }
1472
1473 static void nv_start_rx(struct net_device *dev)
1474 {
1475         struct fe_priv *np = netdev_priv(dev);
1476         u8 __iomem *base = get_hwbase(dev);
1477         u32 rx_ctrl = readl(base + NvRegReceiverControl);
1478
1479         dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
1480         /* Already running? Stop it. */
1481         if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) {
1482                 rx_ctrl &= ~NVREG_RCVCTL_START;
1483                 writel(rx_ctrl, base + NvRegReceiverControl);
1484                 pci_push(base);
1485         }
1486         writel(np->linkspeed, base + NvRegLinkSpeed);
1487         pci_push(base);
1488         rx_ctrl |= NVREG_RCVCTL_START;
1489         if (np->mac_in_use)
1490                 rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN;
1491         writel(rx_ctrl, base + NvRegReceiverControl);
1492         dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
1493                                 dev->name, np->duplex, np->linkspeed);
1494         pci_push(base);
1495 }
1496
1497 static void nv_stop_rx(struct net_device *dev)
1498 {
1499         struct fe_priv *np = netdev_priv(dev);
1500         u8 __iomem *base = get_hwbase(dev);
1501         u32 rx_ctrl = readl(base + NvRegReceiverControl);
1502
1503         dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
1504         if (!np->mac_in_use)
1505                 rx_ctrl &= ~NVREG_RCVCTL_START;
1506         else
1507                 rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN;
1508         writel(rx_ctrl, base + NvRegReceiverControl);
1509         reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1510                         NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
1511                         KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
1512
1513         udelay(NV_RXSTOP_DELAY2);
1514         if (!np->mac_in_use)
1515                 writel(0, base + NvRegLinkSpeed);
1516 }
1517
1518 static void nv_start_tx(struct net_device *dev)
1519 {
1520         struct fe_priv *np = netdev_priv(dev);
1521         u8 __iomem *base = get_hwbase(dev);
1522         u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1523
1524         dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
1525         tx_ctrl |= NVREG_XMITCTL_START;
1526         if (np->mac_in_use)
1527                 tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN;
1528         writel(tx_ctrl, base + NvRegTransmitterControl);
1529         pci_push(base);
1530 }
1531
1532 static void nv_stop_tx(struct net_device *dev)
1533 {
1534         struct fe_priv *np = netdev_priv(dev);
1535         u8 __iomem *base = get_hwbase(dev);
1536         u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1537
1538         dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
1539         if (!np->mac_in_use)
1540                 tx_ctrl &= ~NVREG_XMITCTL_START;
1541         else
1542                 tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN;
1543         writel(tx_ctrl, base + NvRegTransmitterControl);
1544         reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1545                         NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
1546                         KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
1547
1548         udelay(NV_TXSTOP_DELAY2);
1549         if (!np->mac_in_use)
1550                 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,
1551                        base + NvRegTransmitPoll);
1552 }
1553
1554 static void nv_start_rxtx(struct net_device *dev)
1555 {
1556         nv_start_rx(dev);
1557         nv_start_tx(dev);
1558 }
1559
1560 static void nv_stop_rxtx(struct net_device *dev)
1561 {
1562         nv_stop_rx(dev);
1563         nv_stop_tx(dev);
1564 }
1565
1566 static void nv_txrx_reset(struct net_device *dev)
1567 {
1568         struct fe_priv *np = netdev_priv(dev);
1569         u8 __iomem *base = get_hwbase(dev);
1570
1571         dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
1572         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1573         pci_push(base);
1574         udelay(NV_TXRX_RESET_DELAY);
1575         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1576         pci_push(base);
1577 }
1578
1579 static void nv_mac_reset(struct net_device *dev)
1580 {
1581         struct fe_priv *np = netdev_priv(dev);
1582         u8 __iomem *base = get_hwbase(dev);
1583         u32 temp1, temp2, temp3;
1584
1585         dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name);
1586
1587         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1588         pci_push(base);
1589
1590         /* save registers since they will be cleared on reset */
1591         temp1 = readl(base + NvRegMacAddrA);
1592         temp2 = readl(base + NvRegMacAddrB);
1593         temp3 = readl(base + NvRegTransmitPoll);
1594
1595         writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1596         pci_push(base);
1597         udelay(NV_MAC_RESET_DELAY);
1598         writel(0, base + NvRegMacReset);
1599         pci_push(base);
1600         udelay(NV_MAC_RESET_DELAY);
1601
1602         /* restore saved registers */
1603         writel(temp1, base + NvRegMacAddrA);
1604         writel(temp2, base + NvRegMacAddrB);
1605         writel(temp3, base + NvRegTransmitPoll);
1606
1607         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1608         pci_push(base);
1609 }
1610
1611 static void nv_get_hw_stats(struct net_device *dev)
1612 {
1613         struct fe_priv *np = netdev_priv(dev);
1614         u8 __iomem *base = get_hwbase(dev);
1615
1616         np->estats.tx_bytes += readl(base + NvRegTxCnt);
1617         np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
1618         np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
1619         np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
1620         np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
1621         np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
1622         np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
1623         np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
1624         np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
1625         np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
1626         np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
1627         np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
1628         np->estats.rx_runt += readl(base + NvRegRxRunt);
1629         np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
1630         np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
1631         np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
1632         np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
1633         np->estats.rx_length_error += readl(base + NvRegRxLenErr);
1634         np->estats.rx_unicast += readl(base + NvRegRxUnicast);
1635         np->estats.rx_multicast += readl(base + NvRegRxMulticast);
1636         np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
1637         np->estats.rx_packets =
1638                 np->estats.rx_unicast +
1639                 np->estats.rx_multicast +
1640                 np->estats.rx_broadcast;
1641         np->estats.rx_errors_total =
1642                 np->estats.rx_crc_errors +
1643                 np->estats.rx_over_errors +
1644                 np->estats.rx_frame_error +
1645                 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
1646                 np->estats.rx_late_collision +
1647                 np->estats.rx_runt +
1648                 np->estats.rx_frame_too_long;
1649         np->estats.tx_errors_total =
1650                 np->estats.tx_late_collision +
1651                 np->estats.tx_fifo_errors +
1652                 np->estats.tx_carrier_errors +
1653                 np->estats.tx_excess_deferral +
1654                 np->estats.tx_retry_error;
1655
1656         if (np->driver_data & DEV_HAS_STATISTICS_V2) {
1657                 np->estats.tx_deferral += readl(base + NvRegTxDef);
1658                 np->estats.tx_packets += readl(base + NvRegTxFrame);
1659                 np->estats.rx_bytes += readl(base + NvRegRxCnt);
1660                 np->estats.tx_pause += readl(base + NvRegTxPause);
1661                 np->estats.rx_pause += readl(base + NvRegRxPause);
1662                 np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
1663         }
1664
1665         if (np->driver_data & DEV_HAS_STATISTICS_V3) {
1666                 np->estats.tx_unicast += readl(base + NvRegTxUnicast);
1667                 np->estats.tx_multicast += readl(base + NvRegTxMulticast);
1668                 np->estats.tx_broadcast += readl(base + NvRegTxBroadcast);
1669         }
1670 }
1671
1672 /*
1673  * nv_get_stats: dev->get_stats function
1674  * Get latest stats value from the nic.
1675  * Called with read_lock(&dev_base_lock) held for read -
1676  * only synchronized against unregister_netdevice.
1677  */
1678 static struct net_device_stats *nv_get_stats(struct net_device *dev)
1679 {
1680         struct fe_priv *np = netdev_priv(dev);
1681
1682         /* If the nic supports hw counters then retrieve latest values */
1683         if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3)) {
1684                 nv_get_hw_stats(dev);
1685
1686                 /* copy to net_device stats */
1687                 dev->stats.tx_bytes = np->estats.tx_bytes;
1688                 dev->stats.tx_fifo_errors = np->estats.tx_fifo_errors;
1689                 dev->stats.tx_carrier_errors = np->estats.tx_carrier_errors;
1690                 dev->stats.rx_crc_errors = np->estats.rx_crc_errors;
1691                 dev->stats.rx_over_errors = np->estats.rx_over_errors;
1692                 dev->stats.rx_errors = np->estats.rx_errors_total;
1693                 dev->stats.tx_errors = np->estats.tx_errors_total;
1694         }
1695
1696         return &dev->stats;
1697 }
1698
1699 /*
1700  * nv_alloc_rx: fill rx ring entries.
1701  * Return 1 if the allocations for the skbs failed and the
1702  * rx engine is without Available descriptors
1703  */
1704 static int nv_alloc_rx(struct net_device *dev)
1705 {
1706         struct fe_priv *np = netdev_priv(dev);
1707         struct ring_desc* less_rx;
1708
1709         less_rx = np->get_rx.orig;
1710         if (less_rx-- == np->first_rx.orig)
1711                 less_rx = np->last_rx.orig;
1712
1713         while (np->put_rx.orig != less_rx) {
1714                 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1715                 if (skb) {
1716                         np->put_rx_ctx->skb = skb;
1717                         np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1718                                                              skb->data,
1719                                                              skb_tailroom(skb),
1720                                                              PCI_DMA_FROMDEVICE);
1721                         np->put_rx_ctx->dma_len = skb_tailroom(skb);
1722                         np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma);
1723                         wmb();
1724                         np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
1725                         if (unlikely(np->put_rx.orig++ == np->last_rx.orig))
1726                                 np->put_rx.orig = np->first_rx.orig;
1727                         if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1728                                 np->put_rx_ctx = np->first_rx_ctx;
1729                 } else {
1730                         return 1;
1731                 }
1732         }
1733         return 0;
1734 }
1735
1736 static int nv_alloc_rx_optimized(struct net_device *dev)
1737 {
1738         struct fe_priv *np = netdev_priv(dev);
1739         struct ring_desc_ex* less_rx;
1740
1741         less_rx = np->get_rx.ex;
1742         if (less_rx-- == np->first_rx.ex)
1743                 less_rx = np->last_rx.ex;
1744
1745         while (np->put_rx.ex != less_rx) {
1746                 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1747                 if (skb) {
1748                         np->put_rx_ctx->skb = skb;
1749                         np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1750                                                              skb->data,
1751                                                              skb_tailroom(skb),
1752                                                              PCI_DMA_FROMDEVICE);
1753                         np->put_rx_ctx->dma_len = skb_tailroom(skb);
1754                         np->put_rx.ex->bufhigh = cpu_to_le32(dma_high(np->put_rx_ctx->dma));
1755                         np->put_rx.ex->buflow = cpu_to_le32(dma_low(np->put_rx_ctx->dma));
1756                         wmb();
1757                         np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
1758                         if (unlikely(np->put_rx.ex++ == np->last_rx.ex))
1759                                 np->put_rx.ex = np->first_rx.ex;
1760                         if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1761                                 np->put_rx_ctx = np->first_rx_ctx;
1762                 } else {
1763                         return 1;
1764                 }
1765         }
1766         return 0;
1767 }
1768
1769 /* If rx bufs are exhausted called after 50ms to attempt to refresh */
1770 #ifdef CONFIG_FORCEDETH_NAPI
1771 static void nv_do_rx_refill(unsigned long data)
1772 {
1773         struct net_device *dev = (struct net_device *) data;
1774         struct fe_priv *np = netdev_priv(dev);
1775
1776         /* Just reschedule NAPI rx processing */
1777         napi_schedule(&np->napi);
1778 }
1779 #else
1780 static void nv_do_rx_refill(unsigned long data)
1781 {
1782         struct net_device *dev = (struct net_device *) data;
1783         struct fe_priv *np = netdev_priv(dev);
1784         int retcode;
1785
1786         if (!using_multi_irqs(dev)) {
1787                 if (np->msi_flags & NV_MSI_X_ENABLED)
1788                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1789                 else
1790                         disable_irq(np->pci_dev->irq);
1791         } else {
1792                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1793         }
1794         if (!nv_optimized(np))
1795                 retcode = nv_alloc_rx(dev);
1796         else
1797                 retcode = nv_alloc_rx_optimized(dev);
1798         if (retcode) {
1799                 spin_lock_irq(&np->lock);
1800                 if (!np->in_shutdown)
1801                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1802                 spin_unlock_irq(&np->lock);
1803         }
1804         if (!using_multi_irqs(dev)) {
1805                 if (np->msi_flags & NV_MSI_X_ENABLED)
1806                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1807                 else
1808                         enable_irq(np->pci_dev->irq);
1809         } else {
1810                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1811         }
1812 }
1813 #endif
1814
1815 static void nv_init_rx(struct net_device *dev)
1816 {
1817         struct fe_priv *np = netdev_priv(dev);
1818         int i;
1819
1820         np->get_rx = np->put_rx = np->first_rx = np->rx_ring;
1821
1822         if (!nv_optimized(np))
1823                 np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1];
1824         else
1825                 np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1];
1826         np->get_rx_ctx = np->put_rx_ctx = np->first_rx_ctx = np->rx_skb;
1827         np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1];
1828
1829         for (i = 0; i < np->rx_ring_size; i++) {
1830                 if (!nv_optimized(np)) {
1831                         np->rx_ring.orig[i].flaglen = 0;
1832                         np->rx_ring.orig[i].buf = 0;
1833                 } else {
1834                         np->rx_ring.ex[i].flaglen = 0;
1835                         np->rx_ring.ex[i].txvlan = 0;
1836                         np->rx_ring.ex[i].bufhigh = 0;
1837                         np->rx_ring.ex[i].buflow = 0;
1838                 }
1839                 np->rx_skb[i].skb = NULL;
1840                 np->rx_skb[i].dma = 0;
1841         }
1842 }
1843
1844 static void nv_init_tx(struct net_device *dev)
1845 {
1846         struct fe_priv *np = netdev_priv(dev);
1847         int i;
1848
1849         np->get_tx = np->put_tx = np->first_tx = np->tx_ring;
1850
1851         if (!nv_optimized(np))
1852                 np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1];
1853         else
1854                 np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1];
1855         np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb;
1856         np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1];
1857         np->tx_pkts_in_progress = 0;
1858         np->tx_change_owner = NULL;
1859         np->tx_end_flip = NULL;
1860
1861         for (i = 0; i < np->tx_ring_size; i++) {
1862                 if (!nv_optimized(np)) {
1863                         np->tx_ring.orig[i].flaglen = 0;
1864                         np->tx_ring.orig[i].buf = 0;
1865                 } else {
1866                         np->tx_ring.ex[i].flaglen = 0;
1867                         np->tx_ring.ex[i].txvlan = 0;
1868                         np->tx_ring.ex[i].bufhigh = 0;
1869                         np->tx_ring.ex[i].buflow = 0;
1870                 }
1871                 np->tx_skb[i].skb = NULL;
1872                 np->tx_skb[i].dma = 0;
1873                 np->tx_skb[i].dma_len = 0;
1874                 np->tx_skb[i].first_tx_desc = NULL;
1875                 np->tx_skb[i].next_tx_ctx = NULL;
1876         }
1877 }
1878
1879 static int nv_init_ring(struct net_device *dev)
1880 {
1881         struct fe_priv *np = netdev_priv(dev);
1882
1883         nv_init_tx(dev);
1884         nv_init_rx(dev);
1885
1886         if (!nv_optimized(np))
1887                 return nv_alloc_rx(dev);
1888         else
1889                 return nv_alloc_rx_optimized(dev);
1890 }
1891
1892 static int nv_release_txskb(struct net_device *dev, struct nv_skb_map* tx_skb)
1893 {
1894         struct fe_priv *np = netdev_priv(dev);
1895
1896         if (tx_skb->dma) {
1897                 pci_unmap_page(np->pci_dev, tx_skb->dma,
1898                                tx_skb->dma_len,
1899                                PCI_DMA_TODEVICE);
1900                 tx_skb->dma = 0;
1901         }
1902         if (tx_skb->skb) {
1903                 dev_kfree_skb_any(tx_skb->skb);
1904                 tx_skb->skb = NULL;
1905                 return 1;
1906         } else {
1907                 return 0;
1908         }
1909 }
1910
1911 static void nv_drain_tx(struct net_device *dev)
1912 {
1913         struct fe_priv *np = netdev_priv(dev);
1914         unsigned int i;
1915
1916         for (i = 0; i < np->tx_ring_size; i++) {
1917                 if (!nv_optimized(np)) {
1918                         np->tx_ring.orig[i].flaglen = 0;
1919                         np->tx_ring.orig[i].buf = 0;
1920                 } else {
1921                         np->tx_ring.ex[i].flaglen = 0;
1922                         np->tx_ring.ex[i].txvlan = 0;
1923                         np->tx_ring.ex[i].bufhigh = 0;
1924                         np->tx_ring.ex[i].buflow = 0;
1925                 }
1926                 if (nv_release_txskb(dev, &np->tx_skb[i]))
1927                         dev->stats.tx_dropped++;
1928                 np->tx_skb[i].dma = 0;
1929                 np->tx_skb[i].dma_len = 0;
1930                 np->tx_skb[i].first_tx_desc = NULL;
1931                 np->tx_skb[i].next_tx_ctx = NULL;
1932         }
1933         np->tx_pkts_in_progress = 0;
1934         np->tx_change_owner = NULL;
1935         np->tx_end_flip = NULL;
1936 }
1937
1938 static void nv_drain_rx(struct net_device *dev)
1939 {
1940         struct fe_priv *np = netdev_priv(dev);
1941         int i;
1942
1943         for (i = 0; i < np->rx_ring_size; i++) {
1944                 if (!nv_optimized(np)) {
1945                         np->rx_ring.orig[i].flaglen = 0;
1946                         np->rx_ring.orig[i].buf = 0;
1947                 } else {
1948                         np->rx_ring.ex[i].flaglen = 0;
1949                         np->rx_ring.ex[i].txvlan = 0;
1950                         np->rx_ring.ex[i].bufhigh = 0;
1951                         np->rx_ring.ex[i].buflow = 0;
1952                 }
1953                 wmb();
1954                 if (np->rx_skb[i].skb) {
1955                         pci_unmap_single(np->pci_dev, np->rx_skb[i].dma,
1956                                          (skb_end_pointer(np->rx_skb[i].skb) -
1957                                           np->rx_skb[i].skb->data),
1958                                          PCI_DMA_FROMDEVICE);
1959                         dev_kfree_skb(np->rx_skb[i].skb);
1960                         np->rx_skb[i].skb = NULL;
1961                 }
1962         }
1963 }
1964
1965 static void nv_drain_rxtx(struct net_device *dev)
1966 {
1967         nv_drain_tx(dev);
1968         nv_drain_rx(dev);
1969 }
1970
1971 static inline u32 nv_get_empty_tx_slots(struct fe_priv *np)
1972 {
1973         return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size));
1974 }
1975
1976 static void nv_legacybackoff_reseed(struct net_device *dev)
1977 {
1978         u8 __iomem *base = get_hwbase(dev);
1979         u32 reg;
1980         u32 low;
1981         int tx_status = 0;
1982
1983         reg = readl(base + NvRegSlotTime) & ~NVREG_SLOTTIME_MASK;
1984         get_random_bytes(&low, sizeof(low));
1985         reg |= low & NVREG_SLOTTIME_MASK;
1986
1987         /* Need to stop tx before change takes effect.
1988          * Caller has already gained np->lock.
1989          */
1990         tx_status = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START;
1991         if (tx_status)
1992                 nv_stop_tx(dev);
1993         nv_stop_rx(dev);
1994         writel(reg, base + NvRegSlotTime);
1995         if (tx_status)
1996                 nv_start_tx(dev);
1997         nv_start_rx(dev);
1998 }
1999
2000 /* Gear Backoff Seeds */
2001 #define BACKOFF_SEEDSET_ROWS    8
2002 #define BACKOFF_SEEDSET_LFSRS   15
2003
2004 /* Known Good seed sets */
2005 static const u32 main_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
2006     {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2007     {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 385, 761, 790, 974},
2008     {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2009     {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 386, 761, 790, 974},
2010     {266, 265, 276, 585, 397, 208, 345, 355, 365, 376, 385, 396, 771, 700, 984},
2011     {266, 265, 276, 586, 397, 208, 346, 355, 365, 376, 285, 396, 771, 700, 984},
2012     {366, 365, 376, 686, 497, 308, 447, 455, 466, 476, 485, 496, 871, 800,  84},
2013     {466, 465, 476, 786, 597, 408, 547, 555, 566, 576, 585, 597, 971, 900, 184}};
2014
2015 static const u32 gear_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
2016     {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
2017     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2018     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 397},
2019     {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
2020     {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
2021     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2022     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2023     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395}};
2024
2025 static void nv_gear_backoff_reseed(struct net_device *dev)
2026 {
2027         u8 __iomem *base = get_hwbase(dev);
2028         u32 miniseed1, miniseed2, miniseed2_reversed, miniseed3, miniseed3_reversed;
2029         u32 temp, seedset, combinedSeed;
2030         int i;
2031
2032         /* Setup seed for free running LFSR */
2033         /* We are going to read the time stamp counter 3 times
2034            and swizzle bits around to increase randomness */
2035         get_random_bytes(&miniseed1, sizeof(miniseed1));
2036         miniseed1 &= 0x0fff;
2037         if (miniseed1 == 0)
2038                 miniseed1 = 0xabc;
2039
2040         get_random_bytes(&miniseed2, sizeof(miniseed2));
2041         miniseed2 &= 0x0fff;
2042         if (miniseed2 == 0)
2043                 miniseed2 = 0xabc;
2044         miniseed2_reversed =
2045                 ((miniseed2 & 0xF00) >> 8) |
2046                  (miniseed2 & 0x0F0) |
2047                  ((miniseed2 & 0x00F) << 8);
2048
2049         get_random_bytes(&miniseed3, sizeof(miniseed3));
2050         miniseed3 &= 0x0fff;
2051         if (miniseed3 == 0)
2052                 miniseed3 = 0xabc;
2053         miniseed3_reversed =
2054                 ((miniseed3 & 0xF00) >> 8) |
2055                  (miniseed3 & 0x0F0) |
2056                  ((miniseed3 & 0x00F) << 8);
2057
2058         combinedSeed = ((miniseed1 ^ miniseed2_reversed) << 12) |
2059                        (miniseed2 ^ miniseed3_reversed);
2060
2061         /* Seeds can not be zero */
2062         if ((combinedSeed & NVREG_BKOFFCTRL_SEED_MASK) == 0)
2063                 combinedSeed |= 0x08;
2064         if ((combinedSeed & (NVREG_BKOFFCTRL_SEED_MASK << NVREG_BKOFFCTRL_GEAR)) == 0)
2065                 combinedSeed |= 0x8000;
2066
2067         /* No need to disable tx here */
2068         temp = NVREG_BKOFFCTRL_DEFAULT | (0 << NVREG_BKOFFCTRL_SELECT);
2069         temp |= combinedSeed & NVREG_BKOFFCTRL_SEED_MASK;
2070         temp |= combinedSeed >> NVREG_BKOFFCTRL_GEAR;
2071         writel(temp,base + NvRegBackOffControl);
2072
2073         /* Setup seeds for all gear LFSRs. */
2074         get_random_bytes(&seedset, sizeof(seedset));
2075         seedset = seedset % BACKOFF_SEEDSET_ROWS;
2076         for (i = 1; i <= BACKOFF_SEEDSET_LFSRS; i++)
2077         {
2078                 temp = NVREG_BKOFFCTRL_DEFAULT | (i << NVREG_BKOFFCTRL_SELECT);
2079                 temp |= main_seedset[seedset][i-1] & 0x3ff;
2080                 temp |= ((gear_seedset[seedset][i-1] & 0x3ff) << NVREG_BKOFFCTRL_GEAR);
2081                 writel(temp, base + NvRegBackOffControl);
2082         }
2083 }
2084
2085 /*
2086  * nv_start_xmit: dev->hard_start_xmit function
2087  * Called with netif_tx_lock held.
2088  */
2089 static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
2090 {
2091         struct fe_priv *np = netdev_priv(dev);
2092         u32 tx_flags = 0;
2093         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
2094         unsigned int fragments = skb_shinfo(skb)->nr_frags;
2095         unsigned int i;
2096         u32 offset = 0;
2097         u32 bcnt;
2098         u32 size = skb->len-skb->data_len;
2099         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2100         u32 empty_slots;
2101         struct ring_desc* put_tx;
2102         struct ring_desc* start_tx;
2103         struct ring_desc* prev_tx;
2104         struct nv_skb_map* prev_tx_ctx;
2105         unsigned long flags;
2106
2107         /* add fragments to entries count */
2108         for (i = 0; i < fragments; i++) {
2109                 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
2110                            ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2111         }
2112
2113         spin_lock_irqsave(&np->lock, flags);
2114         empty_slots = nv_get_empty_tx_slots(np);
2115         if (unlikely(empty_slots <= entries)) {
2116                 netif_stop_queue(dev);
2117                 np->tx_stop = 1;
2118                 spin_unlock_irqrestore(&np->lock, flags);
2119                 return NETDEV_TX_BUSY;
2120         }
2121         spin_unlock_irqrestore(&np->lock, flags);
2122
2123         start_tx = put_tx = np->put_tx.orig;
2124
2125         /* setup the header buffer */
2126         do {
2127                 prev_tx = put_tx;
2128                 prev_tx_ctx = np->put_tx_ctx;
2129                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2130                 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2131                                                 PCI_DMA_TODEVICE);
2132                 np->put_tx_ctx->dma_len = bcnt;
2133                 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2134                 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2135
2136                 tx_flags = np->tx_flags;
2137                 offset += bcnt;
2138                 size -= bcnt;
2139                 if (unlikely(put_tx++ == np->last_tx.orig))
2140                         put_tx = np->first_tx.orig;
2141                 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2142                         np->put_tx_ctx = np->first_tx_ctx;
2143         } while (size);
2144
2145         /* setup the fragments */
2146         for (i = 0; i < fragments; i++) {
2147                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2148                 u32 size = frag->size;
2149                 offset = 0;
2150
2151                 do {
2152                         prev_tx = put_tx;
2153                         prev_tx_ctx = np->put_tx_ctx;
2154                         bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2155                         np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
2156                                                            PCI_DMA_TODEVICE);
2157                         np->put_tx_ctx->dma_len = bcnt;
2158                         put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2159                         put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2160
2161                         offset += bcnt;
2162                         size -= bcnt;
2163                         if (unlikely(put_tx++ == np->last_tx.orig))
2164                                 put_tx = np->first_tx.orig;
2165                         if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2166                                 np->put_tx_ctx = np->first_tx_ctx;
2167                 } while (size);
2168         }
2169
2170         /* set last fragment flag  */
2171         prev_tx->flaglen |= cpu_to_le32(tx_flags_extra);
2172
2173         /* save skb in this slot's context area */
2174         prev_tx_ctx->skb = skb;
2175
2176         if (skb_is_gso(skb))
2177                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2178         else
2179                 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2180                          NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2181
2182         spin_lock_irqsave(&np->lock, flags);
2183
2184         /* set tx flags */
2185         start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2186         np->put_tx.orig = put_tx;
2187
2188         spin_unlock_irqrestore(&np->lock, flags);
2189
2190         dprintk(KERN_DEBUG "%s: nv_start_xmit: entries %d queued for transmission. tx_flags_extra: %x\n",
2191                 dev->name, entries, tx_flags_extra);
2192         {
2193                 int j;
2194                 for (j=0; j<64; j++) {
2195                         if ((j%16) == 0)
2196                                 dprintk("\n%03x:", j);
2197                         dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2198                 }
2199                 dprintk("\n");
2200         }
2201
2202         dev->trans_start = jiffies;
2203         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2204         return NETDEV_TX_OK;
2205 }
2206
2207 static int nv_start_xmit_optimized(struct sk_buff *skb, struct net_device *dev)
2208 {
2209         struct fe_priv *np = netdev_priv(dev);
2210         u32 tx_flags = 0;
2211         u32 tx_flags_extra;
2212         unsigned int fragments = skb_shinfo(skb)->nr_frags;
2213         unsigned int i;
2214         u32 offset = 0;
2215         u32 bcnt;
2216         u32 size = skb->len-skb->data_len;
2217         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2218         u32 empty_slots;
2219         struct ring_desc_ex* put_tx;
2220         struct ring_desc_ex* start_tx;
2221         struct ring_desc_ex* prev_tx;
2222         struct nv_skb_map* prev_tx_ctx;
2223         struct nv_skb_map* start_tx_ctx;
2224         unsigned long flags;
2225
2226         /* add fragments to entries count */
2227         for (i = 0; i < fragments; i++) {
2228                 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
2229                            ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2230         }
2231
2232         spin_lock_irqsave(&np->lock, flags);
2233         empty_slots = nv_get_empty_tx_slots(np);
2234         if (unlikely(empty_slots <= entries)) {
2235                 netif_stop_queue(dev);
2236                 np->tx_stop = 1;
2237                 spin_unlock_irqrestore(&np->lock, flags);
2238                 return NETDEV_TX_BUSY;
2239         }
2240         spin_unlock_irqrestore(&np->lock, flags);
2241
2242         start_tx = put_tx = np->put_tx.ex;
2243         start_tx_ctx = np->put_tx_ctx;
2244
2245         /* setup the header buffer */
2246         do {
2247                 prev_tx = put_tx;
2248                 prev_tx_ctx = np->put_tx_ctx;
2249                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2250                 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2251                                                 PCI_DMA_TODEVICE);
2252                 np->put_tx_ctx->dma_len = bcnt;
2253                 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2254                 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2255                 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2256
2257                 tx_flags = NV_TX2_VALID;
2258                 offset += bcnt;
2259                 size -= bcnt;
2260                 if (unlikely(put_tx++ == np->last_tx.ex))
2261                         put_tx = np->first_tx.ex;
2262                 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2263                         np->put_tx_ctx = np->first_tx_ctx;
2264         } while (size);
2265
2266         /* setup the fragments */
2267         for (i = 0; i < fragments; i++) {
2268                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2269                 u32 size = frag->size;
2270                 offset = 0;
2271
2272                 do {
2273                         prev_tx = put_tx;
2274                         prev_tx_ctx = np->put_tx_ctx;
2275                         bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2276                         np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
2277                                                            PCI_DMA_TODEVICE);
2278                         np->put_tx_ctx->dma_len = bcnt;
2279                         put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2280                         put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2281                         put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2282
2283                         offset += bcnt;
2284                         size -= bcnt;
2285                         if (unlikely(put_tx++ == np->last_tx.ex))
2286                                 put_tx = np->first_tx.ex;
2287                         if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2288                                 np->put_tx_ctx = np->first_tx_ctx;
2289                 } while (size);
2290         }
2291
2292         /* set last fragment flag  */
2293         prev_tx->flaglen |= cpu_to_le32(NV_TX2_LASTPACKET);
2294
2295         /* save skb in this slot's context area */
2296         prev_tx_ctx->skb = skb;
2297
2298         if (skb_is_gso(skb))
2299                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2300         else
2301                 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2302                          NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2303
2304         /* vlan tag */
2305         if (likely(!np->vlangrp)) {
2306                 start_tx->txvlan = 0;
2307         } else {
2308                 if (vlan_tx_tag_present(skb))
2309                         start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT | vlan_tx_tag_get(skb));
2310                 else
2311                         start_tx->txvlan = 0;
2312         }
2313
2314         spin_lock_irqsave(&np->lock, flags);
2315
2316         if (np->tx_limit) {
2317                 /* Limit the number of outstanding tx. Setup all fragments, but
2318                  * do not set the VALID bit on the first descriptor. Save a pointer
2319                  * to that descriptor and also for next skb_map element.
2320                  */
2321
2322                 if (np->tx_pkts_in_progress == NV_TX_LIMIT_COUNT) {
2323                         if (!np->tx_change_owner)
2324                                 np->tx_change_owner = start_tx_ctx;
2325
2326                         /* remove VALID bit */
2327                         tx_flags &= ~NV_TX2_VALID;
2328                         start_tx_ctx->first_tx_desc = start_tx;
2329                         start_tx_ctx->next_tx_ctx = np->put_tx_ctx;
2330                         np->tx_end_flip = np->put_tx_ctx;
2331                 } else {
2332                         np->tx_pkts_in_progress++;
2333                 }
2334         }
2335
2336         /* set tx flags */
2337         start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2338         np->put_tx.ex = put_tx;
2339
2340         spin_unlock_irqrestore(&np->lock, flags);
2341
2342         dprintk(KERN_DEBUG "%s: nv_start_xmit_optimized: entries %d queued for transmission. tx_flags_extra: %x\n",
2343                 dev->name, entries, tx_flags_extra);
2344         {
2345                 int j;
2346                 for (j=0; j<64; j++) {
2347                         if ((j%16) == 0)
2348                                 dprintk("\n%03x:", j);
2349                         dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2350                 }
2351                 dprintk("\n");
2352         }
2353
2354         dev->trans_start = jiffies;
2355         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2356         return NETDEV_TX_OK;
2357 }
2358
2359 static inline void nv_tx_flip_ownership(struct net_device *dev)
2360 {
2361         struct fe_priv *np = netdev_priv(dev);
2362
2363         np->tx_pkts_in_progress--;
2364         if (np->tx_change_owner) {
2365                 np->tx_change_owner->first_tx_desc->flaglen |=
2366                         cpu_to_le32(NV_TX2_VALID);
2367                 np->tx_pkts_in_progress++;
2368
2369                 np->tx_change_owner = np->tx_change_owner->next_tx_ctx;
2370                 if (np->tx_change_owner == np->tx_end_flip)
2371                         np->tx_change_owner = NULL;
2372
2373                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2374         }
2375 }
2376
2377 /*
2378  * nv_tx_done: check for completed packets, release the skbs.
2379  *
2380  * Caller must own np->lock.
2381  */
2382 static void nv_tx_done(struct net_device *dev)
2383 {
2384         struct fe_priv *np = netdev_priv(dev);
2385         u32 flags;
2386         struct ring_desc* orig_get_tx = np->get_tx.orig;
2387
2388         while ((np->get_tx.orig != np->put_tx.orig) &&
2389                !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID)) {
2390
2391                 dprintk(KERN_DEBUG "%s: nv_tx_done: flags 0x%x.\n",
2392                                         dev->name, flags);
2393
2394                 pci_unmap_page(np->pci_dev, np->get_tx_ctx->dma,
2395                                np->get_tx_ctx->dma_len,
2396                                PCI_DMA_TODEVICE);
2397                 np->get_tx_ctx->dma = 0;
2398
2399                 if (np->desc_ver == DESC_VER_1) {
2400                         if (flags & NV_TX_LASTPACKET) {
2401                                 if (flags & NV_TX_ERROR) {
2402                                         if (flags & NV_TX_UNDERFLOW)
2403                                                 dev->stats.tx_fifo_errors++;
2404                                         if (flags & NV_TX_CARRIERLOST)
2405                                                 dev->stats.tx_carrier_errors++;
2406                                         if ((flags & NV_TX_RETRYERROR) && !(flags & NV_TX_RETRYCOUNT_MASK))
2407                                                 nv_legacybackoff_reseed(dev);
2408                                         dev->stats.tx_errors++;
2409                                 } else {
2410                                         dev->stats.tx_packets++;
2411                                         dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
2412                                 }
2413                                 dev_kfree_skb_any(np->get_tx_ctx->skb);
2414                                 np->get_tx_ctx->skb = NULL;
2415                         }
2416                 } else {
2417                         if (flags & NV_TX2_LASTPACKET) {
2418                                 if (flags & NV_TX2_ERROR) {
2419                                         if (flags & NV_TX2_UNDERFLOW)
2420                                                 dev->stats.tx_fifo_errors++;
2421                                         if (flags & NV_TX2_CARRIERLOST)
2422                                                 dev->stats.tx_carrier_errors++;
2423                                         if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK))
2424                                                 nv_legacybackoff_reseed(dev);
2425                                         dev->stats.tx_errors++;
2426                                 } else {
2427                                         dev->stats.tx_packets++;
2428                                         dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
2429                                 }
2430                                 dev_kfree_skb_any(np->get_tx_ctx->skb);
2431                                 np->get_tx_ctx->skb = NULL;
2432                         }
2433                 }
2434                 if (unlikely(np->get_tx.orig++ == np->last_tx.orig))
2435                         np->get_tx.orig = np->first_tx.orig;
2436                 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2437                         np->get_tx_ctx = np->first_tx_ctx;
2438         }
2439         if (unlikely((np->tx_stop == 1) && (np->get_tx.orig != orig_get_tx))) {
2440                 np->tx_stop = 0;
2441                 netif_wake_queue(dev);
2442         }
2443 }
2444
2445 static void nv_tx_done_optimized(struct net_device *dev, int limit)
2446 {
2447         struct fe_priv *np = netdev_priv(dev);
2448         u32 flags;
2449         struct ring_desc_ex* orig_get_tx = np->get_tx.ex;
2450
2451         while ((np->get_tx.ex != np->put_tx.ex) &&
2452                !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX_VALID) &&
2453                (limit-- > 0)) {
2454
2455                 dprintk(KERN_DEBUG "%s: nv_tx_done_optimized: flags 0x%x.\n",
2456                                         dev->name, flags);
2457
2458                 pci_unmap_page(np->pci_dev, np->get_tx_ctx->dma,
2459                                np->get_tx_ctx->dma_len,
2460                                PCI_DMA_TODEVICE);
2461                 np->get_tx_ctx->dma = 0;
2462
2463                 if (flags & NV_TX2_LASTPACKET) {
2464                         if (!(flags & NV_TX2_ERROR))
2465                                 dev->stats.tx_packets++;
2466                         else {
2467                                 if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK)) {
2468                                         if (np->driver_data & DEV_HAS_GEAR_MODE)
2469                                                 nv_gear_backoff_reseed(dev);
2470                                         else
2471                                                 nv_legacybackoff_reseed(dev);
2472                                 }
2473                         }
2474
2475                         dev_kfree_skb_any(np->get_tx_ctx->skb);
2476                         np->get_tx_ctx->skb = NULL;
2477
2478                         if (np->tx_limit) {
2479                                 nv_tx_flip_ownership(dev);
2480                         }
2481                 }
2482                 if (unlikely(np->get_tx.ex++ == np->last_tx.ex))
2483                         np->get_tx.ex = np->first_tx.ex;
2484                 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2485                         np->get_tx_ctx = np->first_tx_ctx;
2486         }
2487         if (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) {
2488                 np->tx_stop = 0;
2489                 netif_wake_queue(dev);
2490         }
2491 }
2492
2493 /*
2494  * nv_tx_timeout: dev->tx_timeout function
2495  * Called with netif_tx_lock held.
2496  */
2497 static void nv_tx_timeout(struct net_device *dev)
2498 {
2499         struct fe_priv *np = netdev_priv(dev);
2500         u8 __iomem *base = get_hwbase(dev);
2501         u32 status;
2502
2503         if (np->msi_flags & NV_MSI_X_ENABLED)
2504                 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2505         else
2506                 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2507
2508         printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name, status);
2509
2510         {
2511                 int i;
2512
2513                 printk(KERN_INFO "%s: Ring at %lx\n",
2514                        dev->name, (unsigned long)np->ring_addr);
2515                 printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
2516                 for (i=0;i<=np->register_size;i+= 32) {
2517                         printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
2518                                         i,
2519                                         readl(base + i + 0), readl(base + i + 4),
2520                                         readl(base + i + 8), readl(base + i + 12),
2521                                         readl(base + i + 16), readl(base + i + 20),
2522                                         readl(base + i + 24), readl(base + i + 28));
2523                 }
2524                 printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
2525                 for (i=0;i<np->tx_ring_size;i+= 4) {
2526                         if (!nv_optimized(np)) {
2527                                 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
2528                                        i,
2529                                        le32_to_cpu(np->tx_ring.orig[i].buf),
2530                                        le32_to_cpu(np->tx_ring.orig[i].flaglen),
2531                                        le32_to_cpu(np->tx_ring.orig[i+1].buf),
2532                                        le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
2533                                        le32_to_cpu(np->tx_ring.orig[i+2].buf),
2534                                        le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
2535                                        le32_to_cpu(np->tx_ring.orig[i+3].buf),
2536                                        le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
2537                         } else {
2538                                 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
2539                                        i,
2540                                        le32_to_cpu(np->tx_ring.ex[i].bufhigh),
2541                                        le32_to_cpu(np->tx_ring.ex[i].buflow),
2542                                        le32_to_cpu(np->tx_ring.ex[i].flaglen),
2543                                        le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
2544                                        le32_to_cpu(np->tx_ring.ex[i+1].buflow),
2545                                        le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
2546                                        le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
2547                                        le32_to_cpu(np->tx_ring.ex[i+2].buflow),
2548                                        le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
2549                                        le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
2550                                        le32_to_cpu(np->tx_ring.ex[i+3].buflow),
2551                                        le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
2552                         }
2553                 }
2554         }
2555
2556         spin_lock_irq(&np->lock);
2557
2558         /* 1) stop tx engine */
2559         nv_stop_tx(dev);
2560
2561         /* 2) check that the packets were not sent already: */
2562         if (!nv_optimized(np))
2563                 nv_tx_done(dev);
2564         else
2565                 nv_tx_done_optimized(dev, np->tx_ring_size);
2566
2567         /* 3) if there are dead entries: clear everything */
2568         if (np->get_tx_ctx != np->put_tx_ctx) {
2569                 printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name);
2570                 nv_drain_tx(dev);
2571                 nv_init_tx(dev);
2572                 setup_hw_rings(dev, NV_SETUP_TX_RING);
2573         }
2574
2575         netif_wake_queue(dev);
2576
2577         /* 4) restart tx engine */
2578         nv_start_tx(dev);
2579         spin_unlock_irq(&np->lock);
2580 }
2581
2582 /*
2583  * Called when the nic notices a mismatch between the actual data len on the
2584  * wire and the len indicated in the 802 header
2585  */
2586 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
2587 {
2588         int hdrlen;     /* length of the 802 header */
2589         int protolen;   /* length as stored in the proto field */
2590
2591         /* 1) calculate len according to header */
2592         if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
2593                 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
2594                 hdrlen = VLAN_HLEN;
2595         } else {
2596                 protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
2597                 hdrlen = ETH_HLEN;
2598         }
2599         dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
2600                                 dev->name, datalen, protolen, hdrlen);
2601         if (protolen > ETH_DATA_LEN)
2602                 return datalen; /* Value in proto field not a len, no checks possible */
2603
2604         protolen += hdrlen;
2605         /* consistency checks: */
2606         if (datalen > ETH_ZLEN) {
2607                 if (datalen >= protolen) {
2608                         /* more data on wire than in 802 header, trim of
2609                          * additional data.
2610                          */
2611                         dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2612                                         dev->name, protolen);
2613                         return protolen;
2614                 } else {
2615                         /* less data on wire than mentioned in header.
2616                          * Discard the packet.
2617                          */
2618                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
2619                                         dev->name);
2620                         return -1;
2621                 }
2622         } else {
2623                 /* short packet. Accept only if 802 values are also short */
2624                 if (protolen > ETH_ZLEN) {
2625                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
2626                                         dev->name);
2627                         return -1;
2628                 }
2629                 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2630                                 dev->name, datalen);
2631                 return datalen;
2632         }
2633 }
2634
2635 static int nv_rx_process(struct net_device *dev, int limit)
2636 {
2637         struct fe_priv *np = netdev_priv(dev);
2638         u32 flags;
2639         int rx_work = 0;
2640         struct sk_buff *skb;
2641         int len;
2642
2643         while((np->get_rx.orig != np->put_rx.orig) &&
2644               !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) &&
2645                 (rx_work < limit)) {
2646
2647                 dprintk(KERN_DEBUG "%s: nv_rx_process: flags 0x%x.\n",
2648                                         dev->name, flags);
2649
2650                 /*
2651                  * the packet is for us - immediately tear down the pci mapping.
2652                  * TODO: check if a prefetch of the first cacheline improves
2653                  * the performance.
2654                  */
2655                 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2656                                 np->get_rx_ctx->dma_len,
2657                                 PCI_DMA_FROMDEVICE);
2658                 skb = np->get_rx_ctx->skb;
2659                 np->get_rx_ctx->skb = NULL;
2660
2661                 {
2662                         int j;
2663                         dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
2664                         for (j=0; j<64; j++) {
2665                                 if ((j%16) == 0)
2666                                         dprintk("\n%03x:", j);
2667                                 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2668                         }
2669                         dprintk("\n");
2670                 }
2671                 /* look at what we actually got: */
2672                 if (np->desc_ver == DESC_VER_1) {
2673                         if (likely(flags & NV_RX_DESCRIPTORVALID)) {
2674                                 len = flags & LEN_MASK_V1;
2675                                 if (unlikely(flags & NV_RX_ERROR)) {
2676                                         if ((flags & NV_RX_ERROR_MASK) == NV_RX_ERROR4) {
2677                                                 len = nv_getlen(dev, skb->data, len);
2678                                                 if (len < 0) {
2679                                                         dev->stats.rx_errors++;
2680                                                         dev_kfree_skb(skb);
2681                                                         goto next_pkt;
2682                                                 }
2683                                         }
2684                                         /* framing errors are soft errors */
2685                                         else if ((flags & NV_RX_ERROR_MASK) == NV_RX_FRAMINGERR) {
2686                                                 if (flags & NV_RX_SUBSTRACT1) {
2687                                                         len--;
2688                                                 }
2689                                         }
2690                                         /* the rest are hard errors */
2691                                         else {
2692                                                 if (flags & NV_RX_MISSEDFRAME)
2693                                                         dev->stats.rx_missed_errors++;
2694                                                 if (flags & NV_RX_CRCERR)
2695                                                         dev->stats.rx_crc_errors++;
2696                                                 if (flags & NV_RX_OVERFLOW)
2697                                                         dev->stats.rx_over_errors++;
2698                                                 dev->stats.rx_errors++;
2699                                                 dev_kfree_skb(skb);
2700                                                 goto next_pkt;
2701                                         }
2702                                 }
2703                         } else {
2704                                 dev_kfree_skb(skb);
2705                                 goto next_pkt;
2706                         }
2707                 } else {
2708                         if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2709                                 len = flags & LEN_MASK_V2;
2710                                 if (unlikely(flags & NV_RX2_ERROR)) {
2711                                         if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
2712                                                 len = nv_getlen(dev, skb->data, len);
2713                                                 if (len < 0) {
2714                                                         dev->stats.rx_errors++;
2715                                                         dev_kfree_skb(skb);
2716                                                         goto next_pkt;
2717                                                 }
2718                                         }
2719                                         /* framing errors are soft errors */
2720                                         else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
2721                                                 if (flags & NV_RX2_SUBSTRACT1) {
2722                                                         len--;
2723                                                 }
2724                                         }
2725                                         /* the rest are hard errors */
2726                                         else {
2727                                                 if (flags & NV_RX2_CRCERR)
2728                                                         dev->stats.rx_crc_errors++;
2729                                                 if (flags & NV_RX2_OVERFLOW)
2730                                                         dev->stats.rx_over_errors++;
2731                                                 dev->stats.rx_errors++;
2732                                                 dev_kfree_skb(skb);
2733                                                 goto next_pkt;
2734                                         }
2735                                 }
2736                                 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2737                                     ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP))   /*ip and udp */
2738                                         skb->ip_summed = CHECKSUM_UNNECESSARY;
2739                         } else {
2740                                 dev_kfree_skb(skb);
2741                                 goto next_pkt;
2742                         }
2743                 }
2744                 /* got a valid packet - forward it to the network core */
2745                 skb_put(skb, len);
2746                 skb->protocol = eth_type_trans(skb, dev);
2747                 dprintk(KERN_DEBUG "%s: nv_rx_process: %d bytes, proto %d accepted.\n",
2748                                         dev->name, len, skb->protocol);
2749 #ifdef CONFIG_FORCEDETH_NAPI
2750                 netif_receive_skb(skb);
2751 #else
2752                 netif_rx(skb);
2753 #endif
2754                 dev->stats.rx_packets++;
2755                 dev->stats.rx_bytes += len;
2756 next_pkt:
2757                 if (unlikely(np->get_rx.orig++ == np->last_rx.orig))
2758                         np->get_rx.orig = np->first_rx.orig;
2759                 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2760                         np->get_rx_ctx = np->first_rx_ctx;
2761
2762                 rx_work++;
2763         }
2764
2765         return rx_work;
2766 }
2767
2768 static int nv_rx_process_optimized(struct net_device *dev, int limit)
2769 {
2770         struct fe_priv *np = netdev_priv(dev);
2771         u32 flags;
2772         u32 vlanflags = 0;
2773         int rx_work = 0;
2774         struct sk_buff *skb;
2775         int len;
2776
2777         while((np->get_rx.ex != np->put_rx.ex) &&
2778               !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) &&
2779               (rx_work < limit)) {
2780
2781                 dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: flags 0x%x.\n",
2782                                         dev->name, flags);
2783
2784                 /*
2785                  * the packet is for us - immediately tear down the pci mapping.
2786                  * TODO: check if a prefetch of the first cacheline improves
2787                  * the performance.
2788                  */
2789                 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2790                                 np->get_rx_ctx->dma_len,
2791                                 PCI_DMA_FROMDEVICE);
2792                 skb = np->get_rx_ctx->skb;
2793                 np->get_rx_ctx->skb = NULL;
2794
2795                 {
2796                         int j;
2797                         dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
2798                         for (j=0; j<64; j++) {
2799                                 if ((j%16) == 0)
2800                                         dprintk("\n%03x:", j);
2801                                 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2802                         }
2803                         dprintk("\n");
2804                 }
2805                 /* look at what we actually got: */
2806                 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2807                         len = flags & LEN_MASK_V2;
2808                         if (unlikely(flags & NV_RX2_ERROR)) {
2809                                 if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
2810                                         len = nv_getlen(dev, skb->data, len);
2811                                         if (len < 0) {
2812                                                 dev_kfree_skb(skb);
2813                                                 goto next_pkt;
2814                                         }
2815                                 }
2816                                 /* framing errors are soft errors */
2817                                 else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
2818                                         if (flags & NV_RX2_SUBSTRACT1) {
2819                                                 len--;
2820                                         }
2821                                 }
2822                                 /* the rest are hard errors */
2823                                 else {
2824                                         dev_kfree_skb(skb);
2825                                         goto next_pkt;
2826                                 }
2827                         }
2828
2829                         if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2830                             ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP))   /*ip and udp */
2831                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2832
2833                         /* got a valid packet - forward it to the network core */
2834                         skb_put(skb, len);
2835                         skb->protocol = eth_type_trans(skb, dev);
2836                         prefetch(skb->data);
2837
2838                         dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: %d bytes, proto %d accepted.\n",
2839                                 dev->name, len, skb->protocol);
2840
2841                         if (likely(!np->vlangrp)) {
2842 #ifdef CONFIG_FORCEDETH_NAPI
2843                                 netif_receive_skb(skb);
2844 #else
2845                                 netif_rx(skb);
2846 #endif
2847                         } else {
2848                                 vlanflags = le32_to_cpu(np->get_rx.ex->buflow);
2849                                 if (vlanflags & NV_RX3_VLAN_TAG_PRESENT) {
2850 #ifdef CONFIG_FORCEDETH_NAPI
2851                                         vlan_hwaccel_receive_skb(skb, np->vlangrp,
2852                                                                  vlanflags & NV_RX3_VLAN_TAG_MASK);
2853 #else
2854                                         vlan_hwaccel_rx(skb, np->vlangrp,
2855                                                         vlanflags & NV_RX3_VLAN_TAG_MASK);
2856 #endif
2857                                 } else {
2858 #ifdef CONFIG_FORCEDETH_NAPI
2859                                         netif_receive_skb(skb);
2860 #else
2861                                         netif_rx(skb);
2862 #endif
2863                                 }
2864                         }
2865
2866                         dev->stats.rx_packets++;
2867                         dev->stats.rx_bytes += len;
2868                 } else {
2869                         dev_kfree_skb(skb);
2870                 }
2871 next_pkt:
2872                 if (unlikely(np->get_rx.ex++ == np->last_rx.ex))
2873                         np->get_rx.ex = np->first_rx.ex;
2874                 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2875                         np->get_rx_ctx = np->first_rx_ctx;
2876
2877                 rx_work++;
2878         }
2879
2880         return rx_work;
2881 }
2882
2883 static void set_bufsize(struct net_device *dev)
2884 {
2885         struct fe_priv *np = netdev_priv(dev);
2886
2887         if (dev->mtu <= ETH_DATA_LEN)
2888                 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
2889         else
2890                 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
2891 }
2892
2893 /*
2894  * nv_change_mtu: dev->change_mtu function
2895  * Called with dev_base_lock held for read.
2896  */
2897 static int nv_change_mtu(struct net_device *dev, int new_mtu)
2898 {
2899         struct fe_priv *np = netdev_priv(dev);
2900         int old_mtu;
2901
2902         if (new_mtu < 64 || new_mtu > np->pkt_limit)
2903                 return -EINVAL;
2904
2905         old_mtu = dev->mtu;
2906         dev->mtu = new_mtu;
2907
2908         /* return early if the buffer sizes will not change */
2909         if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
2910                 return 0;
2911         if (old_mtu == new_mtu)
2912                 return 0;
2913
2914         /* synchronized against open : rtnl_lock() held by caller */
2915         if (netif_running(dev)) {
2916                 u8 __iomem *base = get_hwbase(dev);
2917                 /*
2918                  * It seems that the nic preloads valid ring entries into an
2919                  * internal buffer. The procedure for flushing everything is
2920                  * guessed, there is probably a simpler approach.
2921                  * Changing the MTU is a rare event, it shouldn't matter.
2922                  */
2923                 nv_disable_irq(dev);
2924                 netif_tx_lock_bh(dev);
2925                 netif_addr_lock(dev);
2926                 spin_lock(&np->lock);
2927                 /* stop engines */
2928                 nv_stop_rxtx(dev);
2929                 nv_txrx_reset(dev);
2930                 /* drain rx queue */
2931                 nv_drain_rxtx(dev);
2932                 /* reinit driver view of the rx queue */
2933                 set_bufsize(dev);
2934                 if (nv_init_ring(dev)) {
2935                         if (!np->in_shutdown)
2936                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2937                 }
2938                 /* reinit nic view of the rx queue */
2939                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
2940                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
2941                 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
2942                         base + NvRegRingSizes);
2943                 pci_push(base);
2944                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2945                 pci_push(base);
2946
2947                 /* restart rx engine */
2948                 nv_start_rxtx(dev);
2949                 spin_unlock(&np->lock);
2950                 netif_addr_unlock(dev);
2951                 netif_tx_unlock_bh(dev);
2952                 nv_enable_irq(dev);
2953         }
2954         return 0;
2955 }
2956
2957 static void nv_copy_mac_to_hw(struct net_device *dev)
2958 {
2959         u8 __iomem *base = get_hwbase(dev);
2960         u32 mac[2];
2961
2962         mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
2963                         (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
2964         mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
2965
2966         writel(mac[0], base + NvRegMacAddrA);
2967         writel(mac[1], base + NvRegMacAddrB);
2968 }
2969
2970 /*
2971  * nv_set_mac_address: dev->set_mac_address function
2972  * Called with rtnl_lock() held.
2973  */
2974 static int nv_set_mac_address(struct net_device *dev, void *addr)
2975 {
2976         struct fe_priv *np = netdev_priv(dev);
2977         struct sockaddr *macaddr = (struct sockaddr*)addr;
2978
2979         if (!is_valid_ether_addr(macaddr->sa_data))
2980                 return -EADDRNOTAVAIL;
2981
2982         /* synchronized against open : rtnl_lock() held by caller */
2983         memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
2984
2985         if (netif_running(dev)) {
2986                 netif_tx_lock_bh(dev);
2987                 netif_addr_lock(dev);
2988                 spin_lock_irq(&np->lock);
2989
2990                 /* stop rx engine */
2991                 nv_stop_rx(dev);
2992
2993                 /* set mac address */
2994                 nv_copy_mac_to_hw(dev);
2995
2996                 /* restart rx engine */
2997                 nv_start_rx(dev);
2998                 spin_unlock_irq(&np->lock);
2999                 netif_addr_unlock(dev);
3000                 netif_tx_unlock_bh(dev);
3001         } else {
3002                 nv_copy_mac_to_hw(dev);
3003         }
3004         return 0;
3005 }
3006
3007 /*
3008  * nv_set_multicast: dev->set_multicast function
3009  * Called with netif_tx_lock held.
3010  */
3011 static void nv_set_multicast(struct net_device *dev)
3012 {
3013         struct fe_priv *np = netdev_priv(dev);
3014         u8 __iomem *base = get_hwbase(dev);
3015         u32 addr[2];
3016         u32 mask[2];
3017         u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
3018
3019         memset(addr, 0, sizeof(addr));
3020         memset(mask, 0, sizeof(mask));
3021
3022         if (dev->flags & IFF_PROMISC) {
3023                 pff |= NVREG_PFF_PROMISC;
3024         } else {
3025                 pff |= NVREG_PFF_MYADDR;
3026
3027                 if (dev->flags & IFF_ALLMULTI || dev->mc_list) {
3028                         u32 alwaysOff[2];
3029                         u32 alwaysOn[2];
3030
3031                         alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
3032                         if (dev->flags & IFF_ALLMULTI) {
3033                                 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
3034                         } else {
3035                                 struct dev_mc_list *walk;
3036
3037                                 walk = dev->mc_list;
3038                                 while (walk != NULL) {
3039                                         u32 a, b;
3040                                         a = le32_to_cpu(*(__le32 *) walk->dmi_addr);
3041                                         b = le16_to_cpu(*(__le16 *) (&walk->dmi_addr[4]));
3042                                         alwaysOn[0] &= a;
3043                                         alwaysOff[0] &= ~a;
3044                                         alwaysOn[1] &= b;
3045                                         alwaysOff[1] &= ~b;
3046                                         walk = walk->next;
3047                                 }
3048                         }
3049                         addr[0] = alwaysOn[0];
3050                         addr[1] = alwaysOn[1];
3051                         mask[0] = alwaysOn[0] | alwaysOff[0];
3052                         mask[1] = alwaysOn[1] | alwaysOff[1];
3053                 } else {
3054                         mask[0] = NVREG_MCASTMASKA_NONE;
3055                         mask[1] = NVREG_MCASTMASKB_NONE;
3056                 }
3057         }
3058         addr[0] |= NVREG_MCASTADDRA_FORCE;
3059         pff |= NVREG_PFF_ALWAYS;
3060         spin_lock_irq(&np->lock);
3061         nv_stop_rx(dev);
3062         writel(addr[0], base + NvRegMulticastAddrA);
3063         writel(addr[1], base + NvRegMulticastAddrB);
3064         writel(mask[0], base + NvRegMulticastMaskA);
3065         writel(mask[1], base + NvRegMulticastMaskB);
3066         writel(pff, base + NvRegPacketFilterFlags);
3067         dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
3068                 dev->name);
3069         nv_start_rx(dev);
3070         spin_unlock_irq(&np->lock);
3071 }
3072
3073 static void nv_update_pause(struct net_device *dev, u32 pause_flags)
3074 {
3075         struct fe_priv *np = netdev_priv(dev);
3076         u8 __iomem *base = get_hwbase(dev);
3077
3078         np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
3079
3080         if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
3081                 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
3082                 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
3083                         writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
3084                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3085                 } else {
3086                         writel(pff, base + NvRegPacketFilterFlags);
3087                 }
3088         }
3089         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
3090                 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
3091                 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
3092                         u32 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V1;
3093                         if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V2)
3094                                 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V2;
3095                         if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V3) {
3096                                 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V3;
3097                                 /* limit the number of tx pause frames to a default of 8 */
3098                                 writel(readl(base + NvRegTxPauseFrameLimit)|NVREG_TX_PAUSEFRAMELIMIT_ENABLE, base + NvRegTxPauseFrameLimit);
3099                         }
3100                         writel(pause_enable,  base + NvRegTxPauseFrame);
3101                         writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
3102                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3103                 } else {
3104                         writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
3105                         writel(regmisc, base + NvRegMisc1);
3106                 }
3107         }
3108 }
3109
3110 /**
3111  * nv_update_linkspeed: Setup the MAC according to the link partner
3112  * @dev: Network device to be configured
3113  *
3114  * The function queries the PHY and checks if there is a link partner.
3115  * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
3116  * set to 10 MBit HD.
3117  *
3118  * The function returns 0 if there is no link partner and 1 if there is
3119  * a good link partner.
3120  */
3121 static int nv_update_linkspeed(struct net_device *dev)
3122 {
3123         struct fe_priv *np = netdev_priv(dev);
3124         u8 __iomem *base = get_hwbase(dev);
3125         int adv = 0;
3126         int lpa = 0;
3127         int adv_lpa, adv_pause, lpa_pause;
3128         int newls = np->linkspeed;
3129         int newdup = np->duplex;
3130         int mii_status;
3131         int retval = 0;
3132         u32 control_1000, status_1000, phyreg, pause_flags, txreg;
3133         u32 txrxFlags = 0;
3134         u32 phy_exp;
3135
3136         /* BMSR_LSTATUS is latched, read it twice:
3137          * we want the current value.
3138          */
3139         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3140         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3141
3142         if (!(mii_status & BMSR_LSTATUS)) {
3143                 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
3144                                 dev->name);
3145                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3146                 newdup = 0;
3147                 retval = 0;
3148                 goto set_speed;
3149         }
3150
3151         if (np->autoneg == 0) {
3152                 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
3153                                 dev->name, np->fixed_mode);
3154                 if (np->fixed_mode & LPA_100FULL) {
3155                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3156                         newdup = 1;
3157                 } else if (np->fixed_mode & LPA_100HALF) {
3158                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3159                         newdup = 0;
3160                 } else if (np->fixed_mode & LPA_10FULL) {
3161                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3162                         newdup = 1;
3163                 } else {
3164                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3165                         newdup = 0;
3166                 }
3167                 retval = 1;
3168                 goto set_speed;
3169         }
3170         /* check auto negotiation is complete */
3171         if (!(mii_status & BMSR_ANEGCOMPLETE)) {
3172                 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
3173                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3174                 newdup = 0;
3175                 retval = 0;
3176                 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
3177                 goto set_speed;
3178         }
3179
3180         adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3181         lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
3182         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
3183                                 dev->name, adv, lpa);
3184
3185         retval = 1;
3186         if (np->gigabit == PHY_GIGABIT) {
3187                 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3188                 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
3189
3190                 if ((control_1000 & ADVERTISE_1000FULL) &&
3191                         (status_1000 & LPA_1000FULL)) {
3192                         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
3193                                 dev->name);
3194                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
3195                         newdup = 1;
3196                         goto set_speed;
3197                 }
3198         }
3199
3200         /* FIXME: handle parallel detection properly */
3201         adv_lpa = lpa & adv;
3202         if (adv_lpa & LPA_100FULL) {
3203                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3204                 newdup = 1;
3205         } else if (adv_lpa & LPA_100HALF) {
3206                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3207                 newdup = 0;
3208         } else if (adv_lpa & LPA_10FULL) {
3209                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3210                 newdup = 1;
3211         } else if (adv_lpa & LPA_10HALF) {
3212                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3213                 newdup = 0;
3214         } else {
3215                 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, adv_lpa);
3216                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3217                 newdup = 0;
3218         }
3219
3220 set_speed:
3221         if (np->duplex == newdup && np->linkspeed == newls)
3222                 return retval;
3223
3224         dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
3225                         dev->name, np->linkspeed, np->duplex, newls, newdup);
3226
3227         np->duplex = newdup;
3228         np->linkspeed = newls;
3229
3230         /* The transmitter and receiver must be restarted for safe update */
3231         if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START) {
3232                 txrxFlags |= NV_RESTART_TX;
3233                 nv_stop_tx(dev);
3234         }
3235         if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
3236                 txrxFlags |= NV_RESTART_RX;
3237                 nv_stop_rx(dev);
3238         }
3239
3240         if (np->gigabit == PHY_GIGABIT) {
3241                 phyreg = readl(base + NvRegSlotTime);
3242                 phyreg &= ~(0x3FF00);
3243                 if (((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) ||
3244                     ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100))
3245                         phyreg |= NVREG_SLOTTIME_10_100_FULL;
3246                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
3247                         phyreg |= NVREG_SLOTTIME_1000_FULL;
3248                 writel(phyreg, base + NvRegSlotTime);
3249         }
3250
3251         phyreg = readl(base + NvRegPhyInterface);
3252         phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
3253         if (np->duplex == 0)
3254                 phyreg |= PHY_HALF;
3255         if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
3256                 phyreg |= PHY_100;
3257         else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3258                 phyreg |= PHY_1000;
3259         writel(phyreg, base + NvRegPhyInterface);
3260
3261         phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */
3262         if (phyreg & PHY_RGMII) {
3263                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) {
3264                         txreg = NVREG_TX_DEFERRAL_RGMII_1000;
3265                 } else {
3266                         if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX)) {
3267                                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_10)
3268                                         txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_10;
3269                                 else
3270                                         txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_100;
3271                         } else {
3272                                 txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
3273                         }
3274                 }
3275         } else {
3276                 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX))
3277                         txreg = NVREG_TX_DEFERRAL_MII_STRETCH;
3278                 else
3279                         txreg = NVREG_TX_DEFERRAL_DEFAULT;
3280         }
3281         writel(txreg, base + NvRegTxDeferral);
3282
3283         if (np->desc_ver == DESC_VER_1) {
3284                 txreg = NVREG_TX_WM_DESC1_DEFAULT;
3285         } else {
3286                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3287                         txreg = NVREG_TX_WM_DESC2_3_1000;
3288                 else
3289                         txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
3290         }
3291         writel(txreg, base + NvRegTxWatermark);
3292
3293         writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
3294                 base + NvRegMisc1);
3295         pci_push(base);
3296         writel(np->linkspeed, base + NvRegLinkSpeed);
3297         pci_push(base);
3298
3299         pause_flags = 0;
3300         /* setup pause frame */
3301         if (np->duplex != 0) {
3302                 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
3303                         adv_pause = adv & (ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM);
3304                         lpa_pause = lpa & (LPA_PAUSE_CAP| LPA_PAUSE_ASYM);
3305
3306                         switch (adv_pause) {
3307                         case ADVERTISE_PAUSE_CAP:
3308                                 if (lpa_pause & LPA_PAUSE_CAP) {
3309                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3310                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3311                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3312                                 }
3313                                 break;
3314                         case ADVERTISE_PAUSE_ASYM:
3315                                 if (lpa_pause == (LPA_PAUSE_CAP| LPA_PAUSE_ASYM))
3316                                 {
3317                                         pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3318                                 }
3319                                 break;
3320                         case ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM:
3321                                 if (lpa_pause & LPA_PAUSE_CAP)
3322                                 {
3323                                         pause_flags |=  NV_PAUSEFRAME_RX_ENABLE;
3324                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3325                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3326                                 }
3327                                 if (lpa_pause == LPA_PAUSE_ASYM)
3328                                 {
3329                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3330                                 }
3331                                 break;
3332                         }
3333                 } else {
3334                         pause_flags = np->pause_flags;
3335                 }
3336         }
3337         nv_update_pause(dev, pause_flags);
3338
3339         if (txrxFlags & NV_RESTART_TX)
3340                 nv_start_tx(dev);
3341         if (txrxFlags & NV_RESTART_RX)
3342                 nv_start_rx(dev);
3343
3344         return retval;
3345 }
3346
3347 static void nv_linkchange(struct net_device *dev)
3348 {
3349         if (nv_update_linkspeed(dev)) {
3350                 if (!netif_carrier_ok(dev)) {
3351                         netif_carrier_on(dev);
3352                         printk(KERN_INFO "%s: link up.\n", dev->name);
3353                         nv_start_rx(dev);
3354                 }
3355         } else {
3356                 if (netif_carrier_ok(dev)) {
3357                         netif_carrier_off(dev);
3358                         printk(KERN_INFO "%s: link down.\n", dev->name);
3359                         nv_stop_rx(dev);
3360                 }
3361         }
3362 }
3363
3364 static void nv_link_irq(struct net_device *dev)
3365 {
3366         u8 __iomem *base = get_hwbase(dev);
3367         u32 miistat;
3368
3369         miistat = readl(base + NvRegMIIStatus);
3370         writel(NVREG_MIISTAT_LINKCHANGE, base + NvRegMIIStatus);
3371         dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
3372
3373         if (miistat & (NVREG_MIISTAT_LINKCHANGE))
3374                 nv_linkchange(dev);
3375         dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
3376 }
3377
3378 static void nv_msi_workaround(struct fe_priv *np)
3379 {
3380
3381         /* Need to toggle the msi irq mask within the ethernet device,
3382          * otherwise, future interrupts will not be detected.
3383          */
3384         if (np->msi_flags & NV_MSI_ENABLED) {
3385                 u8 __iomem *base = np->base;
3386
3387                 writel(0, base + NvRegMSIIrqMask);
3388                 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3389         }
3390 }
3391
3392 static irqreturn_t nv_nic_irq(int foo, void *data)
3393 {
3394         struct net_device *dev = (struct net_device *) data;
3395         struct fe_priv *np = netdev_priv(dev);
3396         u8 __iomem *base = get_hwbase(dev);
3397         u32 events;
3398         int i;
3399
3400         dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
3401
3402         for (i=0; ; i++) {
3403                 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3404                         events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3405                         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3406                 } else {
3407                         events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3408                         writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
3409                 }
3410                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3411                 if (!(events & np->irqmask))
3412                         break;
3413
3414                 nv_msi_workaround(np);
3415
3416                 spin_lock(&np->lock);
3417                 nv_tx_done(dev);
3418                 spin_unlock(&np->lock);
3419
3420 #ifdef CONFIG_FORCEDETH_NAPI
3421                 if (events & NVREG_IRQ_RX_ALL) {
3422                         spin_lock(&np->lock);
3423                         napi_schedule(&np->napi);
3424
3425                         /* Disable furthur receive irq's */
3426                         np->irqmask &= ~NVREG_IRQ_RX_ALL;
3427
3428                         if (np->msi_flags & NV_MSI_X_ENABLED)
3429                                 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3430                         else
3431                                 writel(np->irqmask, base + NvRegIrqMask);
3432                         spin_unlock(&np->lock);
3433                 }
3434 #else
3435                 if (nv_rx_process(dev, RX_WORK_PER_LOOP)) {
3436                         if (unlikely(nv_alloc_rx(dev))) {
3437                                 spin_lock(&np->lock);
3438                                 if (!np->in_shutdown)
3439                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3440                                 spin_unlock(&np->lock);
3441                         }
3442                 }
3443 #endif
3444                 if (unlikely(events & NVREG_IRQ_LINK)) {
3445                         spin_lock(&np->lock);
3446                         nv_link_irq(dev);
3447                         spin_unlock(&np->lock);
3448                 }
3449                 if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3450                         spin_lock(&np->lock);
3451                         nv_linkchange(dev);
3452                         spin_unlock(&np->lock);
3453                         np->link_timeout = jiffies + LINK_TIMEOUT;
3454                 }
3455                 if (unlikely(events & (NVREG_IRQ_TX_ERR))) {
3456                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
3457                                                 dev->name, events);
3458                 }
3459                 if (unlikely(events & (NVREG_IRQ_UNKNOWN))) {
3460                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
3461                                                 dev->name, events);
3462                 }
3463                 if (unlikely(events & NVREG_IRQ_RECOVER_ERROR)) {
3464                         spin_lock(&np->lock);
3465                         /* disable interrupts on the nic */
3466                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
3467                                 writel(0, base + NvRegIrqMask);
3468                         else
3469                                 writel(np->irqmask, base + NvRegIrqMask);
3470                         pci_push(base);
3471
3472                         if (!np->in_shutdown) {
3473                                 np->nic_poll_irq = np->irqmask;
3474                                 np->recover_error = 1;
3475                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3476                         }
3477                         spin_unlock(&np->lock);
3478                         break;
3479                 }
3480                 if (unlikely(i > max_interrupt_work)) {
3481                         spin_lock(&np->lock);
3482                         /* disable interrupts on the nic */
3483                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
3484                                 writel(0, base + NvRegIrqMask);
3485                         else
3486                                 writel(np->irqmask, base + NvRegIrqMask);
3487                         pci_push(base);
3488
3489                         if (!np->in_shutdown) {
3490                                 np->nic_poll_irq = np->irqmask;
3491                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3492                         }
3493                         spin_unlock(&np->lock);
3494                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
3495                         break;
3496                 }
3497
3498         }
3499         dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
3500
3501         return IRQ_RETVAL(i);
3502 }
3503
3504 /**
3505  * All _optimized functions are used to help increase performance
3506  * (reduce CPU and increase throughput). They use descripter version 3,
3507  * compiler directives, and reduce memory accesses.
3508  */
3509 static irqreturn_t nv_nic_irq_optimized(int foo, void *data)
3510 {
3511         struct net_device *dev = (struct net_device *) data;
3512         struct fe_priv *np = netdev_priv(dev);
3513         u8 __iomem *base = get_hwbase(dev);
3514         u32 events;
3515         int i;
3516
3517         dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized\n", dev->name);
3518
3519         for (i=0; ; i++) {
3520                 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3521                         events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3522                         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3523                 } else {
3524                         events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3525                         writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
3526                 }
3527                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3528                 if (!(events & np->irqmask))
3529                         break;
3530
3531                 nv_msi_workaround(np);
3532
3533                 spin_lock(&np->lock);
3534                 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3535                 spin_unlock(&np->lock);
3536
3537 #ifdef CONFIG_FORCEDETH_NAPI
3538                 if (events & NVREG_IRQ_RX_ALL) {
3539                         spin_lock(&np->lock);
3540                         napi_schedule(&np->napi);
3541
3542                         /* Disable furthur receive irq's */
3543                         np->irqmask &= ~NVREG_IRQ_RX_ALL;
3544
3545                         if (np->msi_flags & NV_MSI_X_ENABLED)
3546                                 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3547                         else
3548                                 writel(np->irqmask, base + NvRegIrqMask);
3549                         spin_unlock(&np->lock);
3550                 }
3551 #else
3552                 if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
3553                         if (unlikely(nv_alloc_rx_optimized(dev))) {
3554                                 spin_lock(&np->lock);
3555                                 if (!np->in_shutdown)
3556                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3557                                 spin_unlock(&np->lock);
3558                         }
3559                 }
3560 #endif
3561                 if (unlikely(events & NVREG_IRQ_LINK)) {
3562                         spin_lock(&np->lock);
3563                         nv_link_irq(dev);
3564                         spin_unlock(&np->lock);
3565                 }
3566                 if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3567                         spin_lock(&np->lock);
3568                         nv_linkchange(dev);
3569                         spin_unlock(&np->lock);
3570                         np->link_timeout = jiffies + LINK_TIMEOUT;
3571                 }
3572                 if (unlikely(events & (NVREG_IRQ_TX_ERR))) {
3573                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
3574                                                 dev->name, events);
3575                 }
3576                 if (unlikely(events & (NVREG_IRQ_UNKNOWN))) {
3577                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
3578                                                 dev->name, events);
3579                 }
3580                 if (unlikely(events & NVREG_IRQ_RECOVER_ERROR)) {
3581                         spin_lock(&np->lock);
3582                         /* disable interrupts on the nic */
3583                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
3584                                 writel(0, base + NvRegIrqMask);
3585                         else
3586                                 writel(np->irqmask, base + NvRegIrqMask);
3587                         pci_push(base);
3588
3589                         if (!np->in_shutdown) {
3590                                 np->nic_poll_irq = np->irqmask;
3591                                 np->recover_error = 1;
3592                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3593                         }
3594                         spin_unlock(&np->lock);
3595                         break;
3596                 }
3597
3598                 if (unlikely(i > max_interrupt_work)) {
3599                         spin_lock(&np->lock);
3600                         /* disable interrupts on the nic */
3601                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
3602                                 writel(0, base + NvRegIrqMask);
3603                         else
3604                                 writel(np->irqmask, base + NvRegIrqMask);
3605                         pci_push(base);
3606
3607                         if (!np->in_shutdown) {
3608                                 np->nic_poll_irq = np->irqmask;
3609                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3610                         }
3611                         spin_unlock(&np->lock);
3612                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
3613                         break;
3614                 }
3615
3616         }
3617         dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized completed\n", dev->name);
3618
3619         return IRQ_RETVAL(i);
3620 }
3621
3622 static irqreturn_t nv_nic_irq_tx(int foo, void *data)
3623 {
3624         struct net_device *dev = (struct net_device *) data;
3625         struct fe_priv *np = netdev_priv(dev);
3626         u8 __iomem *base = get_hwbase(dev);
3627         u32 events;
3628         int i;
3629         unsigned long flags;
3630
3631         dprintk(KERN_DEBUG "%s: nv_nic_irq_tx\n", dev->name);
3632
3633         for (i=0; ; i++) {
3634                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
3635                 writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);
3636                 dprintk(KERN_DEBUG "%s: tx irq: %08x\n", dev->name, events);
3637                 if (!(events & np->irqmask))
3638                         break;
3639
3640                 spin_lock_irqsave(&np->lock, flags);
3641                 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3642                 spin_unlock_irqrestore(&np->lock, flags);
3643
3644                 if (unlikely(events & (NVREG_IRQ_TX_ERR))) {
3645                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
3646                                                 dev->name, events);
3647                 }
3648                 if (unlikely(i > max_interrupt_work)) {
3649                         spin_lock_irqsave(&np->lock, flags);
3650                         /* disable interrupts on the nic */
3651                         writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
3652                         pci_push(base);
3653
3654                         if (!np->in_shutdown) {
3655                                 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
3656                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3657                         }
3658                         spin_unlock_irqrestore(&np->lock, flags);
3659                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i);
3660                         break;
3661                 }
3662
3663         }
3664         dprintk(KERN_DEBUG "%s: nv_nic_irq_tx completed\n", dev->name);
3665
3666         return IRQ_RETVAL(i);
3667 }
3668
3669 #ifdef CONFIG_FORCEDETH_NAPI
3670 static int nv_napi_poll(struct napi_struct *napi, int budget)
3671 {
3672         struct fe_priv *np = container_of(napi, struct fe_priv, napi);
3673         struct net_device *dev = np->dev;
3674         u8 __iomem *base = get_hwbase(dev);
3675         unsigned long flags;
3676         int pkts, retcode;
3677
3678         if (!nv_optimized(np)) {
3679                 pkts = nv_rx_process(dev, budget);
3680                 retcode = nv_alloc_rx(dev);
3681         } else {
3682                 pkts = nv_rx_process_optimized(dev, budget);
3683                 retcode = nv_alloc_rx_optimized(dev);
3684         }
3685
3686         if (retcode) {
3687                 spin_lock_irqsave(&np->lock, flags);
3688                 if (!np->in_shutdown)
3689                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3690                 spin_unlock_irqrestore(&np->lock, flags);
3691         }
3692
3693         if (pkts < budget) {
3694                 /* re-enable receive interrupts */
3695                 spin_lock_irqsave(&np->lock, flags);
3696
3697                 __napi_complete(napi);
3698
3699                 np->irqmask |= NVREG_IRQ_RX_ALL;
3700                 if (np->msi_flags & NV_MSI_X_ENABLED)
3701                         writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3702                 else
3703                         writel(np->irqmask, base + NvRegIrqMask);
3704
3705                 spin_unlock_irqrestore(&np->lock, flags);
3706         }
3707         return pkts;
3708 }
3709 #endif
3710
3711 #ifdef CONFIG_FORCEDETH_NAPI
3712 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
3713 {
3714         struct net_device *dev = (struct net_device *) data;
3715         struct fe_priv *np = netdev_priv(dev);
3716         u8 __iomem *base = get_hwbase(dev);
3717         u32 events;
3718
3719         events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3720
3721         if (events) {
3722                 /* disable receive interrupts on the nic */
3723                 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3724                 pci_push(base);
3725                 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
3726                 napi_schedule(&np->napi);
3727         }
3728         return IRQ_HANDLED;
3729 }
3730 #else
3731 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
3732 {
3733         struct net_device *dev = (struct net_device *) data;
3734         struct fe_priv *np = netdev_priv(dev);
3735         u8 __iomem *base = get_hwbase(dev);
3736         u32 events;
3737         int i;
3738         unsigned long flags;
3739
3740         dprintk(KERN_DEBUG "%s: nv_nic_irq_rx\n", dev->name);
3741
3742         for (i=0; ; i++) {
3743                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3744                 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
3745                 dprintk(KERN_DEBUG "%s: rx irq: %08x\n", dev->name, events);
3746                 if (!(events & np->irqmask))
3747                         break;
3748
3749                 if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
3750                         if (unlikely(nv_alloc_rx_optimized(dev))) {
3751                                 spin_lock_irqsave(&np->lock, flags);
3752                                 if (!np->in_shutdown)
3753                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3754                                 spin_unlock_irqrestore(&np->lock, flags);
3755                         }
3756                 }
3757
3758                 if (unlikely(i > max_interrupt_work)) {
3759                         spin_lock_irqsave(&np->lock, flags);
3760                         /* disable interrupts on the nic */
3761                         writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3762                         pci_push(base);
3763
3764                         if (!np->in_shutdown) {
3765                                 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
3766                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3767                         }
3768                         spin_unlock_irqrestore(&np->lock, flags);
3769                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i);
3770                         break;
3771                 }
3772         }
3773         dprintk(KERN_DEBUG "%s: nv_nic_irq_rx completed\n", dev->name);
3774
3775         return IRQ_RETVAL(i);
3776 }
3777 #endif
3778
3779 static irqreturn_t nv_nic_irq_other(int foo, void *data)
3780 {
3781         struct net_device *dev = (struct net_device *) data;
3782         struct fe_priv *np = netdev_priv(dev);
3783         u8 __iomem *base = get_hwbase(dev);
3784         u32 events;
3785         int i;
3786         unsigned long flags;
3787
3788         dprintk(KERN_DEBUG "%s: nv_nic_irq_other\n", dev->name);
3789
3790         for (i=0; ; i++) {
3791                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
3792                 writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus);
3793                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3794                 if (!(events & np->irqmask))
3795                         break;
3796
3797                 /* check tx in case we reached max loop limit in tx isr */
3798                 spin_lock_irqsave(&np->lock, flags);
3799                 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3800                 spin_unlock_irqrestore(&np->lock, flags);
3801
3802                 if (events & NVREG_IRQ_LINK) {
3803                         spin_lock_irqsave(&np->lock, flags);
3804                         nv_link_irq(dev);
3805                         spin_unlock_irqrestore(&np->lock, flags);
3806                 }
3807                 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
3808                         spin_lock_irqsave(&np->lock, flags);
3809                         nv_linkchange(dev);
3810                         spin_unlock_irqrestore(&np->lock, flags);
3811                         np->link_timeout = jiffies + LINK_TIMEOUT;
3812                 }
3813                 if (events & NVREG_IRQ_RECOVER_ERROR) {
3814                         spin_lock_irq(&np->lock);
3815                         /* disable interrupts on the nic */
3816                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3817                         pci_push(base);
3818
3819                         if (!np->in_shutdown) {
3820                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3821                                 np->recover_error = 1;
3822                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3823                         }
3824                         spin_unlock_irq(&np->lock);
3825                         break;
3826                 }
3827                 if (events & (NVREG_IRQ_UNKNOWN)) {
3828                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
3829                                                 dev->name, events);
3830                 }
3831                 if (unlikely(i > max_interrupt_work)) {
3832                         spin_lock_irqsave(&np->lock, flags);
3833                         /* disable interrupts on the nic */
3834                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3835                         pci_push(base);
3836
3837                         if (!np->in_shutdown) {
3838                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3839                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3840                         }
3841                         spin_unlock_irqrestore(&np->lock, flags);
3842                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i);
3843                         break;
3844                 }
3845
3846         }
3847         dprintk(KERN_DEBUG "%s: nv_nic_irq_other completed\n", dev->name);
3848
3849         return IRQ_RETVAL(i);
3850 }
3851
3852 static irqreturn_t nv_nic_irq_test(int foo, void *data)
3853 {
3854         struct net_device *dev = (struct net_device *) data;
3855         struct fe_priv *np = netdev_priv(dev);
3856         u8 __iomem *base = get_hwbase(dev);
3857         u32 events;
3858
3859         dprintk(KERN_DEBUG "%s: nv_nic_irq_test\n", dev->name);
3860
3861         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3862                 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3863                 writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus);
3864         } else {
3865                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3866                 writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
3867         }
3868         pci_push(base);
3869         dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3870         if (!(events & NVREG_IRQ_TIMER))
3871                 return IRQ_RETVAL(0);
3872
3873         nv_msi_workaround(np);
3874
3875         spin_lock(&np->lock);
3876         np->intr_test = 1;
3877         spin_unlock(&np->lock);
3878
3879         dprintk(KERN_DEBUG "%s: nv_nic_irq_test completed\n", dev->name);
3880
3881         return IRQ_RETVAL(1);
3882 }
3883
3884 static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
3885 {
3886         u8 __iomem *base = get_hwbase(dev);
3887         int i;
3888         u32 msixmap = 0;
3889
3890         /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
3891          * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
3892          * the remaining 8 interrupts.
3893          */
3894         for (i = 0; i < 8; i++) {
3895                 if ((irqmask >> i) & 0x1) {
3896                         msixmap |= vector << (i << 2);
3897                 }
3898         }
3899         writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
3900
3901         msixmap = 0;
3902         for (i = 0; i < 8; i++) {
3903                 if ((irqmask >> (i + 8)) & 0x1) {
3904                         msixmap |= vector << (i << 2);
3905                 }
3906         }
3907         writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
3908 }
3909
3910 static int nv_request_irq(struct net_device *dev, int intr_test)
3911 {
3912         struct fe_priv *np = get_nvpriv(dev);
3913         u8 __iomem *base = get_hwbase(dev);
3914         int ret = 1;
3915         int i;
3916         irqreturn_t (*handler)(int foo, void *data);
3917
3918         if (intr_test) {
3919                 handler = nv_nic_irq_test;
3920         } else {
3921                 if (nv_optimized(np))
3922                         handler = nv_nic_irq_optimized;
3923                 else
3924                         handler = nv_nic_irq;
3925         }
3926
3927         if (np->msi_flags & NV_MSI_X_CAPABLE) {
3928                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
3929                         np->msi_x_entry[i].entry = i;
3930                 }
3931                 if ((ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK))) == 0) {
3932                         np->msi_flags |= NV_MSI_X_ENABLED;
3933                         if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
3934                                 /* Request irq for rx handling */
3935                                 sprintf(np->name_rx, "%s-rx", dev->name);
3936                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector,
3937                                                 &nv_nic_irq_rx, IRQF_SHARED, np->name_rx, dev) != 0) {
3938                                         printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret);
3939                                         pci_disable_msix(np->pci_dev);
3940                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3941                                         goto out_err;
3942                                 }
3943                                 /* Request irq for tx handling */
3944                                 sprintf(np->name_tx, "%s-tx", dev->name);
3945                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector,
3946                                                 &nv_nic_irq_tx, IRQF_SHARED, np->name_tx, dev) != 0) {
3947                                         printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret);
3948                                         pci_disable_msix(np->pci_dev);
3949                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3950                                         goto out_free_rx;
3951                                 }
3952                                 /* Request irq for link and timer handling */
3953                                 sprintf(np->name_other, "%s-other", dev->name);
3954                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector,
3955                                                 &nv_nic_irq_other, IRQF_SHARED, np->name_other, dev) != 0) {
3956                                         printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret);
3957                                         pci_disable_msix(np->pci_dev);
3958                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3959                                         goto out_free_tx;
3960                                 }
3961                                 /* map interrupts to their respective vector */
3962                                 writel(0, base + NvRegMSIXMap0);
3963                                 writel(0, base + NvRegMSIXMap1);
3964                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
3965                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
3966                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
3967                         } else {
3968                                 /* Request irq for all interrupts */
3969                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, handler, IRQF_SHARED, dev->name, dev) != 0) {
3970                                         printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
3971                                         pci_disable_msix(np->pci_dev);
3972                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3973                                         goto out_err;
3974                                 }
3975
3976                                 /* map interrupts to vector 0 */
3977                                 writel(0, base + NvRegMSIXMap0);
3978                                 writel(0, base + NvRegMSIXMap1);
3979                         }
3980                 }
3981         }
3982         if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
3983                 if ((ret = pci_enable_msi(np->pci_dev)) == 0) {
3984                         np->msi_flags |= NV_MSI_ENABLED;
3985                         dev->irq = np->pci_dev->irq;
3986                         if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) {
3987                                 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
3988                                 pci_disable_msi(np->pci_dev);
3989                                 np->msi_flags &= ~NV_MSI_ENABLED;
3990                                 dev->irq = np->pci_dev->irq;
3991                                 goto out_err;
3992                         }
3993
3994                         /* map interrupts to vector 0 */
3995                         writel(0, base + NvRegMSIMap0);
3996                         writel(0, base + NvRegMSIMap1);
3997                         /* enable msi vector 0 */
3998                         writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3999                 }
4000         }
4001         if (ret != 0) {
4002                 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0)
4003                         goto out_err;
4004
4005         }
4006
4007         return 0;
4008 out_free_tx:
4009         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
4010 out_free_rx:
4011         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
4012 out_err:
4013         return 1;
4014 }
4015
4016 static void nv_free_irq(struct net_device *dev)
4017 {
4018         struct fe_priv *np = get_nvpriv(dev);
4019         int i;
4020
4021         if (np->msi_flags & NV_MSI_X_ENABLED) {
4022                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
4023                         free_irq(np->msi_x_entry[i].vector, dev);
4024                 }
4025                 pci_disable_msix(np->pci_dev);
4026                 np->msi_flags &= ~NV_MSI_X_ENABLED;
4027         } else {
4028                 free_irq(np->pci_dev->irq, dev);
4029                 if (np->msi_flags & NV_MSI_ENABLED) {
4030                         pci_disable_msi(np->pci_dev);
4031                         np->msi_flags &= ~NV_MSI_ENABLED;
4032                 }
4033         }
4034 }
4035
4036 static void nv_do_nic_poll(unsigned long data)
4037 {
4038         struct net_device *dev = (struct net_device *) data;
4039         struct fe_priv *np = netdev_priv(dev);
4040         u8 __iomem *base = get_hwbase(dev);
4041         u32 mask = 0;
4042
4043         /*
4044          * First disable irq(s) and then
4045          * reenable interrupts on the nic, we have to do this before calling
4046          * nv_nic_irq because that may decide to do otherwise
4047          */
4048
4049         if (!using_multi_irqs(dev)) {
4050                 if (np->msi_flags & NV_MSI_X_ENABLED)
4051                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
4052                 else
4053                         disable_irq_lockdep(np->pci_dev->irq);
4054                 mask = np->irqmask;
4055         } else {
4056                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
4057                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
4058                         mask |= NVREG_IRQ_RX_ALL;
4059                 }
4060                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
4061                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
4062                         mask |= NVREG_IRQ_TX_ALL;
4063                 }
4064                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
4065                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
4066                         mask |= NVREG_IRQ_OTHER;
4067                 }
4068         }
4069         /* disable_irq() contains synchronize_irq, thus no irq handler can run now */
4070
4071         if (np->recover_error) {
4072                 np->recover_error = 0;
4073                 printk(KERN_INFO "forcedeth: MAC in recoverable error state\n");
4074                 if (netif_running(dev)) {
4075                         netif_tx_lock_bh(dev);
4076                         netif_addr_lock(dev);
4077                         spin_lock(&np->lock);
4078                         /* stop engines */
4079                         nv_stop_rxtx(dev);
4080                         nv_txrx_reset(dev);
4081                         /* drain rx queue */
4082                         nv_drain_rxtx(dev);
4083                         /* reinit driver view of the rx queue */
4084                         set_bufsize(dev);
4085                         if (nv_init_ring(dev)) {
4086                                 if (!np->in_shutdown)
4087                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4088                         }
4089                         /* reinit nic view of the rx queue */
4090                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4091                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4092                         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4093                                 base + NvRegRingSizes);
4094                         pci_push(base);
4095                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4096                         pci_push(base);
4097
4098                         /* restart rx engine */
4099                         nv_start_rxtx(dev);
4100                         spin_unlock(&np->lock);
4101                         netif_addr_unlock(dev);
4102                         netif_tx_unlock_bh(dev);
4103                 }
4104         }
4105
4106         writel(mask, base + NvRegIrqMask);
4107         pci_push(base);
4108
4109         if (!using_multi_irqs(dev)) {
4110                 np->nic_poll_irq = 0;
4111                 if (nv_optimized(np))
4112                         nv_nic_irq_optimized(0, dev);
4113                 else
4114                         nv_nic_irq(0, dev);
4115                 if (np->msi_flags & NV_MSI_X_ENABLED)
4116                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
4117                 else
4118                         enable_irq_lockdep(np->pci_dev->irq);
4119         } else {
4120                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
4121                         np->nic_poll_irq &= ~NVREG_IRQ_RX_ALL;
4122                         nv_nic_irq_rx(0, dev);
4123                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
4124                 }
4125                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
4126                         np->nic_poll_irq &= ~NVREG_IRQ_TX_ALL;
4127                         nv_nic_irq_tx(0, dev);
4128                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
4129                 }
4130                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
4131                         np->nic_poll_irq &= ~NVREG_IRQ_OTHER;
4132                         nv_nic_irq_other(0, dev);
4133                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
4134                 }
4135         }
4136
4137 }
4138
4139 #ifdef CONFIG_NET_POLL_CONTROLLER
4140 static void nv_poll_controller(struct net_device *dev)
4141 {
4142         nv_do_nic_poll((unsigned long) dev);
4143 }
4144 #endif
4145
4146 static void nv_do_stats_poll(unsigned long data)
4147 {
4148         struct net_device *dev = (struct net_device *) data;
4149         struct fe_priv *np = netdev_priv(dev);
4150
4151         nv_get_hw_stats(dev);
4152
4153         if (!np->in_shutdown)
4154                 mod_timer(&np->stats_poll,
4155                         round_jiffies(jiffies + STATS_INTERVAL));
4156 }
4157
4158 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4159 {
4160         struct fe_priv *np = netdev_priv(dev);
4161         strcpy(info->driver, DRV_NAME);
4162         strcpy(info->version, FORCEDETH_VERSION);
4163         strcpy(info->bus_info, pci_name(np->pci_dev));
4164 }
4165
4166 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4167 {
4168         struct fe_priv *np = netdev_priv(dev);
4169         wolinfo->supported = WAKE_MAGIC;
4170
4171         spin_lock_irq(&np->lock);
4172         if (np->wolenabled)
4173                 wolinfo->wolopts = WAKE_MAGIC;
4174         spin_unlock_irq(&np->lock);
4175 }
4176
4177 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4178 {
4179         struct fe_priv *np = netdev_priv(dev);
4180         u8 __iomem *base = get_hwbase(dev);
4181         u32 flags = 0;
4182
4183         if (wolinfo->wolopts == 0) {
4184                 np->wolenabled = 0;
4185         } else if (wolinfo->wolopts & WAKE_MAGIC) {
4186                 np->wolenabled = 1;
4187                 flags = NVREG_WAKEUPFLAGS_ENABLE;
4188         }
4189         if (netif_running(dev)) {
4190                 spin_lock_irq(&np->lock);
4191                 writel(flags, base + NvRegWakeUpFlags);
4192                 spin_unlock_irq(&np->lock);
4193         }
4194         return 0;
4195 }
4196
4197 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4198 {
4199         struct fe_priv *np = netdev_priv(dev);
4200         int adv;
4201
4202         spin_lock_irq(&np->lock);
4203         ecmd->port = PORT_MII;
4204         if (!netif_running(dev)) {
4205                 /* We do not track link speed / duplex setting if the
4206                  * interface is disabled. Force a link check */
4207                 if (nv_update_linkspeed(dev)) {
4208                         if (!netif_carrier_ok(dev))
4209                                 netif_carrier_on(dev);
4210                 } else {
4211                         if (netif_carrier_ok(dev))
4212                                 netif_carrier_off(dev);
4213                 }
4214         }
4215
4216         if (netif_carrier_ok(dev)) {
4217                 switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) {
4218                 case NVREG_LINKSPEED_10:
4219                         ecmd->speed = SPEED_10;
4220                         break;
4221                 case NVREG_LINKSPEED_100:
4222                         ecmd->speed = SPEED_100;
4223                         break;
4224                 case NVREG_LINKSPEED_1000:
4225                         ecmd->speed = SPEED_1000;
4226                         break;
4227                 }
4228                 ecmd->duplex = DUPLEX_HALF;
4229                 if (np->duplex)
4230                         ecmd->duplex = DUPLEX_FULL;
4231         } else {
4232                 ecmd->speed = -1;
4233                 ecmd->duplex = -1;
4234         }
4235
4236         ecmd->autoneg = np->autoneg;
4237
4238         ecmd->advertising = ADVERTISED_MII;
4239         if (np->autoneg) {
4240                 ecmd->advertising |= ADVERTISED_Autoneg;
4241                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4242                 if (adv & ADVERTISE_10HALF)
4243                         ecmd->advertising |= ADVERTISED_10baseT_Half;
4244                 if (adv & ADVERTISE_10FULL)
4245                         ecmd->advertising |= ADVERTISED_10baseT_Full;
4246                 if (adv & ADVERTISE_100HALF)
4247                         ecmd->advertising |= ADVERTISED_100baseT_Half;
4248                 if (adv & ADVERTISE_100FULL)
4249                         ecmd->advertising |= ADVERTISED_100baseT_Full;
4250                 if (np->gigabit == PHY_GIGABIT) {
4251                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4252                         if (adv & ADVERTISE_1000FULL)
4253                                 ecmd->advertising |= ADVERTISED_1000baseT_Full;
4254                 }
4255         }
4256         ecmd->supported = (SUPPORTED_Autoneg |
4257                 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
4258                 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
4259                 SUPPORTED_MII);
4260         if (np->gigabit == PHY_GIGABIT)
4261                 ecmd->supported |= SUPPORTED_1000baseT_Full;
4262
4263         ecmd->phy_address = np->phyaddr;
4264         ecmd->transceiver = XCVR_EXTERNAL;
4265
4266         /* ignore maxtxpkt, maxrxpkt for now */
4267         spin_unlock_irq(&np->lock);
4268         return 0;
4269 }
4270
4271 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4272 {
4273         struct fe_priv *np = netdev_priv(dev);
4274
4275         if (ecmd->port != PORT_MII)
4276                 return -EINVAL;
4277         if (ecmd->transceiver != XCVR_EXTERNAL)
4278                 return -EINVAL;
4279         if (ecmd->phy_address != np->phyaddr) {
4280                 /* TODO: support switching between multiple phys. Should be
4281                  * trivial, but not enabled due to lack of test hardware. */
4282                 return -EINVAL;
4283         }
4284         if (ecmd->autoneg == AUTONEG_ENABLE) {
4285                 u32 mask;
4286
4287                 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4288                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4289                 if (np->gigabit == PHY_GIGABIT)
4290                         mask |= ADVERTISED_1000baseT_Full;
4291
4292                 if ((ecmd->advertising & mask) == 0)
4293                         return -EINVAL;
4294
4295         } else if (ecmd->autoneg == AUTONEG_DISABLE) {
4296                 /* Note: autonegotiation disable, speed 1000 intentionally
4297                  * forbidden - noone should need that. */
4298
4299                 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
4300                         return -EINVAL;
4301                 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
4302                         return -EINVAL;
4303         } else {
4304                 return -EINVAL;
4305         }
4306
4307         netif_carrier_off(dev);
4308         if (netif_running(dev)) {
4309                 unsigned long flags;
4310
4311                 nv_disable_irq(dev);
4312                 netif_tx_lock_bh(dev);
4313                 netif_addr_lock(dev);
4314                 /* with plain spinlock lockdep complains */
4315                 spin_lock_irqsave(&np->lock, flags);
4316                 /* stop engines */
4317                 /* FIXME:
4318                  * this can take some time, and interrupts are disabled
4319                  * due to spin_lock_irqsave, but let's hope no daemon
4320                  * is going to change the settings very often...
4321                  * Worst case:
4322                  * NV_RXSTOP_DELAY1MAX + NV_TXSTOP_DELAY1MAX
4323                  * + some minor delays, which is up to a second approximately
4324                  */
4325                 nv_stop_rxtx(dev);
4326                 spin_unlock_irqrestore(&np->lock, flags);
4327                 netif_addr_unlock(dev);
4328                 netif_tx_unlock_bh(dev);
4329         }
4330
4331         if (ecmd->autoneg == AUTONEG_ENABLE) {
4332                 int adv, bmcr;
4333
4334                 np->autoneg = 1;
4335
4336                 /* advertise only what has been requested */
4337                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4338                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4339                 if (ecmd->advertising & ADVERTISED_10baseT_Half)
4340                         adv |= ADVERTISE_10HALF;
4341                 if (ecmd->advertising & ADVERTISED_10baseT_Full)
4342                         adv |= ADVERTISE_10FULL;
4343                 if (ecmd->advertising & ADVERTISED_100baseT_Half)
4344                         adv |= ADVERTISE_100HALF;
4345                 if (ecmd->advertising & ADVERTISED_100baseT_Full)
4346                         adv |= ADVERTISE_100FULL;
4347                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ)  /* for rx we set both advertisments but disable tx pause */
4348                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4349                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4350                         adv |=  ADVERTISE_PAUSE_ASYM;
4351                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4352
4353                 if (np->gigabit == PHY_GIGABIT) {
4354                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4355                         adv &= ~ADVERTISE_1000FULL;
4356                         if (ecmd->advertising & ADVERTISED_1000baseT_Full)
4357                                 adv |= ADVERTISE_1000FULL;
4358                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4359                 }
4360
4361                 if (netif_running(dev))
4362                         printk(KERN_INFO "%s: link down.\n", dev->name);
4363                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4364                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4365                         bmcr |= BMCR_ANENABLE;
4366                         /* reset the phy in order for settings to stick,
4367                          * and cause autoneg to start */
4368                         if (phy_reset(dev, bmcr)) {
4369                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4370                                 return -EINVAL;
4371                         }
4372                 } else {
4373                         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4374                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4375                 }
4376         } else {
4377                 int adv, bmcr;
4378
4379                 np->autoneg = 0;
4380
4381                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4382                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4383                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
4384                         adv |= ADVERTISE_10HALF;
4385                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
4386                         adv |= ADVERTISE_10FULL;
4387                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
4388                         adv |= ADVERTISE_100HALF;
4389                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
4390                         adv |= ADVERTISE_100FULL;
4391                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4392                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisments but disable tx pause */
4393                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4394                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4395                 }
4396                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
4397                         adv |=  ADVERTISE_PAUSE_ASYM;
4398                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4399                 }
4400                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4401                 np->fixed_mode = adv;
4402
4403                 if (np->gigabit == PHY_GIGABIT) {
4404                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4405                         adv &= ~ADVERTISE_1000FULL;
4406                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4407                 }
4408
4409                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4410                 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
4411                 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
4412                         bmcr |= BMCR_FULLDPLX;
4413                 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
4414                         bmcr |= BMCR_SPEED100;
4415                 if (np->phy_oui == PHY_OUI_MARVELL) {
4416                         /* reset the phy in order for forced mode settings to stick */
4417                         if (phy_reset(dev, bmcr)) {
4418                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4419                                 return -EINVAL;
4420                         }
4421                 } else {
4422                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4423                         if (netif_running(dev)) {
4424                                 /* Wait a bit and then reconfigure the nic. */
4425                                 udelay(10);
4426                                 nv_linkchange(dev);
4427                         }
4428                 }
4429         }
4430
4431         if (netif_running(dev)) {
4432                 nv_start_rxtx(dev);
4433                 nv_enable_irq(dev);
4434         }
4435
4436         return 0;
4437 }
4438
4439 #define FORCEDETH_REGS_VER      1
4440
4441 static int nv_get_regs_len(struct net_device *dev)
4442 {
4443         struct fe_priv *np = netdev_priv(dev);
4444         return np->register_size;
4445 }
4446
4447 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
4448 {
4449         struct fe_priv *np = netdev_priv(dev);
4450         u8 __iomem *base = get_hwbase(dev);
4451         u32 *rbuf = buf;
4452         int i;
4453
4454         regs->version = FORCEDETH_REGS_VER;
4455         spin_lock_irq(&np->lock);
4456         for (i = 0;i <= np->register_size/sizeof(u32); i++)
4457                 rbuf[i] = readl(base + i*sizeof(u32));
4458         spin_unlock_irq(&np->lock);
4459 }
4460
4461 static int nv_nway_reset(struct net_device *dev)
4462 {
4463         struct fe_priv *np = netdev_priv(dev);
4464         int ret;
4465
4466         if (np->autoneg) {
4467                 int bmcr;
4468
4469                 netif_carrier_off(dev);
4470                 if (netif_running(dev)) {
4471                         nv_disable_irq(dev);
4472                         netif_tx_lock_bh(dev);
4473                         netif_addr_lock(dev);
4474                         spin_lock(&np->lock);
4475                         /* stop engines */
4476                         nv_stop_rxtx(dev);
4477                         spin_unlock(&np->lock);
4478                         netif_addr_unlock(dev);
4479                         netif_tx_unlock_bh(dev);
4480                         printk(KERN_INFO "%s: link down.\n", dev->name);
4481                 }
4482
4483                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4484                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4485                         bmcr |= BMCR_ANENABLE;
4486                         /* reset the phy in order for settings to stick*/
4487                         if (phy_reset(dev, bmcr)) {
4488                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4489                                 return -EINVAL;
4490                         }
4491                 } else {
4492                         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4493                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4494                 }
4495
4496                 if (netif_running(dev)) {
4497                         nv_start_rxtx(dev);
4498                         nv_enable_irq(dev);
4499                 }
4500                 ret = 0;
4501         } else {
4502                 ret = -EINVAL;
4503         }
4504
4505         return ret;
4506 }
4507
4508 static int nv_set_tso(struct net_device *dev, u32 value)
4509 {
4510         struct fe_priv *np = netdev_priv(dev);
4511
4512         if ((np->driver_data & DEV_HAS_CHECKSUM))
4513                 return ethtool_op_set_tso(dev, value);
4514         else
4515                 return -EOPNOTSUPP;
4516 }
4517
4518 static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4519 {
4520         struct fe_priv *np = netdev_priv(dev);
4521
4522         ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4523         ring->rx_mini_max_pending = 0;
4524         ring->rx_jumbo_max_pending = 0;
4525         ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4526
4527         ring->rx_pending = np->rx_ring_size;
4528         ring->rx_mini_pending = 0;
4529         ring->rx_jumbo_pending = 0;
4530         ring->tx_pending = np->tx_ring_size;
4531 }
4532
4533 static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4534 {
4535         struct fe_priv *np = netdev_priv(dev);
4536         u8 __iomem *base = get_hwbase(dev);
4537         u8 *rxtx_ring, *rx_skbuff, *tx_skbuff;
4538         dma_addr_t ring_addr;
4539
4540         if (ring->rx_pending < RX_RING_MIN ||
4541             ring->tx_pending < TX_RING_MIN ||
4542             ring->rx_mini_pending != 0 ||
4543             ring->rx_jumbo_pending != 0 ||
4544             (np->desc_ver == DESC_VER_1 &&
4545              (ring->rx_pending > RING_MAX_DESC_VER_1 ||
4546               ring->tx_pending > RING_MAX_DESC_VER_1)) ||
4547             (np->desc_ver != DESC_VER_1 &&
4548              (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
4549               ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
4550                 return -EINVAL;
4551         }
4552
4553         /* allocate new rings */
4554         if (!nv_optimized(np)) {
4555                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4556                                             sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4557                                             &ring_addr);
4558         } else {
4559                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4560                                             sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4561                                             &ring_addr);
4562         }
4563         rx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->rx_pending, GFP_KERNEL);
4564         tx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->tx_pending, GFP_KERNEL);
4565         if (!rxtx_ring || !rx_skbuff || !tx_skbuff) {
4566                 /* fall back to old rings */
4567                 if (!nv_optimized(np)) {
4568                         if (rxtx_ring)
4569                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4570                                                     rxtx_ring, ring_addr);
4571                 } else {
4572                         if (rxtx_ring)
4573                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4574                                                     rxtx_ring, ring_addr);
4575                 }
4576                 if (rx_skbuff)
4577                         kfree(rx_skbuff);
4578                 if (tx_skbuff)
4579                         kfree(tx_skbuff);
4580                 goto exit;
4581         }
4582
4583         if (netif_running(dev)) {
4584                 nv_disable_irq(dev);
4585                 netif_tx_lock_bh(dev);
4586                 netif_addr_lock(dev);
4587                 spin_lock(&np->lock);
4588                 /* stop engines */
4589                 nv_stop_rxtx(dev);
4590                 nv_txrx_reset(dev);
4591                 /* drain queues */
4592                 nv_drain_rxtx(dev);
4593                 /* delete queues */
4594                 free_rings(dev);
4595         }
4596
4597         /* set new values */
4598         np->rx_ring_size = ring->rx_pending;
4599         np->tx_ring_size = ring->tx_pending;
4600
4601         if (!nv_optimized(np)) {
4602                 np->rx_ring.orig = (struct ring_desc*)rxtx_ring;
4603                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4604         } else {
4605                 np->rx_ring.ex = (struct ring_desc_ex*)rxtx_ring;
4606                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4607         }
4608         np->rx_skb = (struct nv_skb_map*)rx_skbuff;
4609         np->tx_skb = (struct nv_skb_map*)tx_skbuff;
4610         np->ring_addr = ring_addr;
4611
4612         memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
4613         memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
4614
4615         if (netif_running(dev)) {
4616                 /* reinit driver view of the queues */
4617                 set_bufsize(dev);
4618                 if (nv_init_ring(dev)) {
4619                         if (!np->in_shutdown)
4620                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4621                 }
4622
4623                 /* reinit nic view of the queues */
4624                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4625                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4626                 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4627                         base + NvRegRingSizes);
4628                 pci_push(base);
4629                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4630                 pci_push(base);
4631
4632                 /* restart engines */
4633                 nv_start_rxtx(dev);
4634                 spin_unlock(&np->lock);
4635                 netif_addr_unlock(dev);
4636                 netif_tx_unlock_bh(dev);
4637                 nv_enable_irq(dev);
4638         }
4639         return 0;
4640 exit:
4641         return -ENOMEM;
4642 }
4643
4644 static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4645 {
4646         struct fe_priv *np = netdev_priv(dev);
4647
4648         pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
4649         pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
4650         pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
4651 }
4652
4653 static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4654 {
4655         struct fe_priv *np = netdev_priv(dev);
4656         int adv, bmcr;
4657
4658         if ((!np->autoneg && np->duplex == 0) ||
4659             (np->autoneg && !pause->autoneg && np->duplex == 0)) {
4660                 printk(KERN_INFO "%s: can not set pause settings when forced link is in half duplex.\n",
4661                        dev->name);
4662                 return -EINVAL;
4663         }
4664         if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
4665                 printk(KERN_INFO "%s: hardware does not support tx pause frames.\n", dev->name);
4666                 return -EINVAL;
4667         }
4668
4669         netif_carrier_off(dev);
4670         if (netif_running(dev)) {
4671                 nv_disable_irq(dev);
4672                 netif_tx_lock_bh(dev);
4673                 netif_addr_lock(dev);
4674                 spin_lock(&np->lock);
4675                 /* stop engines */
4676                 nv_stop_rxtx(dev);
4677                 spin_unlock(&np->lock);
4678                 netif_addr_unlock(dev);
4679                 netif_tx_unlock_bh(dev);
4680         }
4681
4682         np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
4683         if (pause->rx_pause)
4684                 np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
4685         if (pause->tx_pause)
4686                 np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
4687
4688         if (np->autoneg && pause->autoneg) {
4689                 np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
4690
4691                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4692                 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4693                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
4694                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4695                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4696                         adv |=  ADVERTISE_PAUSE_ASYM;
4697                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4698
4699                 if (netif_running(dev))
4700                         printk(KERN_INFO "%s: link down.\n", dev->name);
4701                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4702                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4703                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4704         } else {
4705                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4706                 if (pause->rx_pause)
4707                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4708                 if (pause->tx_pause)
4709                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4710
4711                 if (!netif_running(dev))
4712                         nv_update_linkspeed(dev);
4713                 else
4714                         nv_update_pause(dev, np->pause_flags);
4715         }
4716
4717         if (netif_running(dev)) {
4718                 nv_start_rxtx(dev);
4719                 nv_enable_irq(dev);
4720         }
4721         return 0;
4722 }
4723
4724 static u32 nv_get_rx_csum(struct net_device *dev)
4725 {
4726         struct fe_priv *np = netdev_priv(dev);
4727         return (np->rx_csum) != 0;
4728 }
4729
4730 static int nv_set_rx_csum(struct net_device *dev, u32 data)
4731 {
4732         struct fe_priv *np = netdev_priv(dev);
4733         u8 __iomem *base = get_hwbase(dev);
4734         int retcode = 0;
4735
4736         if (np->driver_data & DEV_HAS_CHECKSUM) {
4737                 if (data) {
4738                         np->rx_csum = 1;
4739                         np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
4740                 } else {
4741                         np->rx_csum = 0;
4742                         /* vlan is dependent on rx checksum offload */
4743                         if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE))
4744                                 np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
4745                 }
4746                 if (netif_running(dev)) {
4747                         spin_lock_irq(&np->lock);
4748                         writel(np->txrxctl_bits, base + NvRegTxRxControl);
4749                         spin_unlock_irq(&np->lock);
4750                 }
4751         } else {
4752                 return -EINVAL;
4753         }
4754
4755         return retcode;
4756 }
4757
4758 static int nv_set_tx_csum(struct net_device *dev, u32 data)
4759 {
4760         struct fe_priv *np = netdev_priv(dev);
4761
4762         if (np->driver_data & DEV_HAS_CHECKSUM)
4763                 return ethtool_op_set_tx_hw_csum(dev, data);
4764         else
4765                 return -EOPNOTSUPP;
4766 }
4767
4768 static int nv_set_sg(struct net_device *dev, u32 data)
4769 {
4770         struct fe_priv *np = netdev_priv(dev);
4771
4772         if (np->driver_data & DEV_HAS_CHECKSUM)
4773                 return ethtool_op_set_sg(dev, data);
4774         else
4775                 return -EOPNOTSUPP;
4776 }
4777
4778 static int nv_get_sset_count(struct net_device *dev, int sset)
4779 {
4780         struct fe_priv *np = netdev_priv(dev);
4781
4782         switch (sset) {
4783         case ETH_SS_TEST:
4784                 if (np->driver_data & DEV_HAS_TEST_EXTENDED)
4785                         return NV_TEST_COUNT_EXTENDED;
4786                 else
4787                         return NV_TEST_COUNT_BASE;
4788         case ETH_SS_STATS:
4789                 if (np->driver_data & DEV_HAS_STATISTICS_V1)
4790                         return NV_DEV_STATISTICS_V1_COUNT;
4791                 else if (np->driver_data & DEV_HAS_STATISTICS_V2)
4792                         return NV_DEV_STATISTICS_V2_COUNT;
4793                 else if (np->driver_data & DEV_HAS_STATISTICS_V3)
4794                         return NV_DEV_STATISTICS_V3_COUNT;
4795                 else
4796                         return 0;
4797         default:
4798                 return -EOPNOTSUPP;
4799         }
4800 }
4801
4802 static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer)
4803 {
4804         struct fe_priv *np = netdev_priv(dev);
4805
4806         /* update stats */
4807         nv_do_stats_poll((unsigned long)dev);
4808
4809         memcpy(buffer, &np->estats, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(u64));
4810 }
4811
4812 static int nv_link_test(struct net_device *dev)
4813 {
4814         struct fe_priv *np = netdev_priv(dev);
4815         int mii_status;
4816
4817         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4818         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4819
4820         /* check phy link status */
4821         if (!(mii_status & BMSR_LSTATUS))
4822                 return 0;
4823         else
4824                 return 1;
4825 }
4826
4827 static int nv_register_test(struct net_device *dev)
4828 {
4829         u8 __iomem *base = get_hwbase(dev);
4830         int i = 0;
4831         u32 orig_read, new_read;
4832
4833         do {
4834                 orig_read = readl(base + nv_registers_test[i].reg);
4835
4836                 /* xor with mask to toggle bits */
4837                 orig_read ^= nv_registers_test[i].mask;
4838
4839                 writel(orig_read, base + nv_registers_test[i].reg);
4840
4841                 new_read = readl(base + nv_registers_test[i].reg);
4842
4843                 if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
4844                         return 0;
4845
4846                 /* restore original value */
4847                 orig_read ^= nv_registers_test[i].mask;
4848                 writel(orig_read, base + nv_registers_test[i].reg);
4849
4850         } while (nv_registers_test[++i].reg != 0);
4851
4852         return 1;
4853 }
4854
4855 static int nv_interrupt_test(struct net_device *dev)
4856 {
4857         struct fe_priv *np = netdev_priv(dev);
4858         u8 __iomem *base = get_hwbase(dev);
4859         int ret = 1;
4860         int testcnt;
4861         u32 save_msi_flags, save_poll_interval = 0;
4862
4863         if (netif_running(dev)) {
4864                 /* free current irq */
4865                 nv_free_irq(dev);
4866                 save_poll_interval = readl(base+NvRegPollingInterval);
4867         }
4868
4869         /* flag to test interrupt handler */
4870         np->intr_test = 0;
4871
4872         /* setup test irq */
4873         save_msi_flags = np->msi_flags;
4874         np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
4875         np->msi_flags |= 0x001; /* setup 1 vector */
4876         if (nv_request_irq(dev, 1))
4877                 return 0;
4878
4879         /* setup timer interrupt */
4880         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4881         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4882
4883         nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4884
4885         /* wait for at least one interrupt */
4886         msleep(100);
4887
4888         spin_lock_irq(&np->lock);
4889
4890         /* flag should be set within ISR */
4891         testcnt = np->intr_test;
4892         if (!testcnt)
4893                 ret = 2;
4894
4895         nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4896         if (!(np->msi_flags & NV_MSI_X_ENABLED))
4897                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4898         else
4899                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4900
4901         spin_unlock_irq(&np->lock);
4902
4903         nv_free_irq(dev);
4904
4905         np->msi_flags = save_msi_flags;
4906
4907         if (netif_running(dev)) {
4908                 writel(save_poll_interval, base + NvRegPollingInterval);
4909                 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4910                 /* restore original irq */
4911                 if (nv_request_irq(dev, 0))
4912                         return 0;
4913         }
4914
4915         return ret;
4916 }
4917
4918 static int nv_loopback_test(struct net_device *dev)
4919 {
4920         struct fe_priv *np = netdev_priv(dev);
4921         u8 __iomem *base = get_hwbase(dev);
4922         struct sk_buff *tx_skb, *rx_skb;
4923         dma_addr_t test_dma_addr;
4924         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
4925         u32 flags;
4926         int len, i, pkt_len;
4927         u8 *pkt_data;
4928         u32 filter_flags = 0;
4929         u32 misc1_flags = 0;
4930         int ret = 1;
4931
4932         if (netif_running(dev)) {
4933                 nv_disable_irq(dev);
4934                 filter_flags = readl(base + NvRegPacketFilterFlags);
4935                 misc1_flags = readl(base + NvRegMisc1);
4936         } else {
4937                 nv_txrx_reset(dev);
4938         }
4939
4940         /* reinit driver view of the rx queue */
4941         set_bufsize(dev);
4942         nv_init_ring(dev);
4943
4944         /* setup hardware for loopback */
4945         writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
4946         writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
4947
4948         /* reinit nic view of the rx queue */
4949         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4950         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4951         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4952                 base + NvRegRingSizes);
4953         pci_push(base);
4954
4955         /* restart rx engine */
4956         nv_start_rxtx(dev);
4957
4958         /* setup packet for tx */
4959         pkt_len = ETH_DATA_LEN;
4960         tx_skb = dev_alloc_skb(pkt_len);
4961         if (!tx_skb) {
4962                 printk(KERN_ERR "dev_alloc_skb() failed during loopback test"
4963                          " of %s\n", dev->name);
4964                 ret = 0;
4965                 goto out;
4966         }
4967         test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
4968                                        skb_tailroom(tx_skb),
4969                                        PCI_DMA_FROMDEVICE);
4970         pkt_data = skb_put(tx_skb, pkt_len);
4971         for (i = 0; i < pkt_len; i++)
4972                 pkt_data[i] = (u8)(i & 0xff);
4973
4974         if (!nv_optimized(np)) {
4975                 np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
4976                 np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
4977         } else {
4978                 np->tx_ring.ex[0].bufhigh = cpu_to_le32(dma_high(test_dma_addr));
4979                 np->tx_ring.ex[0].buflow = cpu_to_le32(dma_low(test_dma_addr));
4980                 np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
4981         }
4982         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4983         pci_push(get_hwbase(dev));
4984
4985         msleep(500);
4986
4987         /* check for rx of the packet */
4988         if (!nv_optimized(np)) {
4989                 flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
4990                 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
4991
4992         } else {
4993                 flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
4994                 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
4995         }
4996
4997         if (flags & NV_RX_AVAIL) {
4998                 ret = 0;
4999         } else if (np->desc_ver == DESC_VER_1) {
5000                 if (flags & NV_RX_ERROR)
5001                         ret = 0;
5002         } else {
5003                 if (flags & NV_RX2_ERROR) {
5004                         ret = 0;
5005                 }
5006         }
5007
5008         if (ret) {
5009                 if (len != pkt_len) {
5010                         ret = 0;
5011                         dprintk(KERN_DEBUG "%s: loopback len mismatch %d vs %d\n",
5012                                 dev->name, len, pkt_len);
5013                 } else {
5014                         rx_skb = np->rx_skb[0].skb;
5015                         for (i = 0; i < pkt_len; i++) {
5016                                 if (rx_skb->data[i] != (u8)(i & 0xff)) {
5017                                         ret = 0;
5018                                         dprintk(KERN_DEBUG "%s: loopback pattern check failed on byte %d\n",
5019                                                 dev->name, i);
5020                                         break;
5021                                 }
5022                         }
5023                 }
5024         } else {
5025                 dprintk(KERN_DEBUG "%s: loopback - did not receive test packet\n", dev->name);
5026         }
5027
5028         pci_unmap_page(np->pci_dev, test_dma_addr,
5029                        (skb_end_pointer(tx_skb) - tx_skb->data),
5030                        PCI_DMA_TODEVICE);
5031         dev_kfree_skb_any(tx_skb);
5032  out:
5033         /* stop engines */
5034         nv_stop_rxtx(dev);
5035         nv_txrx_reset(dev);
5036         /* drain rx queue */
5037         nv_drain_rxtx(dev);
5038
5039         if (netif_running(dev)) {
5040                 writel(misc1_flags, base + NvRegMisc1);
5041                 writel(filter_flags, base + NvRegPacketFilterFlags);
5042                 nv_enable_irq(dev);
5043         }
5044
5045         return ret;
5046 }
5047
5048 static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
5049 {
5050         struct fe_priv *np = netdev_priv(dev);
5051         u8 __iomem *base = get_hwbase(dev);
5052         int result;
5053         memset(buffer, 0, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(u64));
5054
5055         if (!nv_link_test(dev)) {
5056                 test->flags |= ETH_TEST_FL_FAILED;
5057                 buffer[0] = 1;
5058         }
5059
5060         if (test->flags & ETH_TEST_FL_OFFLINE) {
5061                 if (netif_running(dev)) {
5062                         netif_stop_queue(dev);
5063 #ifdef CONFIG_FORCEDETH_NAPI
5064                         napi_disable(&np->napi);
5065 #endif
5066                         netif_tx_lock_bh(dev);
5067                         netif_addr_lock(dev);
5068                         spin_lock_irq(&np->lock);
5069                         nv_disable_hw_interrupts(dev, np->irqmask);
5070                         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
5071                                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5072                         } else {
5073                                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
5074                         }
5075                         /* stop engines */
5076                         nv_stop_rxtx(dev);
5077                         nv_txrx_reset(dev);
5078                         /* drain rx queue */
5079                         nv_drain_rxtx(dev);
5080                         spin_unlock_irq(&np->lock);
5081                         netif_addr_unlock(dev);
5082                         netif_tx_unlock_bh(dev);
5083                 }
5084
5085                 if (!nv_register_test(dev)) {
5086                         test->flags |= ETH_TEST_FL_FAILED;
5087                         buffer[1] = 1;
5088                 }
5089
5090                 result = nv_interrupt_test(dev);
5091                 if (result != 1) {
5092                         test->flags |= ETH_TEST_FL_FAILED;
5093                         buffer[2] = 1;
5094                 }
5095                 if (result == 0) {
5096                         /* bail out */
5097                         return;
5098                 }
5099
5100                 if (!nv_loopback_test(dev)) {
5101                         test->flags |= ETH_TEST_FL_FAILED;
5102                         buffer[3] = 1;
5103                 }
5104
5105                 if (netif_running(dev)) {
5106                         /* reinit driver view of the rx queue */
5107                         set_bufsize(dev);
5108                         if (nv_init_ring(dev)) {
5109                                 if (!np->in_shutdown)
5110                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5111                         }
5112                         /* reinit nic view of the rx queue */
5113                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5114                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5115                         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5116                                 base + NvRegRingSizes);
5117                         pci_push(base);
5118                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5119                         pci_push(base);
5120                         /* restart rx engine */
5121                         nv_start_rxtx(dev);
5122                         netif_start_queue(dev);
5123 #ifdef CONFIG_FORCEDETH_NAPI
5124                         napi_enable(&np->napi);
5125 #endif
5126                         nv_enable_hw_interrupts(dev, np->irqmask);
5127                 }
5128         }
5129 }
5130
5131 static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
5132 {
5133         switch (stringset) {
5134         case ETH_SS_STATS:
5135                 memcpy(buffer, &nv_estats_str, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(struct nv_ethtool_str));
5136                 break;
5137         case ETH_SS_TEST:
5138                 memcpy(buffer, &nv_etests_str, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(struct nv_ethtool_str));
5139                 break;
5140         }
5141 }
5142
5143 static const struct ethtool_ops ops = {
5144         .get_drvinfo = nv_get_drvinfo,
5145         .get_link = ethtool_op_get_link,
5146         .get_wol = nv_get_wol,
5147         .set_wol = nv_set_wol,
5148         .get_settings = nv_get_settings,
5149         .set_settings = nv_set_settings,
5150         .get_regs_len = nv_get_regs_len,
5151         .get_regs = nv_get_regs,
5152         .nway_reset = nv_nway_reset,
5153         .set_tso = nv_set_tso,
5154         .get_ringparam = nv_get_ringparam,
5155         .set_ringparam = nv_set_ringparam,
5156         .get_pauseparam = nv_get_pauseparam,
5157         .set_pauseparam = nv_set_pauseparam,
5158         .get_rx_csum = nv_get_rx_csum,
5159         .set_rx_csum = nv_set_rx_csum,
5160         .set_tx_csum = nv_set_tx_csum,
5161         .set_sg = nv_set_sg,
5162         .get_strings = nv_get_strings,
5163         .get_ethtool_stats = nv_get_ethtool_stats,
5164         .get_sset_count = nv_get_sset_count,
5165         .self_test = nv_self_test,
5166 };
5167
5168 static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
5169 {
5170         struct fe_priv *np = get_nvpriv(dev);
5171
5172         spin_lock_irq(&np->lock);
5173
5174         /* save vlan group */
5175         np->vlangrp = grp;
5176
5177         if (grp) {
5178                 /* enable vlan on MAC */
5179                 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS;
5180         } else {
5181                 /* disable vlan on MAC */
5182                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
5183                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
5184         }
5185
5186         writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5187
5188         spin_unlock_irq(&np->lock);
5189 }
5190
5191 /* The mgmt unit and driver use a semaphore to access the phy during init */
5192 static int nv_mgmt_acquire_sema(struct net_device *dev)
5193 {
5194         struct fe_priv *np = netdev_priv(dev);
5195         u8 __iomem *base = get_hwbase(dev);
5196         int i;
5197         u32 tx_ctrl, mgmt_sema;
5198
5199         for (i = 0; i < 10; i++) {
5200                 mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK;
5201                 if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE)
5202                         break;
5203                 msleep(500);
5204         }
5205
5206         if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE)
5207                 return 0;
5208
5209         for (i = 0; i < 2; i++) {
5210                 tx_ctrl = readl(base + NvRegTransmitterControl);
5211                 tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ;
5212                 writel(tx_ctrl, base + NvRegTransmitterControl);
5213
5214                 /* verify that semaphore was acquired */
5215                 tx_ctrl = readl(base + NvRegTransmitterControl);
5216                 if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) &&
5217                     ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE)) {
5218                         np->mgmt_sema = 1;
5219                         return 1;
5220                 }
5221                 else
5222                         udelay(50);
5223         }
5224
5225         return 0;
5226 }
5227
5228 static void nv_mgmt_release_sema(struct net_device *dev)
5229 {
5230         struct fe_priv *np = netdev_priv(dev);
5231         u8 __iomem *base = get_hwbase(dev);
5232         u32 tx_ctrl;
5233
5234         if (np->driver_data & DEV_HAS_MGMT_UNIT) {
5235                 if (np->mgmt_sema) {
5236                         tx_ctrl = readl(base + NvRegTransmitterControl);
5237                         tx_ctrl &= ~NVREG_XMITCTL_HOST_SEMA_ACQ;
5238                         writel(tx_ctrl, base + NvRegTransmitterControl);
5239                 }
5240         }
5241 }
5242
5243
5244 static int nv_mgmt_get_version(struct net_device *dev)
5245 {
5246         struct fe_priv *np = netdev_priv(dev);
5247         u8 __iomem *base = get_hwbase(dev);
5248         u32 data_ready = readl(base + NvRegTransmitterControl);
5249         u32 data_ready2 = 0;
5250         unsigned long start;
5251         int ready = 0;
5252
5253         writel(NVREG_MGMTUNITGETVERSION, base + NvRegMgmtUnitGetVersion);
5254         writel(data_ready ^ NVREG_XMITCTL_DATA_START, base + NvRegTransmitterControl);
5255         start = jiffies;
5256         while (time_before(jiffies, start + 5*HZ)) {
5257                 data_ready2 = readl(base + NvRegTransmitterControl);
5258                 if ((data_ready & NVREG_XMITCTL_DATA_READY) != (data_ready2 & NVREG_XMITCTL_DATA_READY)) {
5259                         ready = 1;
5260                         break;
5261                 }
5262                 schedule_timeout_uninterruptible(1);
5263         }
5264
5265         if (!ready || (data_ready2 & NVREG_XMITCTL_DATA_ERROR))
5266                 return 0;
5267
5268         np->mgmt_version = readl(base + NvRegMgmtUnitVersion) & NVREG_MGMTUNITVERSION;
5269
5270         return 1;
5271 }
5272
5273 static int nv_open(struct net_device *dev)
5274 {
5275         struct fe_priv *np = netdev_priv(dev);
5276         u8 __iomem *base = get_hwbase(dev);
5277         int ret = 1;
5278         int oom, i;
5279         u32 low;
5280
5281         dprintk(KERN_DEBUG "nv_open: begin\n");
5282
5283         /* power up phy */
5284         mii_rw(dev, np->phyaddr, MII_BMCR,
5285                mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN);
5286
5287         /* erase previous misconfiguration */
5288         if (np->driver_data & DEV_HAS_POWER_CNTRL)
5289                 nv_mac_reset(dev);
5290         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5291         writel(0, base + NvRegMulticastAddrB);
5292         writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5293         writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5294         writel(0, base + NvRegPacketFilterFlags);
5295
5296         writel(0, base + NvRegTransmitterControl);
5297         writel(0, base + NvRegReceiverControl);
5298
5299         writel(0, base + NvRegAdapterControl);
5300
5301         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
5302                 writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
5303
5304         /* initialize descriptor rings */
5305         set_bufsize(dev);
5306         oom = nv_init_ring(dev);
5307
5308         writel(0, base + NvRegLinkSpeed);
5309         writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5310         nv_txrx_reset(dev);
5311         writel(0, base + NvRegUnknownSetupReg6);
5312
5313         np->in_shutdown = 0;
5314
5315         /* give hw rings */
5316         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5317         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5318                 base + NvRegRingSizes);
5319
5320         writel(np->linkspeed, base + NvRegLinkSpeed);
5321         if (np->desc_ver == DESC_VER_1)
5322                 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
5323         else
5324                 writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
5325         writel(np->txrxctl_bits, base + NvRegTxRxControl);
5326         writel(np->vlanctl_bits, base + NvRegVlanControl);
5327         pci_push(base);
5328         writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
5329         reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
5330                         NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
5331                         KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
5332
5333         writel(0, base + NvRegMIIMask);
5334         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5335         writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5336
5337         writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
5338         writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
5339         writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
5340         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5341
5342         writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
5343
5344         get_random_bytes(&low, sizeof(low));
5345         low &= NVREG_SLOTTIME_MASK;
5346         if (np->desc_ver == DESC_VER_1) {
5347                 writel(low|NVREG_SLOTTIME_DEFAULT, base + NvRegSlotTime);
5348         } else {
5349                 if (!(np->driver_data & DEV_HAS_GEAR_MODE)) {
5350                         /* setup legacy backoff */
5351                         writel(NVREG_SLOTTIME_LEGBF_ENABLED|NVREG_SLOTTIME_10_100_FULL|low, base + NvRegSlotTime);
5352                 } else {
5353                         writel(NVREG_SLOTTIME_10_100_FULL, base + NvRegSlotTime);
5354                         nv_gear_backoff_reseed(dev);
5355                 }
5356         }
5357         writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
5358         writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
5359         if (poll_interval == -1) {
5360                 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
5361                         writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
5362                 else
5363                         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
5364         }
5365         else
5366                 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
5367         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
5368         writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
5369                         base + NvRegAdapterControl);
5370         writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
5371         writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);
5372         if (np->wolenabled)
5373                 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
5374
5375         i = readl(base + NvRegPowerState);
5376         if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
5377                 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
5378
5379         pci_push(base);
5380         udelay(10);
5381         writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
5382
5383         nv_disable_hw_interrupts(dev, np->irqmask);
5384         pci_push(base);
5385         writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5386         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5387         pci_push(base);
5388
5389         if (nv_request_irq(dev, 0)) {
5390                 goto out_drain;
5391         }
5392
5393         /* ask for interrupts */
5394         nv_enable_hw_interrupts(dev, np->irqmask);
5395
5396         spin_lock_irq(&np->lock);
5397         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5398         writel(0, base + NvRegMulticastAddrB);
5399         writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5400         writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5401         writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5402         /* One manual link speed update: Interrupts are enabled, future link
5403          * speed changes cause interrupts and are handled by nv_link_irq().
5404          */
5405         {
5406                 u32 miistat;
5407                 miistat = readl(base + NvRegMIIStatus);
5408                 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5409                 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
5410         }
5411         /* set linkspeed to invalid value, thus force nv_update_linkspeed
5412          * to init hw */
5413         np->linkspeed = 0;
5414         ret = nv_update_linkspeed(dev);
5415         nv_start_rxtx(dev);
5416         netif_start_queue(dev);
5417 #ifdef CONFIG_FORCEDETH_NAPI
5418         napi_enable(&np->napi);
5419 #endif
5420
5421         if (ret) {
5422                 netif_carrier_on(dev);
5423         } else {
5424                 printk(KERN_INFO "%s: no link during initialization.\n", dev->name);
5425                 netif_carrier_off(dev);
5426         }
5427         if (oom)
5428                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5429
5430         /* start statistics timer */
5431         if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
5432                 mod_timer(&np->stats_poll,
5433                         round_jiffies(jiffies + STATS_INTERVAL));
5434
5435         spin_unlock_irq(&np->lock);
5436
5437         return 0;
5438 out_drain:
5439         nv_drain_rxtx(dev);
5440         return ret;
5441 }
5442
5443 static int nv_close(struct net_device *dev)
5444 {
5445         struct fe_priv *np = netdev_priv(dev);
5446         u8 __iomem *base;
5447
5448         spin_lock_irq(&np->lock);
5449         np->in_shutdown = 1;
5450         spin_unlock_irq(&np->lock);
5451 #ifdef CONFIG_FORCEDETH_NAPI
5452         napi_disable(&np->napi);
5453 #endif
5454         synchronize_irq(np->pci_dev->irq);
5455
5456         del_timer_sync(&np->oom_kick);
5457         del_timer_sync(&np->nic_poll);
5458         del_timer_sync(&np->stats_poll);
5459
5460         netif_stop_queue(dev);
5461         spin_lock_irq(&np->lock);
5462         nv_stop_rxtx(dev);
5463         nv_txrx_reset(dev);
5464
5465         /* disable interrupts on the nic or we will lock up */
5466         base = get_hwbase(dev);
5467         nv_disable_hw_interrupts(dev, np->irqmask);
5468         pci_push(base);
5469         dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
5470
5471         spin_unlock_irq(&np->lock);
5472
5473         nv_free_irq(dev);
5474
5475         nv_drain_rxtx(dev);
5476
5477         if (np->wolenabled) {
5478                 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5479                 nv_start_rx(dev);
5480         } else {
5481                 /* power down phy */
5482                 mii_rw(dev, np->phyaddr, MII_BMCR,
5483                        mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ)|BMCR_PDOWN);
5484         }
5485
5486         /* FIXME: power down nic */
5487
5488         return 0;
5489 }
5490
5491 static const struct net_device_ops nv_netdev_ops = {
5492         .ndo_open               = nv_open,
5493         .ndo_stop               = nv_close,
5494         .ndo_get_stats          = nv_get_stats,
5495         .ndo_start_xmit         = nv_start_xmit,
5496         .ndo_tx_timeout         = nv_tx_timeout,
5497         .ndo_change_mtu         = nv_change_mtu,
5498         .ndo_validate_addr      = eth_validate_addr,
5499         .ndo_set_mac_address    = nv_set_mac_address,
5500         .ndo_set_multicast_list = nv_set_multicast,
5501         .ndo_vlan_rx_register   = nv_vlan_rx_register,
5502 #ifdef CONFIG_NET_POLL_CONTROLLER
5503         .ndo_poll_controller    = nv_poll_controller,
5504 #endif
5505 };
5506
5507 static const struct net_device_ops nv_netdev_ops_optimized = {
5508         .ndo_open               = nv_open,
5509         .ndo_stop               = nv_close,
5510         .ndo_get_stats          = nv_get_stats,
5511         .ndo_start_xmit         = nv_start_xmit_optimized,
5512         .ndo_tx_timeout         = nv_tx_timeout,
5513         .ndo_change_mtu         = nv_change_mtu,
5514         .ndo_validate_addr      = eth_validate_addr,
5515         .ndo_set_mac_address    = nv_set_mac_address,
5516         .ndo_set_multicast_list = nv_set_multicast,
5517         .ndo_vlan_rx_register   = nv_vlan_rx_register,
5518 #ifdef CONFIG_NET_POLL_CONTROLLER
5519         .ndo_poll_controller    = nv_poll_controller,
5520 #endif
5521 };
5522
5523 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
5524 {
5525         struct net_device *dev;
5526         struct fe_priv *np;
5527         unsigned long addr;
5528         u8 __iomem *base;
5529         int err, i;
5530         u32 powerstate, txreg;
5531         u32 phystate_orig = 0, phystate;
5532         int phyinitialized = 0;
5533         static int printed_version;
5534
5535         if (!printed_version++)
5536                 printk(KERN_INFO "%s: Reverse Engineered nForce ethernet"
5537                        " driver. Version %s.\n", DRV_NAME, FORCEDETH_VERSION);
5538
5539         dev = alloc_etherdev(sizeof(struct fe_priv));
5540         err = -ENOMEM;
5541         if (!dev)
5542                 goto out;
5543
5544         np = netdev_priv(dev);
5545         np->dev = dev;
5546         np->pci_dev = pci_dev;
5547         spin_lock_init(&np->lock);
5548         SET_NETDEV_DEV(dev, &pci_dev->dev);
5549
5550         init_timer(&np->oom_kick);
5551         np->oom_kick.data = (unsigned long) dev;
5552         np->oom_kick.function = &nv_do_rx_refill;       /* timer handler */
5553         init_timer(&np->nic_poll);
5554         np->nic_poll.data = (unsigned long) dev;
5555         np->nic_poll.function = &nv_do_nic_poll;        /* timer handler */
5556         init_timer(&np->stats_poll);
5557         np->stats_poll.data = (unsigned long) dev;
5558         np->stats_poll.function = &nv_do_stats_poll;    /* timer handler */
5559
5560         err = pci_enable_device(pci_dev);
5561         if (err)
5562                 goto out_free;
5563
5564         pci_set_master(pci_dev);
5565
5566         err = pci_request_regions(pci_dev, DRV_NAME);
5567         if (err < 0)
5568                 goto out_disable;
5569
5570         if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
5571                 np->register_size = NV_PCI_REGSZ_VER3;
5572         else if (id->driver_data & DEV_HAS_STATISTICS_V1)
5573                 np->register_size = NV_PCI_REGSZ_VER2;
5574         else
5575                 np->register_size = NV_PCI_REGSZ_VER1;
5576
5577         err = -EINVAL;
5578         addr = 0;
5579         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
5580                 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
5581                                 pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
5582                                 pci_resource_len(pci_dev, i),
5583                                 pci_resource_flags(pci_dev, i));
5584                 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
5585                                 pci_resource_len(pci_dev, i) >= np->register_size) {
5586                         addr = pci_resource_start(pci_dev, i);
5587                         break;
5588                 }
5589         }
5590         if (i == DEVICE_COUNT_RESOURCE) {
5591                 dev_printk(KERN_INFO, &pci_dev->dev,
5592                            "Couldn't find register window\n");
5593                 goto out_relreg;
5594         }
5595
5596         /* copy of driver data */
5597         np->driver_data = id->driver_data;
5598         /* copy of device id */
5599         np->device_id = id->device;
5600
5601         /* handle different descriptor versions */
5602         if (id->driver_data & DEV_HAS_HIGH_DMA) {
5603                 /* packet format 3: supports 40-bit addressing */
5604                 np->desc_ver = DESC_VER_3;
5605                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
5606                 if (dma_64bit) {
5607                         if (pci_set_dma_mask(pci_dev, DMA_39BIT_MASK))
5608                                 dev_printk(KERN_INFO, &pci_dev->dev,
5609                                         "64-bit DMA failed, using 32-bit addressing\n");
5610                         else
5611                                 dev->features |= NETIF_F_HIGHDMA;
5612                         if (pci_set_consistent_dma_mask(pci_dev, DMA_39BIT_MASK)) {
5613                                 dev_printk(KERN_INFO, &pci_dev->dev,
5614                                         "64-bit DMA (consistent) failed, using 32-bit ring buffers\n");
5615                         }
5616                 }
5617         } else if (id->driver_data & DEV_HAS_LARGEDESC) {
5618                 /* packet format 2: supports jumbo frames */
5619                 np->desc_ver = DESC_VER_2;
5620                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
5621         } else {
5622                 /* original packet format */
5623                 np->desc_ver = DESC_VER_1;
5624                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
5625         }
5626
5627         np->pkt_limit = NV_PKTLIMIT_1;
5628         if (id->driver_data & DEV_HAS_LARGEDESC)
5629                 np->pkt_limit = NV_PKTLIMIT_2;
5630
5631         if (id->driver_data & DEV_HAS_CHECKSUM) {
5632                 np->rx_csum = 1;
5633                 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
5634                 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
5635                 dev->features |= NETIF_F_TSO;
5636         }
5637
5638         np->vlanctl_bits = 0;
5639         if (id->driver_data & DEV_HAS_VLAN) {
5640                 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
5641                 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX;
5642         }
5643
5644         np->msi_flags = 0;
5645         if ((id->driver_data & DEV_HAS_MSI) && msi) {
5646                 np->msi_flags |= NV_MSI_CAPABLE;
5647         }
5648         if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
5649                 np->msi_flags |= NV_MSI_X_CAPABLE;
5650         }
5651
5652         np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
5653         if ((id->driver_data & DEV_HAS_PAUSEFRAME_TX_V1) ||
5654             (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V2) ||
5655             (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V3)) {
5656                 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
5657         }
5658
5659
5660         err = -ENOMEM;
5661         np->base = ioremap(addr, np->register_size);
5662         if (!np->base)
5663                 goto out_relreg;
5664         dev->base_addr = (unsigned long)np->base;
5665
5666         dev->irq = pci_dev->irq;
5667
5668         np->rx_ring_size = RX_RING_DEFAULT;
5669         np->tx_ring_size = TX_RING_DEFAULT;
5670
5671         if (!nv_optimized(np)) {
5672                 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
5673                                         sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
5674                                         &np->ring_addr);
5675                 if (!np->rx_ring.orig)
5676                         goto out_unmap;
5677                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
5678         } else {
5679                 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
5680                                         sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
5681                                         &np->ring_addr);
5682                 if (!np->rx_ring.ex)
5683                         goto out_unmap;
5684                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
5685         }
5686         np->rx_skb = kcalloc(np->rx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5687         np->tx_skb = kcalloc(np->tx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5688         if (!np->rx_skb || !np->tx_skb)
5689                 goto out_freering;
5690
5691         if (!nv_optimized(np))
5692                 dev->netdev_ops = &nv_netdev_ops;
5693         else
5694                 dev->netdev_ops = &nv_netdev_ops_optimized;
5695
5696 #ifdef CONFIG_FORCEDETH_NAPI
5697         netif_napi_add(dev, &np->napi, nv_napi_poll, RX_WORK_PER_LOOP);
5698 #endif
5699         SET_ETHTOOL_OPS(dev, &ops);
5700         dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
5701
5702         pci_set_drvdata(pci_dev, dev);
5703
5704         /* read the mac address */
5705         base = get_hwbase(dev);
5706         np->orig_mac[0] = readl(base + NvRegMacAddrA);
5707         np->orig_mac[1] = readl(base + NvRegMacAddrB);
5708
5709         /* check the workaround bit for correct mac address order */
5710         txreg = readl(base + NvRegTransmitPoll);
5711         if (id->driver_data & DEV_HAS_CORRECT_MACADDR) {
5712                 /* mac address is already in correct order */
5713                 dev->dev_addr[0] = (np->orig_mac[0] >>  0) & 0xff;
5714                 dev->dev_addr[1] = (np->orig_mac[0] >>  8) & 0xff;
5715                 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5716                 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5717                 dev->dev_addr[4] = (np->orig_mac[1] >>  0) & 0xff;
5718                 dev->dev_addr[5] = (np->orig_mac[1] >>  8) & 0xff;
5719         } else if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) {
5720                 /* mac address is already in correct order */
5721                 dev->dev_addr[0] = (np->orig_mac[0] >>  0) & 0xff;
5722                 dev->dev_addr[1] = (np->orig_mac[0] >>  8) & 0xff;
5723                 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5724                 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5725                 dev->dev_addr[4] = (np->orig_mac[1] >>  0) & 0xff;
5726                 dev->dev_addr[5] = (np->orig_mac[1] >>  8) & 0xff;
5727                 /*
5728                  * Set orig mac address back to the reversed version.
5729                  * This flag will be cleared during low power transition.
5730                  * Therefore, we should always put back the reversed address.
5731                  */
5732                 np->orig_mac[0] = (dev->dev_addr[5] << 0) + (dev->dev_addr[4] << 8) +
5733                         (dev->dev_addr[3] << 16) + (dev->dev_addr[2] << 24);
5734                 np->orig_mac[1] = (dev->dev_addr[1] << 0) + (dev->dev_addr[0] << 8);
5735         } else {
5736                 /* need to reverse mac address to correct order */
5737                 dev->dev_addr[0] = (np->orig_mac[1] >>  8) & 0xff;
5738                 dev->dev_addr[1] = (np->orig_mac[1] >>  0) & 0xff;
5739                 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
5740                 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
5741                 dev->dev_addr[4] = (np->orig_mac[0] >>  8) & 0xff;
5742                 dev->dev_addr[5] = (np->orig_mac[0] >>  0) & 0xff;
5743                 writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5744                 printk(KERN_DEBUG "nv_probe: set workaround bit for reversed mac addr\n");
5745         }
5746         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
5747
5748         if (!is_valid_ether_addr(dev->perm_addr)) {
5749                 /*
5750                  * Bad mac address. At least one bios sets the mac address
5751                  * to 01:23:45:67:89:ab
5752                  */
5753                 dev_printk(KERN_ERR, &pci_dev->dev,
5754                         "Invalid Mac address detected: %pM\n",
5755                         dev->dev_addr);
5756                 dev_printk(KERN_ERR, &pci_dev->dev,
5757                         "Please complain to your hardware vendor. Switching to a random MAC.\n");
5758                 dev->dev_addr[0] = 0x00;
5759                 dev->dev_addr[1] = 0x00;
5760                 dev->dev_addr[2] = 0x6c;
5761                 get_random_bytes(&dev->dev_addr[3], 3);
5762         }
5763
5764         dprintk(KERN_DEBUG "%s: MAC Address %pM\n",
5765                 pci_name(pci_dev), dev->dev_addr);
5766
5767         /* set mac address */
5768         nv_copy_mac_to_hw(dev);
5769
5770         /* Workaround current PCI init glitch:  wakeup bits aren't
5771          * being set from PCI PM capability.
5772          */
5773         device_init_wakeup(&pci_dev->dev, 1);
5774
5775         /* disable WOL */
5776         writel(0, base + NvRegWakeUpFlags);
5777         np->wolenabled = 0;
5778
5779         if (id->driver_data & DEV_HAS_POWER_CNTRL) {
5780
5781                 /* take phy and nic out of low power mode */
5782                 powerstate = readl(base + NvRegPowerState2);
5783                 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
5784                 if ((id->device == PCI_DEVICE_ID_NVIDIA_NVENET_12 ||
5785                      id->device == PCI_DEVICE_ID_NVIDIA_NVENET_13) &&
5786                     pci_dev->revision >= 0xA3)
5787                         powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
5788                 writel(powerstate, base + NvRegPowerState2);
5789         }
5790
5791         if (np->desc_ver == DESC_VER_1) {
5792                 np->tx_flags = NV_TX_VALID;
5793         } else {
5794                 np->tx_flags = NV_TX2_VALID;
5795         }
5796         if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT) {
5797                 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5798                 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5799                         np->msi_flags |= 0x0003;
5800         } else {
5801                 np->irqmask = NVREG_IRQMASK_CPU;
5802                 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5803                         np->msi_flags |= 0x0001;
5804         }
5805
5806         if (id->driver_data & DEV_NEED_TIMERIRQ)
5807                 np->irqmask |= NVREG_IRQ_TIMER;
5808         if (id->driver_data & DEV_NEED_LINKTIMER) {
5809                 dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev));
5810                 np->need_linktimer = 1;
5811                 np->link_timeout = jiffies + LINK_TIMEOUT;
5812         } else {
5813                 dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev));
5814                 np->need_linktimer = 0;
5815         }
5816
5817         /* Limit the number of tx's outstanding for hw bug */
5818         if (id->driver_data & DEV_NEED_TX_LIMIT) {
5819                 np->tx_limit = 1;
5820                 if ((id->device == PCI_DEVICE_ID_NVIDIA_NVENET_32 ||
5821                      id->device == PCI_DEVICE_ID_NVIDIA_NVENET_33 ||
5822                      id->device == PCI_DEVICE_ID_NVIDIA_NVENET_34 ||
5823                      id->device == PCI_DEVICE_ID_NVIDIA_NVENET_35 ||
5824                      id->device == PCI_DEVICE_ID_NVIDIA_NVENET_36 ||
5825                      id->device == PCI_DEVICE_ID_NVIDIA_NVENET_37 ||
5826                      id->device == PCI_DEVICE_ID_NVIDIA_NVENET_38 ||
5827                      id->device == PCI_DEVICE_ID_NVIDIA_NVENET_39) &&
5828                     pci_dev->revision >= 0xA2)
5829                         np->tx_limit = 0;
5830         }
5831
5832         /* clear phy state and temporarily halt phy interrupts */
5833         writel(0, base + NvRegMIIMask);
5834         phystate = readl(base + NvRegAdapterControl);
5835         if (phystate & NVREG_ADAPTCTL_RUNNING) {
5836                 phystate_orig = 1;
5837                 phystate &= ~NVREG_ADAPTCTL_RUNNING;
5838                 writel(phystate, base + NvRegAdapterControl);
5839         }
5840         writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5841
5842         if (id->driver_data & DEV_HAS_MGMT_UNIT) {
5843                 /* management unit running on the mac? */
5844                 if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST) &&
5845                     (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) &&
5846                     nv_mgmt_acquire_sema(dev) &&
5847                     nv_mgmt_get_version(dev)) {
5848                         np->mac_in_use = 1;
5849                         if (np->mgmt_version > 0) {
5850                                 np->mac_in_use = readl(base + NvRegMgmtUnitControl) & NVREG_MGMTUNITCONTROL_INUSE;
5851                         }
5852                         dprintk(KERN_INFO "%s: mgmt unit is running. mac in use %x.\n",
5853                                 pci_name(pci_dev), np->mac_in_use);
5854                         /* management unit setup the phy already? */
5855                         if (np->mac_in_use &&
5856                             ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) ==
5857                              NVREG_XMITCTL_SYNC_PHY_INIT)) {
5858                                 /* phy is inited by mgmt unit */
5859                                 phyinitialized = 1;
5860                                 dprintk(KERN_INFO "%s: Phy already initialized by mgmt unit.\n",
5861                                         pci_name(pci_dev));
5862                         } else {
5863                                 /* we need to init the phy */
5864                         }
5865                 }
5866         }
5867
5868         /* find a suitable phy */
5869         for (i = 1; i <= 32; i++) {
5870                 int id1, id2;
5871                 int phyaddr = i & 0x1F;
5872
5873                 spin_lock_irq(&np->lock);
5874                 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
5875                 spin_unlock_irq(&np->lock);
5876                 if (id1 < 0 || id1 == 0xffff)
5877                         continue;
5878                 spin_lock_irq(&np->lock);
5879                 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
5880                 spin_unlock_irq(&np->lock);
5881                 if (id2 < 0 || id2 == 0xffff)
5882                         continue;
5883
5884                 np->phy_model = id2 & PHYID2_MODEL_MASK;
5885                 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
5886                 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
5887                 dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
5888                         pci_name(pci_dev), id1, id2, phyaddr);
5889                 np->phyaddr = phyaddr;
5890                 np->phy_oui = id1 | id2;
5891
5892                 /* Realtek hardcoded phy id1 to all zero's on certain phys */
5893                 if (np->phy_oui == PHY_OUI_REALTEK2)
5894                         np->phy_oui = PHY_OUI_REALTEK;
5895                 /* Setup phy revision for Realtek */
5896                 if (np->phy_oui == PHY_OUI_REALTEK && np->phy_model == PHY_MODEL_REALTEK_8211)
5897                         np->phy_rev = mii_rw(dev, phyaddr, MII_RESV1, MII_READ) & PHY_REV_MASK;
5898
5899                 break;
5900         }
5901         if (i == 33) {
5902                 dev_printk(KERN_INFO, &pci_dev->dev,
5903                         "open: Could not find a valid PHY.\n");
5904                 goto out_error;
5905         }
5906
5907         if (!phyinitialized) {
5908                 /* reset it */
5909                 phy_init(dev);
5910         } else {
5911                 /* see if it is a gigabit phy */
5912                 u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
5913                 if (mii_status & PHY_GIGABIT) {
5914                         np->gigabit = PHY_GIGABIT;
5915                 }
5916         }
5917
5918         /* set default link speed settings */
5919         np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
5920         np->duplex = 0;
5921         np->autoneg = 1;
5922
5923         err = register_netdev(dev);
5924         if (err) {
5925                 dev_printk(KERN_INFO, &pci_dev->dev,
5926                            "unable to register netdev: %d\n", err);
5927                 goto out_error;
5928         }
5929
5930         dev_printk(KERN_INFO, &pci_dev->dev, "ifname %s, PHY OUI 0x%x @ %d, "
5931                    "addr %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n",
5932                    dev->name,
5933                    np->phy_oui,
5934                    np->phyaddr,
5935                    dev->dev_addr[0],
5936                    dev->dev_addr[1],
5937                    dev->dev_addr[2],
5938                    dev->dev_addr[3],
5939                    dev->dev_addr[4],
5940                    dev->dev_addr[5]);
5941
5942         dev_printk(KERN_INFO, &pci_dev->dev, "%s%s%s%s%s%s%s%s%s%sdesc-v%u\n",
5943                    dev->features & NETIF_F_HIGHDMA ? "highdma " : "",
5944                    dev->features & (NETIF_F_IP_CSUM | NETIF_F_SG) ?
5945                         "csum " : "",
5946                    dev->features & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX) ?
5947                         "vlan " : "",
5948                    id->driver_data & DEV_HAS_POWER_CNTRL ? "pwrctl " : "",
5949                    id->driver_data & DEV_HAS_MGMT_UNIT ? "mgmt " : "",
5950                    id->driver_data & DEV_NEED_TIMERIRQ ? "timirq " : "",
5951                    np->gigabit == PHY_GIGABIT ? "gbit " : "",
5952                    np->need_linktimer ? "lnktim " : "",
5953                    np->msi_flags & NV_MSI_CAPABLE ? "msi " : "",
5954                    np->msi_flags & NV_MSI_X_CAPABLE ? "msi-x " : "",
5955                    np->desc_ver);
5956
5957         return 0;
5958
5959 out_error:
5960         if (phystate_orig)
5961                 writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
5962         pci_set_drvdata(pci_dev, NULL);
5963 out_freering:
5964         free_rings(dev);
5965 out_unmap:
5966         iounmap(get_hwbase(dev));
5967 out_relreg:
5968         pci_release_regions(pci_dev);
5969 out_disable:
5970         pci_disable_device(pci_dev);
5971 out_free:
5972         free_netdev(dev);
5973 out:
5974         return err;
5975 }
5976
5977 static void nv_restore_phy(struct net_device *dev)
5978 {
5979         struct fe_priv *np = netdev_priv(dev);
5980         u16 phy_reserved, mii_control;
5981
5982         if (np->phy_oui == PHY_OUI_REALTEK &&
5983             np->phy_model == PHY_MODEL_REALTEK_8201 &&
5984             phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
5985                 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3);
5986                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
5987                 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
5988                 phy_reserved |= PHY_REALTEK_INIT8;
5989                 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved);
5990                 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1);
5991
5992                 /* restart auto negotiation */
5993                 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
5994                 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
5995                 mii_rw(dev, np->phyaddr, MII_BMCR, mii_control);
5996         }
5997 }
5998
5999 static void nv_restore_mac_addr(struct pci_dev *pci_dev)
6000 {
6001         struct net_device *dev = pci_get_drvdata(pci_dev);
6002         struct fe_priv *np = netdev_priv(dev);
6003         u8 __iomem *base = get_hwbase(dev);
6004
6005         /* special op: write back the misordered MAC address - otherwise
6006          * the next nv_probe would see a wrong address.
6007          */
6008         writel(np->orig_mac[0], base + NvRegMacAddrA);
6009         writel(np->orig_mac[1], base + NvRegMacAddrB);
6010         writel(readl(base + NvRegTransmitPoll) & ~NVREG_TRANSMITPOLL_MAC_ADDR_REV,
6011                base + NvRegTransmitPoll);
6012 }
6013
6014 static void __devexit nv_remove(struct pci_dev *pci_dev)
6015 {
6016         struct net_device *dev = pci_get_drvdata(pci_dev);
6017
6018         unregister_netdev(dev);
6019
6020         nv_restore_mac_addr(pci_dev);
6021
6022         /* restore any phy related changes */
6023         nv_restore_phy(dev);
6024
6025         nv_mgmt_release_sema(dev);
6026
6027         /* free all structures */
6028         free_rings(dev);
6029         iounmap(get_hwbase(dev));
6030         pci_release_regions(pci_dev);
6031         pci_disable_device(pci_dev);
6032         free_netdev(dev);
6033         pci_set_drvdata(pci_dev, NULL);
6034 }
6035
6036 #ifdef CONFIG_PM
6037 static int nv_suspend(struct pci_dev *pdev, pm_message_t state)
6038 {
6039         struct net_device *dev = pci_get_drvdata(pdev);
6040         struct fe_priv *np = netdev_priv(dev);
6041         u8 __iomem *base = get_hwbase(dev);
6042         int i;
6043
6044         if (netif_running(dev)) {
6045                 // Gross.
6046                 nv_close(dev);
6047         }
6048         netif_device_detach(dev);
6049
6050         /* save non-pci configuration space */
6051         for (i = 0;i <= np->register_size/sizeof(u32); i++)
6052                 np->saved_config_space[i] = readl(base + i*sizeof(u32));
6053
6054         pci_save_state(pdev);
6055         pci_enable_wake(pdev, pci_choose_state(pdev, state), np->wolenabled);
6056         pci_disable_device(pdev);
6057         pci_set_power_state(pdev, pci_choose_state(pdev, state));
6058         return 0;
6059 }
6060
6061 static int nv_resume(struct pci_dev *pdev)
6062 {
6063         struct net_device *dev = pci_get_drvdata(pdev);
6064         struct fe_priv *np = netdev_priv(dev);
6065         u8 __iomem *base = get_hwbase(dev);
6066         int i, rc = 0;
6067
6068         pci_set_power_state(pdev, PCI_D0);
6069         pci_restore_state(pdev);
6070         /* ack any pending wake events, disable PME */
6071         pci_enable_wake(pdev, PCI_D0, 0);
6072
6073         /* restore non-pci configuration space */
6074         for (i = 0;i <= np->register_size/sizeof(u32); i++)
6075                 writel(np->saved_config_space[i], base+i*sizeof(u32));
6076
6077         netif_device_attach(dev);
6078         if (netif_running(dev)) {
6079                 rc = nv_open(dev);
6080                 nv_set_multicast(dev);
6081         }
6082         return rc;
6083 }
6084
6085 static void nv_shutdown(struct pci_dev *pdev)
6086 {
6087         struct net_device *dev = pci_get_drvdata(pdev);
6088         struct fe_priv *np = netdev_priv(dev);
6089
6090         if (netif_running(dev))
6091                 nv_close(dev);
6092
6093         nv_restore_mac_addr(pdev);
6094
6095         pci_disable_device(pdev);
6096         if (system_state == SYSTEM_POWER_OFF) {
6097                 if (pci_enable_wake(pdev, PCI_D3cold, np->wolenabled))
6098                         pci_enable_wake(pdev, PCI_D3hot, np->wolenabled);
6099                 pci_set_power_state(pdev, PCI_D3hot);
6100         }
6101 }
6102 #else
6103 #define nv_suspend NULL
6104 #define nv_shutdown NULL
6105 #define nv_resume NULL
6106 #endif /* CONFIG_PM */
6107
6108 static struct pci_device_id pci_tbl[] = {
6109         {       /* nForce Ethernet Controller */
6110                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_1),
6111                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
6112         },
6113         {       /* nForce2 Ethernet Controller */
6114                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_2),
6115                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
6116         },
6117         {       /* nForce3 Ethernet Controller */
6118                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_3),
6119                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
6120         },
6121         {       /* nForce3 Ethernet Controller */
6122                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_4),
6123                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6124         },
6125         {       /* nForce3 Ethernet Controller */
6126                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_5),
6127                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6128         },
6129         {       /* nForce3 Ethernet Controller */
6130                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_6),
6131                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6132         },
6133         {       /* nForce3 Ethernet Controller */
6134                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_7),
6135                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6136         },
6137         {       /* CK804 Ethernet Controller */
6138                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_8),
6139                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6140         },
6141         {       /* CK804 Ethernet Controller */
6142                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_9),
6143                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6144         },
6145         {       /* MCP04 Ethernet Controller */
6146                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_10),
6147                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6148         },
6149         {       /* MCP04 Ethernet Controller */
6150                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_11),
6151                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6152         },
6153         {       /* MCP51 Ethernet Controller */
6154                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_12),
6155                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1,
6156         },
6157         {       /* MCP51 Ethernet Controller */
6158                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_13),
6159                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1,
6160         },
6161         {       /* MCP55 Ethernet Controller */
6162                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14),
6163                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT,
6164         },
6165         {       /* MCP55 Ethernet Controller */
6166                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15),
6167                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT,
6168         },
6169         {       /* MCP61 Ethernet Controller */
6170                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_16),
6171                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
6172         },
6173         {       /* MCP61 Ethernet Controller */
6174                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_17),
6175                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
6176         },
6177         {       /* MCP61 Ethernet Controller */
6178                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_18),
6179                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
6180         },
6181         {       /* MCP61 Ethernet Controller */
6182                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_19),
6183                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
6184         },
6185         {       /* MCP65 Ethernet Controller */
6186                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_20),
6187                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6188         },
6189         {       /* MCP65 Ethernet Controller */
6190                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_21),
6191                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6192         },
6193         {       /* MCP65 Ethernet Controller */
6194                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_22),
6195                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6196         },
6197         {       /* MCP65 Ethernet Controller */
6198                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_23),
6199                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6200         },
6201         {       /* MCP67 Ethernet Controller */
6202                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_24),
6203                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE,
6204         },
6205         {       /* MCP67 Ethernet Controller */
6206                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_25),
6207                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE,
6208         },
6209         {       /* MCP67 Ethernet Controller */
6210                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_26),
6211                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE,
6212         },
6213         {       /* MCP67 Ethernet Controller */
6214                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_27),
6215                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE,
6216         },
6217         {       /* MCP73 Ethernet Controller */
6218                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_28),
6219                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE,
6220         },
6221         {       /* MCP73 Ethernet Controller */
6222                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_29),
6223                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE,
6224         },
6225         {       /* MCP73 Ethernet Controller */
6226                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_30),
6227                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE,
6228         },
6229         {       /* MCP73 Ethernet Controller */
6230                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_31),
6231                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE,
6232         },
6233         {       /* MCP77 Ethernet Controller */
6234                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_32),
6235                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6236         },
6237         {       /* MCP77 Ethernet Controller */
6238                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_33),
6239                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6240         },
6241         {       /* MCP77 Ethernet Controller */
6242                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_34),
6243                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6244         },
6245         {       /* MCP77 Ethernet Controller */
6246                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_35),
6247                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6248         },
6249         {       /* MCP79 Ethernet Controller */
6250                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_36),
6251                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6252         },
6253         {       /* MCP79 Ethernet Controller */
6254                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_37),
6255                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6256         },
6257         {       /* MCP79 Ethernet Controller */
6258                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_38),
6259                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6260         },
6261         {       /* MCP79 Ethernet Controller */
6262                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_39),
6263                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6264         },
6265         {0,},
6266 };
6267
6268 static struct pci_driver driver = {
6269         .name           = DRV_NAME,
6270         .id_table       = pci_tbl,
6271         .probe          = nv_probe,
6272         .remove         = __devexit_p(nv_remove),
6273         .suspend        = nv_suspend,
6274         .resume         = nv_resume,
6275         .shutdown       = nv_shutdown,
6276 };
6277
6278 static int __init init_nic(void)
6279 {
6280         return pci_register_driver(&driver);
6281 }
6282
6283 static void __exit exit_nic(void)
6284 {
6285         pci_unregister_driver(&driver);
6286 }
6287
6288 module_param(max_interrupt_work, int, 0);
6289 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
6290 module_param(optimization_mode, int, 0);
6291 MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer.");
6292 module_param(poll_interval, int, 0);
6293 MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
6294 module_param(msi, int, 0);
6295 MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
6296 module_param(msix, int, 0);
6297 MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
6298 module_param(dma_64bit, int, 0);
6299 MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
6300 module_param(phy_cross, int, 0);
6301 MODULE_PARM_DESC(phy_cross, "Phy crossover detection for Realtek 8201 phy is enabled by setting to 1 and disabled by setting to 0.");
6302
6303 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
6304 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
6305 MODULE_LICENSE("GPL");
6306
6307 MODULE_DEVICE_TABLE(pci, pci_tbl);
6308
6309 module_init(init_nic);
6310 module_exit(exit_nic);