2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 Abstract: Data structures and registers for the rt2500usb module.
24 Supported chipsets: RT2570.
37 #define RF2525E 0x0005
43 #define RT2570_VERSION_B 2
44 #define RT2570_VERSION_C 3
45 #define RT2570_VERSION_D 4
49 * Defaul offset is required for RSSI <-> dBm conversion.
51 #define DEFAULT_RSSI_OFFSET 120
54 * Register layout information.
56 #define CSR_REG_BASE 0x0400
57 #define CSR_REG_SIZE 0x0100
58 #define EEPROM_BASE 0x0000
59 #define EEPROM_SIZE 0x006a
60 #define BBP_SIZE 0x0060
61 #define RF_SIZE 0x0014
64 * Number of TX queues.
66 #define NUM_TX_QUEUES 2
69 * Control/Status Registers(CSR).
70 * Some values are set in TU, whereas 1 TU == 1024 us.
74 * MAC_CSR0: ASIC revision number.
76 #define MAC_CSR0 0x0400
79 * MAC_CSR1: System control.
80 * SOFT_RESET: Software reset, 1: reset, 0: normal.
81 * BBP_RESET: Hardware reset, 1: reset, 0, release.
82 * HOST_READY: Host ready after initialization.
84 #define MAC_CSR1 0x0402
85 #define MAC_CSR1_SOFT_RESET FIELD16(0x00000001)
86 #define MAC_CSR1_BBP_RESET FIELD16(0x00000002)
87 #define MAC_CSR1_HOST_READY FIELD16(0x00000004)
90 * MAC_CSR2: STA MAC register 0.
92 #define MAC_CSR2 0x0404
93 #define MAC_CSR2_BYTE0 FIELD16(0x00ff)
94 #define MAC_CSR2_BYTE1 FIELD16(0xff00)
97 * MAC_CSR3: STA MAC register 1.
99 #define MAC_CSR3 0x0406
100 #define MAC_CSR3_BYTE2 FIELD16(0x00ff)
101 #define MAC_CSR3_BYTE3 FIELD16(0xff00)
104 * MAC_CSR4: STA MAC register 2.
106 #define MAC_CSR4 0X0408
107 #define MAC_CSR4_BYTE4 FIELD16(0x00ff)
108 #define MAC_CSR4_BYTE5 FIELD16(0xff00)
111 * MAC_CSR5: BSSID register 0.
113 #define MAC_CSR5 0x040a
114 #define MAC_CSR5_BYTE0 FIELD16(0x00ff)
115 #define MAC_CSR5_BYTE1 FIELD16(0xff00)
118 * MAC_CSR6: BSSID register 1.
120 #define MAC_CSR6 0x040c
121 #define MAC_CSR6_BYTE2 FIELD16(0x00ff)
122 #define MAC_CSR6_BYTE3 FIELD16(0xff00)
125 * MAC_CSR7: BSSID register 2.
127 #define MAC_CSR7 0x040e
128 #define MAC_CSR7_BYTE4 FIELD16(0x00ff)
129 #define MAC_CSR7_BYTE5 FIELD16(0xff00)
132 * MAC_CSR8: Max frame length.
134 #define MAC_CSR8 0x0410
135 #define MAC_CSR8_MAX_FRAME_UNIT FIELD16(0x0fff)
138 * Misc MAC_CSR registers.
139 * MAC_CSR9: Timer control.
140 * MAC_CSR10: Slot time.
143 * MAC_CSR13: Power mode0.
144 * MAC_CSR14: Power mode1.
145 * MAC_CSR15: Power saving transition0
146 * MAC_CSR16: Power saving transition1
148 #define MAC_CSR9 0x0412
149 #define MAC_CSR10 0x0414
150 #define MAC_CSR11 0x0416
151 #define MAC_CSR12 0x0418
152 #define MAC_CSR13 0x041a
153 #define MAC_CSR14 0x041c
154 #define MAC_CSR15 0x041e
155 #define MAC_CSR16 0x0420
158 * MAC_CSR17: Manual power control / status register.
159 * Allowed state: 0 deep_sleep, 1: sleep, 2: standby, 3: awake.
160 * SET_STATE: Set state. Write 1 to trigger, self cleared.
161 * BBP_DESIRE_STATE: BBP desired state.
162 * RF_DESIRE_STATE: RF desired state.
163 * BBP_CURRENT_STATE: BBP current state.
164 * RF_CURRENT_STATE: RF current state.
165 * PUT_TO_SLEEP: Put to sleep. Write 1 to trigger, self cleared.
167 #define MAC_CSR17 0x0422
168 #define MAC_CSR17_SET_STATE FIELD16(0x0001)
169 #define MAC_CSR17_BBP_DESIRE_STATE FIELD16(0x0006)
170 #define MAC_CSR17_RF_DESIRE_STATE FIELD16(0x0018)
171 #define MAC_CSR17_BBP_CURR_STATE FIELD16(0x0060)
172 #define MAC_CSR17_RF_CURR_STATE FIELD16(0x0180)
173 #define MAC_CSR17_PUT_TO_SLEEP FIELD16(0x0200)
176 * MAC_CSR18: Wakeup timer register.
177 * DELAY_AFTER_BEACON: Delay after Tbcn expired in units of 1/16 TU.
178 * BEACONS_BEFORE_WAKEUP: Number of beacon before wakeup.
179 * AUTO_WAKE: Enable auto wakeup / sleep mechanism.
181 #define MAC_CSR18 0x0424
182 #define MAC_CSR18_DELAY_AFTER_BEACON FIELD16(0x00ff)
183 #define MAC_CSR18_BEACONS_BEFORE_WAKEUP FIELD16(0x7f00)
184 #define MAC_CSR18_AUTO_WAKE FIELD16(0x8000)
187 * MAC_CSR19: GPIO control register.
189 #define MAC_CSR19 0x0426
192 * MAC_CSR20: LED control register.
193 * ACTIVITY: 0: idle, 1: active.
194 * LINK: 0: linkoff, 1: linkup.
195 * ACTIVITY_POLARITY: 0: active low, 1: active high.
197 #define MAC_CSR20 0x0428
198 #define MAC_CSR20_ACTIVITY FIELD16(0x0001)
199 #define MAC_CSR20_LINK FIELD16(0x0002)
200 #define MAC_CSR20_ACTIVITY_POLARITY FIELD16(0x0004)
203 * MAC_CSR21: LED control register.
204 * ON_PERIOD: On period, default 70ms.
205 * OFF_PERIOD: Off period, default 30ms.
207 #define MAC_CSR21 0x042a
208 #define MAC_CSR21_ON_PERIOD FIELD16(0x00ff)
209 #define MAC_CSR21_OFF_PERIOD FIELD16(0xff00)
212 * Collision window control register.
214 #define MAC_CSR22 0x042c
217 * Transmit related CSRs.
218 * Some values are set in TU, whereas 1 TU == 1024 us.
222 * TXRX_CSR0: Security control register.
224 #define TXRX_CSR0 0x0440
225 #define TXRX_CSR0_ALGORITHM FIELD16(0x0007)
226 #define TXRX_CSR0_IV_OFFSET FIELD16(0x01f8)
227 #define TXRX_CSR0_KEY_ID FIELD16(0x1e00)
230 * TXRX_CSR1: TX configuration.
231 * ACK_TIMEOUT: ACK Timeout in unit of 1-us.
232 * TSF_OFFSET: TSF offset in MAC header.
233 * AUTO_SEQUENCE: Let ASIC control frame sequence number.
235 #define TXRX_CSR1 0x0442
236 #define TXRX_CSR1_ACK_TIMEOUT FIELD16(0x00ff)
237 #define TXRX_CSR1_TSF_OFFSET FIELD16(0x7f00)
238 #define TXRX_CSR1_AUTO_SEQUENCE FIELD16(0x8000)
241 * TXRX_CSR2: RX control.
242 * DISABLE_RX: Disable rx engine.
243 * DROP_CRC: Drop crc error.
244 * DROP_PHYSICAL: Drop physical error.
245 * DROP_CONTROL: Drop control frame.
246 * DROP_NOT_TO_ME: Drop not to me unicast frame.
247 * DROP_TODS: Drop frame tods bit is true.
248 * DROP_VERSION_ERROR: Drop version error frame.
249 * DROP_MCAST: Drop multicast frames.
250 * DROP_BCAST: Drop broadcast frames.
252 #define TXRX_CSR2 0x0444
253 #define TXRX_CSR2_DISABLE_RX FIELD16(0x0001)
254 #define TXRX_CSR2_DROP_CRC FIELD16(0x0002)
255 #define TXRX_CSR2_DROP_PHYSICAL FIELD16(0x0004)
256 #define TXRX_CSR2_DROP_CONTROL FIELD16(0x0008)
257 #define TXRX_CSR2_DROP_NOT_TO_ME FIELD16(0x0010)
258 #define TXRX_CSR2_DROP_TODS FIELD16(0x0020)
259 #define TXRX_CSR2_DROP_VERSION_ERROR FIELD16(0x0040)
260 #define TXRX_CSR2_DROP_MULTICAST FIELD16(0x0200)
261 #define TXRX_CSR2_DROP_BROADCAST FIELD16(0x0400)
264 * RX BBP ID registers
265 * TXRX_CSR3: CCK RX BBP ID.
266 * TXRX_CSR4: OFDM RX BBP ID.
268 #define TXRX_CSR3 0x0446
269 #define TXRX_CSR4 0x0448
272 * TXRX_CSR5: CCK TX BBP ID0.
274 #define TXRX_CSR5 0x044a
275 #define TXRX_CSR5_BBP_ID0 FIELD16(0x007f)
276 #define TXRX_CSR5_BBP_ID0_VALID FIELD16(0x0080)
277 #define TXRX_CSR5_BBP_ID1 FIELD16(0x7f00)
278 #define TXRX_CSR5_BBP_ID1_VALID FIELD16(0x8000)
281 * TXRX_CSR6: CCK TX BBP ID1.
283 #define TXRX_CSR6 0x044c
284 #define TXRX_CSR6_BBP_ID0 FIELD16(0x007f)
285 #define TXRX_CSR6_BBP_ID0_VALID FIELD16(0x0080)
286 #define TXRX_CSR6_BBP_ID1 FIELD16(0x7f00)
287 #define TXRX_CSR6_BBP_ID1_VALID FIELD16(0x8000)
290 * TXRX_CSR7: OFDM TX BBP ID0.
292 #define TXRX_CSR7 0x044e
293 #define TXRX_CSR7_BBP_ID0 FIELD16(0x007f)
294 #define TXRX_CSR7_BBP_ID0_VALID FIELD16(0x0080)
295 #define TXRX_CSR7_BBP_ID1 FIELD16(0x7f00)
296 #define TXRX_CSR7_BBP_ID1_VALID FIELD16(0x8000)
299 * TXRX_CSR5: OFDM TX BBP ID1.
301 #define TXRX_CSR8 0x0450
302 #define TXRX_CSR8_BBP_ID0 FIELD16(0x007f)
303 #define TXRX_CSR8_BBP_ID0_VALID FIELD16(0x0080)
304 #define TXRX_CSR8_BBP_ID1 FIELD16(0x7f00)
305 #define TXRX_CSR8_BBP_ID1_VALID FIELD16(0x8000)
308 * TXRX_CSR9: TX ACK time-out.
310 #define TXRX_CSR9 0x0452
313 * TXRX_CSR10: Auto responder control.
315 #define TXRX_CSR10 0x0454
316 #define TXRX_CSR10_AUTORESPOND_PREAMBLE FIELD16(0x0004)
319 * TXRX_CSR11: Auto responder basic rate.
321 #define TXRX_CSR11 0x0456
324 * ACK/CTS time registers.
326 #define TXRX_CSR12 0x0458
327 #define TXRX_CSR13 0x045a
328 #define TXRX_CSR14 0x045c
329 #define TXRX_CSR15 0x045e
330 #define TXRX_CSR16 0x0460
331 #define TXRX_CSR17 0x0462
334 * TXRX_CSR18: Synchronization control register.
336 #define TXRX_CSR18 0x0464
337 #define TXRX_CSR18_OFFSET FIELD16(0x000f)
338 #define TXRX_CSR18_INTERVAL FIELD16(0xfff0)
341 * TXRX_CSR19: Synchronization control register.
342 * TSF_COUNT: Enable TSF auto counting.
343 * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode.
344 * TBCN: Enable Tbcn with reload value.
345 * BEACON_GEN: Enable beacon generator.
347 #define TXRX_CSR19 0x0466
348 #define TXRX_CSR19_TSF_COUNT FIELD16(0x0001)
349 #define TXRX_CSR19_TSF_SYNC FIELD16(0x0006)
350 #define TXRX_CSR19_TBCN FIELD16(0x0008)
351 #define TXRX_CSR19_BEACON_GEN FIELD16(0x0010)
354 * TXRX_CSR20: Tx BEACON offset time control register.
355 * OFFSET: In units of usec.
356 * BCN_EXPECT_WINDOW: Default: 2^CWmin
358 #define TXRX_CSR20 0x0468
359 #define TXRX_CSR20_OFFSET FIELD16(0x1fff)
360 #define TXRX_CSR20_BCN_EXPECT_WINDOW FIELD16(0xe000)
365 #define TXRX_CSR21 0x046a
368 * Encryption related CSRs.
373 * SEC_CSR0-SEC_CSR7: Shared key 0, word 0-7
375 #define SEC_CSR0 0x0480
376 #define SEC_CSR1 0x0482
377 #define SEC_CSR2 0x0484
378 #define SEC_CSR3 0x0486
379 #define SEC_CSR4 0x0488
380 #define SEC_CSR5 0x048a
381 #define SEC_CSR6 0x048c
382 #define SEC_CSR7 0x048e
385 * SEC_CSR8-SEC_CSR15: Shared key 1, word 0-7
387 #define SEC_CSR8 0x0490
388 #define SEC_CSR9 0x0492
389 #define SEC_CSR10 0x0494
390 #define SEC_CSR11 0x0496
391 #define SEC_CSR12 0x0498
392 #define SEC_CSR13 0x049a
393 #define SEC_CSR14 0x049c
394 #define SEC_CSR15 0x049e
397 * SEC_CSR16-SEC_CSR23: Shared key 2, word 0-7
399 #define SEC_CSR16 0x04a0
400 #define SEC_CSR17 0x04a2
401 #define SEC_CSR18 0X04A4
402 #define SEC_CSR19 0x04a6
403 #define SEC_CSR20 0x04a8
404 #define SEC_CSR21 0x04aa
405 #define SEC_CSR22 0x04ac
406 #define SEC_CSR23 0x04ae
409 * SEC_CSR24-SEC_CSR31: Shared key 3, word 0-7
411 #define SEC_CSR24 0x04b0
412 #define SEC_CSR25 0x04b2
413 #define SEC_CSR26 0x04b4
414 #define SEC_CSR27 0x04b6
415 #define SEC_CSR28 0x04b8
416 #define SEC_CSR29 0x04ba
417 #define SEC_CSR30 0x04bc
418 #define SEC_CSR31 0x04be
421 * PHY control registers.
425 * PHY_CSR0: RF switching timing control.
427 #define PHY_CSR0 0x04c0
430 * PHY_CSR1: TX PA configuration.
432 #define PHY_CSR1 0x04c2
435 * MAC configuration registers.
439 * PHY_CSR2: TX MAC configuration.
440 * NOTE: Both register fields are complete dummy,
441 * documentation and legacy drivers are unclear un
442 * what this register means or what fields exists.
444 #define PHY_CSR2 0x04c4
445 #define PHY_CSR2_LNA FIELD16(0x0002)
446 #define PHY_CSR2_LNA_MODE FIELD16(0x3000)
449 * PHY_CSR3: RX MAC configuration.
451 #define PHY_CSR3 0x04c6
454 * PHY_CSR4: Interface configuration.
456 #define PHY_CSR4 0x04c8
457 #define PHY_CSR4_LOW_RF_LE FIELD16(0x0001)
460 * BBP pre-TX registers.
461 * PHY_CSR5: BBP pre-TX CCK.
463 #define PHY_CSR5 0x04ca
464 #define PHY_CSR5_CCK FIELD16(0x0003)
465 #define PHY_CSR5_CCK_FLIP FIELD16(0x0004)
468 * BBP pre-TX registers.
469 * PHY_CSR6: BBP pre-TX OFDM.
471 #define PHY_CSR6 0x04cc
472 #define PHY_CSR6_OFDM FIELD16(0x0003)
473 #define PHY_CSR6_OFDM_FLIP FIELD16(0x0004)
476 * PHY_CSR7: BBP access register 0.
477 * BBP_DATA: BBP data.
478 * BBP_REG_ID: BBP register ID.
479 * BBP_READ_CONTROL: 0: write, 1: read.
481 #define PHY_CSR7 0x04ce
482 #define PHY_CSR7_DATA FIELD16(0x00ff)
483 #define PHY_CSR7_REG_ID FIELD16(0x7f00)
484 #define PHY_CSR7_READ_CONTROL FIELD16(0x8000)
487 * PHY_CSR8: BBP access register 1.
488 * BBP_BUSY: ASIC is busy execute BBP programming.
490 #define PHY_CSR8 0x04d0
491 #define PHY_CSR8_BUSY FIELD16(0x0001)
494 * PHY_CSR9: RF access register.
495 * RF_VALUE: Register value + id to program into rf/if.
497 #define PHY_CSR9 0x04d2
498 #define PHY_CSR9_RF_VALUE FIELD16(0xffff)
501 * PHY_CSR10: RF access register.
502 * RF_VALUE: Register value + id to program into rf/if.
503 * RF_NUMBER_OF_BITS: Number of bits used in value (i:20, rfmd:22).
504 * RF_IF_SELECT: Chip to program: 0: rf, 1: if.
505 * RF_PLL_LD: Rf pll_ld status.
506 * RF_BUSY: 1: asic is busy execute rf programming.
508 #define PHY_CSR10 0x04d4
509 #define PHY_CSR10_RF_VALUE FIELD16(0x00ff)
510 #define PHY_CSR10_RF_NUMBER_OF_BITS FIELD16(0x1f00)
511 #define PHY_CSR10_RF_IF_SELECT FIELD16(0x2000)
512 #define PHY_CSR10_RF_PLL_LD FIELD16(0x4000)
513 #define PHY_CSR10_RF_BUSY FIELD16(0x8000)
516 * STA_CSR0: FCS error count.
517 * FCS_ERROR: FCS error count, cleared when read.
519 #define STA_CSR0 0x04e0
520 #define STA_CSR0_FCS_ERROR FIELD16(0xffff)
523 * STA_CSR1: PLCP error count.
525 #define STA_CSR1 0x04e2
528 * STA_CSR2: LONG error count.
530 #define STA_CSR2 0x04e4
533 * STA_CSR3: CCA false alarm.
534 * FALSE_CCA_ERROR: False CCA error count, cleared when read.
536 #define STA_CSR3 0x04e6
537 #define STA_CSR3_FALSE_CCA_ERROR FIELD16(0xffff)
540 * STA_CSR4: RX FIFO overflow.
542 #define STA_CSR4 0x04e8
545 * STA_CSR5: Beacon sent counter.
547 #define STA_CSR5 0x04ea
550 * Statistics registers
552 #define STA_CSR6 0x04ec
553 #define STA_CSR7 0x04ee
554 #define STA_CSR8 0x04f0
555 #define STA_CSR9 0x04f2
556 #define STA_CSR10 0x04f4
560 * The wordsize of the BBP is 8 bits.
564 * R2: TX antenna control
566 #define BBP_R2_TX_ANTENNA FIELD8(0x03)
567 #define BBP_R2_TX_IQ_FLIP FIELD8(0x04)
570 * R14: RX antenna control
572 #define BBP_R14_RX_ANTENNA FIELD8(0x03)
573 #define BBP_R14_RX_IQ_FLIP FIELD8(0x04)
582 #define RF1_TUNER FIELD32(0x00020000)
587 #define RF3_TUNER FIELD32(0x00000100)
588 #define RF3_TXPOWER FIELD32(0x00003e00)
597 #define EEPROM_MAC_ADDR_0 0x0002
598 #define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
599 #define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
600 #define EEPROM_MAC_ADDR1 0x0003
601 #define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
602 #define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
603 #define EEPROM_MAC_ADDR_2 0x0004
604 #define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
605 #define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
609 * ANTENNA_NUM: Number of antenna's.
610 * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
611 * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
612 * LED_MODE: 0: default, 1: TX/RX activity, 2: Single (ignore link), 3: rsvd.
613 * DYN_TXAGC: Dynamic TX AGC control.
614 * HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0.
615 * RF_TYPE: Rf_type of this adapter.
617 #define EEPROM_ANTENNA 0x000b
618 #define EEPROM_ANTENNA_NUM FIELD16(0x0003)
619 #define EEPROM_ANTENNA_TX_DEFAULT FIELD16(0x000c)
620 #define EEPROM_ANTENNA_RX_DEFAULT FIELD16(0x0030)
621 #define EEPROM_ANTENNA_LED_MODE FIELD16(0x01c0)
622 #define EEPROM_ANTENNA_DYN_TXAGC FIELD16(0x0200)
623 #define EEPROM_ANTENNA_HARDWARE_RADIO FIELD16(0x0400)
624 #define EEPROM_ANTENNA_RF_TYPE FIELD16(0xf800)
628 * CARDBUS_ACCEL: 0: enable, 1: disable.
629 * DYN_BBP_TUNE: 0: enable, 1: disable.
630 * CCK_TX_POWER: CCK TX power compensation.
632 #define EEPROM_NIC 0x000c
633 #define EEPROM_NIC_CARDBUS_ACCEL FIELD16(0x0001)
634 #define EEPROM_NIC_DYN_BBP_TUNE FIELD16(0x0002)
635 #define EEPROM_NIC_CCK_TX_POWER FIELD16(0x000c)
639 * GEO: Default geography setting for device.
641 #define EEPROM_GEOGRAPHY 0x000d
642 #define EEPROM_GEOGRAPHY_GEO FIELD16(0x0f00)
647 #define EEPROM_BBP_START 0x000e
648 #define EEPROM_BBP_SIZE 16
649 #define EEPROM_BBP_VALUE FIELD16(0x00ff)
650 #define EEPROM_BBP_REG_ID FIELD16(0xff00)
655 #define EEPROM_TXPOWER_START 0x001e
656 #define EEPROM_TXPOWER_SIZE 7
657 #define EEPROM_TXPOWER_1 FIELD16(0x00ff)
658 #define EEPROM_TXPOWER_2 FIELD16(0xff00)
661 * EEPROM Tuning threshold
663 #define EEPROM_BBPTUNE 0x0030
664 #define EEPROM_BBPTUNE_THRESHOLD FIELD16(0x00ff)
667 * EEPROM BBP R24 Tuning.
669 #define EEPROM_BBPTUNE_R24 0x0031
670 #define EEPROM_BBPTUNE_R24_LOW FIELD16(0x00ff)
671 #define EEPROM_BBPTUNE_R24_HIGH FIELD16(0xff00)
674 * EEPROM BBP R25 Tuning.
676 #define EEPROM_BBPTUNE_R25 0x0032
677 #define EEPROM_BBPTUNE_R25_LOW FIELD16(0x00ff)
678 #define EEPROM_BBPTUNE_R25_HIGH FIELD16(0xff00)
681 * EEPROM BBP R24 Tuning.
683 #define EEPROM_BBPTUNE_R61 0x0033
684 #define EEPROM_BBPTUNE_R61_LOW FIELD16(0x00ff)
685 #define EEPROM_BBPTUNE_R61_HIGH FIELD16(0xff00)
688 * EEPROM BBP VGC Tuning.
690 #define EEPROM_BBPTUNE_VGC 0x0034
691 #define EEPROM_BBPTUNE_VGCUPPER FIELD16(0x00ff)
692 #define EEPROM_BBPTUNE_VGCLOWER FIELD16(0xff00)
695 * EEPROM BBP R17 Tuning.
697 #define EEPROM_BBPTUNE_R17 0x0035
698 #define EEPROM_BBPTUNE_R17_LOW FIELD16(0x00ff)
699 #define EEPROM_BBPTUNE_R17_HIGH FIELD16(0xff00)
702 * RSSI <-> dBm offset calibration
704 #define EEPROM_CALIBRATE_OFFSET 0x0036
705 #define EEPROM_CALIBRATE_OFFSET_RSSI FIELD16(0x00ff)
708 * DMA descriptor defines.
710 #define TXD_DESC_SIZE ( 5 * sizeof(__le32) )
711 #define RXD_DESC_SIZE ( 4 * sizeof(__le32) )
714 * TX descriptor format for TX, PRIO, ATIM and Beacon Ring.
720 #define TXD_W0_PACKET_ID FIELD32(0x0000000f)
721 #define TXD_W0_RETRY_LIMIT FIELD32(0x000000f0)
722 #define TXD_W0_MORE_FRAG FIELD32(0x00000100)
723 #define TXD_W0_ACK FIELD32(0x00000200)
724 #define TXD_W0_TIMESTAMP FIELD32(0x00000400)
725 #define TXD_W0_OFDM FIELD32(0x00000800)
726 #define TXD_W0_NEW_SEQ FIELD32(0x00001000)
727 #define TXD_W0_IFS FIELD32(0x00006000)
728 #define TXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
729 #define TXD_W0_CIPHER FIELD32(0x20000000)
730 #define TXD_W0_KEY_ID FIELD32(0xc0000000)
735 #define TXD_W1_IV_OFFSET FIELD32(0x0000003f)
736 #define TXD_W1_AIFS FIELD32(0x000000c0)
737 #define TXD_W1_CWMIN FIELD32(0x00000f00)
738 #define TXD_W1_CWMAX FIELD32(0x0000f000)
741 * Word2: PLCP information
743 #define TXD_W2_PLCP_SIGNAL FIELD32(0x000000ff)
744 #define TXD_W2_PLCP_SERVICE FIELD32(0x0000ff00)
745 #define TXD_W2_PLCP_LENGTH_LOW FIELD32(0x00ff0000)
746 #define TXD_W2_PLCP_LENGTH_HIGH FIELD32(0xff000000)
751 #define TXD_W3_IV FIELD32(0xffffffff)
756 #define TXD_W4_EIV FIELD32(0xffffffff)
759 * RX descriptor format for RX Ring.
765 #define RXD_W0_UNICAST_TO_ME FIELD32(0x00000002)
766 #define RXD_W0_MULTICAST FIELD32(0x00000004)
767 #define RXD_W0_BROADCAST FIELD32(0x00000008)
768 #define RXD_W0_MY_BSS FIELD32(0x00000010)
769 #define RXD_W0_CRC_ERROR FIELD32(0x00000020)
770 #define RXD_W0_OFDM FIELD32(0x00000040)
771 #define RXD_W0_PHYSICAL_ERROR FIELD32(0x00000080)
772 #define RXD_W0_CIPHER FIELD32(0x00000100)
773 #define RXD_W0_CIPHER_ERROR FIELD32(0x00000200)
774 #define RXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
779 #define RXD_W1_RSSI FIELD32(0x000000ff)
780 #define RXD_W1_SIGNAL FIELD32(0x0000ff00)
785 #define RXD_W2_IV FIELD32(0xffffffff)
790 #define RXD_W3_EIV FIELD32(0xffffffff)
793 * Macro's for converting txpower from EEPROM to mac80211 value
794 * and from mac80211 value to register value.
796 #define MIN_TXPOWER 0
797 #define MAX_TXPOWER 31
798 #define DEFAULT_TXPOWER 24
800 #define TXPOWER_FROM_DEV(__txpower) \
802 ((__txpower) > MAX_TXPOWER) ? \
803 DEFAULT_TXPOWER : (__txpower); \
806 #define TXPOWER_TO_DEV(__txpower) \
808 ((__txpower) <= MIN_TXPOWER) ? MIN_TXPOWER : \
809 (((__txpower) >= MAX_TXPOWER) ? MAX_TXPOWER : \
813 #endif /* RT2500USB_H */