git.oblomov.eu Git - linux-2.6/blob - drivers/isdn/hardware/mISDN/hfcmulti.c

   1 /*
   2  * hfcmulti.c  low level driver for hfc-4s/hfc-8s/hfc-e1 based cards
   3  *
   4  * Author       Andreas Eversberg (jolly@eversberg.eu)
   5  * ported to mqueue mechanism:
   6  *              Peter Sprenger (sprengermoving-bytes.de)
   7  *
   8  * inspired by existing hfc-pci driver:
   9  * Copyright 1999  by Werner Cornelius (werner@isdn-development.de)
  10  * Copyright 2008  by Karsten Keil (kkeil@suse.de)
  11  * Copyright 2008  by Andreas Eversberg (jolly@eversberg.eu)
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License as published by
  15  * the Free Software Foundation; either version 2, or (at your option)
  16  * any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  26  *
  27  *
  28  * Thanks to Cologne Chip AG for this great controller!
  29  */
  30
  31 /*
  32  * module parameters:
  33  * type:
  34  *      By default (0), the card is automatically detected.
  35  *      Or use the following combinations:
  36  *      Bit 0-7   = 0x00001 = HFC-E1 (1 port)
  37  * or   Bit 0-7   = 0x00004 = HFC-4S (4 ports)
  38  * or   Bit 0-7   = 0x00008 = HFC-8S (8 ports)
  39  *      Bit 8     = 0x00100 = uLaw (instead of aLaw)
  40  *      Bit 9     = 0x00200 = Disable DTMF detect on all B-channels via hardware
  41  *      Bit 10    = spare
  42  *      Bit 11    = 0x00800 = Force PCM bus into slave mode. (otherwhise auto)
  43  * or   Bit 12    = 0x01000 = Force PCM bus into master mode. (otherwhise auto)
  44  *      Bit 13    = spare
  45  *      Bit 14    = 0x04000 = Use external ram (128K)
  46  *      Bit 15    = 0x08000 = Use external ram (512K)
  47  *      Bit 16    = 0x10000 = Use 64 timeslots instead of 32
  48  * or   Bit 17    = 0x20000 = Use 128 timeslots instead of anything else
  49  *      Bit 18    = spare
  50  *      Bit 19    = 0x80000 = Send the Watchdog a Signal (Dual E1 with Watchdog)
  51  * (all other bits are reserved and shall be 0)
  52  *      example: 0x20204 one HFC-4S with dtmf detection and 128 timeslots on PCM
  53  *               bus (PCM master)
  54  *
  55  * port: (optional or required for all ports on all installed cards)
  56  *      HFC-4S/HFC-8S only bits:
  57  *      Bit 0     = 0x001 = Use master clock for this S/T interface
  58  *                          (ony once per chip).
  59  *      Bit 1     = 0x002 = transmitter line setup (non capacitive mode)
  60  *                          Don't use this unless you know what you are doing!
  61  *      Bit 2     = 0x004 = Disable E-channel. (No E-channel processing)
  62  *      example: 0x0001,0x0000,0x0000,0x0000 one HFC-4S with master clock
  63  *               received from port 1
  64  *
  65  *      HFC-E1 only bits:
  66  *      Bit 0     = 0x0001 = interface: 0=copper, 1=optical
  67  *      Bit 1     = 0x0002 = reserved (later for 32 B-channels transparent mode)
  68  *      Bit 2     = 0x0004 = Report LOS
  69  *      Bit 3     = 0x0008 = Report AIS
  70  *      Bit 4     = 0x0010 = Report SLIP
  71  *      Bit 5     = 0x0020 = Report RDI
  72  *      Bit 8     = 0x0100 = Turn off CRC-4 Multiframe Mode, use double frame
  73  *                           mode instead.
  74  *      Bit 9     = 0x0200 = Force get clock from interface, even in NT mode.
  75  * or   Bit 10    = 0x0400 = Force put clock to interface, even in TE mode.
  76  *      Bit 11    = 0x0800 = Use direct RX clock for PCM sync rather than PLL.
  77  *                           (E1 only)
  78  *      Bit 12-13 = 0xX000 = elastic jitter buffer (1-3), Set both bits to 0
  79  *                           for default.
  80  * (all other bits are reserved and shall be 0)
  81  *
  82  * debug:
  83  *      NOTE: only one debug value must be given for all cards
  84  *      enable debugging (see hfc_multi.h for debug options)
  85  *
  86  * poll:
  87  *      NOTE: only one poll value must be given for all cards
  88  *      Give the number of samples for each fifo process.
  89  *      By default 128 is used. Decrease to reduce delay, increase to
  90  *      reduce cpu load. If unsure, don't mess with it!
  91  *      Valid is 8, 16, 32, 64, 128, 256.
  92  *
  93  * pcm:
  94  *      NOTE: only one pcm value must be given for every card.
  95  *      The PCM bus id tells the mISDNdsp module about the connected PCM bus.
  96  *      By default (0), the PCM bus id is 100 for the card that is PCM master.
  97  *      If multiple cards are PCM master (because they are not interconnected),
  98  *      each card with PCM master will have increasing PCM id.
  99  *      All PCM busses with the same ID are expected to be connected and have
 100  *      common time slots slots.
 101  *      Only one chip of the PCM bus must be master, the others slave.
 102  *      -1 means no support of PCM bus not even.
 103  *      Omit this value, if all cards are interconnected or none is connected.
 104  *      If unsure, don't give this parameter.
 105  *
 106  * dslot:
 107  *      NOTE: only one poll value must be given for every card.
 108  *      Also this value must be given for non-E1 cards. If omitted, the E1
 109  *      card has D-channel on time slot 16, which is default.
 110  *      If 1..15 or 17..31, an alternate time slot is used for D-channel.
 111  *      In this case, the application must be able to handle this.
 112  *      If -1 is given, the D-channel is disabled and all 31 slots can be used
 113  *      for B-channel. (only for specific applications)
 114  *      If you don't know how to use it, you don't need it!
 115  *
 116  * iomode:
 117  *      NOTE: only one mode value must be given for every card.
 118  *      -> See hfc_multi.h for HFC_IO_MODE_* values
 119  *      By default, the IO mode is pci memory IO (MEMIO).
 120  *      Some cards requre specific IO mode, so it cannot be changed.
 121  *      It may be usefull to set IO mode to register io (REGIO) to solve
 122  *      PCI bridge problems.
 123  *      If unsure, don't give this parameter.
 124  *
 125  * clockdelay_nt:
 126  *      NOTE: only one clockdelay_nt value must be given once for all cards.
 127  *      Give the value of the clock control register (A_ST_CLK_DLY)
 128  *      of the S/T interfaces in NT mode.
 129  *      This register is needed for the TBR3 certification, so don't change it.
 130  *
 131  * clockdelay_te:
 132  *      NOTE: only one clockdelay_te value must be given once
 133  *      Give the value of the clock control register (A_ST_CLK_DLY)
 134  *      of the S/T interfaces in TE mode.
 135  *      This register is needed for the TBR3 certification, so don't change it.
 136  */
 137
 138 /*
 139  * debug register access (never use this, it will flood your system log)
 140  * #define HFC_REGISTER_DEBUG
 141  */
 142
 143 static const char *hfcmulti_revision = "2.00";
 144
 145 #include <linux/module.h>
 146 #include <linux/pci.h>
 147 #include <linux/delay.h>
 148 #include <linux/mISDNhw.h>
 149 #include <linux/mISDNdsp.h>
 150
 151 /*
 152 #define IRQCOUNT_DEBUG
 153 #define IRQ_DEBUG
 154 */
 155
 156 #include "hfc_multi.h"
 157 #ifdef ECHOPREP
 158 #include "gaintab.h"
 159 #endif
 160
 161 #define MAX_CARDS       8
 162 #define MAX_PORTS       (8 * MAX_CARDS)
 163
 164 static LIST_HEAD(HFClist);
 165 static spinlock_t HFClock; /* global hfc list lock */
 166
 167 static void ph_state_change(struct dchannel *);
 168 static void (*hfc_interrupt)(void);
 169 static void (*register_interrupt)(void);
 170 static int (*unregister_interrupt)(void);
 171 static int interrupt_registered;
 172
 173 static struct hfc_multi *syncmaster;
 174 int plxsd_master; /* if we have a master card (yet) */
 175 static spinlock_t plx_lock; /* may not acquire other lock inside */
 176 EXPORT_SYMBOL(plx_lock);
 177
 178 #define TYP_E1          1
 179 #define TYP_4S          4
 180 #define TYP_8S          8
 181
 182 static int poll_timer = 6;      /* default = 128 samples = 16ms */
 183 /* number of POLL_TIMER interrupts for G2 timeout (ca 1s) */
 184 static int nt_t1_count[] = { 3840, 1920, 960, 480, 240, 120, 60, 30  };
 185 #define CLKDEL_TE       0x0f    /* CLKDEL in TE mode */
 186 #define CLKDEL_NT       0x6c    /* CLKDEL in NT mode
 187                                    (0x60 MUST be included!) */
 188 static u_char silence = 0xff;   /* silence by LAW */
 189
 190 #define DIP_4S  0x1             /* DIP Switches for Beronet 1S/2S/4S cards */
 191 #define DIP_8S  0x2             /* DIP Switches for Beronet 8S+ cards */
 192 #define DIP_E1  0x3             /* DIP Switches for Beronet E1 cards */
 193
 194 /*
 195  * module stuff
 196  */
 197
 198 static uint     type[MAX_CARDS];
 199 static uint     pcm[MAX_CARDS];
 200 static uint     dslot[MAX_CARDS];
 201 static uint     iomode[MAX_CARDS];
 202 static uint     port[MAX_PORTS];
 203 static uint     debug;
 204 static uint     poll;
 205 static uint     timer;
 206 static uint     clockdelay_te = CLKDEL_TE;
 207 static uint     clockdelay_nt = CLKDEL_NT;
 208
 209 static int      HFC_cnt, Port_cnt, PCM_cnt = 99;
 210
 211 MODULE_AUTHOR("Andreas Eversberg");
 212 MODULE_LICENSE("GPL");
 213 module_param(debug, uint, S_IRUGO | S_IWUSR);
 214 module_param(poll, uint, S_IRUGO | S_IWUSR);
 215 module_param(timer, uint, S_IRUGO | S_IWUSR);
 216 module_param(clockdelay_te, uint, S_IRUGO | S_IWUSR);
 217 module_param(clockdelay_nt, uint, S_IRUGO | S_IWUSR);
 218 module_param_array(type, uint, NULL, S_IRUGO | S_IWUSR);
 219 module_param_array(pcm, uint, NULL, S_IRUGO | S_IWUSR);
 220 module_param_array(dslot, uint, NULL, S_IRUGO | S_IWUSR);
 221 module_param_array(iomode, uint, NULL, S_IRUGO | S_IWUSR);
 222 module_param_array(port, uint, NULL, S_IRUGO | S_IWUSR);
 223
 224 #ifdef HFC_REGISTER_DEBUG
 225 #define HFC_outb(hc, reg, val) \
 226         (hc->HFC_outb(hc, reg, val, __func__, __LINE__))
 227 #define HFC_outb_nodebug(hc, reg, val) \
 228         (hc->HFC_outb_nodebug(hc, reg, val, __func__, __LINE__))
 229 #define HFC_inb(hc, reg) \
 230         (hc->HFC_inb(hc, reg, __func__, __LINE__))
 231 #define HFC_inb_nodebug(hc, reg) \
 232         (hc->HFC_inb_nodebug(hc, reg, __func__, __LINE__))
 233 #define HFC_inw(hc, reg) \
 234         (hc->HFC_inw(hc, reg, __func__, __LINE__))
 235 #define HFC_inw_nodebug(hc, reg) \
 236         (hc->HFC_inw_nodebug(hc, reg, __func__, __LINE__))
 237 #define HFC_wait(hc) \
 238         (hc->HFC_wait(hc, __func__, __LINE__))
 239 #define HFC_wait_nodebug(hc) \
 240         (hc->HFC_wait_nodebug(hc, __func__, __LINE__))
 241 #else
 242 #define HFC_outb(hc, reg, val)          (hc->HFC_outb(hc, reg, val))
 243 #define HFC_outb_nodebug(hc, reg, val)  (hc->HFC_outb_nodebug(hc, reg, val))
 244 #define HFC_inb(hc, reg)                (hc->HFC_inb(hc, reg))
 245 #define HFC_inb_nodebug(hc, reg)        (hc->HFC_inb_nodebug(hc, reg))
 246 #define HFC_inw(hc, reg)                (hc->HFC_inw(hc, reg))
 247 #define HFC_inw_nodebug(hc, reg)        (hc->HFC_inw_nodebug(hc, reg))
 248 #define HFC_wait(hc)                    (hc->HFC_wait(hc))
 249 #define HFC_wait_nodebug(hc)            (hc->HFC_wait_nodebug(hc))
 250 #endif
 251
 252 /* HFC_IO_MODE_PCIMEM */
 253 static void
 254 #ifdef HFC_REGISTER_DEBUG
 255 HFC_outb_pcimem(struct hfc_multi *hc, u_char reg, u_char val,
 256                 const char *function, int line)
 257 #else
 258 HFC_outb_pcimem(struct hfc_multi *hc, u_char reg, u_char val)
 259 #endif
 260 {
 261         writeb(val, (hc->pci_membase)+reg);
 262 }
 263 static u_char
 264 #ifdef HFC_REGISTER_DEBUG
 265 HFC_inb_pcimem(struct hfc_multi *hc, u_char reg, const char *function, int line)
 266 #else
 267 HFC_inb_pcimem(struct hfc_multi *hc, u_char reg)
 268 #endif
 269 {
 270         return readb((hc->pci_membase)+reg);
 271 }
 272 static u_short
 273 #ifdef HFC_REGISTER_DEBUG
 274 HFC_inw_pcimem(struct hfc_multi *hc, u_char reg, const char *function, int line)
 275 #else
 276 HFC_inw_pcimem(struct hfc_multi *hc, u_char reg)
 277 #endif
 278 {
 279         return readw((hc->pci_membase)+reg);
 280 }
 281 static void
 282 #ifdef HFC_REGISTER_DEBUG
 283 HFC_wait_pcimem(struct hfc_multi *hc, const char *function, int line)
 284 #else
 285 HFC_wait_pcimem(struct hfc_multi *hc)
 286 #endif
 287 {
 288         while (readb((hc->pci_membase)+R_STATUS) & V_BUSY);
 289 }
 290
 291 /* HFC_IO_MODE_REGIO */
 292 static void
 293 #ifdef HFC_REGISTER_DEBUG
 294 HFC_outb_regio(struct hfc_multi *hc, u_char reg, u_char val,
 295         const char *function, int line)
 296 #else
 297 HFC_outb_regio(struct hfc_multi *hc, u_char reg, u_char val)
 298 #endif
 299 {
 300         outb(reg, (hc->pci_iobase)+4);
 301         outb(val, hc->pci_iobase);
 302 }
 303 static u_char
 304 #ifdef HFC_REGISTER_DEBUG
 305 HFC_inb_regio(struct hfc_multi *hc, u_char reg, const char *function, int line)
 306 #else
 307 HFC_inb_regio(struct hfc_multi *hc, u_char reg)
 308 #endif
 309 {
 310         outb(reg, (hc->pci_iobase)+4);
 311         return inb(hc->pci_iobase);
 312 }
 313 static u_short
 314 #ifdef HFC_REGISTER_DEBUG
 315 HFC_inw_regio(struct hfc_multi *hc, u_char reg, const char *function, int line)
 316 #else
 317 HFC_inw_regio(struct hfc_multi *hc, u_char reg)
 318 #endif
 319 {
 320         outb(reg, (hc->pci_iobase)+4);
 321         return inw(hc->pci_iobase);
 322 }
 323 static void
 324 #ifdef HFC_REGISTER_DEBUG
 325 HFC_wait_regio(struct hfc_multi *hc, const char *function, int line)
 326 #else
 327 HFC_wait_regio(struct hfc_multi *hc)
 328 #endif
 329 {
 330         outb(R_STATUS, (hc->pci_iobase)+4);
 331         while (inb(hc->pci_iobase) & V_BUSY);
 332 }
 333
 334 #ifdef HFC_REGISTER_DEBUG
 335 static void
 336 HFC_outb_debug(struct hfc_multi *hc, u_char reg, u_char val,
 337                 const char *function, int line)
 338 {
 339         char regname[256] = "", bits[9] = "xxxxxxxx";
 340         int i;
 341
 342         i = -1;
 343         while (hfc_register_names[++i].name) {
 344                 if (hfc_register_names[i].reg == reg)
 345                         strcat(regname, hfc_register_names[i].name);
 346         }
 347         if (regname[0] == '\0')
 348                 strcpy(regname, "register");
 349
 350         bits[7] = '0'+(!!(val&1));
 351         bits[6] = '0'+(!!(val&2));
 352         bits[5] = '0'+(!!(val&4));
 353         bits[4] = '0'+(!!(val&8));
 354         bits[3] = '0'+(!!(val&16));
 355         bits[2] = '0'+(!!(val&32));
 356         bits[1] = '0'+(!!(val&64));
 357         bits[0] = '0'+(!!(val&128));
 358         printk(KERN_DEBUG
 359             "HFC_outb(chip %d, %02x=%s, 0x%02x=%s); in %s() line %d\n",
 360             hc->id, reg, regname, val, bits, function, line);
 361         HFC_outb_nodebug(hc, reg, val);
 362 }
 363 static u_char
 364 HFC_inb_debug(struct hfc_multi *hc, u_char reg, const char *function, int line)
 365 {
 366         char regname[256] = "", bits[9] = "xxxxxxxx";
 367         u_char val = HFC_inb_nodebug(hc, reg);
 368         int i;
 369
 370         i = 0;
 371         while (hfc_register_names[i++].name)
 372                 ;
 373         while (hfc_register_names[++i].name) {
 374                 if (hfc_register_names[i].reg == reg)
 375                         strcat(regname, hfc_register_names[i].name);
 376         }
 377         if (regname[0] == '\0')
 378                 strcpy(regname, "register");
 379
 380         bits[7] = '0'+(!!(val&1));
 381         bits[6] = '0'+(!!(val&2));
 382         bits[5] = '0'+(!!(val&4));
 383         bits[4] = '0'+(!!(val&8));
 384         bits[3] = '0'+(!!(val&16));
 385         bits[2] = '0'+(!!(val&32));
 386         bits[1] = '0'+(!!(val&64));
 387         bits[0] = '0'+(!!(val&128));
 388         printk(KERN_DEBUG
 389             "HFC_inb(chip %d, %02x=%s) = 0x%02x=%s; in %s() line %d\n",
 390             hc->id, reg, regname, val, bits, function, line);
 391         return val;
 392 }
 393 static u_short
 394 HFC_inw_debug(struct hfc_multi *hc, u_char reg, const char *function, int line)
 395 {
 396         char regname[256] = "";
 397         u_short val = HFC_inw_nodebug(hc, reg);
 398         int i;
 399
 400         i = 0;
 401         while (hfc_register_names[i++].name)
 402                 ;
 403         while (hfc_register_names[++i].name) {
 404                 if (hfc_register_names[i].reg == reg)
 405                         strcat(regname, hfc_register_names[i].name);
 406         }
 407         if (regname[0] == '\0')
 408                 strcpy(regname, "register");
 409
 410         printk(KERN_DEBUG
 411             "HFC_inw(chip %d, %02x=%s) = 0x%04x; in %s() line %d\n",
 412             hc->id, reg, regname, val, function, line);
 413         return val;
 414 }
 415 static void
 416 HFC_wait_debug(struct hfc_multi *hc, const char *function, int line)
 417 {
 418         printk(KERN_DEBUG "HFC_wait(chip %d); in %s() line %d\n",
 419             hc->id, function, line);
 420         HFC_wait_nodebug(hc);
 421 }
 422 #endif
 423
 424 /* write fifo data (REGIO) */
 425 void
 426 write_fifo_regio(struct hfc_multi *hc, u_char *data, int len)
 427 {
 428         outb(A_FIFO_DATA0, (hc->pci_iobase)+4);
 429         while (len>>2) {
 430                 outl(*(u32 *)data, hc->pci_iobase);
 431                 data += 4;
 432                 len -= 4;
 433         }
 434         while (len>>1) {
 435                 outw(*(u16 *)data, hc->pci_iobase);
 436                 data += 2;
 437                 len -= 2;
 438         }
 439         while (len) {
 440                 outb(*data, hc->pci_iobase);
 441                 data++;
 442                 len--;
 443         }
 444 }
 445 /* write fifo data (PCIMEM) */
 446 void
 447 write_fifo_pcimem(struct hfc_multi *hc, u_char *data, int len)
 448 {
 449         while (len>>2) {
 450                 writel(*(u32 *)data, (hc->pci_membase)+A_FIFO_DATA0);
 451                 data += 4;
 452                 len -= 4;
 453         }
 454         while (len>>1) {
 455                 writew(*(u16 *)data, (hc->pci_membase)+A_FIFO_DATA0);
 456                 data += 2;
 457                 len -= 2;
 458         }
 459         while (len) {
 460                 writeb(*data, (hc->pci_membase)+A_FIFO_DATA0);
 461                 data++;
 462                 len--;
 463         }
 464 }
 465 /* read fifo data (REGIO) */
 466 void
 467 read_fifo_regio(struct hfc_multi *hc, u_char *data, int len)
 468 {
 469         outb(A_FIFO_DATA0, (hc->pci_iobase)+4);
 470         while (len>>2) {
 471                 *(u32 *)data = inl(hc->pci_iobase);
 472                 data += 4;
 473                 len -= 4;
 474         }
 475         while (len>>1) {
 476                 *(u16 *)data = inw(hc->pci_iobase);
 477                 data += 2;
 478                 len -= 2;
 479         }
 480         while (len) {
 481                 *data = inb(hc->pci_iobase);
 482                 data++;
 483                 len--;
 484         }
 485 }
 486
 487 /* read fifo data (PCIMEM) */
 488 void
 489 read_fifo_pcimem(struct hfc_multi *hc, u_char *data, int len)
 490 {
 491         while (len>>2) {
 492                 *(u32 *)data =
 493                         readl((hc->pci_membase)+A_FIFO_DATA0);
 494                 data += 4;
 495                 len -= 4;
 496         }
 497         while (len>>1) {
 498                 *(u16 *)data =
 499                         readw((hc->pci_membase)+A_FIFO_DATA0);
 500                 data += 2;
 501                 len -= 2;
 502         }
 503         while (len) {
 504                 *data = readb((hc->pci_membase)+A_FIFO_DATA0);
 505                 data++;
 506                 len--;
 507         }
 508 }
 509
 510
 511 static void
 512 enable_hwirq(struct hfc_multi *hc)
 513 {
 514         hc->hw.r_irq_ctrl |= V_GLOB_IRQ_EN;
 515         HFC_outb(hc, R_IRQ_CTRL, hc->hw.r_irq_ctrl);
 516 }
 517
 518 static void
 519 disable_hwirq(struct hfc_multi *hc)
 520 {
 521         hc->hw.r_irq_ctrl &= ~((u_char)V_GLOB_IRQ_EN);
 522         HFC_outb(hc, R_IRQ_CTRL, hc->hw.r_irq_ctrl);
 523 }
 524
 525 #define NUM_EC 2
 526 #define MAX_TDM_CHAN 32
 527
 528
 529 inline void
 530 enablepcibridge(struct hfc_multi *c)
 531 {
 532         HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x3); /* was _io before */
 533 }
 534
 535 inline void
 536 disablepcibridge(struct hfc_multi *c)
 537 {
 538         HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x2); /* was _io before */
 539 }
 540
 541 inline unsigned char
 542 readpcibridge(struct hfc_multi *hc, unsigned char address)
 543 {
 544         unsigned short cipv;
 545         unsigned char data;
 546
 547         if (!hc->pci_iobase)
 548                 return 0;
 549
 550         /* slow down a PCI read access by 1 PCI clock cycle */
 551         HFC_outb(hc, R_CTRL, 0x4); /*was _io before*/
 552
 553         if (address == 0)
 554                 cipv = 0x4000;
 555         else
 556                 cipv = 0x5800;
 557
 558         /* select local bridge port address by writing to CIP port */
 559         /* data = HFC_inb(c, cipv); * was _io before */
 560         outw(cipv, hc->pci_iobase + 4);
 561         data = inb(hc->pci_iobase);
 562
 563         /* restore R_CTRL for normal PCI read cycle speed */
 564         HFC_outb(hc, R_CTRL, 0x0); /* was _io before */
 565
 566         return data;
 567 }
 568
 569 inline void
 570 writepcibridge(struct hfc_multi *hc, unsigned char address, unsigned char data)
 571 {
 572         unsigned short cipv;
 573         unsigned int datav;
 574
 575         if (!hc->pci_iobase)
 576                 return;
 577
 578         if (address == 0)
 579                 cipv = 0x4000;
 580         else
 581                 cipv = 0x5800;
 582
 583         /* select local bridge port address by writing to CIP port */
 584         outw(cipv, hc->pci_iobase + 4);
 585         /* define a 32 bit dword with 4 identical bytes for write sequence */
 586         datav = data | ((__u32) data << 8) | ((__u32) data << 16) |
 587             ((__u32) data << 24);
 588
 589         /*
 590          * write this 32 bit dword to the bridge data port
 591          * this will initiate a write sequence of up to 4 writes to the same
 592          * address on the local bus interface the number of write accesses
 593          * is undefined but >=1 and depends on the next PCI transaction
 594          * during write sequence on the local bus
 595          */
 596         outl(datav, hc->pci_iobase);
 597 }
 598
 599 inline void
 600 cpld_set_reg(struct hfc_multi *hc, unsigned char reg)
 601 {
 602         /* Do data pin read low byte */
 603         HFC_outb(hc, R_GPIO_OUT1, reg);
 604 }
 605
 606 inline void
 607 cpld_write_reg(struct hfc_multi *hc, unsigned char reg, unsigned char val)
 608 {
 609         cpld_set_reg(hc, reg);
 610
 611         enablepcibridge(hc);
 612         writepcibridge(hc, 1, val);
 613         disablepcibridge(hc);
 614
 615         return;
 616 }
 617
 618 inline unsigned char
 619 cpld_read_reg(struct hfc_multi *hc, unsigned char reg)
 620 {
 621         unsigned char bytein;
 622
 623         cpld_set_reg(hc, reg);
 624
 625         /* Do data pin read low byte */
 626         HFC_outb(hc, R_GPIO_OUT1, reg);
 627
 628         enablepcibridge(hc);
 629         bytein = readpcibridge(hc, 1);
 630         disablepcibridge(hc);
 631
 632         return bytein;
 633 }
 634
 635 inline void
 636 vpm_write_address(struct hfc_multi *hc, unsigned short addr)
 637 {
 638         cpld_write_reg(hc, 0, 0xff & addr);
 639         cpld_write_reg(hc, 1, 0x01 & (addr >> 8));
 640 }
 641
 642 inline unsigned short
 643 vpm_read_address(struct hfc_multi *c)
 644 {
 645         unsigned short addr;
 646         unsigned short highbit;
 647
 648         addr = cpld_read_reg(c, 0);
 649         highbit = cpld_read_reg(c, 1);
 650
 651         addr = addr | (highbit << 8);
 652
 653         return addr & 0x1ff;
 654 }
 655
 656 inline unsigned char
 657 vpm_in(struct hfc_multi *c, int which, unsigned short addr)
 658 {
 659         unsigned char res;
 660
 661         vpm_write_address(c, addr);
 662
 663         if (!which)
 664                 cpld_set_reg(c, 2);
 665         else
 666                 cpld_set_reg(c, 3);
 667
 668         enablepcibridge(c);
 669         res = readpcibridge(c, 1);
 670         disablepcibridge(c);
 671
 672         cpld_set_reg(c, 0);
 673
 674         return res;
 675 }
 676
 677 inline void
 678 vpm_out(struct hfc_multi *c, int which, unsigned short addr,
 679     unsigned char data)
 680 {
 681         vpm_write_address(c, addr);
 682
 683         enablepcibridge(c);
 684
 685         if (!which)
 686                 cpld_set_reg(c, 2);
 687         else
 688                 cpld_set_reg(c, 3);
 689
 690         writepcibridge(c, 1, data);
 691
 692         cpld_set_reg(c, 0);
 693
 694         disablepcibridge(c);
 695
 696         {
 697         unsigned char regin;
 698         regin = vpm_in(c, which, addr);
 699         if (regin != data)
 700                 printk(KERN_DEBUG "Wrote 0x%x to register 0x%x but got back "
 701                         "0x%x\n", data, addr, regin);
 702         }
 703
 704 }
 705
 706
 707 void
 708 vpm_init(struct hfc_multi *wc)
 709 {
 710         unsigned char reg;
 711         unsigned int mask;
 712         unsigned int i, x, y;
 713         unsigned int ver;
 714
 715         for (x = 0; x < NUM_EC; x++) {
 716                 /* Setup GPIO's */
 717                 if (!x) {
 718                         ver = vpm_in(wc, x, 0x1a0);
 719                         printk(KERN_DEBUG "VPM: Chip %d: ver %02x\n", x, ver);
 720                 }
 721
 722                 for (y = 0; y < 4; y++) {
 723                         vpm_out(wc, x, 0x1a8 + y, 0x00); /* GPIO out */
 724                         vpm_out(wc, x, 0x1ac + y, 0x00); /* GPIO dir */
 725                         vpm_out(wc, x, 0x1b0 + y, 0x00); /* GPIO sel */
 726                 }
 727
 728                 /* Setup TDM path - sets fsync and tdm_clk as inputs */
 729                 reg = vpm_in(wc, x, 0x1a3); /* misc_con */
 730                 vpm_out(wc, x, 0x1a3, reg & ~2);
 731
 732                 /* Setup Echo length (256 taps) */
 733                 vpm_out(wc, x, 0x022, 1);
 734                 vpm_out(wc, x, 0x023, 0xff);
 735
 736                 /* Setup timeslots */
 737                 vpm_out(wc, x, 0x02f, 0x00);
 738                 mask = 0x02020202 << (x * 4);
 739
 740                 /* Setup the tdm channel masks for all chips */
 741                 for (i = 0; i < 4; i++)
 742                         vpm_out(wc, x, 0x33 - i, (mask >> (i << 3)) & 0xff);
 743
 744                 /* Setup convergence rate */
 745                 printk(KERN_DEBUG "VPM: A-law mode\n");
 746                 reg = 0x00 | 0x10 | 0x01;
 747                 vpm_out(wc, x, 0x20, reg);
 748                 printk(KERN_DEBUG "VPM reg 0x20 is %x\n", reg);
 749                 /*vpm_out(wc, x, 0x20, (0x00 | 0x08 | 0x20 | 0x10)); */
 750
 751                 vpm_out(wc, x, 0x24, 0x02);
 752                 reg = vpm_in(wc, x, 0x24);
 753                 printk(KERN_DEBUG "NLP Thresh is set to %d (0x%x)\n", reg, reg);
 754
 755                 /* Initialize echo cans */
 756                 for (i = 0; i < MAX_TDM_CHAN; i++) {
 757                         if (mask & (0x00000001 << i))
 758                                 vpm_out(wc, x, i, 0x00);
 759                 }
 760
 761                 /*
 762                  * ARM arch at least disallows a udelay of
 763                  * more than 2ms... it gives a fake "__bad_udelay"
 764                  * reference at link-time.
 765                  * long delays in kernel code are pretty sucky anyway
 766                  * for now work around it using 5 x 2ms instead of 1 x 10ms
 767                  */
 768
 769                 udelay(2000);
 770                 udelay(2000);
 771                 udelay(2000);
 772                 udelay(2000);
 773                 udelay(2000);
 774
 775                 /* Put in bypass mode */
 776                 for (i = 0; i < MAX_TDM_CHAN; i++) {
 777                         if (mask & (0x00000001 << i))
 778                                 vpm_out(wc, x, i, 0x01);
 779                 }
 780
 781                 /* Enable bypass */
 782                 for (i = 0; i < MAX_TDM_CHAN; i++) {
 783                         if (mask & (0x00000001 << i))
 784                                 vpm_out(wc, x, 0x78 + i, 0x01);
 785                 }
 786
 787         }
 788 }
 789
 790 void
 791 vpm_check(struct hfc_multi *hctmp)
 792 {
 793         unsigned char gpi2;
 794
 795         gpi2 = HFC_inb(hctmp, R_GPI_IN2);
 796
 797         if ((gpi2 & 0x3) != 0x3)
 798                 printk(KERN_DEBUG "Got interrupt 0x%x from VPM!\n", gpi2);
 799 }
 800
 801
 802 /*
 803  * Interface to enable/disable the HW Echocan
 804  *
 805  * these functions are called within a spin_lock_irqsave on
 806  * the channel instance lock, so we are not disturbed by irqs
 807  *
 808  * we can later easily change the interface to make  other
 809  * things configurable, for now we configure the taps
 810  *
 811  */
 812
 813 void
 814 vpm_echocan_on(struct hfc_multi *hc, int ch, int taps)
 815 {
 816         unsigned int timeslot;
 817         unsigned int unit;
 818         struct bchannel *bch = hc->chan[ch].bch;
 819 #ifdef TXADJ
 820         int txadj = -4;
 821         struct sk_buff *skb;
 822 #endif
 823         if (hc->chan[ch].protocol != ISDN_P_B_RAW)
 824                 return;
 825
 826         if (!bch)
 827                 return;
 828
 829 #ifdef TXADJ
 830         skb = _alloc_mISDN_skb(PH_CONTROL_IND, HFC_VOL_CHANGE_TX,
 831                 sizeof(int), &txadj, GFP_ATOMIC);
 832         if (skb)
 833                 recv_Bchannel_skb(bch, skb);
 834 #endif
 835
 836         timeslot = ((ch/4)*8) + ((ch%4)*4) + 1;
 837         unit = ch % 4;
 838
 839         printk(KERN_NOTICE "vpm_echocan_on called taps [%d] on timeslot %d\n",
 840             taps, timeslot);
 841
 842         vpm_out(hc, unit, timeslot, 0x7e);
 843 }
 844
 845 void
 846 vpm_echocan_off(struct hfc_multi *hc, int ch)
 847 {
 848         unsigned int timeslot;
 849         unsigned int unit;
 850         struct bchannel *bch = hc->chan[ch].bch;
 851 #ifdef TXADJ
 852         int txadj = 0;
 853         struct sk_buff *skb;
 854 #endif
 855
 856         if (hc->chan[ch].protocol != ISDN_P_B_RAW)
 857                 return;
 858
 859         if (!bch)
 860                 return;
 861
 862 #ifdef TXADJ
 863         skb = _alloc_mISDN_skb(PH_CONTROL_IND, HFC_VOL_CHANGE_TX,
 864                 sizeof(int), &txadj, GFP_ATOMIC);
 865         if (skb)
 866                 recv_Bchannel_skb(bch, skb);
 867 #endif
 868
 869         timeslot = ((ch/4)*8) + ((ch%4)*4) + 1;
 870         unit = ch % 4;
 871
 872         printk(KERN_NOTICE "vpm_echocan_off called on timeslot %d\n",
 873             timeslot);
 874         /* FILLME */
 875         vpm_out(hc, unit, timeslot, 0x01);
 876 }
 877
 878
 879 /*
 880  * Speech Design resync feature
 881  * NOTE: This is called sometimes outside interrupt handler.
 882  * We must lock irqsave, so no other interrupt (other card) will occurr!
 883  * Also multiple interrupts may nest, so must lock each access (lists, card)!
 884  */
 885 static inline void
 886 hfcmulti_resync(struct hfc_multi *locked, struct hfc_multi *newmaster, int rm)
 887 {
 888         struct hfc_multi *hc, *next, *pcmmaster = 0;
 889         u_int *plx_acc_32, pv;
 890         u_long flags;
 891
 892         spin_lock_irqsave(&HFClock, flags);
 893         spin_lock(&plx_lock); /* must be locked inside other locks */
 894
 895         if (debug & DEBUG_HFCMULTI_PLXSD)
 896                 printk(KERN_DEBUG "%s: RESYNC(syncmaster=0x%p)\n",
 897                         __func__, syncmaster);
 898
 899         /* select new master */
 900         if (newmaster) {
 901                 if (debug & DEBUG_HFCMULTI_PLXSD)
 902                         printk(KERN_DEBUG "using provided controller\n");
 903         } else {
 904                 list_for_each_entry_safe(hc, next, &HFClist, list) {
 905                         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
 906                                 if (hc->syncronized) {
 907                                         newmaster = hc;
 908                                         break;
 909                                 }
 910                         }
 911                 }
 912         }
 913
 914         /* Disable sync of all cards */
 915         list_for_each_entry_safe(hc, next, &HFClist, list) {
 916                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
 917                         plx_acc_32 = (u_int *)(hc->plx_membase+PLX_GPIOC);
 918                         pv = readl(plx_acc_32);
 919                         pv &= ~PLX_SYNC_O_EN;
 920                         writel(pv, plx_acc_32);
 921                         if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)) {
 922                                 pcmmaster = hc;
 923                                 if (hc->type == 1) {
 924                                         if (debug & DEBUG_HFCMULTI_PLXSD)
 925                                                 printk(KERN_DEBUG
 926                                                         "Schedule SYNC_I\n");
 927                                         hc->e1_resync |= 1; /* get SYNC_I */
 928                                 }
 929                         }
 930                 }
 931         }
 932
 933         if (newmaster) {
 934                 hc = newmaster;
 935                 if (debug & DEBUG_HFCMULTI_PLXSD)
 936                         printk(KERN_DEBUG "id=%d (0x%p) = syncronized with "
 937                                 "interface.\n", hc->id, hc);
 938                 /* Enable new sync master */
 939                 plx_acc_32 = (u_int *)(hc->plx_membase+PLX_GPIOC);
 940                 pv = readl(plx_acc_32);
 941                 pv |= PLX_SYNC_O_EN;
 942                 writel(pv, plx_acc_32);
 943                 /* switch to jatt PLL, if not disabled by RX_SYNC */
 944                 if (hc->type == 1 && !test_bit(HFC_CHIP_RX_SYNC, &hc->chip)) {
 945                         if (debug & DEBUG_HFCMULTI_PLXSD)
 946                                 printk(KERN_DEBUG "Schedule jatt PLL\n");
 947                         hc->e1_resync |= 2; /* switch to jatt */
 948                 }
 949         } else {
 950                 if (pcmmaster) {
 951                         hc = pcmmaster;
 952                         if (debug & DEBUG_HFCMULTI_PLXSD)
 953                                 printk(KERN_DEBUG
 954                                         "id=%d (0x%p) = PCM master syncronized "
 955                                         "with QUARTZ\n", hc->id, hc);
 956                         if (hc->type == 1) {
 957                                 /* Use the crystal clock for the PCM
 958                                    master card */
 959                                 if (debug & DEBUG_HFCMULTI_PLXSD)
 960                                         printk(KERN_DEBUG
 961                                             "Schedule QUARTZ for HFC-E1\n");
 962                                 hc->e1_resync |= 4; /* switch quartz */
 963                         } else {
 964                                 if (debug & DEBUG_HFCMULTI_PLXSD)
 965                                         printk(KERN_DEBUG
 966                                             "QUARTZ is automatically "
 967                                             "enabled by HFC-%dS\n", hc->type);
 968                         }
 969                         plx_acc_32 = (u_int *)(hc->plx_membase+PLX_GPIOC);
 970                         pv = readl(plx_acc_32);
 971                         pv |= PLX_SYNC_O_EN;
 972                         writel(pv, plx_acc_32);
 973                 } else
 974                         if (!rm)
 975                                 printk(KERN_ERR "%s no pcm master, this MUST "
 976                                         "not happen!\n", __func__);
 977         }
 978         syncmaster = newmaster;
 979
 980         spin_unlock(&plx_lock);
 981         spin_unlock_irqrestore(&HFClock, flags);
 982 }
 983
 984 /* This must be called AND hc must be locked irqsave!!! */
 985 inline void
 986 plxsd_checksync(struct hfc_multi *hc, int rm)
 987 {
 988         if (hc->syncronized) {
 989                 if (syncmaster == NULL) {
 990                         if (debug & DEBUG_HFCMULTI_PLXSD)
 991                                 printk(KERN_WARNING "%s: GOT sync on card %d"
 992                                         " (id=%d)\n", __func__, hc->id + 1,
 993                                         hc->id);
 994                         hfcmulti_resync(hc, hc, rm);
 995                 }
 996         } else {
 997                 if (syncmaster == hc) {
 998                         if (debug & DEBUG_HFCMULTI_PLXSD)
 999                                 printk(KERN_WARNING "%s: LOST sync on card %d"
1000                                         " (id=%d)\n", __func__, hc->id + 1,
1001                                         hc->id);
1002                         hfcmulti_resync(hc, NULL, rm);
1003                 }
1004         }
1005 }
1006
1007
1008 /*
1009  * free hardware resources used by driver
1010  */
1011 static void
1012 release_io_hfcmulti(struct hfc_multi *hc)
1013 {
1014         u_int   *plx_acc_32, pv;
1015         u_long  plx_flags;
1016
1017         if (debug & DEBUG_HFCMULTI_INIT)
1018                 printk(KERN_DEBUG "%s: entered\n", __func__);
1019
1020         /* soft reset also masks all interrupts */
1021         hc->hw.r_cirm |= V_SRES;
1022         HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1023         udelay(1000);
1024         hc->hw.r_cirm &= ~V_SRES;
1025         HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1026         udelay(1000); /* instead of 'wait' that may cause locking */
1027
1028         /* release Speech Design card, if PLX was initialized */
1029         if (test_bit(HFC_CHIP_PLXSD, &hc->chip) && hc->plx_membase) {
1030                 if (debug & DEBUG_HFCMULTI_PLXSD)
1031                         printk(KERN_DEBUG "%s: release PLXSD card %d\n",
1032                             __func__, hc->id + 1);
1033                 spin_lock_irqsave(&plx_lock, plx_flags);
1034                 plx_acc_32 = (u_int *)(hc->plx_membase+PLX_GPIOC);
1035                 writel(PLX_GPIOC_INIT, plx_acc_32);
1036                 pv = readl(plx_acc_32);
1037                 /* Termination off */
1038                 pv &= ~PLX_TERM_ON;
1039                 /* Disconnect the PCM */
1040                 pv |= PLX_SLAVE_EN_N;
1041                 pv &= ~PLX_MASTER_EN;
1042                 pv &= ~PLX_SYNC_O_EN;
1043                 /* Put the DSP in Reset */
1044                 pv &= ~PLX_DSP_RES_N;
1045                 writel(pv, plx_acc_32);
1046                 if (debug & DEBUG_HFCMULTI_INIT)
1047                         printk(KERN_WARNING "%s: PCM off: PLX_GPIO=%x\n",
1048                                 __func__, pv);
1049                 spin_unlock_irqrestore(&plx_lock, plx_flags);
1050         }
1051
1052         /* disable memory mapped ports / io ports */
1053         test_and_clear_bit(HFC_CHIP_PLXSD, &hc->chip); /* prevent resync */
1054         pci_write_config_word(hc->pci_dev, PCI_COMMAND, 0);
1055         if (hc->pci_membase)
1056                 iounmap((void *)hc->pci_membase);
1057         if (hc->plx_membase)
1058                 iounmap((void *)hc->plx_membase);
1059         if (hc->pci_iobase)
1060                 release_region(hc->pci_iobase, 8);
1061
1062         if (hc->pci_dev) {
1063                 pci_disable_device(hc->pci_dev);
1064                 pci_set_drvdata(hc->pci_dev, NULL);
1065         }
1066         if (debug & DEBUG_HFCMULTI_INIT)
1067                 printk(KERN_DEBUG "%s: done\n", __func__);
1068 }
1069
1070 /*
1071  * function called to reset the HFC chip. A complete software reset of chip
1072  * and fifos is done. All configuration of the chip is done.
1073  */
1074
1075 static int
1076 init_chip(struct hfc_multi *hc)
1077 {
1078         u_long                  flags, val, val2 = 0, rev;
1079         int                     i, err = 0;
1080         u_char                  r_conf_en, rval;
1081         u_int                   *plx_acc_32, pv;
1082         u_long                  plx_flags, hfc_flags;
1083         int                     plx_count;
1084         struct hfc_multi        *pos, *next, *plx_last_hc;
1085
1086         spin_lock_irqsave(&hc->lock, flags);
1087         /* reset all registers */
1088         memset(&hc->hw, 0, sizeof(struct hfcm_hw));
1089
1090         /* revision check */
1091         if (debug & DEBUG_HFCMULTI_INIT)
1092                 printk(KERN_DEBUG "%s: entered\n", __func__);
1093         val = HFC_inb(hc, R_CHIP_ID)>>4;
1094         if (val != 0x8 && val != 0xc && val != 0xe) {
1095                 printk(KERN_INFO "HFC_multi: unknown CHIP_ID:%x\n", (u_int)val);
1096                 err = -EIO;
1097                 goto out;
1098         }
1099         rev = HFC_inb(hc, R_CHIP_RV);
1100         printk(KERN_INFO
1101             "HFC_multi: detected HFC with chip ID=0x%lx revision=%ld%s\n",
1102             val, rev, (rev == 0) ? " (old FIFO handling)" : "");
1103         if (rev == 0) {
1104                 test_and_set_bit(HFC_CHIP_REVISION0, &hc->chip);
1105                 printk(KERN_WARNING
1106                     "HFC_multi: NOTE: Your chip is revision 0, "
1107                     "ask Cologne Chip for update. Newer chips "
1108                     "have a better FIFO handling. Old chips "
1109                     "still work but may have slightly lower "
1110                     "HDLC transmit performance.\n");
1111         }
1112         if (rev > 1) {
1113                 printk(KERN_WARNING "HFC_multi: WARNING: This driver doesn't "
1114                     "consider chip revision = %ld. The chip / "
1115                     "bridge may not work.\n", rev);
1116         }
1117
1118         /* set s-ram size */
1119         hc->Flen = 0x10;
1120         hc->Zmin = 0x80;
1121         hc->Zlen = 384;
1122         hc->DTMFbase = 0x1000;
1123         if (test_bit(HFC_CHIP_EXRAM_128, &hc->chip)) {
1124                 if (debug & DEBUG_HFCMULTI_INIT)
1125                         printk(KERN_DEBUG "%s: changing to 128K extenal RAM\n",
1126                             __func__);
1127                 hc->hw.r_ctrl |= V_EXT_RAM;
1128                 hc->hw.r_ram_sz = 1;
1129                 hc->Flen = 0x20;
1130                 hc->Zmin = 0xc0;
1131                 hc->Zlen = 1856;
1132                 hc->DTMFbase = 0x2000;
1133         }
1134         if (test_bit(HFC_CHIP_EXRAM_512, &hc->chip)) {
1135                 if (debug & DEBUG_HFCMULTI_INIT)
1136                         printk(KERN_DEBUG "%s: changing to 512K extenal RAM\n",
1137                             __func__);
1138                 hc->hw.r_ctrl |= V_EXT_RAM;
1139                 hc->hw.r_ram_sz = 2;
1140                 hc->Flen = 0x20;
1141                 hc->Zmin = 0xc0;
1142                 hc->Zlen = 8000;
1143                 hc->DTMFbase = 0x2000;
1144         }
1145         hc->max_trans = poll << 1;
1146         if (hc->max_trans > hc->Zlen)
1147                 hc->max_trans = hc->Zlen;
1148
1149         /* Speech Design PLX bridge */
1150         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1151                 if (debug & DEBUG_HFCMULTI_PLXSD)
1152                         printk(KERN_DEBUG "%s: initializing PLXSD card %d\n",
1153                             __func__, hc->id + 1);
1154                 spin_lock_irqsave(&plx_lock, plx_flags);
1155                 plx_acc_32 = (u_int *)(hc->plx_membase+PLX_GPIOC);
1156                 writel(PLX_GPIOC_INIT, plx_acc_32);
1157                 pv = readl(plx_acc_32);
1158                 /* The first and the last cards are terminating the PCM bus */
1159                 pv |= PLX_TERM_ON; /* hc is currently the last */
1160                 /* Disconnect the PCM */
1161                 pv |= PLX_SLAVE_EN_N;
1162                 pv &= ~PLX_MASTER_EN;
1163                 pv &= ~PLX_SYNC_O_EN;
1164                 /* Put the DSP in Reset */
1165                 pv &= ~PLX_DSP_RES_N;
1166                 writel(pv, plx_acc_32);
1167                 spin_unlock_irqrestore(&plx_lock, plx_flags);
1168                 if (debug & DEBUG_HFCMULTI_INIT)
1169                         printk(KERN_WARNING "%s: slave/term: PLX_GPIO=%x\n",
1170                                 __func__, pv);
1171                 /*
1172                  * If we are the 3rd PLXSD card or higher, we must turn
1173                  * termination of last PLXSD card off.
1174                  */
1175                 spin_lock_irqsave(&HFClock, hfc_flags);
1176                 plx_count = 0;
1177                 plx_last_hc = NULL;
1178                 list_for_each_entry_safe(pos, next, &HFClist, list) {
1179                         if (test_bit(HFC_CHIP_PLXSD, &pos->chip)) {
1180                                 plx_count++;
1181                                 if (pos != hc)
1182                                         plx_last_hc = pos;
1183                         }
1184                 }
1185                 if (plx_count >= 3) {
1186                         if (debug & DEBUG_HFCMULTI_PLXSD)
1187                                 printk(KERN_DEBUG "%s: card %d is between, so "
1188                                         "we disable termination\n",
1189                                     __func__, plx_last_hc->id + 1);
1190                         spin_lock_irqsave(&plx_lock, plx_flags);
1191                         plx_acc_32 = (u_int *)(plx_last_hc->plx_membase
1192                                         + PLX_GPIOC);
1193                         pv = readl(plx_acc_32);
1194                         pv &= ~PLX_TERM_ON;
1195                         writel(pv, plx_acc_32);
1196                         spin_unlock_irqrestore(&plx_lock, plx_flags);
1197                         if (debug & DEBUG_HFCMULTI_INIT)
1198                             printk(KERN_WARNING "%s: term off: PLX_GPIO=%x\n",
1199                                         __func__, pv);
1200                 }
1201                 spin_unlock_irqrestore(&HFClock, hfc_flags);
1202                 hc->hw.r_pcm_md0 = V_F0_LEN; /* shift clock for DSP */
1203         }
1204
1205         /* we only want the real Z2 read-pointer for revision > 0 */
1206         if (!test_bit(HFC_CHIP_REVISION0, &hc->chip))
1207                 hc->hw.r_ram_sz |= V_FZ_MD;
1208
1209         /* select pcm mode */
1210         if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
1211                 if (debug & DEBUG_HFCMULTI_INIT)
1212                         printk(KERN_DEBUG "%s: setting PCM into slave mode\n",
1213                             __func__);
1214         } else
1215         if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip) && !plxsd_master) {
1216                 if (debug & DEBUG_HFCMULTI_INIT)
1217                         printk(KERN_DEBUG "%s: setting PCM into master mode\n",
1218                             __func__);
1219                 hc->hw.r_pcm_md0 |= V_PCM_MD;
1220         } else {
1221                 if (debug & DEBUG_HFCMULTI_INIT)
1222                         printk(KERN_DEBUG "%s: performing PCM auto detect\n",
1223                             __func__);
1224         }
1225
1226         /* soft reset */
1227         HFC_outb(hc, R_CTRL, hc->hw.r_ctrl);
1228         HFC_outb(hc, R_RAM_SZ, hc->hw.r_ram_sz);
1229         HFC_outb(hc, R_FIFO_MD, 0);
1230         hc->hw.r_cirm = V_SRES | V_HFCRES | V_PCMRES | V_STRES | V_RLD_EPR;
1231         HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1232         udelay(100);
1233         hc->hw.r_cirm = 0;
1234         HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1235         udelay(100);
1236         HFC_outb(hc, R_RAM_SZ, hc->hw.r_ram_sz);
1237
1238         /* Speech Design PLX bridge pcm and sync mode */
1239         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1240                 spin_lock_irqsave(&plx_lock, plx_flags);
1241                 plx_acc_32 = (u_int *)(hc->plx_membase+PLX_GPIOC);
1242                 pv = readl(plx_acc_32);
1243                 /* Connect PCM */
1244                 if (hc->hw.r_pcm_md0 & V_PCM_MD) {
1245                         pv |= PLX_MASTER_EN | PLX_SLAVE_EN_N;
1246                         pv |= PLX_SYNC_O_EN;
1247                         if (debug & DEBUG_HFCMULTI_INIT)
1248                                 printk(KERN_WARNING "%s: master: PLX_GPIO=%x\n",
1249                                         __func__, pv);
1250                 } else {
1251                         pv &= ~(PLX_MASTER_EN | PLX_SLAVE_EN_N);
1252                         pv &= ~PLX_SYNC_O_EN;
1253                         if (debug & DEBUG_HFCMULTI_INIT)
1254                                 printk(KERN_WARNING "%s: slave: PLX_GPIO=%x\n",
1255                                         __func__, pv);
1256                 }
1257                 writel(pv, plx_acc_32);
1258                 spin_unlock_irqrestore(&plx_lock, plx_flags);
1259         }
1260
1261         /* PCM setup */
1262         HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x90);
1263         if (hc->slots == 32)
1264                 HFC_outb(hc, R_PCM_MD1, 0x00);
1265         if (hc->slots == 64)
1266                 HFC_outb(hc, R_PCM_MD1, 0x10);
1267         if (hc->slots == 128)
1268                 HFC_outb(hc, R_PCM_MD1, 0x20);
1269         HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0xa0);
1270         if (test_bit(HFC_CHIP_PLXSD, &hc->chip))
1271                 HFC_outb(hc, R_PCM_MD2, V_SYNC_SRC); /* sync via SYNC_I / O */
1272         else
1273                 HFC_outb(hc, R_PCM_MD2, 0x00); /* sync from interface */
1274         HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x00);
1275         for (i = 0; i < 256; i++) {
1276                 HFC_outb_nodebug(hc, R_SLOT, i);
1277                 HFC_outb_nodebug(hc, A_SL_CFG, 0);
1278                 HFC_outb_nodebug(hc, A_CONF, 0);
1279                 hc->slot_owner[i] = -1;
1280         }
1281
1282         /* set clock speed */
1283         if (test_bit(HFC_CHIP_CLOCK2, &hc->chip)) {
1284                 if (debug & DEBUG_HFCMULTI_INIT)
1285                         printk(KERN_DEBUG
1286                             "%s: setting double clock\n", __func__);
1287                 HFC_outb(hc, R_BRG_PCM_CFG, V_PCM_CLK);
1288         }
1289
1290         /* B410P GPIO */
1291         if (test_bit(HFC_CHIP_B410P, &hc->chip)) {
1292                 printk(KERN_NOTICE "Setting GPIOs\n");
1293                 HFC_outb(hc, R_GPIO_SEL, 0x30);
1294                 HFC_outb(hc, R_GPIO_EN1, 0x3);
1295                 udelay(1000);
1296                 printk(KERN_NOTICE "calling vpm_init\n");
1297                 vpm_init(hc);
1298         }
1299
1300         /* check if R_F0_CNT counts (8 kHz frame count) */
1301         val = HFC_inb(hc, R_F0_CNTL);
1302         val += HFC_inb(hc, R_F0_CNTH) << 8;
1303         if (debug & DEBUG_HFCMULTI_INIT)
1304                 printk(KERN_DEBUG
1305                     "HFC_multi F0_CNT %ld after reset\n", val);
1306         spin_unlock_irqrestore(&hc->lock, flags);
1307         set_current_state(TASK_UNINTERRUPTIBLE);
1308         schedule_timeout((HZ/100)?:1); /* Timeout minimum 10ms */
1309         spin_lock_irqsave(&hc->lock, flags);
1310         val2 = HFC_inb(hc, R_F0_CNTL);
1311         val2 += HFC_inb(hc, R_F0_CNTH) << 8;
1312         if (debug & DEBUG_HFCMULTI_INIT)
1313                 printk(KERN_DEBUG
1314                         "HFC_multi F0_CNT %ld after 10 ms (1st try)\n",
1315                     val2);
1316         if (val2 >= val+8) { /* 1 ms */
1317                 /* it counts, so we keep the pcm mode */
1318                 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip))
1319                         printk(KERN_INFO "controller is PCM bus MASTER\n");
1320                 else
1321                 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip))
1322                         printk(KERN_INFO "controller is PCM bus SLAVE\n");
1323                 else {
1324                         test_and_set_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
1325                         printk(KERN_INFO "controller is PCM bus SLAVE "
1326                                 "(auto detected)\n");
1327                 }
1328         } else {
1329                 /* does not count */
1330                 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)) {
1331 controller_fail:
1332                         printk(KERN_ERR "HFC_multi ERROR, getting no 125us "
1333                             "pulse. Seems that controller fails.\n");
1334                         err = -EIO;
1335                         goto out;
1336                 }
1337                 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
1338                         printk(KERN_INFO "controller is PCM bus SLAVE "
1339                                 "(ignoring missing PCM clock)\n");
1340                 } else {
1341                         /* only one pcm master */
1342                         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)
1343                                 && plxsd_master) {
1344                                 printk(KERN_ERR "HFC_multi ERROR, no clock "
1345                                     "on another Speech Design card found. "
1346                                     "Please be sure to connect PCM cable.\n");
1347                                 err = -EIO;
1348                                 goto out;
1349                         }
1350                         /* retry with master clock */
1351                         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1352                                 spin_lock_irqsave(&plx_lock, plx_flags);
1353                                 plx_acc_32 = (u_int *)(hc->plx_membase +
1354                                         PLX_GPIOC);
1355                                 pv = readl(plx_acc_32);
1356                                 pv |= PLX_MASTER_EN | PLX_SLAVE_EN_N;
1357                                 pv |= PLX_SYNC_O_EN;
1358                                 writel(pv, plx_acc_32);
1359                                 spin_unlock_irqrestore(&plx_lock, plx_flags);
1360                                 if (debug & DEBUG_HFCMULTI_INIT)
1361                                     printk(KERN_WARNING "%s: master: PLX_GPIO"
1362                                         "=%x\n", __func__, pv);
1363                         }
1364                         hc->hw.r_pcm_md0 |= V_PCM_MD;
1365                         HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x00);
1366                         spin_unlock_irqrestore(&hc->lock, flags);
1367                         set_current_state(TASK_UNINTERRUPTIBLE);
1368                         schedule_timeout((HZ/100)?:1); /* Timeout min. 10ms */
1369                         spin_lock_irqsave(&hc->lock, flags);
1370                         val2 = HFC_inb(hc, R_F0_CNTL);
1371                         val2 += HFC_inb(hc, R_F0_CNTH) << 8;
1372                         if (debug & DEBUG_HFCMULTI_INIT)
1373                                 printk(KERN_DEBUG "HFC_multi F0_CNT %ld after "
1374                                         "10 ms (2nd try)\n", val2);
1375                         if (val2 >= val+8) { /* 1 ms */
1376                                 test_and_set_bit(HFC_CHIP_PCM_MASTER,
1377                                         &hc->chip);
1378                                 printk(KERN_INFO "controller is PCM bus MASTER "
1379                                         "(auto detected)\n");
1380                         } else
1381                                 goto controller_fail;
1382                 }
1383         }
1384
1385         /* Release the DSP Reset */
1386         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1387                 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip))
1388                         plxsd_master = 1;
1389                 spin_lock_irqsave(&plx_lock, plx_flags);
1390                 plx_acc_32 = (u_int *)(hc->plx_membase+PLX_GPIOC);
1391                 pv = readl(plx_acc_32);
1392                 pv |=  PLX_DSP_RES_N;
1393                 writel(pv, plx_acc_32);
1394                 spin_unlock_irqrestore(&plx_lock, plx_flags);
1395                 if (debug & DEBUG_HFCMULTI_INIT)
1396                         printk(KERN_WARNING "%s: reset off: PLX_GPIO=%x\n",
1397                                 __func__, pv);
1398         }
1399
1400         /* pcm id */
1401         if (hc->pcm)
1402                 printk(KERN_INFO "controller has given PCM BUS ID %d\n",
1403                         hc->pcm);
1404         else {
1405                 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)
1406                  || test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1407                         PCM_cnt++; /* SD has proprietary bridging */
1408                 }
1409                 hc->pcm = PCM_cnt;
1410                 printk(KERN_INFO "controller has PCM BUS ID %d "
1411                         "(auto selected)\n", hc->pcm);
1412         }
1413
1414         /* set up timer */
1415         HFC_outb(hc, R_TI_WD, poll_timer);
1416         hc->hw.r_irqmsk_misc |= V_TI_IRQMSK;
1417
1418         /*
1419          * set up 125us interrupt, only if function pointer is available
1420          * and module parameter timer is set
1421          */
1422         if (timer && hfc_interrupt && register_interrupt) {
1423                 /* only one chip should use this interrupt */
1424                 timer = 0;
1425                 interrupt_registered = 1;
1426                 hc->hw.r_irqmsk_misc |= V_PROC_IRQMSK;
1427                 /* deactivate other interrupts in ztdummy */
1428                 register_interrupt();
1429         }
1430
1431         /* set E1 state machine IRQ */
1432         if (hc->type == 1)
1433                 hc->hw.r_irqmsk_misc |= V_STA_IRQMSK;
1434
1435         /* set DTMF detection */
1436         if (test_bit(HFC_CHIP_DTMF, &hc->chip)) {
1437                 if (debug & DEBUG_HFCMULTI_INIT)
1438                         printk(KERN_DEBUG "%s: enabling DTMF detection "
1439                             "for all B-channel\n", __func__);
1440                 hc->hw.r_dtmf = V_DTMF_EN | V_DTMF_STOP;
1441                 if (test_bit(HFC_CHIP_ULAW, &hc->chip))
1442                         hc->hw.r_dtmf |= V_ULAW_SEL;
1443                 HFC_outb(hc, R_DTMF_N, 102 - 1);
1444                 hc->hw.r_irqmsk_misc |= V_DTMF_IRQMSK;
1445         }
1446
1447         /* conference engine */
1448         if (test_bit(HFC_CHIP_ULAW, &hc->chip))
1449                 r_conf_en = V_CONF_EN | V_ULAW;
1450         else
1451                 r_conf_en = V_CONF_EN;
1452         HFC_outb(hc, R_CONF_EN, r_conf_en);
1453
1454         /* setting leds */
1455         switch (hc->leds) {
1456         case 1: /* HFC-E1 OEM */
1457                 if (test_bit(HFC_CHIP_WATCHDOG, &hc->chip))
1458                         HFC_outb(hc, R_GPIO_SEL, 0x32);
1459                 else
1460                         HFC_outb(hc, R_GPIO_SEL, 0x30);
1461
1462                 HFC_outb(hc, R_GPIO_EN1, 0x0f);
1463                 HFC_outb(hc, R_GPIO_OUT1, 0x00);
1464
1465                 HFC_outb(hc, R_GPIO_EN0, V_GPIO_EN2 | V_GPIO_EN3);
1466                 break;
1467
1468         case 2: /* HFC-4S OEM */
1469         case 3:
1470                 HFC_outb(hc, R_GPIO_SEL, 0xf0);
1471                 HFC_outb(hc, R_GPIO_EN1, 0xff);
1472                 HFC_outb(hc, R_GPIO_OUT1, 0x00);
1473                 break;
1474         }
1475
1476         /* set master clock */
1477         if (hc->masterclk >= 0) {
1478                 if (debug & DEBUG_HFCMULTI_INIT)
1479                         printk(KERN_DEBUG "%s: setting ST master clock "
1480                             "to port %d (0..%d)\n",
1481                             __func__, hc->masterclk, hc->ports-1);
1482                 hc->hw.r_st_sync = hc->masterclk | V_AUTO_SYNC;
1483                 HFC_outb(hc, R_ST_SYNC, hc->hw.r_st_sync);
1484         }
1485
1486         /* setting misc irq */
1487         HFC_outb(hc, R_IRQMSK_MISC, hc->hw.r_irqmsk_misc);
1488         if (debug & DEBUG_HFCMULTI_INIT)
1489                 printk(KERN_DEBUG "r_irqmsk_misc.2: 0x%x\n",
1490                     hc->hw.r_irqmsk_misc);
1491
1492         /* RAM access test */
1493         HFC_outb(hc, R_RAM_ADDR0, 0);
1494         HFC_outb(hc, R_RAM_ADDR1, 0);
1495         HFC_outb(hc, R_RAM_ADDR2, 0);
1496         for (i = 0; i < 256; i++) {
1497                 HFC_outb_nodebug(hc, R_RAM_ADDR0, i);
1498                 HFC_outb_nodebug(hc, R_RAM_DATA, ((i*3)&0xff));
1499         }
1500         for (i = 0; i < 256; i++) {
1501                 HFC_outb_nodebug(hc, R_RAM_ADDR0, i);
1502                 HFC_inb_nodebug(hc, R_RAM_DATA);
1503                 rval = HFC_inb_nodebug(hc, R_INT_DATA);
1504                 if (rval != ((i * 3) & 0xff)) {
1505                         printk(KERN_DEBUG
1506                             "addr:%x val:%x should:%x\n", i, rval,
1507                             (i * 3) & 0xff);
1508                         err++;
1509                 }
1510         }
1511         if (err) {
1512                 printk(KERN_DEBUG "aborting - %d RAM access errors\n", err);
1513                 err = -EIO;
1514                 goto out;
1515         }
1516
1517         if (debug & DEBUG_HFCMULTI_INIT)
1518                 printk(KERN_DEBUG "%s: done\n", __func__);
1519 out:
1520         spin_unlock_irqrestore(&hc->lock, flags);
1521         return err;
1522 }
1523
1524
1525 /*
1526  * control the watchdog
1527  */
1528 static void
1529 hfcmulti_watchdog(struct hfc_multi *hc)
1530 {
1531         hc->wdcount++;
1532
1533         if (hc->wdcount > 10) {
1534                 hc->wdcount = 0;
1535                 hc->wdbyte = hc->wdbyte == V_GPIO_OUT2 ?
1536                     V_GPIO_OUT3 : V_GPIO_OUT2;
1537
1538         /* printk("Sending Watchdog Kill %x\n",hc->wdbyte); */
1539                 HFC_outb(hc, R_GPIO_EN0, V_GPIO_EN2 | V_GPIO_EN3);
1540                 HFC_outb(hc, R_GPIO_OUT0, hc->wdbyte);
1541         }
1542 }
1543
1544
1545
1546 /*
1547  * output leds
1548  */
1549 static void
1550 hfcmulti_leds(struct hfc_multi *hc)
1551 {
1552         unsigned long lled;
1553         unsigned long leddw;
1554         int i, state, active, leds;
1555         struct dchannel *dch;
1556         int led[4];
1557
1558         hc->ledcount += poll;
1559         if (hc->ledcount > 4096) {
1560                 hc->ledcount -= 4096;
1561                 hc->ledstate = 0xAFFEAFFE;
1562         }
1563
1564         switch (hc->leds) {
1565         case 1: /* HFC-E1 OEM */
1566                 /* 2 red blinking: NT mode deactivate
1567                  * 2 red steady:   TE mode deactivate
1568                  * left green:     L1 active
1569                  * left red:       frame sync, but no L1
1570                  * right green:    L2 active
1571                  */
1572                 if (hc->chan[hc->dslot].sync != 2) { /* no frame sync */
1573                         if (hc->chan[hc->dslot].dch->dev.D.protocol
1574                                 != ISDN_P_NT_E1) {
1575                                 led[0] = 1;
1576                                 led[1] = 1;
1577                         } else if (hc->ledcount>>11) {
1578                                 led[0] = 1;
1579                                 led[1] = 1;
1580                         } else {
1581                                 led[0] = 0;
1582                                 led[1] = 0;
1583                         }
1584                         led[2] = 0;
1585                         led[3] = 0;
1586                 } else { /* with frame sync */
1587                         /* TODO make it work */
1588                         led[0] = 0;
1589                         led[1] = 0;
1590                         led[2] = 0;
1591                         led[3] = 1;
1592                 }
1593                 leds = (led[0] | (led[1]<<2) | (led[2]<<1) | (led[3]<<3))^0xF;
1594                         /* leds are inverted */
1595                 if (leds != (int)hc->ledstate) {
1596                         HFC_outb_nodebug(hc, R_GPIO_OUT1, leds);
1597                         hc->ledstate = leds;
1598                 }
1599                 break;
1600
1601         case 2: /* HFC-4S OEM */
1602                 /* red blinking = PH_DEACTIVATE NT Mode
1603                  * red steady   = PH_DEACTIVATE TE Mode
1604                  * green steady = PH_ACTIVATE
1605                  */
1606                 for (i = 0; i < 4; i++) {
1607                         state = 0;
1608                         active = -1;
1609                         dch = hc->chan[(i << 2) | 2].dch;
1610                         if (dch) {
1611                                 state = dch->state;
1612                                 if (dch->dev.D.protocol == ISDN_P_NT_S0)
1613                                         active = 3;
1614                                 else
1615                                         active = 7;
1616                         }
1617                         if (state) {
1618                                 if (state == active) {
1619                                         led[i] = 1; /* led green */
1620                                 } else
1621                                         if (dch->dev.D.protocol == ISDN_P_TE_S0)
1622                                                 /* TE mode: led red */
1623                                                 led[i] = 2;
1624                                         else
1625                                                 if (hc->ledcount>>11)
1626                                                         /* led red */
1627                                                         led[i] = 2;
1628                                                 else
1629                                                         /* led off */
1630                                                         led[i] = 0;
1631                         } else
1632                                 led[i] = 0; /* led off */
1633                 }
1634                 if (test_bit(HFC_CHIP_B410P, &hc->chip)) {
1635                         leds = 0;
1636                         for (i = 0; i < 4; i++) {
1637                                 if (led[i] == 1) {
1638                                         /*green*/
1639                                         leds |= (0x2 << (i * 2));
1640                                 } else if (led[i] == 2) {
1641                                         /*red*/
1642                                         leds |= (0x1 << (i * 2));
1643                                 }
1644                         }
1645                         if (leds != (int)hc->ledstate) {
1646                                 vpm_out(hc, 0, 0x1a8 + 3, leds);
1647                                 hc->ledstate = leds;
1648                         }
1649                 } else {
1650                         leds = ((led[3] > 0) << 0) | ((led[1] > 0) << 1) |
1651                             ((led[0] > 0) << 2) | ((led[2] > 0) << 3) |
1652                             ((led[3] & 1) << 4) | ((led[1] & 1) << 5) |
1653                             ((led[0] & 1) << 6) | ((led[2] & 1) << 7);
1654                         if (leds != (int)hc->ledstate) {
1655                                 HFC_outb_nodebug(hc, R_GPIO_EN1, leds & 0x0F);
1656                                 HFC_outb_nodebug(hc, R_GPIO_OUT1, leds >> 4);
1657                                 hc->ledstate = leds;
1658                         }
1659                 }
1660                 break;
1661
1662         case 3: /* HFC 1S/2S Beronet */
1663                 /* red blinking = PH_DEACTIVATE NT Mode
1664                  * red steady   = PH_DEACTIVATE TE Mode
1665                  * green steady = PH_ACTIVATE
1666                  */
1667                 for (i = 0; i < 2; i++) {
1668                         state = 0;
1669                         active = -1;
1670                         dch = hc->chan[(i << 2) | 2].dch;
1671                         if (dch) {
1672                                 state = dch->state;
1673                                 if (dch->dev.D.protocol == ISDN_P_NT_S0)
1674                                         active = 3;
1675                                 else
1676                                         active = 7;
1677                         }
1678                         if (state) {
1679                                 if (state == active) {
1680                                         led[i] = 1; /* led green */
1681                                 } else
1682                                         if (dch->dev.D.protocol == ISDN_P_TE_S0)
1683                                                 /* TE mode: led red */
1684                                                 led[i] = 2;
1685                                         else
1686                                                 if (hc->ledcount >> 11)
1687                                                         /* led red */
1688                                                         led[i] = 2;
1689                                                 else
1690                                                         /* led off */
1691                                                         led[i] = 0;
1692                         } else
1693                                 led[i] = 0; /* led off */
1694                 }
1695
1696
1697                 leds = (led[0] > 0) | ((led[1] > 0)<<1) | ((led[0]&1)<<2)
1698                         | ((led[1]&1)<<3);
1699                 if (leds != (int)hc->ledstate) {
1700                         HFC_outb_nodebug(hc, R_GPIO_EN1,
1701                             ((led[0] > 0) << 2) | ((led[1] > 0) << 3));
1702                         HFC_outb_nodebug(hc, R_GPIO_OUT1,
1703                             ((led[0] & 1) << 2) | ((led[1] & 1) << 3));
1704                         hc->ledstate = leds;
1705                 }
1706                 break;
1707         case 8: /* HFC 8S+ Beronet */
1708                 lled = 0;
1709
1710                 for (i = 0; i < 8; i++) {
1711                         state = 0;
1712                         active = -1;
1713                         dch = hc->chan[(i << 2) | 2].dch;
1714                         if (dch) {
1715                                 state = dch->state;
1716                                 if (dch->dev.D.protocol == ISDN_P_NT_S0)
1717                                         active = 3;
1718                                 else
1719                                         active = 7;
1720                         }
1721                         if (state) {
1722                                 if (state == active) {
1723                                         lled |= 0 << i;
1724                                 } else
1725                                         if (hc->ledcount >> 11)
1726                                                 lled |= 0 << i;
1727                                         else
1728                                                 lled |= 1 << i;
1729                         } else
1730                                 lled |= 1 << i;
1731                 }
1732                 leddw = lled << 24 | lled << 16 | lled << 8 | lled;
1733                 if (leddw != hc->ledstate) {
1734                         /* HFC_outb(hc, R_BRG_PCM_CFG, 1);
1735                         HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x3); */
1736                         /* was _io before */
1737                         HFC_outb_nodebug(hc, R_BRG_PCM_CFG, 1 | V_PCM_CLK);
1738                         outw(0x4000, hc->pci_iobase + 4);
1739                         outl(leddw, hc->pci_iobase);
1740                         HFC_outb_nodebug(hc, R_BRG_PCM_CFG, V_PCM_CLK);
1741                         hc->ledstate = leddw;
1742                 }
1743                 break;
1744         }
1745 }
1746 /*
1747  * read dtmf coefficients
1748  */
1749
1750 static void
1751 hfcmulti_dtmf(struct hfc_multi *hc)
1752 {
1753         s32             *coeff;
1754         u_int           mantissa;
1755         int             co, ch;
1756         struct bchannel *bch = NULL;
1757         u8              exponent;
1758         int             dtmf = 0;
1759         int             addr;
1760         u16             w_float;
1761         struct sk_buff  *skb;
1762         struct mISDNhead *hh;
1763
1764         if (debug & DEBUG_HFCMULTI_DTMF)
1765                 printk(KERN_DEBUG "%s: dtmf detection irq\n", __func__);
1766         for (ch = 0; ch <= 31; ch++) {
1767                 /* only process enabled B-channels */
1768                 bch = hc->chan[ch].bch;
1769                 if (!bch)
1770                         continue;
1771                 if (!hc->created[hc->chan[ch].port])
1772                         continue;
1773                 if (!test_bit(FLG_TRANSPARENT, &bch->Flags))
1774                         continue;
1775                 if (debug & DEBUG_HFCMULTI_DTMF)
1776                         printk(KERN_DEBUG "%s: dtmf channel %d:",
1777                                 __func__, ch);
1778                 coeff = &(hc->chan[ch].coeff[hc->chan[ch].coeff_count * 16]);
1779                 dtmf = 1;
1780                 for (co = 0; co < 8; co++) {
1781                         /* read W(n-1) coefficient */
1782                         addr = hc->DTMFbase + ((co<<7) | (ch<<2));
1783                         HFC_outb_nodebug(hc, R_RAM_ADDR0, addr);
1784                         HFC_outb_nodebug(hc, R_RAM_ADDR1, addr>>8);
1785                         HFC_outb_nodebug(hc, R_RAM_ADDR2, (addr>>16)
1786                                 | V_ADDR_INC);
1787                         w_float = HFC_inb_nodebug(hc, R_RAM_DATA);
1788                         w_float |= (HFC_inb_nodebug(hc, R_RAM_DATA) << 8);
1789                         if (debug & DEBUG_HFCMULTI_DTMF)
1790                                 printk(" %04x", w_float);
1791
1792                         /* decode float (see chip doc) */
1793                         mantissa = w_float & 0x0fff;
1794                         if (w_float & 0x8000)
1795                                 mantissa |= 0xfffff000;
1796                         exponent = (w_float>>12) & 0x7;
1797                         if (exponent) {
1798                                 mantissa ^= 0x1000;
1799                                 mantissa <<= (exponent-1);
1800                         }
1801
1802                         /* store coefficient */
1803                         coeff[co<<1] = mantissa;
1804
1805                         /* read W(n) coefficient */
1806                         w_float = HFC_inb_nodebug(hc, R_RAM_DATA);
1807                         w_float |= (HFC_inb_nodebug(hc, R_RAM_DATA) << 8);
1808                         if (debug & DEBUG_HFCMULTI_DTMF)
1809                                 printk(" %04x", w_float);
1810
1811                         /* decode float (see chip doc) */
1812                         mantissa = w_float & 0x0fff;
1813                         if (w_float & 0x8000)
1814                                 mantissa |= 0xfffff000;
1815                         exponent = (w_float>>12) & 0x7;
1816                         if (exponent) {
1817                                 mantissa ^= 0x1000;
1818                                 mantissa <<= (exponent-1);
1819                         }
1820
1821                         /* store coefficient */
1822                         coeff[(co<<1)|1] = mantissa;
1823                 }
1824                 if (debug & DEBUG_HFCMULTI_DTMF)
1825                         printk("%s: DTMF ready %08x %08x %08x %08x "
1826                             "%08x %08x %08x %08x\n", __func__,
1827                             coeff[0], coeff[1], coeff[2], coeff[3],
1828                             coeff[4], coeff[5], coeff[6], coeff[7]);
1829                 hc->chan[ch].coeff_count++;
1830                 if (hc->chan[ch].coeff_count == 8) {
1831                         hc->chan[ch].coeff_count = 0;
1832                         skb = mI_alloc_skb(512, GFP_ATOMIC);
1833                         if (!skb) {
1834                                 printk(KERN_WARNING "%s: No memory for skb\n",
1835                                     __func__);
1836                                 continue;
1837                         }
1838                         hh = mISDN_HEAD_P(skb);
1839                         hh->prim = PH_CONTROL_IND;
1840                         hh->id = DTMF_HFC_COEF;
1841                         memcpy(skb_put(skb, 512), hc->chan[ch].coeff, 512);
1842                         recv_Bchannel_skb(bch, skb);
1843                 }
1844         }
1845
1846         /* restart DTMF processing */
1847         hc->dtmf = dtmf;
1848         if (dtmf)
1849                 HFC_outb_nodebug(hc, R_DTMF, hc->hw.r_dtmf | V_RST_DTMF);
1850 }
1851
1852
1853 /*
1854  * fill fifo as much as possible
1855  */
1856
1857 static void
1858 hfcmulti_tx(struct hfc_multi *hc, int ch)
1859 {
1860         int i, ii, temp, len = 0;
1861         int Zspace, z1, z2; /* must be int for calculation */
1862         int Fspace, f1, f2;
1863         u_char *d;
1864         int *txpending, slot_tx;
1865         struct  bchannel *bch;
1866         struct  dchannel *dch;
1867         struct  sk_buff **sp = NULL;
1868         int *idxp;
1869
1870         bch = hc->chan[ch].bch;
1871         dch = hc->chan[ch].dch;
1872         if ((!dch) && (!bch))
1873                 return;
1874
1875         txpending = &hc->chan[ch].txpending;
1876         slot_tx = hc->chan[ch].slot_tx;
1877         if (dch) {
1878                 if (!test_bit(FLG_ACTIVE, &dch->Flags))
1879                         return;
1880                 sp = &dch->tx_skb;
1881                 idxp = &dch->tx_idx;
1882         } else {
1883                 if (!test_bit(FLG_ACTIVE, &bch->Flags))
1884                         return;
1885                 sp = &bch->tx_skb;
1886                 idxp = &bch->tx_idx;
1887         }
1888         if (*sp)
1889                 len = (*sp)->len;
1890
1891         if ((!len) && *txpending != 1)
1892                 return; /* no data */
1893
1894         if (test_bit(HFC_CHIP_B410P, &hc->chip) &&
1895             (hc->chan[ch].protocol == ISDN_P_B_RAW) &&
1896             (hc->chan[ch].slot_rx < 0) &&
1897             (hc->chan[ch].slot_tx < 0))
1898                 HFC_outb_nodebug(hc, R_FIFO, 0x20 | (ch << 1));
1899         else
1900                 HFC_outb_nodebug(hc, R_FIFO, ch << 1);
1901         HFC_wait_nodebug(hc);
1902
1903         if (*txpending == 2) {
1904                 /* reset fifo */
1905                 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F);
1906                 HFC_wait_nodebug(hc);
1907                 HFC_outb(hc, A_SUBCH_CFG, 0);
1908                 *txpending = 1;
1909         }
1910 next_frame:
1911         if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
1912                 f1 = HFC_inb_nodebug(hc, A_F1);
1913                 f2 = HFC_inb_nodebug(hc, A_F2);
1914                 while (f2 != (temp = HFC_inb_nodebug(hc, A_F2))) {
1915                         if (debug & DEBUG_HFCMULTI_FIFO)
1916                                 printk(KERN_DEBUG
1917                                     "%s(card %d): reread f2 because %d!=%d\n",
1918                                     __func__, hc->id + 1, temp, f2);
1919                         f2 = temp; /* repeat until F2 is equal */
1920                 }
1921                 Fspace = f2 - f1 - 1;
1922                 if (Fspace < 0)
1923                         Fspace += hc->Flen;
1924                 /*
1925                  * Old FIFO handling doesn't give us the current Z2 read
1926                  * pointer, so we cannot send the next frame before the fifo
1927                  * is empty. It makes no difference except for a slightly
1928                  * lower performance.
1929                  */
1930                 if (test_bit(HFC_CHIP_REVISION0, &hc->chip)) {
1931                         if (f1 != f2)
1932                                 Fspace = 0;
1933                         else
1934                                 Fspace = 1;
1935                 }
1936                 /* one frame only for ST D-channels, to allow resending */
1937                 if (hc->type != 1 && dch) {
1938                         if (f1 != f2)
1939                                 Fspace = 0;
1940                 }
1941                 /* F-counter full condition */
1942                 if (Fspace == 0)
1943                         return;
1944         }
1945         z1 = HFC_inw_nodebug(hc, A_Z1) - hc->Zmin;
1946         z2 = HFC_inw_nodebug(hc, A_Z2) - hc->Zmin;
1947         while (z2 != (temp = (HFC_inw_nodebug(hc, A_Z2) - hc->Zmin))) {
1948                 if (debug & DEBUG_HFCMULTI_FIFO)
1949                         printk(KERN_DEBUG "%s(card %d): reread z2 because "
1950                                 "%d!=%d\n", __func__, hc->id + 1, temp, z2);
1951                 z2 = temp; /* repeat unti Z2 is equal */
1952         }
1953         Zspace = z2 - z1;
1954         if (Zspace <= 0)
1955                 Zspace += hc->Zlen;
1956         Zspace -= 4; /* keep not too full, so pointers will not overrun */
1957         /* fill transparent data only to maxinum transparent load (minus 4) */
1958         if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags))
1959                 Zspace = Zspace - hc->Zlen + hc->max_trans;
1960         if (Zspace <= 0) /* no space of 4 bytes */
1961                 return;
1962
1963         /* if no data */
1964         if (!len) {
1965                 if (z1 == z2) { /* empty */
1966                         /* if done with FIFO audio data during PCM connection */
1967                         if (bch && (!test_bit(FLG_HDLC, &bch->Flags)) &&
1968                             *txpending && slot_tx >= 0) {
1969                                 if (debug & DEBUG_HFCMULTI_MODE)
1970                                         printk(KERN_DEBUG
1971                                             "%s: reconnecting PCM due to no "
1972                                             "more FIFO data: channel %d "
1973                                             "slot_tx %d\n",
1974                                             __func__, ch, slot_tx);
1975                                 /* connect slot */
1976                                 HFC_outb(hc, A_CON_HDLC, 0xc0 | 0x00 |
1977                                     V_HDLC_TRP | V_IFF);
1978                                 HFC_outb_nodebug(hc, R_FIFO, ch<<1 | 1);
1979                                 HFC_wait_nodebug(hc);
1980                                 HFC_outb(hc, A_CON_HDLC, 0xc0 | 0x00 |
1981                                     V_HDLC_TRP | V_IFF);
1982                                 HFC_outb_nodebug(hc, R_FIFO, ch<<1);
1983                                 HFC_wait_nodebug(hc);
1984                         }
1985                         *txpending = 0;
1986                 }
1987                 return; /* no data */
1988         }
1989
1990         /* if audio data and connected slot */
1991         if (bch && (!test_bit(FLG_HDLC, &bch->Flags)) && (!*txpending)
1992                 && slot_tx >= 0) {
1993                 if (debug & DEBUG_HFCMULTI_MODE)
1994                         printk(KERN_DEBUG "%s: disconnecting PCM due to "
1995                             "FIFO data: channel %d slot_tx %d\n",
1996                             __func__, ch, slot_tx);
1997                 /* disconnect slot */
1998                 HFC_outb(hc, A_CON_HDLC, 0x80 | 0x00 | V_HDLC_TRP | V_IFF);
1999                 HFC_outb_nodebug(hc, R_FIFO, ch<<1 | 1);
2000                 HFC_wait_nodebug(hc);
2001                 HFC_outb(hc, A_CON_HDLC, 0x80 | 0x00 | V_HDLC_TRP | V_IFF);
2002                 HFC_outb_nodebug(hc, R_FIFO, ch<<1);
2003                 HFC_wait_nodebug(hc);
2004         }
2005         *txpending = 1;
2006
2007         /* show activity */
2008         hc->activity[hc->chan[ch].port] = 1;
2009
2010         /* fill fifo to what we have left */
2011         ii = len;
2012         if (dch || test_bit(FLG_HDLC, &bch->Flags))
2013                 temp = 1;
2014         else
2015                 temp = 0;
2016         i = *idxp;
2017         d = (*sp)->data + i;
2018         if (ii - i > Zspace)
2019                 ii = Zspace + i;
2020         if (debug & DEBUG_HFCMULTI_FIFO)
2021                 printk(KERN_DEBUG "%s(card %d): fifo(%d) has %d bytes space "
2022                     "left (z1=%04x, z2=%04x) sending %d of %d bytes %s\n",
2023                         __func__, hc->id + 1, ch, Zspace, z1, z2, ii-i, len-i,
2024                         temp ? "HDLC":"TRANS");
2025
2026
2027         /* Have to prep the audio data */
2028         hc->write_fifo(hc, d, ii - i);
2029         *idxp = ii;
2030
2031         /* if not all data has been written */
2032         if (ii != len) {
2033                 /* NOTE: fifo is started by the calling function */
2034                 return;
2035         }
2036
2037         /* if all data has been written, terminate frame */
2038         if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
2039                 /* increment f-counter */
2040                 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_INC_F);
2041                 HFC_wait_nodebug(hc);
2042         }
2043
2044         /* send confirm, since get_net_bframe will not do it with trans */
2045         if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags))
2046                 confirm_Bsend(bch);
2047
2048         /* check for next frame */
2049         dev_kfree_skb(*sp);
2050         if (bch && get_next_bframe(bch)) { /* hdlc is confirmed here */
2051                 len = (*sp)->len;
2052                 goto next_frame;
2053         }
2054         if (dch && get_next_dframe(dch)) {
2055                 len = (*sp)->len;
2056                 goto next_frame;
2057         }
2058
2059         /*
2060          * now we have no more data, so in case of transparent,
2061          * we set the last byte in fifo to 'silence' in case we will get
2062          * no more data at all. this prevents sending an undefined value.
2063          */
2064         if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags))
2065                 HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, silence);
2066 }
2067
2068
2069 /* NOTE: only called if E1 card is in active state */
2070 static void
2071 hfcmulti_rx(struct hfc_multi *hc, int ch)
2072 {
2073         int temp;
2074         int Zsize, z1, z2 = 0; /* = 0, to make GCC happy */
2075         int f1 = 0, f2 = 0; /* = 0, to make GCC happy */
2076         int again = 0;
2077         struct  bchannel *bch;
2078         struct  dchannel *dch;
2079         struct sk_buff  *skb, **sp = NULL;
2080         int     maxlen;
2081
2082         bch = hc->chan[ch].bch;
2083         dch = hc->chan[ch].dch;
2084         if ((!dch) && (!bch))
2085                 return;
2086         if (dch) {
2087                 if (!test_bit(FLG_ACTIVE, &dch->Flags))
2088                         return;
2089                 sp = &dch->rx_skb;
2090                 maxlen = dch->maxlen;
2091         } else {
2092                 if (!test_bit(FLG_ACTIVE, &bch->Flags))
2093                         return;
2094                 sp = &bch->rx_skb;
2095                 maxlen = bch->maxlen;
2096         }
2097 next_frame:
2098         /* on first AND before getting next valid frame, R_FIFO must be written
2099            to. */
2100         if (test_bit(HFC_CHIP_B410P, &hc->chip) &&
2101             (hc->chan[ch].protocol == ISDN_P_B_RAW) &&
2102             (hc->chan[ch].slot_rx < 0) &&
2103             (hc->chan[ch].slot_tx < 0))
2104                 HFC_outb_nodebug(hc, R_FIFO, 0x20 | (ch<<1) | 1);
2105         else
2106                 HFC_outb_nodebug(hc, R_FIFO, (ch<<1)|1);
2107         HFC_wait_nodebug(hc);
2108
2109         /* ignore if rx is off BUT change fifo (above) to start pending TX */
2110         if (hc->chan[ch].rx_off)
2111                 return;
2112
2113         if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
2114                 f1 = HFC_inb_nodebug(hc, A_F1);
2115                 while (f1 != (temp = HFC_inb_nodebug(hc, A_F1))) {
2116                         if (debug & DEBUG_HFCMULTI_FIFO)
2117                                 printk(KERN_DEBUG
2118                                     "%s(card %d): reread f1 because %d!=%d\n",
2119                                     __func__, hc->id + 1, temp, f1);
2120                         f1 = temp; /* repeat until F1 is equal */
2121                 }
2122                 f2 = HFC_inb_nodebug(hc, A_F2);
2123         }
2124         z1 = HFC_inw_nodebug(hc, A_Z1) - hc->Zmin;
2125         while (z1 != (temp = (HFC_inw_nodebug(hc, A_Z1) - hc->Zmin))) {
2126                 if (debug & DEBUG_HFCMULTI_FIFO)
2127                         printk(KERN_DEBUG "%s(card %d): reread z2 because "
2128                                 "%d!=%d\n", __func__, hc->id + 1, temp, z2);
2129                 z1 = temp; /* repeat until Z1 is equal */
2130         }
2131         z2 = HFC_inw_nodebug(hc, A_Z2) - hc->Zmin;
2132         Zsize = z1 - z2;
2133         if ((dch || test_bit(FLG_HDLC, &bch->Flags)) && f1 != f2)
2134                 /* complete hdlc frame */
2135                 Zsize++;
2136         if (Zsize < 0)
2137                 Zsize += hc->Zlen;
2138         /* if buffer is empty */
2139         if (Zsize <= 0)
2140                 return;
2141
2142         if (*sp == NULL) {
2143                 *sp = mI_alloc_skb(maxlen + 3, GFP_ATOMIC);
2144                 if (*sp == NULL) {
2145                         printk(KERN_DEBUG "%s: No mem for rx_skb\n",
2146                             __func__);
2147                         return;
2148                 }
2149         }
2150         /* show activity */
2151         hc->activity[hc->chan[ch].port] = 1;
2152
2153         /* empty fifo with what we have */
2154         if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
2155                 if (debug & DEBUG_HFCMULTI_FIFO)
2156                         printk(KERN_DEBUG "%s(card %d): fifo(%d) reading %d "
2157                             "bytes (z1=%04x, z2=%04x) HDLC %s (f1=%d, f2=%d) "
2158                             "got=%d (again %d)\n", __func__, hc->id + 1, ch,
2159                             Zsize, z1, z2, (f1 == f2) ? "fragment" : "COMPLETE",
2160                             f1, f2, Zsize + (*sp)->len, again);
2161                 /* HDLC */
2162                 if ((Zsize + (*sp)->len) > (maxlen + 3)) {
2163                         if (debug & DEBUG_HFCMULTI_FIFO)
2164                                 printk(KERN_DEBUG
2165                                     "%s(card %d): hdlc-frame too large.\n",
2166                                     __func__, hc->id + 1);
2167                         skb_trim(*sp, 0);
2168                         HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F);
2169                         HFC_wait_nodebug(hc);
2170                         return;
2171                 }
2172
2173                 hc->read_fifo(hc, skb_put(*sp, Zsize), Zsize);
2174
2175                 if (f1 != f2) {
2176                         /* increment Z2,F2-counter */
2177                         HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_INC_F);
2178                         HFC_wait_nodebug(hc);
2179                         /* check size */
2180                         if ((*sp)->len < 4) {
2181                                 if (debug & DEBUG_HFCMULTI_FIFO)
2182                                         printk(KERN_DEBUG
2183                                             "%s(card %d): Frame below minimum "
2184                                             "size\n", __func__, hc->id + 1);
2185                                 skb_trim(*sp, 0);
2186                                 goto next_frame;
2187                         }
2188                         /* there is at least one complete frame, check crc */
2189                         if ((*sp)->data[(*sp)->len - 1]) {
2190                                 if (debug & DEBUG_HFCMULTI_CRC)
2191                                         printk(KERN_DEBUG
2192                                             "%s: CRC-error\n", __func__);
2193                                 skb_trim(*sp, 0);
2194                                 goto next_frame;
2195                         }
2196                         skb_trim(*sp, (*sp)->len - 3);
2197                         if ((*sp)->len < MISDN_COPY_SIZE) {
2198                                 skb = *sp;
2199                                 *sp = mI_alloc_skb(skb->len, GFP_ATOMIC);
2200                                 if (*sp) {
2201                                         memcpy(skb_put(*sp, skb->len),
2202                                             skb->data, skb->len);
2203                                         skb_trim(skb, 0);
2204                                 } else {
2205                                         printk(KERN_DEBUG "%s: No mem\n",
2206                                             __func__);
2207                                         *sp = skb;
2208                                         skb = NULL;
2209                                 }
2210                         } else {
2211                                 skb = NULL;
2212                         }
2213                         if (debug & DEBUG_HFCMULTI_FIFO) {
2214                                 printk(KERN_DEBUG "%s(card %d):",
2215                                         __func__, hc->id + 1);
2216                                 temp = 0;
2217                                 while (temp < (*sp)->len)
2218                                         printk(" %02x", (*sp)->data[temp++]);
2219                                 printk("\n");
2220                         }
2221                         if (dch)
2222                                 recv_Dchannel(dch);
2223                         else
2224                                 recv_Bchannel(bch);
2225                         *sp = skb;
2226                         again++;
2227                         goto next_frame;
2228                 }
2229                 /* there is an incomplete frame */
2230         } else {
2231                 /* transparent */
2232                 if (Zsize > skb_tailroom(*sp))
2233                         Zsize = skb_tailroom(*sp);
2234                 hc->read_fifo(hc, skb_put(*sp, Zsize), Zsize);
2235                 if (((*sp)->len) < MISDN_COPY_SIZE) {
2236                         skb = *sp;
2237                         *sp = mI_alloc_skb(skb->len, GFP_ATOMIC);
2238                         if (*sp) {
2239                                 memcpy(skb_put(*sp, skb->len),
2240                                     skb->data, skb->len);
2241                                 skb_trim(skb, 0);
2242                         } else {
2243                                 printk(KERN_DEBUG "%s: No mem\n", __func__);
2244                                 *sp = skb;
2245                                 skb = NULL;
2246                         }
2247                 } else {
2248                         skb = NULL;
2249                 }
2250                 if (debug & DEBUG_HFCMULTI_FIFO)
2251                         printk(KERN_DEBUG
2252                             "%s(card %d): fifo(%d) reading %d bytes "
2253                             "(z1=%04x, z2=%04x) TRANS\n",
2254                                 __func__, hc->id + 1, ch, Zsize, z1, z2);
2255                 /* only bch is transparent */
2256                 recv_Bchannel(bch);
2257                 *sp = skb;
2258         }
2259 }
2260
2261
2262 /*
2263  * Interrupt handler
2264  */
2265 static void
2266 signal_state_up(struct dchannel *dch, int info, char *msg)
2267 {
2268         struct sk_buff  *skb;
2269         int             id, data = info;
2270
2271         if (debug & DEBUG_HFCMULTI_STATE)
2272                 printk(KERN_DEBUG "%s: %s\n", __func__, msg);
2273
2274         id = TEI_SAPI | (GROUP_TEI << 8); /* manager address */
2275
2276         skb = _alloc_mISDN_skb(MPH_INFORMATION_IND, id, sizeof(data), &data,
2277                 GFP_ATOMIC);
2278         if (!skb)
2279                 return;
2280         recv_Dchannel_skb(dch, skb);
2281 }
2282
2283 static inline void
2284 handle_timer_irq(struct hfc_multi *hc)
2285 {
2286         int             ch, temp;
2287         struct dchannel *dch;
2288         u_long          flags;
2289
2290         /* process queued resync jobs */
2291         if (hc->e1_resync) {
2292                 /* lock, so e1_resync gets not changed */
2293                 spin_lock_irqsave(&HFClock, flags);
2294                 if (hc->e1_resync & 1) {
2295                         if (debug & DEBUG_HFCMULTI_PLXSD)
2296                                 printk(KERN_DEBUG "Enable SYNC_I\n");
2297                         HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC);
2298                         /* disable JATT, if RX_SYNC is set */
2299                         if (test_bit(HFC_CHIP_RX_SYNC, &hc->chip))
2300                                 HFC_outb(hc, R_SYNC_OUT, V_SYNC_E1_RX);
2301                 }
2302                 if (hc->e1_resync & 2) {
2303                         if (debug & DEBUG_HFCMULTI_PLXSD)
2304                                 printk(KERN_DEBUG "Enable jatt PLL\n");
2305                         HFC_outb(hc, R_SYNC_CTRL, V_SYNC_OFFS);
2306                 }
2307                 if (hc->e1_resync & 4) {
2308                         if (debug & DEBUG_HFCMULTI_PLXSD)
2309                                 printk(KERN_DEBUG
2310                                     "Enable QUARTZ for HFC-E1\n");
2311                         /* set jatt to quartz */
2312                         HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC
2313                                 | V_JATT_OFF);
2314                         /* switch to JATT, in case it is not already */
2315                         HFC_outb(hc, R_SYNC_OUT, 0);
2316                 }
2317                 hc->e1_resync = 0;
2318                 spin_unlock_irqrestore(&HFClock, flags);
2319         }
2320
2321         if (hc->type != 1 || hc->e1_state == 1)
2322                 for (ch = 0; ch <= 31; ch++) {
2323                         if (hc->created[hc->chan[ch].port]) {
2324                                 hfcmulti_tx(hc, ch);
2325                                 /* fifo is started when switching to rx-fifo */
2326                                 hfcmulti_rx(hc, ch);
2327                                 if (hc->chan[ch].dch &&
2328                                     hc->chan[ch].nt_timer > -1) {
2329                                         dch = hc->chan[ch].dch;
2330                                         if (!(--hc->chan[ch].nt_timer)) {
2331                                                 schedule_event(dch,
2332                                                     FLG_PHCHANGE);
2333                                                 if (debug &
2334                                                     DEBUG_HFCMULTI_STATE)
2335                                                         printk(KERN_DEBUG
2336                                                             "%s: nt_timer at "
2337                                                             "state %x\n",
2338                                                             __func__,
2339                                                             dch->state);
2340                                         }
2341                                 }
2342                         }
2343                 }
2344         if (hc->type == 1 && hc->created[0]) {
2345                 dch = hc->chan[hc->dslot].dch;
2346                 if (test_bit(HFC_CFG_REPORT_LOS, &hc->chan[hc->dslot].cfg)) {
2347                         /* LOS */
2348                         temp = HFC_inb_nodebug(hc, R_SYNC_STA) & V_SIG_LOS;
2349                         if (!temp && hc->chan[hc->dslot].los)
2350                                 signal_state_up(dch, L1_SIGNAL_LOS_ON,
2351                                     "LOS detected");
2352                         if (temp && !hc->chan[hc->dslot].los)
2353                                 signal_state_up(dch, L1_SIGNAL_LOS_OFF,
2354                                     "LOS gone");
2355                         hc->chan[hc->dslot].los = temp;
2356                 }
2357                 if (test_bit(HFC_CFG_REPORT_AIS, &hc->chan[hc->dslot].cfg)) {
2358                         /* AIS */
2359                         temp = HFC_inb_nodebug(hc, R_SYNC_STA) & V_AIS;
2360                         if (!temp && hc->chan[hc->dslot].ais)
2361                                 signal_state_up(dch, L1_SIGNAL_AIS_ON,
2362                                     "AIS detected");
2363                         if (temp && !hc->chan[hc->dslot].ais)
2364                                 signal_state_up(dch, L1_SIGNAL_AIS_OFF,
2365                                     "AIS gone");
2366                         hc->chan[hc->dslot].ais = temp;
2367                 }
2368                 if (test_bit(HFC_CFG_REPORT_SLIP, &hc->chan[hc->dslot].cfg)) {
2369                         /* SLIP */
2370                         temp = HFC_inb_nodebug(hc, R_SLIP) & V_FOSLIP_RX;
2371                         if (!temp && hc->chan[hc->dslot].slip_rx)
2372                                 signal_state_up(dch, L1_SIGNAL_SLIP_RX,
2373                                     " bit SLIP detected RX");
2374                         hc->chan[hc->dslot].slip_rx = temp;
2375                         temp = HFC_inb_nodebug(hc, R_SLIP) & V_FOSLIP_TX;
2376                         if (!temp && hc->chan[hc->dslot].slip_tx)
2377                                 signal_state_up(dch, L1_SIGNAL_SLIP_TX,
2378                                     " bit SLIP detected TX");
2379                         hc->chan[hc->dslot].slip_tx = temp;
2380                 }
2381                 if (test_bit(HFC_CFG_REPORT_RDI, &hc->chan[hc->dslot].cfg)) {
2382                         /* RDI */
2383                         temp = HFC_inb_nodebug(hc, R_RX_SL0_0) & V_A;
2384                         if (!temp && hc->chan[hc->dslot].rdi)
2385                                 signal_state_up(dch, L1_SIGNAL_RDI_ON,
2386                                     "RDI detected");
2387                         if (temp && !hc->chan[hc->dslot].rdi)
2388                                 signal_state_up(dch, L1_SIGNAL_RDI_OFF,
2389                                     "RDI gone");
2390                         hc->chan[hc->dslot].rdi = temp;
2391                 }
2392                 temp = HFC_inb_nodebug(hc, R_JATT_DIR);
2393                 switch (hc->chan[hc->dslot].sync) {
2394                 case 0:
2395                         if ((temp & 0x60) == 0x60) {
2396                                 if (debug & DEBUG_HFCMULTI_SYNC)
2397                                         printk(KERN_DEBUG
2398                                             "%s: (id=%d) E1 now "
2399                                             "in clock sync\n",
2400                                             __func__, hc->id);
2401                                 HFC_outb(hc, R_RX_OFF,
2402                                     hc->chan[hc->dslot].jitter | V_RX_INIT);
2403                                 HFC_outb(hc, R_TX_OFF,
2404                                     hc->chan[hc->dslot].jitter | V_RX_INIT);
2405                                 hc->chan[hc->dslot].sync = 1;
2406                                 goto check_framesync;
2407                         }
2408                         break;
2409                 case 1:
2410                         if ((temp & 0x60) != 0x60) {
2411                                 if (debug & DEBUG_HFCMULTI_SYNC)
2412                                         printk(KERN_DEBUG
2413                                             "%s: (id=%d) E1 "
2414                                             "lost clock sync\n",
2415                                             __func__, hc->id);
2416                                 hc->chan[hc->dslot].sync = 0;
2417                                 break;
2418                         }
2419 check_framesync:
2420                         temp = HFC_inb_nodebug(hc, R_SYNC_STA);
2421                         if (temp == 0x27) {
2422                                 if (debug & DEBUG_HFCMULTI_SYNC)
2423                                         printk(KERN_DEBUG
2424                                             "%s: (id=%d) E1 "
2425                                             "now in frame sync\n",
2426                                             __func__, hc->id);
2427                                 hc->chan[hc->dslot].sync = 2;
2428                         }
2429                         break;
2430                 case 2:
2431                         if ((temp & 0x60) != 0x60) {
2432                                 if (debug & DEBUG_HFCMULTI_SYNC)
2433                                         printk(KERN_DEBUG
2434                                             "%s: (id=%d) E1 lost "
2435                                             "clock & frame sync\n",
2436                                             __func__, hc->id);
2437                                 hc->chan[hc->dslot].sync = 0;
2438                                 break;
2439                         }
2440                         temp = HFC_inb_nodebug(hc, R_SYNC_STA);
2441                         if (temp != 0x27) {
2442                                 if (debug & DEBUG_HFCMULTI_SYNC)
2443                                         printk(KERN_DEBUG
2444                                             "%s: (id=%d) E1 "
2445                                             "lost frame sync\n",
2446                                             __func__, hc->id);
2447                                 hc->chan[hc->dslot].sync = 1;
2448                         }
2449                         break;
2450                 }
2451         }
2452
2453         if (test_bit(HFC_CHIP_WATCHDOG, &hc->chip))
2454                 hfcmulti_watchdog(hc);
2455
2456         if (hc->leds)
2457                 hfcmulti_leds(hc);
2458 }
2459
2460 static void
2461 ph_state_irq(struct hfc_multi *hc, u_char r_irq_statech)
2462 {
2463         struct dchannel *dch;
2464         int             ch;
2465         int             active;
2466         u_char          st_status, temp;
2467
2468         /* state machine */
2469         for (ch = 0; ch <= 31; ch++) {
2470                 if (hc->chan[ch].dch) {
2471                         dch = hc->chan[ch].dch;
2472                         if (r_irq_statech & 1) {
2473                                 HFC_outb_nodebug(hc, R_ST_SEL,
2474                                         hc->chan[ch].port);
2475                                 /* undocumented: delay after R_ST_SEL */
2476                                 udelay(1);
2477                                 /* undocumented: status changes during read */
2478                                 st_status = HFC_inb_nodebug(hc, A_ST_RD_STATE);
2479                                 while (st_status != (temp =
2480                                         HFC_inb_nodebug(hc, A_ST_RD_STATE))) {
2481                                         if (debug & DEBUG_HFCMULTI_STATE)
2482                                                 printk(KERN_DEBUG "%s: reread "
2483                                                     "STATE because %d!=%d\n",
2484                                                     __func__, temp,
2485                                                     st_status);
2486                                         st_status = temp; /* repeat */
2487                                 }
2488
2489                                 /* Speech Design TE-sync indication */
2490                                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip) &&
2491                                         dch->dev.D.protocol == ISDN_P_TE_S0) {
2492                                         if (st_status & V_FR_SYNC_ST)
2493                                                 hc->syncronized |=
2494                                                     (1 << hc->chan[ch].port);
2495                                         else
2496                                                 hc->syncronized &=
2497                                                    ~(1 << hc->chan[ch].port);
2498                                 }
2499                                 dch->state = st_status & 0x0f;
2500                                 if (dch->dev.D.protocol == ISDN_P_NT_S0)
2501                                         active = 3;
2502                                 else
2503                                         active = 7;
2504                                 if (dch->state == active) {
2505                                         HFC_outb_nodebug(hc, R_FIFO,
2506                                                 (ch << 1) | 1);
2507                                         HFC_wait_nodebug(hc);
2508                                         HFC_outb_nodebug(hc,
2509                                                 R_INC_RES_FIFO, V_RES_F);
2510                                         HFC_wait_nodebug(hc);
2511                                         dch->tx_idx = 0;
2512                                 }
2513                                 schedule_event(dch, FLG_PHCHANGE);
2514                                 if (debug & DEBUG_HFCMULTI_STATE)
2515                                         printk(KERN_DEBUG
2516                                             "%s: S/T newstate %x port %d\n",
2517                                             __func__, dch->state,
2518                                             hc->chan[ch].port);
2519                         }
2520                         r_irq_statech >>= 1;
2521                 }
2522         }
2523         if (test_bit(HFC_CHIP_PLXSD, &hc->chip))
2524                 plxsd_checksync(hc, 0);
2525 }
2526
2527 static void
2528 fifo_irq(struct hfc_multi *hc, int block)
2529 {
2530         int     ch, j;
2531         struct dchannel *dch;
2532         struct bchannel *bch;
2533         u_char r_irq_fifo_bl;
2534
2535         r_irq_fifo_bl = HFC_inb_nodebug(hc, R_IRQ_FIFO_BL0 + block);
2536         j = 0;
2537         while (j < 8) {
2538                 ch = (block << 2) + (j >> 1);
2539                 dch = hc->chan[ch].dch;
2540                 bch = hc->chan[ch].bch;
2541                 if (((!dch) && (!bch)) || (!hc->created[hc->chan[ch].port])) {
2542                         j += 2;
2543                         continue;
2544                 }
2545                 if (dch && (r_irq_fifo_bl & (1 << j)) &&
2546                     test_bit(FLG_ACTIVE, &dch->Flags)) {
2547                         hfcmulti_tx(hc, ch);
2548                         /* start fifo */
2549                         HFC_outb_nodebug(hc, R_FIFO, 0);
2550                         HFC_wait_nodebug(hc);
2551                 }
2552                 if (bch && (r_irq_fifo_bl & (1 << j)) &&
2553                     test_bit(FLG_ACTIVE, &bch->Flags)) {
2554                         hfcmulti_tx(hc, ch);
2555                         /* start fifo */
2556                         HFC_outb_nodebug(hc, R_FIFO, 0);
2557                         HFC_wait_nodebug(hc);
2558                 }
2559                 j++;
2560                 if (dch && (r_irq_fifo_bl & (1 << j)) &&
2561                     test_bit(FLG_ACTIVE, &dch->Flags)) {
2562                         hfcmulti_rx(hc, ch);
2563                 }
2564                 if (bch && (r_irq_fifo_bl & (1 << j)) &&
2565                     test_bit(FLG_ACTIVE, &bch->Flags)) {
2566                         hfcmulti_rx(hc, ch);
2567                 }
2568                 j++;
2569         }
2570 }
2571
2572 #ifdef IRQ_DEBUG
2573 int irqsem;
2574 #endif
2575 static irqreturn_t
2576 hfcmulti_interrupt(int intno, void *dev_id)
2577 {
2578 #ifdef IRQCOUNT_DEBUG
2579         static int iq1 = 0, iq2 = 0, iq3 = 0, iq4 = 0,
2580             iq5 = 0, iq6 = 0, iqcnt = 0;
2581 #endif
2582         static int              count;
2583         struct hfc_multi        *hc = dev_id;
2584         struct dchannel         *dch;
2585         u_char                  r_irq_statech, status, r_irq_misc, r_irq_oview;
2586         int                     i;
2587         u_short                 *plx_acc, wval;
2588         u_char                  e1_syncsta, temp;
2589         u_long                  flags;
2590
2591         if (!hc) {
2592                 printk(KERN_ERR "HFC-multi: Spurious interrupt!\n");
2593                 return IRQ_NONE;
2594         }
2595
2596         spin_lock(&hc->lock);
2597
2598 #ifdef IRQ_DEBUG
2599         if (irqsem)
2600                 printk(KERN_ERR "irq for card %d during irq from "
2601                 "card %d, this is no bug.\n", hc->id + 1, irqsem);
2602         irqsem = hc->id + 1;
2603 #endif
2604
2605         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
2606                 spin_lock_irqsave(&plx_lock, flags);
2607                 plx_acc = (u_short *)(hc->plx_membase + PLX_INTCSR);
2608                 wval = readw(plx_acc);
2609                 spin_unlock_irqrestore(&plx_lock, flags);
2610                 if (!(wval & PLX_INTCSR_LINTI1_STATUS))
2611                         goto irq_notforus;
2612         }
2613
2614         status = HFC_inb_nodebug(hc, R_STATUS);
2615         r_irq_statech = HFC_inb_nodebug(hc, R_IRQ_STATECH);
2616 #ifdef IRQCOUNT_DEBUG
2617         if (r_irq_statech)
2618                 iq1++;
2619         if (status & V_DTMF_STA)
2620                 iq2++;
2621         if (status & V_LOST_STA)
2622                 iq3++;
2623         if (status & V_EXT_IRQSTA)
2624                 iq4++;
2625         if (status & V_MISC_IRQSTA)
2626                 iq5++;
2627         if (status & V_FR_IRQSTA)
2628                 iq6++;
2629         if (iqcnt++ > 5000) {
2630                 printk(KERN_ERR "iq1:%x iq2:%x iq3:%x iq4:%x iq5:%x iq6:%x\n",
2631                     iq1, iq2, iq3, iq4, iq5, iq6);
2632                 iqcnt = 0;
2633         }
2634 #endif
2635         if (!r_irq_statech &&
2636             !(status & (V_DTMF_STA | V_LOST_STA | V_EXT_IRQSTA |
2637             V_MISC_IRQSTA | V_FR_IRQSTA))) {
2638                 /* irq is not for us */
2639                 goto irq_notforus;
2640         }
2641         hc->irqcnt++;
2642         if (r_irq_statech) {
2643                 if (hc->type != 1)
2644                         ph_state_irq(hc, r_irq_statech);
2645         }
2646         if (status & V_EXT_IRQSTA)
2647                 ; /* external IRQ */
2648         if (status & V_LOST_STA) {
2649                 /* LOST IRQ */
2650                 HFC_outb(hc, R_INC_RES_FIFO, V_RES_LOST); /* clear irq! */
2651         }
2652         if (status & V_MISC_IRQSTA) {
2653                 /* misc IRQ */
2654                 r_irq_misc = HFC_inb_nodebug(hc, R_IRQ_MISC);
2655                 if (r_irq_misc & V_STA_IRQ) {
2656                         if (hc->type == 1) {
2657                                 /* state machine */
2658                                 dch = hc->chan[hc->dslot].dch;
2659                                 e1_syncsta = HFC_inb_nodebug(hc, R_SYNC_STA);
2660                                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)
2661                                  && hc->e1_getclock) {
2662                                         if (e1_syncsta & V_FR_SYNC_E1)
2663                                                 hc->syncronized = 1;
2664                                         else
2665                                                 hc->syncronized = 0;
2666                                 }
2667                                 /* undocumented: status changes during read */
2668                                 dch->state = HFC_inb_nodebug(hc, R_E1_RD_STA);
2669                                 while (dch->state != (temp =
2670                                         HFC_inb_nodebug(hc, R_E1_RD_STA))) {
2671                                         if (debug & DEBUG_HFCMULTI_STATE)
2672                                                 printk(KERN_DEBUG "%s: reread "
2673                                                     "STATE because %d!=%d\n",
2674                                                     __func__, temp,
2675                                                     dch->state);
2676                                         dch->state = temp; /* repeat */
2677                                 }
2678                                 dch->state = HFC_inb_nodebug(hc, R_E1_RD_STA)
2679                                         & 0x7;
2680                                 schedule_event(dch, FLG_PHCHANGE);
2681                                 if (debug & DEBUG_HFCMULTI_STATE)
2682                                         printk(KERN_DEBUG
2683                                             "%s: E1 (id=%d) newstate %x\n",
2684                                             __func__, hc->id, dch->state);
2685                                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip))
2686                                         plxsd_checksync(hc, 0);
2687                         }
2688                 }
2689                 if (r_irq_misc & V_TI_IRQ)
2690                         handle_timer_irq(hc);
2691
2692                 if (r_irq_misc & V_DTMF_IRQ) {
2693                         /* -> DTMF IRQ */
2694                         hfcmulti_dtmf(hc);
2695                 }
2696                 /* TODO: REPLACE !!!! 125 us Interrupts are not acceptable  */
2697                 if (r_irq_misc & V_IRQ_PROC) {
2698                         /* IRQ every 125us */
2699                         count++;
2700                         /* generate 1kHz signal */
2701                         if (count == 8) {
2702                                 if (hfc_interrupt)
2703                                         hfc_interrupt();
2704                                 count = 0;
2705                         }
2706                 }
2707
2708         }
2709         if (status & V_FR_IRQSTA) {
2710                 /* FIFO IRQ */
2711                 r_irq_oview = HFC_inb_nodebug(hc, R_IRQ_OVIEW);
2712                 for (i = 0; i < 8; i++) {
2713                         if (r_irq_oview & (1 << i))
2714                                 fifo_irq(hc, i);
2715                 }
2716         }
2717
2718 #ifdef IRQ_DEBUG
2719         irqsem = 0;
2720 #endif
2721         spin_unlock(&hc->lock);
2722         return IRQ_HANDLED;
2723
2724 irq_notforus:
2725 #ifdef IRQ_DEBUG
2726         irqsem = 0;
2727 #endif
2728         spin_unlock(&hc->lock);
2729         return IRQ_NONE;
2730 }
2731
2732
2733 /*
2734  * timer callback for D-chan busy resolution. Currently no function
2735  */
2736
2737 static void
2738 hfcmulti_dbusy_timer(struct hfc_multi *hc)
2739 {
2740 }
2741
2742
2743 /*
2744  * activate/deactivate hardware for selected channels and mode
2745  *
2746  * configure B-channel with the given protocol
2747  * ch eqals to the HFC-channel (0-31)
2748  * ch is the number of channel (0-4,4-7,8-11,12-15,16-19,20-23,24-27,28-31
2749  * for S/T, 1-31 for E1)
2750  * the hdlc interrupts will be set/unset
2751  */
2752 static int
2753 mode_hfcmulti(struct hfc_multi *hc, int ch, int protocol, int slot_tx,
2754     int bank_tx, int slot_rx, int bank_rx)
2755 {
2756         int flow_tx = 0, flow_rx = 0, routing = 0;
2757         int oslot_tx, oslot_rx;
2758         int conf;
2759
2760         if (ch < 0 || ch > 31)
2761                 return EINVAL;
2762         oslot_tx = hc->chan[ch].slot_tx;
2763         oslot_rx = hc->chan[ch].slot_rx;
2764         conf = hc->chan[ch].conf;
2765
2766         if (debug & DEBUG_HFCMULTI_MODE)
2767                 printk(KERN_DEBUG
2768                     "%s: card %d channel %d protocol %x slot old=%d new=%d "
2769                     "bank new=%d (TX) slot old=%d new=%d bank new=%d (RX)\n",
2770                     __func__, hc->id, ch, protocol, oslot_tx, slot_tx,
2771                     bank_tx, oslot_rx, slot_rx, bank_rx);
2772
2773         if (oslot_tx >= 0 && slot_tx != oslot_tx) {
2774                 /* remove from slot */
2775                 if (debug & DEBUG_HFCMULTI_MODE)
2776                         printk(KERN_DEBUG "%s: remove from slot %d (TX)\n",
2777                             __func__, oslot_tx);
2778                 if (hc->slot_owner[oslot_tx<<1] == ch) {
2779                         HFC_outb(hc, R_SLOT, oslot_tx << 1);
2780                         HFC_outb(hc, A_SL_CFG, 0);
2781                         HFC_outb(hc, A_CONF, 0);
2782                         hc->slot_owner[oslot_tx<<1] = -1;
2783                 } else {
2784                         if (debug & DEBUG_HFCMULTI_MODE)
2785                                 printk(KERN_DEBUG
2786                                     "%s: we are not owner of this tx slot "
2787                                     "anymore, channel %d is.\n",
2788                                     __func__, hc->slot_owner[oslot_tx<<1]);
2789                 }
2790         }
2791
2792         if (oslot_rx >= 0 && slot_rx != oslot_rx) {
2793                 /* remove from slot */
2794                 if (debug & DEBUG_HFCMULTI_MODE)
2795                         printk(KERN_DEBUG
2796                             "%s: remove from slot %d (RX)\n",
2797                             __func__, oslot_rx);
2798                 if (hc->slot_owner[(oslot_rx << 1) | 1] == ch) {
2799                         HFC_outb(hc, R_SLOT, (oslot_rx << 1) | V_SL_DIR);
2800                         HFC_outb(hc, A_SL_CFG, 0);
2801                         hc->slot_owner[(oslot_rx << 1) | 1] = -1;
2802                 } else {
2803                         if (debug & DEBUG_HFCMULTI_MODE)
2804                                 printk(KERN_DEBUG
2805                                     "%s: we are not owner of this rx slot "
2806                                     "anymore, channel %d is.\n",
2807                                     __func__,
2808                                     hc->slot_owner[(oslot_rx << 1) | 1]);
2809                 }
2810         }
2811
2812         if (slot_tx < 0) {
2813                 flow_tx = 0x80; /* FIFO->ST */
2814                 /* disable pcm slot */
2815                 hc->chan[ch].slot_tx = -1;
2816                 hc->chan[ch].bank_tx = 0;
2817         } else {
2818                 /* set pcm slot */
2819                 if (hc->chan[ch].txpending)
2820                         flow_tx = 0x80; /* FIFO->ST */
2821                 else
2822                         flow_tx = 0xc0; /* PCM->ST */
2823                 /* put on slot */
2824                 routing = bank_tx ? 0xc0 : 0x80;
2825                 if (conf >= 0 || bank_tx > 1)
2826                         routing = 0x40; /* loop */
2827                 if (debug & DEBUG_HFCMULTI_MODE)
2828                         printk(KERN_DEBUG "%s: put channel %d to slot %d bank"
2829                             " %d flow %02x routing %02x conf %d (TX)\n",
2830                             __func__, ch, slot_tx, bank_tx,
2831                             flow_tx, routing, conf);
2832                 HFC_outb(hc, R_SLOT, slot_tx << 1);
2833                 HFC_outb(hc, A_SL_CFG, (ch<<1) | routing);
2834                 HFC_outb(hc, A_CONF, (conf < 0) ? 0 : (conf | V_CONF_SL));
2835                 hc->slot_owner[slot_tx << 1] = ch;
2836                 hc->chan[ch].slot_tx = slot_tx;
2837                 hc->chan[ch].bank_tx = bank_tx;
2838         }
2839         if (slot_rx < 0) {
2840                 /* disable pcm slot */
2841                 flow_rx = 0x80; /* ST->FIFO */
2842                 hc->chan[ch].slot_rx = -1;
2843                 hc->chan[ch].bank_rx = 0;
2844         } else {
2845                 /* set pcm slot */
2846                 if (hc->chan[ch].txpending)
2847                         flow_rx = 0x80; /* ST->FIFO */
2848                 else
2849                         flow_rx = 0xc0; /* ST->(FIFO,PCM) */
2850                 /* put on slot */
2851                 routing = bank_rx?0x80:0xc0; /* reversed */
2852                 if (conf >= 0 || bank_rx > 1)
2853                         routing = 0x40; /* loop */
2854                 if (debug & DEBUG_HFCMULTI_MODE)
2855                         printk(KERN_DEBUG "%s: put channel %d to slot %d bank"
2856                             " %d flow %02x routing %02x conf %d (RX)\n",
2857                             __func__, ch, slot_rx, bank_rx,
2858                             flow_rx, routing, conf);
2859                 HFC_outb(hc, R_SLOT, (slot_rx<<1) | V_SL_DIR);
2860                 HFC_outb(hc, A_SL_CFG, (ch<<1) | V_CH_DIR | routing);
2861                 hc->slot_owner[(slot_rx<<1)|1] = ch;
2862                 hc->chan[ch].slot_rx = slot_rx;
2863                 hc->chan[ch].bank_rx = bank_rx;
2864         }
2865
2866         switch (protocol) {
2867         case (ISDN_P_NONE):
2868                 /* disable TX fifo */
2869                 HFC_outb(hc, R_FIFO, ch << 1);
2870                 HFC_wait(hc);
2871                 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x00 | V_IFF);
2872                 HFC_outb(hc, A_SUBCH_CFG, 0);
2873                 HFC_outb(hc, A_IRQ_MSK, 0);
2874                 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2875                 HFC_wait(hc);
2876                 /* disable RX fifo */
2877                 HFC_outb(hc, R_FIFO, (ch<<1)|1);
2878                 HFC_wait(hc);
2879                 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x00);
2880                 HFC_outb(hc, A_SUBCH_CFG, 0);
2881                 HFC_outb(hc, A_IRQ_MSK, 0);
2882                 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2883                 HFC_wait(hc);
2884                 if (hc->chan[ch].bch && hc->type != 1) {
2885                         hc->hw.a_st_ctrl0[hc->chan[ch].port] &=
2886                             ((ch & 0x3) == 0)? ~V_B1_EN: ~V_B2_EN;
2887                         HFC_outb(hc, R_ST_SEL, hc->chan[ch].port);
2888                         /* undocumented: delay after R_ST_SEL */
2889                         udelay(1);
2890                         HFC_outb(hc, A_ST_CTRL0,
2891                             hc->hw.a_st_ctrl0[hc->chan[ch].port]);
2892                 }
2893                 if (hc->chan[ch].bch) {
2894                         test_and_clear_bit(FLG_HDLC, &hc->chan[ch].bch->Flags);
2895                         test_and_clear_bit(FLG_TRANSPARENT,
2896                             &hc->chan[ch].bch->Flags);
2897                 }
2898                 break;
2899         case (ISDN_P_B_RAW): /* B-channel */
2900
2901                 if (test_bit(HFC_CHIP_B410P, &hc->chip) &&
2902                     (hc->chan[ch].slot_rx < 0) &&
2903                     (hc->chan[ch].slot_tx < 0)) {
2904
2905                         printk(KERN_DEBUG
2906                             "Setting B-channel %d to echo cancelable "
2907                             "state on PCM slot %d\n", ch,
2908                             ((ch / 4) * 8) + ((ch % 4) * 4) + 1);
2909                         printk(KERN_DEBUG
2910                             "Enabling pass through for channel\n");
2911                         vpm_out(hc, ch, ((ch / 4) * 8) +
2912                             ((ch % 4) * 4) + 1, 0x01);
2913                         /* rx path */
2914                         /* S/T -> PCM */
2915                         HFC_outb(hc, R_FIFO, (ch << 1));
2916                         HFC_wait(hc);
2917                         HFC_outb(hc, A_CON_HDLC, 0xc0 | V_HDLC_TRP | V_IFF);
2918                         HFC_outb(hc, R_SLOT, (((ch / 4) * 8) +
2919                             ((ch % 4) * 4) + 1) << 1);
2920                         HFC_outb(hc, A_SL_CFG, 0x80 | (ch << 1));
2921
2922                         /* PCM -> FIFO */
2923                         HFC_outb(hc, R_FIFO, 0x20 | (ch << 1) | 1);
2924                         HFC_wait(hc);
2925                         HFC_outb(hc, A_CON_HDLC, 0x20 | V_HDLC_TRP | V_IFF);
2926                         HFC_outb(hc, A_SUBCH_CFG, 0);
2927                         HFC_outb(hc, A_IRQ_MSK, 0);
2928                         HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2929                         HFC_wait(hc);
2930                         HFC_outb(hc, R_SLOT, ((((ch / 4) * 8) +
2931                             ((ch % 4) * 4) + 1) << 1) | 1);
2932                         HFC_outb(hc, A_SL_CFG, 0x80 | 0x20 | (ch << 1) | 1);
2933
2934                         /* tx path */
2935                         /* PCM -> S/T */
2936                         HFC_outb(hc, R_FIFO, (ch << 1) | 1);
2937                         HFC_wait(hc);
2938                         HFC_outb(hc, A_CON_HDLC, 0xc0 | V_HDLC_TRP | V_IFF);
2939                         HFC_outb(hc, R_SLOT, ((((ch / 4) * 8) +
2940                             ((ch % 4) * 4)) << 1) | 1);
2941                         HFC_outb(hc, A_SL_CFG, 0x80 | 0x40 | (ch << 1) | 1);
2942
2943                         /* FIFO -> PCM */
2944                         HFC_outb(hc, R_FIFO, 0x20 | (ch << 1));
2945                         HFC_wait(hc);
2946                         HFC_outb(hc, A_CON_HDLC, 0x20 | V_HDLC_TRP | V_IFF);
2947                         HFC_outb(hc, A_SUBCH_CFG, 0);
2948                         HFC_outb(hc, A_IRQ_MSK, 0);
2949                         HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2950                         HFC_wait(hc);
2951                         /* tx silence */
2952                         HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, silence);
2953                         HFC_outb(hc, R_SLOT, (((ch / 4) * 8) +
2954                             ((ch % 4) * 4)) << 1);
2955                         HFC_outb(hc, A_SL_CFG, 0x80 | 0x20 | (ch << 1));
2956                 } else {
2957                         /* enable TX fifo */
2958                         HFC_outb(hc, R_FIFO, ch << 1);
2959                         HFC_wait(hc);
2960                         HFC_outb(hc, A_CON_HDLC, flow_tx | 0x00 |
2961                             V_HDLC_TRP | V_IFF);
2962                         HFC_outb(hc, A_SUBCH_CFG, 0);
2963                         HFC_outb(hc, A_IRQ_MSK, 0);
2964                         HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2965                         HFC_wait(hc);
2966                         /* tx silence */
2967                         HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, silence);
2968                         /* enable RX fifo */
2969                         HFC_outb(hc, R_FIFO, (ch<<1)|1);
2970                         HFC_wait(hc);
2971                         HFC_outb(hc, A_CON_HDLC, flow_rx | 0x00 | V_HDLC_TRP);
2972                         HFC_outb(hc, A_SUBCH_CFG, 0);
2973                         HFC_outb(hc, A_IRQ_MSK, 0);
2974                         HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2975                         HFC_wait(hc);
2976                 }
2977                 if (hc->type != 1) {
2978                         hc->hw.a_st_ctrl0[hc->chan[ch].port] |=
2979                             ((ch & 0x3) == 0) ? V_B1_EN : V_B2_EN;
2980                         HFC_outb(hc, R_ST_SEL, hc->chan[ch].port);
2981                         /* undocumented: delay after R_ST_SEL */
2982                         udelay(1);
2983                         HFC_outb(hc, A_ST_CTRL0,
2984                             hc->hw.a_st_ctrl0[hc->chan[ch].port]);
2985                 }
2986                 if (hc->chan[ch].bch)
2987                         test_and_set_bit(FLG_TRANSPARENT,
2988                             &hc->chan[ch].bch->Flags);
2989                 break;
2990         case (ISDN_P_B_HDLC): /* B-channel */
2991         case (ISDN_P_TE_S0): /* D-channel */
2992         case (ISDN_P_NT_S0):
2993         case (ISDN_P_TE_E1):
2994         case (ISDN_P_NT_E1):
2995                 /* enable TX fifo */
2996                 HFC_outb(hc, R_FIFO, ch<<1);
2997                 HFC_wait(hc);
2998                 if (hc->type == 1 || hc->chan[ch].bch) {
2999                         /* E1 or B-channel */
3000                         HFC_outb(hc, A_CON_HDLC, flow_tx | 0x04);
3001                         HFC_outb(hc, A_SUBCH_CFG, 0);
3002                 } else {
3003                         /* D-Channel without HDLC fill flags */
3004                         HFC_outb(hc, A_CON_HDLC, flow_tx | 0x04 | V_IFF);
3005                         HFC_outb(hc, A_SUBCH_CFG, 2);
3006                 }
3007                 HFC_outb(hc, A_IRQ_MSK, V_IRQ);
3008                 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3009                 HFC_wait(hc);
3010                 /* enable RX fifo */
3011                 HFC_outb(hc, R_FIFO, (ch<<1)|1);
3012                 HFC_wait(hc);
3013                 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x04);
3014                 if (hc->type == 1 || hc->chan[ch].bch)
3015                         HFC_outb(hc, A_SUBCH_CFG, 0); /* full 8 bits */
3016                 else
3017                         HFC_outb(hc, A_SUBCH_CFG, 2); /* 2 bits dchannel */
3018                 HFC_outb(hc, A_IRQ_MSK, V_IRQ);
3019                 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3020                 HFC_wait(hc);
3021                 if (hc->chan[ch].bch) {
3022                         test_and_set_bit(FLG_HDLC, &hc->chan[ch].bch->Flags);
3023                         if (hc->type != 1) {
3024                                 hc->hw.a_st_ctrl0[hc->chan[ch].port] |=
3025                                   ((ch&0x3) == 0) ? V_B1_EN : V_B2_EN;
3026                                 HFC_outb(hc, R_ST_SEL, hc->chan[ch].port);
3027                                 /* undocumented: delay after R_ST_SEL */
3028                                 udelay(1);
3029                                 HFC_outb(hc, A_ST_CTRL0,
3030                                   hc->hw.a_st_ctrl0[hc->chan[ch].port]);
3031                         }
3032                 }
3033                 break;
3034         default:
3035                 printk(KERN_DEBUG "%s: protocol not known %x\n",
3036                     __func__, protocol);
3037                 hc->chan[ch].protocol = ISDN_P_NONE;
3038                 return -ENOPROTOOPT;
3039         }
3040         hc->chan[ch].protocol = protocol;
3041         return 0;
3042 }
3043
3044
3045 /*
3046  * connect/disconnect PCM
3047  */
3048
3049 static void
3050 hfcmulti_pcm(struct hfc_multi *hc, int ch, int slot_tx, int bank_tx,
3051     int slot_rx, int bank_rx)
3052 {
3053         if (slot_rx < 0 || slot_rx < 0 || bank_tx < 0 || bank_rx < 0) {
3054                 /* disable PCM */
3055                 mode_hfcmulti(hc, ch, hc->chan[ch].protocol, -1, 0, -1, 0);
3056                 return;
3057         }
3058
3059         /* enable pcm */
3060         mode_hfcmulti(hc, ch, hc->chan[ch].protocol, slot_tx, bank_tx,
3061                 slot_rx, bank_rx);
3062 }
3063
3064 /*
3065  * set/disable conference
3066  */
3067
3068 static void
3069 hfcmulti_conf(struct hfc_multi *hc, int ch, int num)
3070 {
3071         if (num >= 0 && num <= 7)
3072                 hc->chan[ch].conf = num;
3073         else
3074                 hc->chan[ch].conf = -1;
3075         mode_hfcmulti(hc, ch, hc->chan[ch].protocol, hc->chan[ch].slot_tx,
3076             hc->chan[ch].bank_tx, hc->chan[ch].slot_rx,
3077             hc->chan[ch].bank_rx);
3078 }
3079
3080
3081 /*
3082  * set/disable sample loop
3083  */
3084
3085 /* NOTE: this function is experimental and therefore disabled */
3086
3087 /*
3088  * Layer 1 callback function
3089  */
3090 static int
3091 hfcm_l1callback(struct dchannel *dch, u_int cmd)
3092 {
3093         struct hfc_multi        *hc = dch->hw;
3094         u_long  flags;
3095
3096         switch (cmd) {
3097         case INFO3_P8:
3098         case INFO3_P10:
3099                 break;
3100         case HW_RESET_REQ:
3101                 /* start activation */
3102                 spin_lock_irqsave(&hc->lock, flags);
3103                 if (hc->type == 1) {
3104                         if (debug & DEBUG_HFCMULTI_MSG)
3105                                 printk(KERN_DEBUG
3106                                     "%s: HW_RESET_REQ no BRI\n",
3107                                     __func__);
3108                 } else {
3109                         HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port);
3110                         /* undocumented: delay after R_ST_SEL */
3111                         udelay(1);
3112                         HFC_outb(hc, A_ST_WR_STATE, V_ST_LD_STA | 3); /* F3 */
3113                         udelay(6); /* wait at least 5,21us */
3114                         HFC_outb(hc, A_ST_WR_STATE, 3);
3115                         HFC_outb(hc, A_ST_WR_STATE, 3 | (V_ST_ACT*3));
3116                                 /* activate */
3117                 }
3118                 spin_unlock_irqrestore(&hc->lock, flags);
3119                 l1_event(dch->l1, HW_POWERUP_IND);
3120                 break;
3121         case HW_DEACT_REQ:
3122                 /* start deactivation */
3123                 spin_lock_irqsave(&hc->lock, flags);
3124                 if (hc->type == 1) {
3125                         if (debug & DEBUG_HFCMULTI_MSG)
3126                                 printk(KERN_DEBUG
3127                                     "%s: HW_DEACT_REQ no BRI\n",
3128                                     __func__);
3129                 } else {
3130                         HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port);
3131                         /* undocumented: delay after R_ST_SEL */
3132                         udelay(1);
3133                         HFC_outb(hc, A_ST_WR_STATE, V_ST_ACT*2);
3134                                 /* deactivate */
3135                         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
3136                                 hc->syncronized &=
3137                                    ~(1 << hc->chan[dch->slot].port);
3138                                 plxsd_checksync(hc, 0);
3139                         }
3140                 }
3141                 skb_queue_purge(&dch->squeue);
3142                 if (dch->tx_skb) {
3143                         dev_kfree_skb(dch->tx_skb);
3144                         dch->tx_skb = NULL;
3145                 }
3146                 dch->tx_idx = 0;
3147                 if (dch->rx_skb) {
3148                         dev_kfree_skb(dch->rx_skb);
3149                         dch->rx_skb = NULL;
3150                 }
3151                 test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
3152                 if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
3153                         del_timer(&dch->timer);
3154                 spin_unlock_irqrestore(&hc->lock, flags);
3155                 break;
3156         case HW_POWERUP_REQ:
3157                 spin_lock_irqsave(&hc->lock, flags);
3158                 if (hc->type == 1) {
3159                         if (debug & DEBUG_HFCMULTI_MSG)
3160                                 printk(KERN_DEBUG
3161                                     "%s: HW_POWERUP_REQ no BRI\n",
3162                                     __func__);
3163                 } else {
3164                         HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port);
3165                         /* undocumented: delay after R_ST_SEL */
3166                         udelay(1);
3167                         HFC_outb(hc, A_ST_WR_STATE, 3 | 0x10); /* activate */
3168                         udelay(6); /* wait at least 5,21us */
3169                         HFC_outb(hc, A_ST_WR_STATE, 3); /* activate */
3170                 }
3171                 spin_unlock_irqrestore(&hc->lock, flags);
3172                 break;
3173         case PH_ACTIVATE_IND:
3174                 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
3175                 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
3176                         GFP_ATOMIC);
3177                 break;
3178         case PH_DEACTIVATE_IND:
3179                 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
3180                 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
3181                         GFP_ATOMIC);
3182                 break;
3183         default:
3184                 if (dch->debug & DEBUG_HW)
3185                         printk(KERN_DEBUG "%s: unknown command %x\n",
3186                             __func__, cmd);
3187                 return -1;
3188         }
3189         return 0;
3190 }
3191
3192 /*
3193  * Layer2 -> Layer 1 Transfer
3194  */
3195
3196 static int
3197 handle_dmsg(struct mISDNchannel *ch, struct sk_buff *skb)
3198 {
3199         struct mISDNdevice      *dev = container_of(ch, struct mISDNdevice, D);
3200         struct dchannel         *dch = container_of(dev, struct dchannel, dev);
3201         struct hfc_multi        *hc = dch->hw;
3202         struct mISDNhead        *hh = mISDN_HEAD_P(skb);
3203         int                     ret = -EINVAL;
3204         unsigned int            id;
3205         u_long                  flags;
3206
3207         switch (hh->prim) {
3208         case PH_DATA_REQ:
3209                 if (skb->len < 1)
3210                         break;
3211                 spin_lock_irqsave(&hc->lock, flags);
3212                 ret = dchannel_senddata(dch, skb);
3213                 if (ret > 0) { /* direct TX */
3214                         id = hh->id; /* skb can be freed */
3215                         hfcmulti_tx(hc, dch->slot);
3216                         ret = 0;
3217                         /* start fifo */
3218                         HFC_outb(hc, R_FIFO, 0);
3219                         HFC_wait(hc);
3220                         spin_unlock_irqrestore(&hc->lock, flags);
3221                         queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
3222                 } else
3223                         spin_unlock_irqrestore(&hc->lock, flags);
3224                 return ret;
3225         case PH_ACTIVATE_REQ:
3226                 if (dch->dev.D.protocol != ISDN_P_TE_S0) {
3227                         spin_lock_irqsave(&hc->lock, flags);
3228                         ret = 0;
3229                         if (debug & DEBUG_HFCMULTI_MSG)
3230                                 printk(KERN_DEBUG
3231                                     "%s: PH_ACTIVATE port %d (0..%d)\n",
3232                                     __func__, hc->chan[dch->slot].port,
3233                                     hc->ports-1);
3234                         /* start activation */
3235                         if (hc->type == 1) {
3236                                 ph_state_change(dch);
3237                                 if (debug & DEBUG_HFCMULTI_STATE)
3238                                         printk(KERN_DEBUG
3239                                             "%s: E1 report state %x \n",
3240                                             __func__, dch->state);
3241                         } else {
3242                                 HFC_outb(hc, R_ST_SEL,
3243                                     hc->chan[dch->slot].port);
3244                                 /* undocumented: delay after R_ST_SEL */
3245                                 udelay(1);
3246                                 HFC_outb(hc, A_ST_WR_STATE, V_ST_LD_STA | 1);
3247                                     /* G1 */
3248                                 udelay(6); /* wait at least 5,21us */
3249                                 HFC_outb(hc, A_ST_WR_STATE, 1);
3250                                 HFC_outb(hc, A_ST_WR_STATE, 1 |
3251                                     (V_ST_ACT*3)); /* activate */
3252                                 dch->state = 1;
3253                         }
3254                         spin_unlock_irqrestore(&hc->lock, flags);
3255                 } else
3256                         ret = l1_event(dch->l1, hh->prim);
3257                 break;
3258         case PH_DEACTIVATE_REQ:
3259                 test_and_clear_bit(FLG_L2_ACTIVATED, &dch->Flags);
3260                 if (dch->dev.D.protocol != ISDN_P_TE_S0) {
3261                         spin_lock_irqsave(&hc->lock, flags);
3262                         if (debug & DEBUG_HFCMULTI_MSG)
3263                                 printk(KERN_DEBUG
3264                                     "%s: PH_DEACTIVATE port %d (0..%d)\n",
3265                                     __func__, hc->chan[dch->slot].port,
3266                                     hc->ports-1);
3267                         /* start deactivation */
3268                         if (hc->type == 1) {
3269                                 if (debug & DEBUG_HFCMULTI_MSG)
3270                                         printk(KERN_DEBUG
3271                                             "%s: PH_DEACTIVATE no BRI\n",
3272                                             __func__);
3273                         } else {
3274                                 HFC_outb(hc, R_ST_SEL,
3275                                     hc->chan[dch->slot].port);
3276                                 /* undocumented: delay after R_ST_SEL */
3277                                 udelay(1);
3278                                 HFC_outb(hc, A_ST_WR_STATE, V_ST_ACT * 2);
3279                                     /* deactivate */
3280                                 dch->state = 1;
3281                         }
3282                         skb_queue_purge(&dch->squeue);
3283                         if (dch->tx_skb) {
3284                                 dev_kfree_skb(dch->tx_skb);
3285                                 dch->tx_skb = NULL;
3286                         }
3287                         dch->tx_idx = 0;
3288                         if (dch->rx_skb) {
3289                                 dev_kfree_skb(dch->rx_skb);
3290                                 dch->rx_skb = NULL;
3291                         }
3292                         test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
3293                         if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
3294                                 del_timer(&dch->timer);
3295 #ifdef FIXME
3296                         if (test_and_clear_bit(FLG_L1_BUSY, &dch->Flags))
3297                                 dchannel_sched_event(&hc->dch, D_CLEARBUSY);
3298 #endif
3299                         ret = 0;
3300                         spin_unlock_irqrestore(&hc->lock, flags);
3301                 } else
3302                         ret = l1_event(dch->l1, hh->prim);
3303                 break;
3304         }
3305         if (!ret)
3306                 dev_kfree_skb(skb);
3307         return ret;
3308 }
3309
3310 static void
3311 deactivate_bchannel(struct bchannel *bch)
3312 {
3313         struct hfc_multi        *hc = bch->hw;
3314         u_long                  flags;
3315
3316         spin_lock_irqsave(&hc->lock, flags);
3317         if (test_and_clear_bit(FLG_TX_NEXT, &bch->Flags)) {
3318                 dev_kfree_skb(bch->next_skb);
3319                 bch->next_skb = NULL;
3320         }
3321         if (bch->tx_skb) {
3322                 dev_kfree_skb(bch->tx_skb);
3323                 bch->tx_skb = NULL;
3324         }
3325         bch->tx_idx = 0;
3326         if (bch->rx_skb) {
3327                 dev_kfree_skb(bch->rx_skb);
3328                 bch->rx_skb = NULL;
3329         }
3330         hc->chan[bch->slot].coeff_count = 0;
3331         test_and_clear_bit(FLG_ACTIVE, &bch->Flags);
3332         test_and_clear_bit(FLG_TX_BUSY, &bch->Flags);
3333         hc->chan[bch->slot].rx_off = 0;
3334         hc->chan[bch->slot].conf = -1;
3335         mode_hfcmulti(hc, bch->slot, ISDN_P_NONE, -1, 0, -1, 0);
3336         spin_unlock_irqrestore(&hc->lock, flags);
3337 }
3338
3339 static int
3340 handle_bmsg(struct mISDNchannel *ch, struct sk_buff *skb)
3341 {
3342         struct bchannel         *bch = container_of(ch, struct bchannel, ch);
3343         struct hfc_multi        *hc = bch->hw;
3344         int                     ret = -EINVAL;
3345         struct mISDNhead        *hh = mISDN_HEAD_P(skb);
3346         unsigned int            id;
3347         u_long                  flags;
3348
3349         switch (hh->prim) {
3350         case PH_DATA_REQ:
3351                 if (!skb->len)
3352                         break;
3353                 spin_lock_irqsave(&hc->lock, flags);
3354                 ret = bchannel_senddata(bch, skb);
3355                 if (ret > 0) { /* direct TX */
3356                         id = hh->id; /* skb can be freed */
3357                         hfcmulti_tx(hc, bch->slot);
3358                         ret = 0;
3359                         /* start fifo */
3360                         HFC_outb_nodebug(hc, R_FIFO, 0);
3361                         HFC_wait_nodebug(hc);
3362                         if (!test_bit(FLG_TRANSPARENT, &bch->Flags)) {
3363                                 spin_unlock_irqrestore(&hc->lock, flags);
3364                                 queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
3365                         } else
3366                                 spin_unlock_irqrestore(&hc->lock, flags);
3367                 } else
3368                         spin_unlock_irqrestore(&hc->lock, flags);
3369                 return ret;
3370         case PH_ACTIVATE_REQ:
3371                 if (debug & DEBUG_HFCMULTI_MSG)
3372                         printk(KERN_DEBUG "%s: PH_ACTIVATE ch %d (0..32)\n",
3373                                 __func__, bch->slot);
3374                 spin_lock_irqsave(&hc->lock, flags);
3375                 /* activate B-channel if not already activated */
3376                 if (!test_and_set_bit(FLG_ACTIVE, &bch->Flags)) {
3377                         hc->chan[bch->slot].txpending = 0;
3378                         ret = mode_hfcmulti(hc, bch->slot,
3379                                 ch->protocol,
3380                                 hc->chan[bch->slot].slot_tx,
3381                                 hc->chan[bch->slot].bank_tx,
3382                                 hc->chan[bch->slot].slot_rx,
3383                                 hc->chan[bch->slot].bank_rx);
3384                         if (!ret) {
3385                                 if (ch->protocol == ISDN_P_B_RAW && !hc->dtmf
3386                                         && test_bit(HFC_CHIP_DTMF, &hc->chip)) {
3387                                         /* start decoder */
3388                                         hc->dtmf = 1;
3389                                         if (debug & DEBUG_HFCMULTI_DTMF)
3390                                                 printk(KERN_DEBUG
3391                                                     "%s: start dtmf decoder\n",
3392                                                         __func__);
3393                                         HFC_outb(hc, R_DTMF, hc->hw.r_dtmf |
3394                                             V_RST_DTMF);
3395                                 }
3396                         }
3397                 } else
3398                         ret = 0;
3399                 spin_unlock_irqrestore(&hc->lock, flags);
3400                 if (!ret)
3401                         _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY, 0, NULL,
3402                                 GFP_KERNEL);
3403                 break;
3404         case PH_CONTROL_REQ:
3405                 spin_lock_irqsave(&hc->lock, flags);
3406                 switch (hh->id) {
3407                 case HFC_SPL_LOOP_ON: /* set sample loop */
3408                         if (debug & DEBUG_HFCMULTI_MSG)
3409                         printk(KERN_DEBUG
3410                             "%s: HFC_SPL_LOOP_ON (len = %d)\n",
3411                             __func__, skb->len);
3412                         ret = 0;
3413                         break;
3414                 case HFC_SPL_LOOP_OFF: /* set silence */
3415                         if (debug & DEBUG_HFCMULTI_MSG)
3416                                 printk(KERN_DEBUG "%s: HFC_SPL_LOOP_OFF\n",
3417                                     __func__);
3418                         ret = 0;
3419                         break;
3420                 default:
3421                         printk(KERN_ERR
3422                              "%s: unknown PH_CONTROL_REQ info %x\n",
3423                              __func__, hh->id);
3424                         ret = -EINVAL;
3425                 }
3426                 spin_unlock_irqrestore(&hc->lock, flags);
3427                 break;
3428         case PH_DEACTIVATE_REQ:
3429                 deactivate_bchannel(bch); /* locked there */
3430                 _queue_data(ch, PH_DEACTIVATE_IND, MISDN_ID_ANY, 0, NULL,
3431                         GFP_KERNEL);
3432                 ret = 0;
3433                 break;
3434         }
3435         if (!ret)
3436                 dev_kfree_skb(skb);
3437         return ret;
3438 }
3439
3440 /*
3441  * bchannel control function
3442  */
3443 static int
3444 channel_bctrl(struct bchannel *bch, struct mISDN_ctrl_req *cq)
3445 {
3446         int                     ret = 0;
3447         struct dsp_features     *features =
3448                 (struct dsp_features *)(*((u_long *)&cq->p1));
3449         struct hfc_multi        *hc = bch->hw;
3450         int                     slot_tx;
3451         int                     bank_tx;
3452         int                     slot_rx;
3453         int                     bank_rx;
3454         int                     num;
3455
3456         switch (cq->op) {
3457         case MISDN_CTRL_GETOP:
3458                 cq->op = MISDN_CTRL_HFC_OP | MISDN_CTRL_HW_FEATURES_OP
3459                         | MISDN_CTRL_RX_OFF;
3460                 break;
3461         case MISDN_CTRL_RX_OFF: /* turn off / on rx stream */
3462                 hc->chan[bch->slot].rx_off = !!cq->p1;
3463                 if (!hc->chan[bch->slot].rx_off) {
3464                         /* reset fifo on rx on */
3465                         HFC_outb_nodebug(hc, R_FIFO, (bch->slot << 1) | 1);
3466                         HFC_wait_nodebug(hc);
3467                         HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F);
3468                         HFC_wait_nodebug(hc);
3469                 }
3470                 if (debug & DEBUG_HFCMULTI_MSG)
3471                         printk(KERN_DEBUG "%s: RX_OFF request (nr=%d off=%d)\n",
3472                             __func__, bch->nr, hc->chan[bch->slot].rx_off);
3473                 break;
3474         case MISDN_CTRL_HW_FEATURES: /* fill features structure */
3475                 if (debug & DEBUG_HFCMULTI_MSG)
3476                         printk(KERN_DEBUG "%s: HW_FEATURE request\n",
3477                             __func__);
3478                 /* create confirm */
3479                 features->hfc_id = hc->id;
3480                 if (test_bit(HFC_CHIP_DTMF, &hc->chip))
3481                         features->hfc_dtmf = 1;
3482                 features->hfc_loops = 0;
3483                 if (test_bit(HFC_CHIP_B410P, &hc->chip)) {
3484                         features->hfc_echocanhw = 1;
3485                 } else {
3486                         features->pcm_id = hc->pcm;
3487                         features->pcm_slots = hc->slots;
3488                         features->pcm_banks = 2;
3489                 }
3490                 break;
3491         case MISDN_CTRL_HFC_PCM_CONN: /* connect to pcm timeslot (0..N) */
3492                 slot_tx = cq->p1 & 0xff;
3493                 bank_tx = cq->p1 >> 8;
3494                 slot_rx = cq->p2 & 0xff;
3495                 bank_rx = cq->p2 >> 8;
3496                 if (debug & DEBUG_HFCMULTI_MSG)
3497                         printk(KERN_DEBUG
3498                             "%s: HFC_PCM_CONN slot %d bank %d (TX) "
3499                             "slot %d bank %d (RX)\n",
3500                             __func__, slot_tx, bank_tx,
3501                             slot_rx, bank_rx);
3502                 if (slot_tx < hc->slots && bank_tx <= 2 &&
3503                     slot_rx < hc->slots && bank_rx <= 2)
3504                         hfcmulti_pcm(hc, bch->slot,
3505                             slot_tx, bank_tx, slot_rx, bank_rx);
3506                 else {
3507                         printk(KERN_WARNING
3508                             "%s: HFC_PCM_CONN slot %d bank %d (TX) "
3509                             "slot %d bank %d (RX) out of range\n",
3510                             __func__, slot_tx, bank_tx,
3511                             slot_rx, bank_rx);
3512                         ret = -EINVAL;
3513                 }
3514                 break;
3515         case MISDN_CTRL_HFC_PCM_DISC: /* release interface from pcm timeslot */
3516                 if (debug & DEBUG_HFCMULTI_MSG)
3517                         printk(KERN_DEBUG "%s: HFC_PCM_DISC\n",
3518                             __func__);
3519                 hfcmulti_pcm(hc, bch->slot, -1, 0, -1, 0);
3520                 break;
3521         case MISDN_CTRL_HFC_CONF_JOIN: /* join conference (0..7) */
3522                 num = cq->p1 & 0xff;
3523                 if (debug & DEBUG_HFCMULTI_MSG)
3524                         printk(KERN_DEBUG "%s: HFC_CONF_JOIN conf %d\n",
3525                             __func__, num);
3526                 if (num <= 7)
3527                         hfcmulti_conf(hc, bch->slot, num);
3528                 else {
3529                         printk(KERN_WARNING
3530                             "%s: HW_CONF_JOIN conf %d out of range\n",
3531                             __func__, num);
3532                         ret = -EINVAL;
3533                 }
3534                 break;
3535         case MISDN_CTRL_HFC_CONF_SPLIT: /* split conference */
3536                 if (debug & DEBUG_HFCMULTI_MSG)
3537                         printk(KERN_DEBUG "%s: HFC_CONF_SPLIT\n", __func__);
3538                 hfcmulti_conf(hc, bch->slot, -1);
3539                 break;
3540         case MISDN_CTRL_HFC_ECHOCAN_ON:
3541                 if (debug & DEBUG_HFCMULTI_MSG)
3542                         printk(KERN_DEBUG "%s: HFC_ECHOCAN_ON\n", __func__);
3543                 if (test_bit(HFC_CHIP_B410P, &hc->chip))
3544                         vpm_echocan_on(hc, bch->slot, cq->p1);
3545                 else
3546                         ret = -EINVAL;
3547                 break;
3548
3549         case MISDN_CTRL_HFC_ECHOCAN_OFF:
3550                 if (debug & DEBUG_HFCMULTI_MSG)
3551                         printk(KERN_DEBUG "%s: HFC_ECHOCAN_OFF\n",
3552                                 __func__);
3553                 if (test_bit(HFC_CHIP_B410P, &hc->chip))
3554                         vpm_echocan_off(hc, bch->slot);
3555                 else
3556                         ret = -EINVAL;
3557                 break;
3558         default:
3559                 printk(KERN_WARNING "%s: unknown Op %x\n",
3560                     __func__, cq->op);
3561                 ret = -EINVAL;
3562                 break;
3563         }
3564         return ret;
3565 }
3566
3567 static int
3568 hfcm_bctrl(struct mISDNchannel *ch, u_int cmd, void *arg)
3569 {
3570         struct bchannel         *bch = container_of(ch, struct bchannel, ch);
3571         struct hfc_multi        *hc = bch->hw;
3572         int                     err = -EINVAL;
3573         u_long  flags;
3574
3575         if (bch->debug & DEBUG_HW)
3576                 printk(KERN_DEBUG "%s: cmd:%x %p\n",
3577                     __func__, cmd, arg);
3578         switch (cmd) {
3579         case CLOSE_CHANNEL:
3580                 test_and_clear_bit(FLG_OPEN, &bch->Flags);
3581                 if (test_bit(FLG_ACTIVE, &bch->Flags))
3582                         deactivate_bchannel(bch); /* locked there */
3583                 ch->protocol = ISDN_P_NONE;
3584                 ch->peer = NULL;
3585                 module_put(THIS_MODULE);
3586                 err = 0;
3587                 break;
3588         case CONTROL_CHANNEL:
3589                 spin_lock_irqsave(&hc->lock, flags);
3590                 err = channel_bctrl(bch, arg);
3591                 spin_unlock_irqrestore(&hc->lock, flags);
3592                 break;
3593         default:
3594                 printk(KERN_WARNING "%s: unknown prim(%x)\n",
3595                         __func__, cmd);
3596         }
3597         return err;
3598 }
3599
3600 /*
3601  * handle D-channel events
3602  *
3603  * handle state change event
3604  */
3605 static void
3606 ph_state_change(struct dchannel *dch)
3607 {
3608         struct hfc_multi *hc = dch->hw;
3609         int ch, i;
3610
3611         if (!dch) {
3612                 printk(KERN_WARNING "%s: ERROR given dch is NULL\n",
3613                     __func__);
3614                 return;
3615         }
3616         ch = dch->slot;
3617
3618         if (hc->type == 1) {
3619                 if (dch->dev.D.protocol == ISDN_P_TE_E1) {
3620                         if (debug & DEBUG_HFCMULTI_STATE)
3621                                 printk(KERN_DEBUG
3622                                     "%s: E1 TE (id=%d) newstate %x\n",
3623                                     __func__, hc->id, dch->state);
3624                 } else {
3625                         if (debug & DEBUG_HFCMULTI_STATE)
3626                                 printk(KERN_DEBUG
3627                                     "%s: E1 NT (id=%d) newstate %x\n",
3628                                     __func__, hc->id, dch->state);
3629                 }
3630                 switch (dch->state) {
3631                 case (1):
3632                         if (hc->e1_state != 1) {
3633                             for (i = 1; i <= 31; i++) {
3634                                 /* reset fifos on e1 activation */
3635                                 HFC_outb_nodebug(hc, R_FIFO, (i << 1) | 1);
3636                                 HFC_wait_nodebug(hc);
3637                                 HFC_outb_nodebug(hc,
3638                                         R_INC_RES_FIFO, V_RES_F);
3639                                 HFC_wait_nodebug(hc);
3640                             }
3641                         }
3642                         test_and_set_bit(FLG_ACTIVE, &dch->Flags);
3643                         _queue_data(&dch->dev.D, PH_ACTIVATE_IND,
3644                             MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
3645                         break;
3646
3647                 default:
3648                         if (hc->e1_state != 1)
3649                                 return;
3650                         test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
3651                         _queue_data(&dch->dev.D, PH_DEACTIVATE_IND,
3652                             MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
3653                 }
3654                 hc->e1_state = dch->state;
3655         } else {
3656                 if (dch->dev.D.protocol == ISDN_P_TE_S0) {
3657                         if (debug & DEBUG_HFCMULTI_STATE)
3658                                 printk(KERN_DEBUG
3659                                     "%s: S/T TE newstate %x\n",
3660                                     __func__, dch->state);
3661                         switch (dch->state) {
3662                         case (0):
3663                                 l1_event(dch->l1, HW_RESET_IND);
3664                                 break;
3665                         case (3):
3666                                 l1_event(dch->l1, HW_DEACT_IND);
3667                                 break;
3668                         case (5):
3669                         case (8):
3670                                 l1_event(dch->l1, ANYSIGNAL);
3671                                 break;
3672                         case (6):
3673                                 l1_event(dch->l1, INFO2);
3674                                 break;
3675                         case (7):
3676                                 l1_event(dch->l1, INFO4_P8);
3677                                 break;
3678                         }
3679                 } else {
3680                         if (debug & DEBUG_HFCMULTI_STATE)
3681                                 printk(KERN_DEBUG "%s: S/T NT newstate %x\n",
3682                                     __func__, dch->state);
3683                         switch (dch->state) {
3684                         case (2):
3685                                 if (hc->chan[ch].nt_timer == 0) {
3686                                         hc->chan[ch].nt_timer = -1;
3687                                         HFC_outb(hc, R_ST_SEL,
3688                                             hc->chan[ch].port);
3689                                         /* undocumented: delay after R_ST_SEL */
3690                                         udelay(1);
3691                                         HFC_outb(hc, A_ST_WR_STATE, 4 |
3692                                             V_ST_LD_STA); /* G4 */
3693                                         udelay(6); /* wait at least 5,21us */
3694                                         HFC_outb(hc, A_ST_WR_STATE, 4);
3695                                         dch->state = 4;
3696                                 } else {
3697                                         /* one extra count for the next event */
3698                                         hc->chan[ch].nt_timer =
3699                                             nt_t1_count[poll_timer] + 1;
3700                                         HFC_outb(hc, R_ST_SEL,
3701                                             hc->chan[ch].port);
3702                                         /* undocumented: delay after R_ST_SEL */
3703                                         udelay(1);
3704                                         /* allow G2 -> G3 transition */
3705                                         HFC_outb(hc, A_ST_WR_STATE, 2 |
3706                                             V_SET_G2_G3);
3707                                 }
3708                                 break;
3709                         case (1):
3710                                 hc->chan[ch].nt_timer = -1;
3711                                 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
3712                                 _queue_data(&dch->dev.D, PH_DEACTIVATE_IND,
3713                                     MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
3714                                 break;
3715                         case (4):
3716                                 hc->chan[ch].nt_timer = -1;
3717                                 break;
3718                         case (3):
3719                                 hc->chan[ch].nt_timer = -1;
3720                                 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
3721                                 _queue_data(&dch->dev.D, PH_ACTIVATE_IND,
3722                                     MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
3723                                 break;
3724                         }
3725                 }
3726         }
3727 }
3728
3729 /*
3730  * called for card mode init message
3731  */
3732
3733 static void
3734 hfcmulti_initmode(struct dchannel *dch)
3735 {
3736         struct hfc_multi *hc = dch->hw;
3737         u_char          a_st_wr_state, r_e1_wr_sta;
3738         int             i, pt;
3739
3740         if (debug & DEBUG_HFCMULTI_INIT)
3741                 printk(KERN_DEBUG "%s: entered\n", __func__);
3742
3743         if (hc->type == 1) {
3744                 hc->chan[hc->dslot].slot_tx = -1;
3745                 hc->chan[hc->dslot].slot_rx = -1;
3746                 hc->chan[hc->dslot].conf = -1;
3747                 if (hc->dslot) {
3748                         mode_hfcmulti(hc, hc->dslot, dch->dev.D.protocol,
3749                                 -1, 0, -1, 0);
3750                         dch->timer.function = (void *) hfcmulti_dbusy_timer;
3751                         dch->timer.data = (long) dch;
3752                         init_timer(&dch->timer);
3753                 }
3754                 for (i = 1; i <= 31; i++) {
3755                         if (i == hc->dslot)
3756                                 continue;
3757                         hc->chan[i].slot_tx = -1;
3758                         hc->chan[i].slot_rx = -1;
3759                         hc->chan[i].conf = -1;
3760                         mode_hfcmulti(hc, i, ISDN_P_NONE, -1, 0, -1, 0);
3761                 }
3762                 /* E1 */
3763                 if (test_bit(HFC_CFG_REPORT_LOS, &hc->chan[hc->dslot].cfg)) {
3764                         HFC_outb(hc, R_LOS0, 255); /* 2 ms */
3765                         HFC_outb(hc, R_LOS1, 255); /* 512 ms */
3766                 }
3767                 if (test_bit(HFC_CFG_OPTICAL, &hc->chan[hc->dslot].cfg)) {
3768                         HFC_outb(hc, R_RX0, 0);
3769                         hc->hw.r_tx0 = 0 | V_OUT_EN;
3770                 } else {
3771                         HFC_outb(hc, R_RX0, 1);
3772                         hc->hw.r_tx0 = 1 | V_OUT_EN;
3773                 }
3774                 hc->hw.r_tx1 = V_ATX | V_NTRI;
3775                 HFC_outb(hc, R_TX0, hc->hw.r_tx0);
3776                 HFC_outb(hc, R_TX1, hc->hw.r_tx1);
3777                 HFC_outb(hc, R_TX_FR0, 0x00);
3778                 HFC_outb(hc, R_TX_FR1, 0xf8);
3779
3780                 if (test_bit(HFC_CFG_CRC4, &hc->chan[hc->dslot].cfg))
3781                         HFC_outb(hc, R_TX_FR2, V_TX_MF | V_TX_E | V_NEG_E);
3782
3783                 HFC_outb(hc, R_RX_FR0, V_AUTO_RESYNC | V_AUTO_RECO | 0);
3784
3785                 if (test_bit(HFC_CFG_CRC4, &hc->chan[hc->dslot].cfg))
3786                         HFC_outb(hc, R_RX_FR1, V_RX_MF | V_RX_MF_SYNC);
3787
3788                 if (dch->dev.D.protocol == ISDN_P_NT_E1) {
3789                         if (debug & DEBUG_HFCMULTI_INIT)
3790                                 printk(KERN_DEBUG "%s: E1 port is NT-mode\n",
3791                                     __func__);
3792                         r_e1_wr_sta = 0; /* G0 */
3793                         hc->e1_getclock = 0;
3794                 } else {
3795                         if (debug & DEBUG_HFCMULTI_INIT)
3796                                 printk(KERN_DEBUG "%s: E1 port is TE-mode\n",
3797                                     __func__);
3798                         r_e1_wr_sta = 0; /* F0 */
3799                         hc->e1_getclock = 1;
3800                 }
3801                 if (test_bit(HFC_CHIP_RX_SYNC, &hc->chip))
3802                         HFC_outb(hc, R_SYNC_OUT, V_SYNC_E1_RX);
3803                 else
3804                         HFC_outb(hc, R_SYNC_OUT, 0);
3805                 if (test_bit(HFC_CHIP_E1CLOCK_GET, &hc->chip))
3806                         hc->e1_getclock = 1;
3807                 if (test_bit(HFC_CHIP_E1CLOCK_PUT, &hc->chip))
3808                         hc->e1_getclock = 0;
3809                 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
3810                         /* SLAVE (clock master) */
3811                         if (debug & DEBUG_HFCMULTI_INIT)
3812                                 printk(KERN_DEBUG
3813                                     "%s: E1 port is clock master "
3814                                     "(clock from PCM)\n", __func__);
3815                         HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC | V_PCM_SYNC);
3816                 } else {
3817                         if (hc->e1_getclock) {
3818                                 /* MASTER (clock slave) */
3819                                 if (debug & DEBUG_HFCMULTI_INIT)
3820                                         printk(KERN_DEBUG
3821                                             "%s: E1 port is clock slave "
3822                                             "(clock to PCM)\n", __func__);
3823                                 HFC_outb(hc, R_SYNC_CTRL, V_SYNC_OFFS);
3824                         } else {
3825                                 /* MASTER (clock master) */
3826                                 if (debug & DEBUG_HFCMULTI_INIT)
3827                                         printk(KERN_DEBUG "%s: E1 port is "
3828                                             "clock master "
3829                                             "(clock from QUARTZ)\n",
3830                                             __func__);
3831                                 HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC |
3832                                     V_PCM_SYNC | V_JATT_OFF);
3833                                 HFC_outb(hc, R_SYNC_OUT, 0);
3834                         }
3835                 }
3836                 HFC_outb(hc, R_JATT_ATT, 0x9c); /* undoc register */
3837                 HFC_outb(hc, R_PWM_MD, V_PWM0_MD);
3838                 HFC_outb(hc, R_PWM0, 0x50);
3839                 HFC_outb(hc, R_PWM1, 0xff);
3840                 /* state machine setup */
3841                 HFC_outb(hc, R_E1_WR_STA, r_e1_wr_sta | V_E1_LD_STA);
3842                 udelay(6); /* wait at least 5,21us */
3843                 HFC_outb(hc, R_E1_WR_STA, r_e1_wr_sta);
3844                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
3845                         hc->syncronized = 0;
3846                         plxsd_checksync(hc, 0);
3847                 }
3848         } else {
3849                 i = dch->slot;
3850                 hc->chan[i].slot_tx = -1;
3851                 hc->chan[i].slot_rx = -1;
3852                 hc->chan[i].conf = -1;
3853                 mode_hfcmulti(hc, i, dch->dev.D.protocol, -1, 0, -1, 0);
3854                 dch->timer.function = (void *)hfcmulti_dbusy_timer;
3855                 dch->timer.data = (long) dch;
3856                 init_timer(&dch->timer);
3857                 hc->chan[i - 2].slot_tx = -1;
3858                 hc->chan[i - 2].slot_rx = -1;
3859                 hc->chan[i - 2].conf = -1;
3860                 mode_hfcmulti(hc, i - 2, ISDN_P_NONE, -1, 0, -1, 0);
3861                 hc->chan[i - 1].slot_tx = -1;
3862                 hc->chan[i - 1].slot_rx = -1;
3863                 hc->chan[i - 1].conf = -1;
3864                 mode_hfcmulti(hc, i - 1, ISDN_P_NONE, -1, 0, -1, 0);
3865                 /* ST */
3866                 pt = hc->chan[i].port;
3867                 /* select interface */
3868                 HFC_outb(hc, R_ST_SEL, pt);
3869                 /* undocumented: delay after R_ST_SEL */
3870                 udelay(1);
3871                 if (dch->dev.D.protocol == ISDN_P_NT_S0) {
3872                         if (debug & DEBUG_HFCMULTI_INIT)
3873                                 printk(KERN_DEBUG
3874                                     "%s: ST port %d is NT-mode\n",
3875                                     __func__, pt);
3876                         /* clock delay */
3877                         HFC_outb(hc, A_ST_CLK_DLY, clockdelay_nt);
3878                         a_st_wr_state = 1; /* G1 */
3879                         hc->hw.a_st_ctrl0[pt] = V_ST_MD;
3880                 } else {
3881                         if (debug & DEBUG_HFCMULTI_INIT)
3882                                 printk(KERN_DEBUG
3883                                     "%s: ST port %d is TE-mode\n",
3884                                     __func__, pt);
3885                         /* clock delay */
3886                         HFC_outb(hc, A_ST_CLK_DLY, clockdelay_te);
3887                         a_st_wr_state = 2; /* F2 */
3888                         hc->hw.a_st_ctrl0[pt] = 0;
3889                 }
3890                 if (!test_bit(HFC_CFG_NONCAP_TX, &hc->chan[i].cfg))
3891                         hc->hw.a_st_ctrl0[pt] |= V_TX_LI;
3892                 /* line setup */
3893                 HFC_outb(hc, A_ST_CTRL0,  hc->hw.a_st_ctrl0[pt]);
3894                 /* disable E-channel */
3895                 if ((dch->dev.D.protocol == ISDN_P_NT_S0) ||
3896                     test_bit(HFC_CFG_DIS_ECHANNEL, &hc->chan[i].cfg))
3897                         HFC_outb(hc, A_ST_CTRL1, V_E_IGNO);
3898                 else
3899                         HFC_outb(hc, A_ST_CTRL1, 0);
3900                 /* enable B-channel receive */
3901                 HFC_outb(hc, A_ST_CTRL2,  V_B1_RX_EN | V_B2_RX_EN);
3902                 /* state machine setup */
3903                 HFC_outb(hc, A_ST_WR_STATE, a_st_wr_state | V_ST_LD_STA);
3904                 udelay(6); /* wait at least 5,21us */
3905                 HFC_outb(hc, A_ST_WR_STATE, a_st_wr_state);
3906                 hc->hw.r_sci_msk |= 1 << pt;
3907                 /* state machine interrupts */
3908                 HFC_outb(hc, R_SCI_MSK, hc->hw.r_sci_msk);
3909                 /* unset sync on port */
3910                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
3911                         hc->syncronized &=
3912                            ~(1 << hc->chan[dch->slot].port);
3913                         plxsd_checksync(hc, 0);
3914                 }
3915         }
3916         if (debug & DEBUG_HFCMULTI_INIT)
3917                 printk("%s: done\n", __func__);
3918 }
3919
3920
3921 static int
3922 open_dchannel(struct hfc_multi *hc, struct dchannel *dch,
3923     struct channel_req *rq)
3924 {
3925         int     err = 0;
3926         u_long  flags;
3927
3928         if (debug & DEBUG_HW_OPEN)
3929                 printk(KERN_DEBUG "%s: dev(%d) open from %p\n", __func__,
3930                     dch->dev.id, __builtin_return_address(0));
3931         if (rq->protocol == ISDN_P_NONE)
3932                 return -EINVAL;
3933         if ((dch->dev.D.protocol != ISDN_P_NONE) &&
3934             (dch->dev.D.protocol != rq->protocol)) {
3935             if (debug & DEBUG_HFCMULTI_MODE)
3936                 printk(KERN_WARNING "%s: change protocol %x to %x\n",
3937                     __func__, dch->dev.D.protocol, rq->protocol);
3938         }
3939         if ((dch->dev.D.protocol == ISDN_P_TE_S0)
3940          && (rq->protocol != ISDN_P_TE_S0))
3941                 l1_event(dch->l1, CLOSE_CHANNEL);
3942         if (dch->dev.D.protocol != rq->protocol) {
3943                 if (rq->protocol == ISDN_P_TE_S0) {
3944                         err = create_l1(dch, hfcm_l1callback);
3945                         if (err)
3946                                 return err;
3947                 }
3948                 dch->dev.D.protocol = rq->protocol;
3949                 spin_lock_irqsave(&hc->lock, flags);
3950                 hfcmulti_initmode(dch);
3951                 spin_unlock_irqrestore(&hc->lock, flags);
3952         }
3953
3954         if (((rq->protocol == ISDN_P_NT_S0) && (dch->state == 3)) ||
3955             ((rq->protocol == ISDN_P_TE_S0) && (dch->state == 7)) ||
3956             ((rq->protocol == ISDN_P_NT_E1) && (dch->state == 1)) ||
3957             ((rq->protocol == ISDN_P_TE_E1) && (dch->state == 1))) {
3958                 _queue_data(&dch->dev.D, PH_ACTIVATE_IND, MISDN_ID_ANY,
3959                     0, NULL, GFP_KERNEL);
3960         }
3961         rq->ch = &dch->dev.D;
3962         if (!try_module_get(THIS_MODULE))
3963                 printk(KERN_WARNING "%s:cannot get module\n", __func__);
3964         return 0;
3965 }
3966
3967 static int
3968 open_bchannel(struct hfc_multi *hc, struct dchannel *dch,
3969     struct channel_req *rq)
3970 {
3971         struct bchannel *bch;
3972         int             ch;
3973
3974         if (!test_bit(rq->adr.channel, &dch->dev.channelmap[0]))
3975                 return -EINVAL;
3976         if (rq->protocol == ISDN_P_NONE)
3977                 return -EINVAL;
3978         if (hc->type == 1)
3979                 ch = rq->adr.channel;
3980         else
3981                 ch = (rq->adr.channel - 1) + (dch->slot - 2);
3982         bch = hc->chan[ch].bch;
3983         if (!bch) {
3984                 printk(KERN_ERR "%s:internal error ch %d has no bch\n",
3985                     __func__, ch);
3986                 return -EINVAL;
3987         }
3988         if (test_and_set_bit(FLG_OPEN, &bch->Flags))
3989                 return -EBUSY; /* b-channel can be only open once */
3990         bch->ch.protocol = rq->protocol;
3991         hc->chan[ch].rx_off = 0;
3992         rq->ch = &bch->ch;
3993         if (!try_module_get(THIS_MODULE))
3994                 printk(KERN_WARNING "%s:cannot get module\n", __func__);
3995         return 0;
3996 }
3997
3998 /*
3999  * device control function
4000  */
4001 static int
4002 channel_dctrl(struct dchannel *dch, struct mISDN_ctrl_req *cq)
4003 {
4004         int     ret = 0;
4005
4006         switch (cq->op) {
4007         case MISDN_CTRL_GETOP:
4008                 cq->op = 0;
4009                 break;
4010         default:
4011                 printk(KERN_WARNING "%s: unknown Op %x\n",
4012                     __func__, cq->op);
4013                 ret = -EINVAL;
4014                 break;
4015         }
4016         return ret;
4017 }
4018
4019 static int
4020 hfcm_dctrl(struct mISDNchannel *ch, u_int cmd, void *arg)
4021 {
4022         struct mISDNdevice      *dev = container_of(ch, struct mISDNdevice, D);
4023         struct dchannel         *dch = container_of(dev, struct dchannel, dev);
4024         struct hfc_multi        *hc = dch->hw;
4025         struct channel_req      *rq;
4026         int                     err = 0;
4027         u_long                  flags;
4028
4029         if (dch->debug & DEBUG_HW)
4030                 printk(KERN_DEBUG "%s: cmd:%x %p\n",
4031                     __func__, cmd, arg);
4032         switch (cmd) {
4033         case OPEN_CHANNEL:
4034                 rq = arg;
4035                 switch (rq->protocol) {
4036                 case ISDN_P_TE_S0:
4037                 case ISDN_P_NT_S0:
4038                         if (hc->type == 1) {
4039                                 err = -EINVAL;
4040                                 break;
4041                         }
4042                         err = open_dchannel(hc, dch, rq); /* locked there */
4043                         break;
4044                 case ISDN_P_TE_E1:
4045                 case ISDN_P_NT_E1:
4046                         if (hc->type != 1) {
4047                                 err = -EINVAL;
4048                                 break;
4049                         }
4050                         err = open_dchannel(hc, dch, rq); /* locked there */
4051                         break;
4052                 default:
4053                         spin_lock_irqsave(&hc->lock, flags);
4054                         err = open_bchannel(hc, dch, rq);
4055                         spin_unlock_irqrestore(&hc->lock, flags);
4056                 }
4057                 break;
4058         case CLOSE_CHANNEL:
4059                 if (debug & DEBUG_HW_OPEN)
4060                         printk(KERN_DEBUG "%s: dev(%d) close from %p\n",
4061                             __func__, dch->dev.id,
4062                             __builtin_return_address(0));
4063                 module_put(THIS_MODULE);
4064                 break;
4065         case CONTROL_CHANNEL:
4066                 spin_lock_irqsave(&hc->lock, flags);
4067                 err = channel_dctrl(dch, arg);
4068                 spin_unlock_irqrestore(&hc->lock, flags);
4069                 break;
4070         default:
4071                 if (dch->debug & DEBUG_HW)
4072                         printk(KERN_DEBUG "%s: unknown command %x\n",
4073                             __func__, cmd);
4074                 err = -EINVAL;
4075         }
4076         return err;
4077 }
4078
4079 /*
4080  * initialize the card
4081  */
4082
4083 /*
4084  * start timer irq, wait some time and check if we have interrupts.
4085  * if not, reset chip and try again.
4086  */
4087 static int
4088 init_card(struct hfc_multi *hc)
4089 {
4090         int     err = -EIO;
4091         u_long  flags;
4092         u_short *plx_acc;
4093         u_long  plx_flags;
4094
4095         if (debug & DEBUG_HFCMULTI_INIT)
4096                 printk(KERN_DEBUG "%s: entered\n", __func__);
4097
4098         spin_lock_irqsave(&hc->lock, flags);
4099         /* set interrupts but leave global interrupt disabled */
4100         hc->hw.r_irq_ctrl = V_FIFO_IRQ;
4101         disable_hwirq(hc);
4102         spin_unlock_irqrestore(&hc->lock, flags);
4103
4104         if (request_irq(hc->pci_dev->irq, hfcmulti_interrupt, IRQF_SHARED,
4105             "HFC-multi", hc)) {
4106                 printk(KERN_WARNING "mISDN: Could not get interrupt %d.\n",
4107                     hc->pci_dev->irq);
4108                 return -EIO;
4109         }
4110         hc->irq = hc->pci_dev->irq;
4111
4112         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4113                 spin_lock_irqsave(&plx_lock, plx_flags);
4114                 plx_acc = (u_short *)(hc->plx_membase+PLX_INTCSR);
4115                 writew((PLX_INTCSR_PCIINT_ENABLE | PLX_INTCSR_LINTI1_ENABLE),
4116                         plx_acc); /* enable PCI & LINT1 irq */
4117                 spin_unlock_irqrestore(&plx_lock, plx_flags);
4118         }
4119
4120         if (debug & DEBUG_HFCMULTI_INIT)
4121                 printk(KERN_DEBUG "%s: IRQ %d count %d\n",
4122                     __func__, hc->irq, hc->irqcnt);
4123         err = init_chip(hc);
4124         if (err)
4125                 goto error;
4126         /*
4127          * Finally enable IRQ output
4128          * this is only allowed, if an IRQ routine is allready
4129          * established for this HFC, so don't do that earlier
4130          */
4131         spin_lock_irqsave(&hc->lock, flags);
4132         enable_hwirq(hc);
4133         spin_unlock_irqrestore(&hc->lock, flags);
4134         /* printk(KERN_DEBUG "no master irq set!!!\n"); */
4135         set_current_state(TASK_UNINTERRUPTIBLE);
4136         schedule_timeout((100*HZ)/1000); /* Timeout 100ms */
4137         /* turn IRQ off until chip is completely initialized */
4138         spin_lock_irqsave(&hc->lock, flags);
4139         disable_hwirq(hc);
4140         spin_unlock_irqrestore(&hc->lock, flags);
4141         if (debug & DEBUG_HFCMULTI_INIT)
4142                 printk(KERN_DEBUG "%s: IRQ %d count %d\n",
4143                     __func__, hc->irq, hc->irqcnt);
4144         if (hc->irqcnt) {
4145                 if (debug & DEBUG_HFCMULTI_INIT)
4146                         printk(KERN_DEBUG "%s: done\n", __func__);
4147
4148                 return 0;
4149         }
4150         if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
4151                 printk(KERN_INFO "ignoring missing interrupts\n");
4152                 return 0;
4153         }
4154
4155         printk(KERN_ERR "HFC PCI: IRQ(%d) getting no interrupts during init.\n",
4156                 hc->irq);
4157
4158         err = -EIO;
4159
4160 error:
4161         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4162                 spin_lock_irqsave(&plx_lock, plx_flags);
4163                 plx_acc = (u_short *)(hc->plx_membase+PLX_INTCSR);
4164                 writew(0x00, plx_acc); /*disable IRQs*/
4165                 spin_unlock_irqrestore(&plx_lock, plx_flags);
4166         }
4167
4168         if (debug & DEBUG_HFCMULTI_INIT)
4169                 printk(KERN_WARNING "%s: free irq %d\n", __func__, hc->irq);
4170         if (hc->irq) {
4171                 free_irq(hc->irq, hc);
4172                 hc->irq = 0;
4173         }
4174
4175         if (debug & DEBUG_HFCMULTI_INIT)
4176                 printk(KERN_DEBUG "%s: done (err=%d)\n", __func__, err);
4177         return err;
4178 }
4179
4180 /*
4181  * find pci device and set it up
4182  */
4183
4184 static int
4185 setup_pci(struct hfc_multi *hc, struct pci_dev *pdev,
4186                 const struct pci_device_id *ent)
4187 {
4188         struct hm_map   *m = (struct hm_map *)ent->driver_data;
4189
4190         printk(KERN_INFO
4191             "HFC-multi: card manufacturer: '%s' card name: '%s' clock: %s\n",
4192             m->vendor_name, m->card_name, m->clock2 ? "double" : "normal");
4193
4194         hc->pci_dev = pdev;
4195         if (m->clock2)
4196                 test_and_set_bit(HFC_CHIP_CLOCK2, &hc->chip);
4197
4198         if (ent->device == 0xB410) {
4199                 test_and_set_bit(HFC_CHIP_B410P, &hc->chip);
4200                 test_and_set_bit(HFC_CHIP_PCM_MASTER, &hc->chip);
4201                 test_and_clear_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
4202                 hc->slots = 32;
4203         }
4204
4205         if (hc->pci_dev->irq <= 0) {
4206                 printk(KERN_WARNING "HFC-multi: No IRQ for PCI card found.\n");
4207                 return -EIO;
4208         }
4209         if (pci_enable_device(hc->pci_dev)) {
4210                 printk(KERN_WARNING "HFC-multi: Error enabling PCI card.\n");
4211                 return -EIO;
4212         }
4213         hc->leds = m->leds;
4214         hc->ledstate = 0xAFFEAFFE;
4215         hc->opticalsupport = m->opticalsupport;
4216
4217         /* set memory access methods */
4218         if (m->io_mode) /* use mode from card config */
4219                 hc->io_mode = m->io_mode;
4220         switch (hc->io_mode) {
4221         case HFC_IO_MODE_PLXSD:
4222                 test_and_set_bit(HFC_CHIP_PLXSD, &hc->chip);
4223                 hc->slots = 128; /* required */
4224                 /* fall through */
4225         case HFC_IO_MODE_PCIMEM:
4226                 hc->HFC_outb = HFC_outb_pcimem;
4227                 hc->HFC_inb = HFC_inb_pcimem;
4228                 hc->HFC_inw = HFC_inw_pcimem;
4229                 hc->HFC_wait = HFC_wait_pcimem;
4230                 hc->read_fifo = read_fifo_pcimem;
4231                 hc->write_fifo = write_fifo_pcimem;
4232                 break;
4233         case HFC_IO_MODE_REGIO:
4234                 hc->HFC_outb = HFC_outb_regio;
4235                 hc->HFC_inb = HFC_inb_regio;
4236                 hc->HFC_inw = HFC_inw_regio;
4237                 hc->HFC_wait = HFC_wait_regio;
4238                 hc->read_fifo = read_fifo_regio;
4239                 hc->write_fifo = write_fifo_regio;
4240                 break;
4241         default:
4242                 printk(KERN_WARNING "HFC-multi: Invalid IO mode.\n");
4243                 pci_disable_device(hc->pci_dev);
4244                 return -EIO;
4245         }
4246         hc->HFC_outb_nodebug = hc->HFC_outb;
4247         hc->HFC_inb_nodebug = hc->HFC_inb;
4248         hc->HFC_inw_nodebug = hc->HFC_inw;
4249         hc->HFC_wait_nodebug = hc->HFC_wait;
4250 #ifdef HFC_REGISTER_DEBUG
4251         hc->HFC_outb = HFC_outb_debug;
4252         hc->HFC_inb = HFC_inb_debug;
4253         hc->HFC_inw = HFC_inw_debug;
4254         hc->HFC_wait = HFC_wait_debug;
4255 #endif
4256         hc->pci_iobase = 0;
4257         hc->pci_membase = NULL;
4258         hc->plx_membase = NULL;
4259
4260         switch (hc->io_mode) {
4261         case HFC_IO_MODE_PLXSD:
4262                 hc->plx_origmembase =  hc->pci_dev->resource[0].start;
4263                 /* MEMBASE 1 is PLX PCI Bridge */
4264
4265                 if (!hc->plx_origmembase) {
4266                         printk(KERN_WARNING
4267                           "HFC-multi: No IO-Memory for PCI PLX bridge found\n");
4268                         pci_disable_device(hc->pci_dev);
4269                         return -EIO;
4270                 }
4271
4272                 hc->plx_membase = ioremap(hc->plx_origmembase, 0x80);
4273                 if (!hc->plx_membase) {
4274                         printk(KERN_WARNING
4275                             "HFC-multi: failed to remap plx address space. "
4276                             "(internal error)\n");
4277                         pci_disable_device(hc->pci_dev);
4278                         return -EIO;
4279                 }
4280                 printk(KERN_INFO
4281                     "HFC-multi: plx_membase:%#lx plx_origmembase:%#lx\n",
4282                     (u_long)hc->plx_membase, hc->plx_origmembase);
4283
4284                 hc->pci_origmembase =  hc->pci_dev->resource[2].start;
4285                     /* MEMBASE 1 is PLX PCI Bridge */
4286                 if (!hc->pci_origmembase) {
4287                         printk(KERN_WARNING
4288                             "HFC-multi: No IO-Memory for PCI card found\n");
4289                         pci_disable_device(hc->pci_dev);
4290                         return -EIO;
4291                 }
4292
4293                 hc->pci_membase = ioremap(hc->pci_origmembase, 0x400);
4294                 if (!hc->pci_membase) {
4295                         printk(KERN_WARNING "HFC-multi: failed to remap io "
4296                             "address space. (internal error)\n");
4297                         pci_disable_device(hc->pci_dev);
4298                         return -EIO;
4299                 }
4300
4301                 printk(KERN_INFO
4302                     "card %d: defined at MEMBASE %#lx (%#lx) IRQ %d HZ %d "
4303                     "leds-type %d\n",
4304                     hc->id, (u_long)hc->pci_membase, hc->pci_origmembase,
4305                     hc->pci_dev->irq, HZ, hc->leds);
4306                 pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_MEMIO);
4307                 break;
4308         case HFC_IO_MODE_PCIMEM:
4309                 hc->pci_origmembase = hc->pci_dev->resource[1].start;
4310                 if (!hc->pci_origmembase) {
4311                         printk(KERN_WARNING
4312                             "HFC-multi: No IO-Memory for PCI card found\n");
4313                         pci_disable_device(hc->pci_dev);
4314                         return -EIO;
4315                 }
4316
4317                 hc->pci_membase = ioremap(hc->pci_origmembase, 256);
4318                 if (!hc->pci_membase) {
4319                         printk(KERN_WARNING
4320                             "HFC-multi: failed to remap io address space. "
4321                             "(internal error)\n");
4322                         pci_disable_device(hc->pci_dev);
4323                         return -EIO;
4324                 }
4325                 printk(KERN_INFO "card %d: defined at MEMBASE %#lx (%#lx) IRQ %d "
4326                     "HZ %d leds-type %d\n", hc->id, (u_long)hc->pci_membase,
4327                     hc->pci_origmembase, hc->pci_dev->irq, HZ, hc->leds);
4328                 pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_MEMIO);
4329                 break;
4330         case HFC_IO_MODE_REGIO:
4331                 hc->pci_iobase = (u_int) hc->pci_dev->resource[0].start;
4332                 if (!hc->pci_iobase) {
4333                         printk(KERN_WARNING
4334                                 "HFC-multi: No IO for PCI card found\n");
4335                         pci_disable_device(hc->pci_dev);
4336                         return -EIO;
4337                 }
4338
4339                 if (!request_region(hc->pci_iobase, 8, "hfcmulti")) {
4340                         printk(KERN_WARNING "HFC-multi: failed to request "
4341                             "address space at 0x%08lx (internal error)\n",
4342                             hc->pci_iobase);
4343                         pci_disable_device(hc->pci_dev);
4344                         return -EIO;
4345                 }
4346
4347                 printk(KERN_INFO
4348                     "%s %s: defined at IOBASE %#x IRQ %d HZ %d leds-type %d\n",
4349                     m->vendor_name, m->card_name, (u_int) hc->pci_iobase,
4350                     hc->pci_dev->irq, HZ, hc->leds);
4351                 pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_REGIO);
4352                 break;
4353         default:
4354                 printk(KERN_WARNING "HFC-multi: Invalid IO mode.\n");
4355                 pci_disable_device(hc->pci_dev);
4356                 return -EIO;
4357         }
4358
4359         pci_set_drvdata(hc->pci_dev, hc);
4360
4361         /* At this point the needed PCI config is done */
4362         /* fifos are still not enabled */
4363         return 0;
4364 }
4365
4366
4367 /*
4368  * remove port
4369  */
4370
4371 static void
4372 release_port(struct hfc_multi *hc, struct dchannel *dch)
4373 {
4374         int     pt, ci, i = 0;
4375         u_long  flags;
4376         struct bchannel *pb;
4377
4378         ci = dch->slot;
4379         pt = hc->chan[ci].port;
4380
4381         if (debug & DEBUG_HFCMULTI_INIT)
4382                 printk(KERN_DEBUG "%s: entered for port %d\n",
4383                         __func__, pt + 1);
4384
4385         if (pt >= hc->ports) {
4386                 printk(KERN_WARNING "%s: ERROR port out of range (%d).\n",
4387                      __func__, pt + 1);
4388                 return;
4389         }
4390
4391         if (debug & DEBUG_HFCMULTI_INIT)
4392                 printk(KERN_DEBUG "%s: releasing port=%d\n",
4393                     __func__, pt + 1);
4394
4395         if (dch->dev.D.protocol == ISDN_P_TE_S0)
4396                 l1_event(dch->l1, CLOSE_CHANNEL);
4397
4398         hc->chan[ci].dch = NULL;
4399
4400         if (hc->created[pt]) {
4401                 hc->created[pt] = 0;
4402                 mISDN_unregister_device(&dch->dev);
4403         }
4404
4405         spin_lock_irqsave(&hc->lock, flags);
4406
4407         if (dch->timer.function) {
4408                 del_timer(&dch->timer);
4409                 dch->timer.function = NULL;
4410         }
4411
4412         if (hc->type == 1) { /* E1 */
4413                 /* remove sync */
4414                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4415                         hc->syncronized = 0;
4416                         plxsd_checksync(hc, 1);
4417                 }
4418                 /* free channels */
4419                 for (i = 0; i <= 31; i++) {
4420                         if (hc->chan[i].bch) {
4421                                 if (debug & DEBUG_HFCMULTI_INIT)
4422                                         printk(KERN_DEBUG
4423                                             "%s: free port %d channel %d\n",
4424                                             __func__, hc->chan[i].port+1, i);
4425                                 pb = hc->chan[i].bch;
4426                                 hc->chan[i].bch = NULL;
4427                                 spin_unlock_irqrestore(&hc->lock, flags);
4428                                 mISDN_freebchannel(pb);
4429                                 kfree(pb);
4430                                 kfree(hc->chan[i].coeff);
4431                                 spin_lock_irqsave(&hc->lock, flags);
4432                         }
4433                 }
4434         } else {
4435                 /* remove sync */
4436                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4437                         hc->syncronized &=
4438                            ~(1 << hc->chan[ci].port);
4439                         plxsd_checksync(hc, 1);
4440                 }
4441                 /* free channels */
4442                 if (hc->chan[ci - 2].bch) {
4443                         if (debug & DEBUG_HFCMULTI_INIT)
4444                                 printk(KERN_DEBUG
4445                                     "%s: free port %d channel %d\n",
4446                                     __func__, hc->chan[ci - 2].port+1,
4447                                     ci - 2);
4448                         pb = hc->chan[ci - 2].bch;
4449                         hc->chan[ci - 2].bch = NULL;
4450                         spin_unlock_irqrestore(&hc->lock, flags);
4451                         mISDN_freebchannel(pb);
4452                         kfree(pb);
4453                         kfree(hc->chan[ci - 2].coeff);
4454                         spin_lock_irqsave(&hc->lock, flags);
4455                 }
4456                 if (hc->chan[ci - 1].bch) {
4457                         if (debug & DEBUG_HFCMULTI_INIT)
4458                                 printk(KERN_DEBUG
4459                                     "%s: free port %d channel %d\n",
4460                                     __func__, hc->chan[ci - 1].port+1,
4461                                     ci - 1);
4462                         pb = hc->chan[ci - 1].bch;
4463                         hc->chan[ci - 1].bch = NULL;
4464                         spin_unlock_irqrestore(&hc->lock, flags);
4465                         mISDN_freebchannel(pb);
4466                         kfree(pb);
4467                         kfree(hc->chan[ci - 1].coeff);
4468                         spin_lock_irqsave(&hc->lock, flags);
4469                 }
4470         }
4471
4472         spin_unlock_irqrestore(&hc->lock, flags);
4473
4474         if (debug & DEBUG_HFCMULTI_INIT)
4475                 printk(KERN_DEBUG "%s: free port %d channel D\n", __func__, pt);
4476         mISDN_freedchannel(dch);
4477         kfree(dch);
4478
4479         if (debug & DEBUG_HFCMULTI_INIT)
4480                 printk(KERN_DEBUG "%s: done!\n", __func__);
4481 }
4482
4483 static void
4484 release_card(struct hfc_multi *hc)
4485 {
4486         u_long  flags;
4487         int     ch;
4488
4489         if (debug & DEBUG_HFCMULTI_INIT)
4490                 printk(KERN_WARNING "%s: release card (%d) entered\n",
4491                     __func__, hc->id);
4492
4493         spin_lock_irqsave(&hc->lock, flags);
4494         disable_hwirq(hc);
4495         spin_unlock_irqrestore(&hc->lock, flags);
4496
4497         udelay(1000);
4498
4499         /* dimm leds */
4500         if (hc->leds)
4501                 hfcmulti_leds(hc);
4502
4503         /* disable D-channels & B-channels */
4504         if (debug & DEBUG_HFCMULTI_INIT)
4505                 printk(KERN_DEBUG "%s: disable all channels (d and b)\n",
4506                     __func__);
4507         for (ch = 0; ch <= 31; ch++) {
4508                 if (hc->chan[ch].dch)
4509                         release_port(hc, hc->chan[ch].dch);
4510         }
4511
4512         /* release hardware & irq */
4513         if (hc->irq) {
4514                 if (debug & DEBUG_HFCMULTI_INIT)
4515                         printk(KERN_WARNING "%s: free irq %d\n",
4516                             __func__, hc->irq);
4517                 free_irq(hc->irq, hc);
4518                 hc->irq = 0;
4519
4520         }
4521         release_io_hfcmulti(hc);
4522
4523         if (debug & DEBUG_HFCMULTI_INIT)
4524                 printk(KERN_WARNING "%s: remove instance from list\n",
4525                      __func__);
4526         list_del(&hc->list);
4527
4528         if (debug & DEBUG_HFCMULTI_INIT)
4529                 printk(KERN_WARNING "%s: delete instance\n", __func__);
4530         if (hc == syncmaster)
4531                 syncmaster = NULL;
4532         kfree(hc);
4533         if (debug & DEBUG_HFCMULTI_INIT)
4534                 printk(KERN_WARNING "%s: card successfully removed\n",
4535                     __func__);
4536 }
4537
4538 static int
4539 init_e1_port(struct hfc_multi *hc, struct hm_map *m)
4540 {
4541         struct dchannel *dch;
4542         struct bchannel *bch;
4543         int             ch, ret = 0;
4544         char            name[MISDN_MAX_IDLEN];
4545
4546         dch = kzalloc(sizeof(struct dchannel), GFP_KERNEL);
4547         if (!dch)
4548                 return -ENOMEM;
4549         dch->debug = debug;
4550         mISDN_initdchannel(dch, MAX_DFRAME_LEN_L1, ph_state_change);
4551         dch->hw = hc;
4552         dch->dev.Dprotocols = (1 << ISDN_P_TE_E1) | (1 << ISDN_P_NT_E1);
4553         dch->dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
4554             (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK));
4555         dch->dev.D.send = handle_dmsg;
4556         dch->dev.D.ctrl = hfcm_dctrl;
4557         dch->dev.nrbchan = (hc->dslot)?30:31;
4558         dch->slot = hc->dslot;
4559         hc->chan[hc->dslot].dch = dch;
4560         hc->chan[hc->dslot].port = 0;
4561         hc->chan[hc->dslot].nt_timer = -1;
4562         for (ch = 1; ch <= 31; ch++) {
4563                 if (ch == hc->dslot) /* skip dchannel */
4564                         continue;
4565                 bch = kzalloc(sizeof(struct bchannel), GFP_KERNEL);
4566                 if (!bch) {
4567                         printk(KERN_ERR "%s: no memory for bchannel\n",
4568                             __func__);
4569                         ret = -ENOMEM;
4570                         goto free_chan;
4571                 }
4572                 hc->chan[ch].coeff = kzalloc(512, GFP_KERNEL);
4573                 if (!hc->chan[ch].coeff) {
4574                         printk(KERN_ERR "%s: no memory for coeffs\n",
4575                             __func__);
4576                         ret = -ENOMEM;
4577                         goto free_chan;
4578                 }
4579                 bch->nr = ch;
4580                 bch->slot = ch;
4581                 bch->debug = debug;
4582                 mISDN_initbchannel(bch, MAX_DATA_MEM);
4583                 bch->hw = hc;
4584                 bch->ch.send = handle_bmsg;
4585                 bch->ch.ctrl = hfcm_bctrl;
4586                 bch->ch.nr = ch;
4587                 list_add(&bch->ch.list, &dch->dev.bchannels);
4588                 hc->chan[ch].bch = bch;
4589                 hc->chan[ch].port = 0;
4590                 test_and_set_bit(bch->nr, &dch->dev.channelmap[0]);
4591         }
4592         /* set optical line type */
4593         if (port[Port_cnt] & 0x001) {
4594                 if (!m->opticalsupport)  {
4595                         printk(KERN_INFO
4596                             "This board has no optical "
4597                             "support\n");
4598                 } else {
4599                         if (debug & DEBUG_HFCMULTI_INIT)
4600                                 printk(KERN_DEBUG
4601                                     "%s: PORT set optical "
4602                                     "interfacs: card(%d) "
4603                                     "port(%d)\n",
4604                                     __func__,
4605                                     HFC_cnt + 1, 1);
4606                         test_and_set_bit(HFC_CFG_OPTICAL,
4607                             &hc->chan[hc->dslot].cfg);
4608                 }
4609         }
4610         /* set LOS report */
4611         if (port[Port_cnt] & 0x004) {
4612                 if (debug & DEBUG_HFCMULTI_INIT)
4613                         printk(KERN_DEBUG "%s: PORT set "
4614                             "LOS report: card(%d) port(%d)\n",
4615                             __func__, HFC_cnt + 1, 1);
4616                 test_and_set_bit(HFC_CFG_REPORT_LOS,
4617                     &hc->chan[hc->dslot].cfg);
4618         }
4619         /* set AIS report */
4620         if (port[Port_cnt] & 0x008) {
4621                 if (debug & DEBUG_HFCMULTI_INIT)
4622                         printk(KERN_DEBUG "%s: PORT set "
4623                             "AIS report: card(%d) port(%d)\n",
4624                             __func__, HFC_cnt + 1, 1);
4625                 test_and_set_bit(HFC_CFG_REPORT_AIS,
4626                     &hc->chan[hc->dslot].cfg);
4627         }
4628         /* set SLIP report */
4629         if (port[Port_cnt] & 0x010) {
4630                 if (debug & DEBUG_HFCMULTI_INIT)
4631                         printk(KERN_DEBUG
4632                             "%s: PORT set SLIP report: "
4633                             "card(%d) port(%d)\n",
4634                             __func__, HFC_cnt + 1, 1);
4635                 test_and_set_bit(HFC_CFG_REPORT_SLIP,
4636                     &hc->chan[hc->dslot].cfg);
4637         }
4638         /* set RDI report */
4639         if (port[Port_cnt] & 0x020) {
4640                 if (debug & DEBUG_HFCMULTI_INIT)
4641                         printk(KERN_DEBUG
4642                             "%s: PORT set RDI report: "
4643                             "card(%d) port(%d)\n",
4644                             __func__, HFC_cnt + 1, 1);
4645                 test_and_set_bit(HFC_CFG_REPORT_RDI,
4646                     &hc->chan[hc->dslot].cfg);
4647         }
4648         /* set CRC-4 Mode */
4649         if (!(port[Port_cnt] & 0x100)) {
4650                 if (debug & DEBUG_HFCMULTI_INIT)
4651                         printk(KERN_DEBUG "%s: PORT turn on CRC4 report:"
4652                                 " card(%d) port(%d)\n",
4653                                 __func__, HFC_cnt + 1, 1);
4654                 test_and_set_bit(HFC_CFG_CRC4,
4655                     &hc->chan[hc->dslot].cfg);
4656         } else {
4657                 if (debug & DEBUG_HFCMULTI_INIT)
4658                         printk(KERN_DEBUG "%s: PORT turn off CRC4"
4659                                 " report: card(%d) port(%d)\n",
4660                                 __func__, HFC_cnt + 1, 1);
4661         }
4662         /* set forced clock */
4663         if (port[Port_cnt] & 0x0200) {
4664                 if (debug & DEBUG_HFCMULTI_INIT)
4665                         printk(KERN_DEBUG "%s: PORT force getting clock from "
4666                                 "E1: card(%d) port(%d)\n",
4667                                 __func__, HFC_cnt + 1, 1);
4668                 test_and_set_bit(HFC_CHIP_E1CLOCK_GET, &hc->chip);
4669         } else
4670         if (port[Port_cnt] & 0x0400) {
4671                 if (debug & DEBUG_HFCMULTI_INIT)
4672                         printk(KERN_DEBUG "%s: PORT force putting clock to "
4673                                 "E1: card(%d) port(%d)\n",
4674                                 __func__, HFC_cnt + 1, 1);
4675                 test_and_set_bit(HFC_CHIP_E1CLOCK_PUT, &hc->chip);
4676         }
4677         /* set JATT PLL */
4678         if (port[Port_cnt] & 0x0800) {
4679                 if (debug & DEBUG_HFCMULTI_INIT)
4680                         printk(KERN_DEBUG "%s: PORT disable JATT PLL on "
4681                                 "E1: card(%d) port(%d)\n",
4682                                 __func__, HFC_cnt + 1, 1);
4683                 test_and_set_bit(HFC_CHIP_RX_SYNC, &hc->chip);
4684         }
4685         /* set elastic jitter buffer */
4686         if (port[Port_cnt] & 0x3000) {
4687                 hc->chan[hc->dslot].jitter = (port[Port_cnt]>>12) & 0x3;
4688                 if (debug & DEBUG_HFCMULTI_INIT)
4689                         printk(KERN_DEBUG
4690                             "%s: PORT set elastic "
4691                             "buffer to %d: card(%d) port(%d)\n",
4692                             __func__, hc->chan[hc->dslot].jitter,
4693                             HFC_cnt + 1, 1);
4694         } else
4695                 hc->chan[hc->dslot].jitter = 2; /* default */
4696         snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-e1.%d", HFC_cnt + 1);
4697         ret = mISDN_register_device(&dch->dev, name);
4698         if (ret)
4699                 goto free_chan;
4700         hc->created[0] = 1;
4701         return ret;
4702 free_chan:
4703         release_port(hc, dch);
4704         return ret;
4705 }
4706
4707 static int
4708 init_multi_port(struct hfc_multi *hc, int pt)
4709 {
4710         struct dchannel *dch;
4711         struct bchannel *bch;
4712         int             ch, i, ret = 0;
4713         char            name[MISDN_MAX_IDLEN];
4714
4715         dch = kzalloc(sizeof(struct dchannel), GFP_KERNEL);
4716         if (!dch)
4717                 return -ENOMEM;
4718         dch->debug = debug;
4719         mISDN_initdchannel(dch, MAX_DFRAME_LEN_L1, ph_state_change);
4720         dch->hw = hc;
4721         dch->dev.Dprotocols = (1 << ISDN_P_TE_S0) | (1 << ISDN_P_NT_S0);
4722         dch->dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
4723             (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK));
4724         dch->dev.D.send = handle_dmsg;
4725         dch->dev.D.ctrl = hfcm_dctrl;
4726         dch->dev.nrbchan = 2;
4727         i = pt << 2;
4728         dch->slot = i + 2;
4729         hc->chan[i + 2].dch = dch;
4730         hc->chan[i + 2].port = pt;
4731         hc->chan[i + 2].nt_timer = -1;
4732         for (ch = 0; ch < dch->dev.nrbchan; ch++) {
4733                 bch = kzalloc(sizeof(struct bchannel), GFP_KERNEL);
4734                 if (!bch) {
4735                         printk(KERN_ERR "%s: no memory for bchannel\n",
4736                             __func__);
4737                         ret = -ENOMEM;
4738                         goto free_chan;
4739                 }
4740                 hc->chan[i + ch].coeff = kzalloc(512, GFP_KERNEL);
4741                 if (!hc->chan[i + ch].coeff) {
4742                         printk(KERN_ERR "%s: no memory for coeffs\n",
4743                             __func__);
4744                         ret = -ENOMEM;
4745                         goto free_chan;
4746                 }
4747                 bch->nr = ch + 1;
4748                 bch->slot = i + ch;
4749                 bch->debug = debug;
4750                 mISDN_initbchannel(bch, MAX_DATA_MEM);
4751                 bch->hw = hc;
4752                 bch->ch.send = handle_bmsg;
4753                 bch->ch.ctrl = hfcm_bctrl;
4754                 bch->ch.nr = ch + 1;
4755                 list_add(&bch->ch.list, &dch->dev.bchannels);
4756                 hc->chan[i + ch].bch = bch;
4757                 hc->chan[i + ch].port = pt;
4758                 test_and_set_bit(bch->nr, &dch->dev.channelmap[0]);
4759         }
4760         /* set master clock */
4761         if (port[Port_cnt] & 0x001) {
4762                 if (debug & DEBUG_HFCMULTI_INIT)
4763                         printk(KERN_DEBUG
4764                             "%s: PROTOCOL set master clock: "
4765                             "card(%d) port(%d)\n",
4766                             __func__, HFC_cnt + 1, pt + 1);
4767                 if (dch->dev.D.protocol != ISDN_P_TE_S0) {
4768                         printk(KERN_ERR "Error: Master clock "
4769                             "for port(%d) of card(%d) is only"
4770                             " possible with TE-mode\n",
4771                             pt + 1, HFC_cnt + 1);
4772                         ret = -EINVAL;
4773                         goto free_chan;
4774                 }
4775                 if (hc->masterclk >= 0) {
4776                         printk(KERN_ERR "Error: Master clock "
4777                             "for port(%d) of card(%d) already "
4778                             "defined for port(%d)\n",
4779                             pt + 1, HFC_cnt + 1, hc->masterclk+1);
4780                         ret = -EINVAL;
4781                         goto free_chan;
4782                 }
4783                 hc->masterclk = pt;
4784         }
4785         /* set transmitter line to non capacitive */
4786         if (port[Port_cnt] & 0x002) {
4787                 if (debug & DEBUG_HFCMULTI_INIT)
4788                         printk(KERN_DEBUG
4789                             "%s: PROTOCOL set non capacitive "
4790                             "transmitter: card(%d) port(%d)\n",
4791                             __func__, HFC_cnt + 1, pt + 1);
4792                 test_and_set_bit(HFC_CFG_NONCAP_TX,
4793                     &hc->chan[i + 2].cfg);
4794         }
4795         /* disable E-channel */
4796         if (port[Port_cnt] & 0x004) {
4797         if (debug & DEBUG_HFCMULTI_INIT)
4798                         printk(KERN_DEBUG
4799                             "%s: PROTOCOL disable E-channel: "
4800                             "card(%d) port(%d)\n",
4801                             __func__, HFC_cnt + 1, pt + 1);
4802                 test_and_set_bit(HFC_CFG_DIS_ECHANNEL,
4803                     &hc->chan[i + 2].cfg);
4804         }
4805         snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-%ds.%d/%d",
4806                 hc->type, HFC_cnt + 1, pt + 1);
4807         ret = mISDN_register_device(&dch->dev, name);
4808         if (ret)
4809                 goto free_chan;
4810         hc->created[pt] = 1;
4811         return ret;
4812 free_chan:
4813         release_port(hc, dch);
4814         return ret;
4815 }
4816
4817 static int
4818 hfcmulti_init(struct pci_dev *pdev, const struct pci_device_id *ent)
4819 {
4820         struct hm_map   *m = (struct hm_map *)ent->driver_data;
4821         int             ret_err = 0;
4822         int             pt;
4823         struct hfc_multi        *hc;
4824         u_long          flags;
4825         u_char          dips = 0, pmj = 0; /* dip settings, port mode Jumpers */
4826
4827         if (HFC_cnt >= MAX_CARDS) {
4828                 printk(KERN_ERR "too many cards (max=%d).\n",
4829                         MAX_CARDS);
4830                 return -EINVAL;
4831         }
4832         if ((type[HFC_cnt] & 0xff) && (type[HFC_cnt] & 0xff) != m->type) {
4833                 printk(KERN_WARNING "HFC-MULTI: Card '%s:%s' type %d found but "
4834                     "type[%d] %d was supplied as module parameter\n",
4835                     m->vendor_name, m->card_name, m->type, HFC_cnt,
4836                     type[HFC_cnt] & 0xff);
4837                 printk(KERN_WARNING "HFC-MULTI: Load module without parameters "
4838                         "first, to see cards and their types.");
4839                 return -EINVAL;
4840         }
4841         if (debug & DEBUG_HFCMULTI_INIT)
4842                 printk(KERN_DEBUG "%s: Registering %s:%s chip type %d (0x%x)\n",
4843                     __func__, m->vendor_name, m->card_name, m->type,
4844                     type[HFC_cnt]);
4845
4846         /* allocate card+fifo structure */
4847         hc = kzalloc(sizeof(struct hfc_multi), GFP_KERNEL);
4848         if (!hc) {
4849                 printk(KERN_ERR "No kmem for HFC-Multi card\n");
4850                 return -ENOMEM;
4851         }
4852         spin_lock_init(&hc->lock);
4853         hc->mtyp = m;
4854         hc->type =  m->type;
4855         hc->ports = m->ports;
4856         hc->id = HFC_cnt;
4857         hc->pcm = pcm[HFC_cnt];
4858         hc->io_mode = iomode[HFC_cnt];
4859         if (dslot[HFC_cnt] < 0) {
4860                 hc->dslot = 0;
4861                 printk(KERN_INFO "HFC-E1 card has disabled D-channel, but "
4862                         "31 B-channels\n");
4863         } if (dslot[HFC_cnt] > 0 && dslot[HFC_cnt] < 32) {
4864                 hc->dslot = dslot[HFC_cnt];
4865                 printk(KERN_INFO "HFC-E1 card has alternating D-channel on "
4866                         "time slot %d\n", dslot[HFC_cnt]);
4867         } else
4868                 hc->dslot = 16;
4869
4870         /* set chip specific features */
4871         hc->masterclk = -1;
4872         if (type[HFC_cnt] & 0x100) {
4873                 test_and_set_bit(HFC_CHIP_ULAW, &hc->chip);
4874                 silence = 0xff; /* ulaw silence */
4875         } else
4876                 silence = 0x2a; /* alaw silence */
4877         if (!(type[HFC_cnt] & 0x200))
4878                 test_and_set_bit(HFC_CHIP_DTMF, &hc->chip);
4879
4880         if (type[HFC_cnt] & 0x800)
4881                 test_and_set_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
4882         if (type[HFC_cnt] & 0x1000) {
4883                 test_and_set_bit(HFC_CHIP_PCM_MASTER, &hc->chip);
4884                 test_and_clear_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
4885         }
4886         if (type[HFC_cnt] & 0x4000)
4887                 test_and_set_bit(HFC_CHIP_EXRAM_128, &hc->chip);
4888         if (type[HFC_cnt] & 0x8000)
4889                 test_and_set_bit(HFC_CHIP_EXRAM_512, &hc->chip);
4890         hc->slots = 32;
4891         if (type[HFC_cnt] & 0x10000)
4892                 hc->slots = 64;
4893         if (type[HFC_cnt] & 0x20000)
4894                 hc->slots = 128;
4895         if (type[HFC_cnt] & 0x80000) {
4896                 test_and_set_bit(HFC_CHIP_WATCHDOG, &hc->chip);
4897                 hc->wdcount = 0;
4898                 hc->wdbyte = V_GPIO_OUT2;
4899                 printk(KERN_NOTICE "Watchdog enabled\n");
4900         }
4901
4902         /* setup pci, hc->slots may change due to PLXSD */
4903         ret_err = setup_pci(hc, pdev, ent);
4904         if (ret_err) {
4905                 if (hc == syncmaster)
4906                         syncmaster = NULL;
4907                 kfree(hc);
4908                 return ret_err;
4909         }
4910
4911         /* crate channels */
4912         for (pt = 0; pt < hc->ports; pt++) {
4913                 if (Port_cnt >= MAX_PORTS) {
4914                         printk(KERN_ERR "too many ports (max=%d).\n",
4915                                 MAX_PORTS);
4916                         ret_err = -EINVAL;
4917                         goto free_card;
4918                 }
4919                 if (hc->type == 1)
4920                         ret_err = init_e1_port(hc, m);
4921                 else
4922                         ret_err = init_multi_port(hc, pt);
4923                 if (debug & DEBUG_HFCMULTI_INIT)
4924                         printk(KERN_DEBUG
4925                             "%s: Registering D-channel, card(%d) port(%d)"
4926                             "result %d\n",
4927                             __func__, HFC_cnt + 1, pt, ret_err);
4928
4929                 if (ret_err) {
4930                         while (pt) { /* release already registered ports */
4931                                 pt--;
4932                                 release_port(hc, hc->chan[(pt << 2) + 2].dch);
4933                         }
4934                         goto free_card;
4935                 }
4936                 Port_cnt++;
4937         }
4938
4939         /* disp switches */
4940         switch (m->dip_type) {
4941         case DIP_4S:
4942                 /*
4943                  * get DIP Setting for beroNet 1S/2S/4S cards
4944                  *  check if Port Jumper config matches
4945                  * module param 'protocol'
4946                  * DIP Setting: (collect GPIO 13/14/15 (R_GPIO_IN1) +
4947                  * GPI 19/23 (R_GPI_IN2))
4948                  */
4949                 dips = ((~HFC_inb(hc, R_GPIO_IN1) & 0xE0) >> 5) |
4950                         ((~HFC_inb(hc, R_GPI_IN2) & 0x80) >> 3) |
4951                         (~HFC_inb(hc, R_GPI_IN2) & 0x08);
4952
4953                 /* Port mode (TE/NT) jumpers */
4954                 pmj = ((HFC_inb(hc, R_GPI_IN3) >> 4)  & 0xf);
4955
4956                 if (test_bit(HFC_CHIP_B410P, &hc->chip))
4957                         pmj = ~pmj & 0xf;
4958
4959                 printk(KERN_INFO "%s: %s DIPs(0x%x) jumpers(0x%x)\n",
4960                         m->vendor_name, m->card_name, dips, pmj);
4961                 break;
4962         case DIP_8S:
4963                 /*
4964                  * get DIP Setting for beroNet 8S0+ cards
4965                  *
4966                  * enable PCI auxbridge function
4967                  */
4968                 HFC_outb(hc, R_BRG_PCM_CFG, 1 | V_PCM_CLK);
4969                 /* prepare access to auxport */
4970                 outw(0x4000, hc->pci_iobase + 4);
4971                 /*
4972                  * some dummy reads are required to
4973                  * read valid DIP switch data
4974                  */
4975                 dips = inb(hc->pci_iobase);
4976                 dips = inb(hc->pci_iobase);
4977                 dips = inb(hc->pci_iobase);
4978                 dips = ~inb(hc->pci_iobase) & 0x3F;
4979                 outw(0x0, hc->pci_iobase + 4);
4980                 /* disable PCI auxbridge function */
4981                 HFC_outb(hc, R_BRG_PCM_CFG, V_PCM_CLK);
4982                 printk(KERN_INFO "%s: %s DIPs(0x%x)\n",
4983                     m->vendor_name, m->card_name, dips);
4984                 break;
4985         case DIP_E1:
4986                 /*
4987                  * get DIP Setting for beroNet E1 cards
4988                  * DIP Setting: collect GPI 4/5/6/7 (R_GPI_IN0)
4989                  */
4990                 dips = (~HFC_inb(hc, R_GPI_IN0) & 0xF0)>>4;
4991                 printk(KERN_INFO "%s: %s DIPs(0x%x)\n",
4992                     m->vendor_name, m->card_name, dips);
4993                 break;
4994         }
4995
4996         /* add to list */
4997         spin_lock_irqsave(&HFClock, flags);
4998         list_add_tail(&hc->list, &HFClist);
4999         spin_unlock_irqrestore(&HFClock, flags);
5000
5001         /* initialize hardware */
5002         ret_err = init_card(hc);
5003         if (ret_err) {
5004                 printk(KERN_ERR "init card returns %d\n", ret_err);
5005                 release_card(hc);
5006                 return ret_err;
5007         }
5008
5009         /* start IRQ and return */
5010         spin_lock_irqsave(&hc->lock, flags);
5011         enable_hwirq(hc);
5012         spin_unlock_irqrestore(&hc->lock, flags);
5013         return 0;
5014
5015 free_card:
5016         release_io_hfcmulti(hc);
5017         if (hc == syncmaster)
5018                 syncmaster = NULL;
5019         kfree(hc);
5020         return ret_err;
5021 }
5022
5023 static void __devexit hfc_remove_pci(struct pci_dev *pdev)
5024 {
5025         struct hfc_multi        *card = pci_get_drvdata(pdev);
5026         u_long                  flags;
5027
5028         if (debug)
5029                 printk(KERN_INFO "removing hfc_multi card vendor:%x "
5030                     "device:%x subvendor:%x subdevice:%x\n",
5031                     pdev->vendor, pdev->device,
5032                     pdev->subsystem_vendor, pdev->subsystem_device);
5033
5034         if (card) {
5035                 spin_lock_irqsave(&HFClock, flags);
5036                 release_card(card);
5037                 spin_unlock_irqrestore(&HFClock, flags);
5038         }  else {
5039                 if (debug)
5040                         printk(KERN_WARNING "%s: drvdata allready removed\n",
5041                             __func__);
5042         }
5043 }
5044
5045 #define VENDOR_CCD      "Cologne Chip AG"
5046 #define VENDOR_BN       "beroNet GmbH"
5047 #define VENDOR_DIG      "Digium Inc."
5048 #define VENDOR_JH       "Junghanns.NET GmbH"
5049 #define VENDOR_PRIM     "PrimuX"
5050
5051 static const struct hm_map hfcm_map[] = {
5052 /*0*/   {VENDOR_BN, "HFC-1S Card (mini PCI)", 4, 1, 1, 3, 0, DIP_4S, 0},
5053 /*1*/   {VENDOR_BN, "HFC-2S Card", 4, 2, 1, 3, 0, DIP_4S},
5054 /*2*/   {VENDOR_BN, "HFC-2S Card (mini PCI)", 4, 2, 1, 3, 0, DIP_4S, 0},
5055 /*3*/   {VENDOR_BN, "HFC-4S Card", 4, 4, 1, 2, 0, DIP_4S, 0},
5056 /*4*/   {VENDOR_BN, "HFC-4S Card (mini PCI)", 4, 4, 1, 2, 0, 0, 0},
5057 /*5*/   {VENDOR_CCD, "HFC-4S Eval (old)", 4, 4, 0, 0, 0, 0, 0},
5058 /*6*/   {VENDOR_CCD, "HFC-4S IOB4ST", 4, 4, 1, 2, 0, 0, 0},
5059 /*7*/   {VENDOR_CCD, "HFC-4S", 4, 4, 1, 2, 0, 0, 0},
5060 /*8*/   {VENDOR_DIG, "HFC-4S Card", 4, 4, 0, 2, 0, 0, HFC_IO_MODE_REGIO},
5061 /*9*/   {VENDOR_CCD, "HFC-4S Swyx 4xS0 SX2 QuadBri", 4, 4, 1, 2, 0, 0, 0},
5062 /*10*/  {VENDOR_JH, "HFC-4S (junghanns 2.0)", 4, 4, 1, 2, 0, 0, 0},
5063 /*11*/  {VENDOR_PRIM, "HFC-2S Primux Card", 4, 2, 0, 0, 0, 0, 0},
5064
5065 /*12*/  {VENDOR_BN, "HFC-8S Card", 8, 8, 1, 0, 0, 0, 0},
5066 /*13*/  {VENDOR_BN, "HFC-8S Card (+)", 8, 8, 1, 8, 0, DIP_8S,
5067                 HFC_IO_MODE_REGIO},
5068 /*14*/  {VENDOR_CCD, "HFC-8S Eval (old)", 8, 8, 0, 0, 0, 0, 0},
5069 /*15*/  {VENDOR_CCD, "HFC-8S IOB4ST Recording", 8, 8, 1, 0, 0, 0, 0},
5070
5071 /*16*/  {VENDOR_CCD, "HFC-8S IOB8ST", 8, 8, 1, 0, 0, 0, 0},
5072 /*17*/  {VENDOR_CCD, "HFC-8S", 8, 8, 1, 0, 0, 0, 0},
5073 /*18*/  {VENDOR_CCD, "HFC-8S", 8, 8, 1, 0, 0, 0, 0},
5074
5075 /*19*/  {VENDOR_BN, "HFC-E1 Card", 1, 1, 0, 1, 0, DIP_E1, 0},
5076 /*20*/  {VENDOR_BN, "HFC-E1 Card (mini PCI)", 1, 1, 0, 1, 0, 0, 0},
5077 /*21*/  {VENDOR_BN, "HFC-E1+ Card (Dual)", 1, 1, 0, 1, 0, DIP_E1, 0},
5078 /*22*/  {VENDOR_BN, "HFC-E1 Card (Dual)", 1, 1, 0, 1, 0, DIP_E1, 0},
5079
5080 /*23*/  {VENDOR_CCD, "HFC-E1 Eval (old)", 1, 1, 0, 0, 0, 0, 0},
5081 /*24*/  {VENDOR_CCD, "HFC-E1 IOB1E1", 1, 1, 0, 1, 0, 0, 0},
5082 /*25*/  {VENDOR_CCD, "HFC-E1", 1, 1, 0, 1, 0, 0, 0},
5083
5084 /*26*/  {VENDOR_CCD, "HFC-4S Speech Design", 4, 4, 0, 0, 0, 0,
5085                 HFC_IO_MODE_PLXSD},
5086 /*27*/  {VENDOR_CCD, "HFC-E1 Speech Design", 1, 1, 0, 0, 0, 0,
5087                 HFC_IO_MODE_PLXSD},
5088 /*28*/  {VENDOR_CCD, "HFC-4S OpenVox", 4, 4, 1, 0, 0, 0, 0},
5089 /*29*/  {VENDOR_CCD, "HFC-2S OpenVox", 4, 2, 1, 0, 0, 0, 0},
5090 /*30*/  {VENDOR_CCD, "HFC-8S OpenVox", 8, 8, 1, 0, 0, 0, 0},
5091 };
5092
5093 #undef H
5094 #define H(x)    ((unsigned long)&hfcm_map[x])
5095 static struct pci_device_id hfmultipci_ids[] __devinitdata = {
5096
5097         /* Cards with HFC-4S Chip */
5098         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5099                 PCI_SUBDEVICE_ID_CCD_BN1SM, 0, 0, H(0)}, /* BN1S mini PCI */
5100         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5101                 PCI_SUBDEVICE_ID_CCD_BN2S, 0, 0, H(1)}, /* BN2S */
5102         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5103                 PCI_SUBDEVICE_ID_CCD_BN2SM, 0, 0, H(2)}, /* BN2S mini PCI */
5104         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5105                 PCI_SUBDEVICE_ID_CCD_BN4S, 0, 0, H(3)}, /* BN4S */
5106         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5107                 PCI_SUBDEVICE_ID_CCD_BN4SM, 0, 0, H(4)}, /* BN4S mini PCI */
5108         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5109                 PCI_DEVICE_ID_CCD_HFC4S, 0, 0, H(5)}, /* Old Eval */
5110         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5111                 PCI_SUBDEVICE_ID_CCD_IOB4ST, 0, 0, H(6)}, /* IOB4ST */
5112         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5113                 PCI_SUBDEVICE_ID_CCD_HFC4S, 0, 0, H(7)}, /* 4S */
5114         { PCI_VENDOR_ID_DIGIUM, PCI_DEVICE_ID_DIGIUM_HFC4S,
5115                 PCI_VENDOR_ID_DIGIUM, PCI_DEVICE_ID_DIGIUM_HFC4S, 0, 0, H(8)},
5116         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5117                 PCI_SUBDEVICE_ID_CCD_SWYX4S, 0, 0, H(9)}, /* 4S Swyx */
5118         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5119                 PCI_SUBDEVICE_ID_CCD_JH4S20, 0, 0, H(10)},
5120         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5121                 PCI_SUBDEVICE_ID_CCD_PMX2S, 0, 0, H(11)}, /* Primux */
5122         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5123                 PCI_SUBDEVICE_ID_CCD_OV4S, 0, 0, H(28)}, /* OpenVox 4 */
5124         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5125                 PCI_SUBDEVICE_ID_CCD_OV2S, 0, 0, H(29)}, /* OpenVox 2 */
5126
5127         /* Cards with HFC-8S Chip */
5128         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5129         PCI_SUBDEVICE_ID_CCD_BN8S, 0, 0, H(12)}, /* BN8S */
5130         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5131         PCI_SUBDEVICE_ID_CCD_BN8SP, 0, 0, H(13)}, /* BN8S+ */
5132         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5133         PCI_DEVICE_ID_CCD_HFC8S, 0, 0, H(14)}, /* old Eval */
5134         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5135         PCI_SUBDEVICE_ID_CCD_IOB8STR, 0, 0, H(15)},
5136             /* IOB8ST Recording */
5137         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5138                 PCI_SUBDEVICE_ID_CCD_IOB8ST, 0, 0, H(16)}, /* IOB8ST  */
5139         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5140                 PCI_SUBDEVICE_ID_CCD_IOB8ST_1, 0, 0, H(17)}, /* IOB8ST  */
5141         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5142                 PCI_SUBDEVICE_ID_CCD_HFC8S, 0, 0, H(18)}, /* 8S */
5143         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5144                 PCI_SUBDEVICE_ID_CCD_OV8S, 0, 0, H(30)}, /* OpenVox 8 */
5145
5146
5147         /* Cards with HFC-E1 Chip */
5148         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5149                 PCI_SUBDEVICE_ID_CCD_BNE1, 0, 0, H(19)}, /* BNE1 */
5150         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5151                 PCI_SUBDEVICE_ID_CCD_BNE1M, 0, 0, H(20)}, /* BNE1 mini PCI */
5152         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5153                 PCI_SUBDEVICE_ID_CCD_BNE1DP, 0, 0, H(21)}, /* BNE1 + (Dual) */
5154         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5155                 PCI_SUBDEVICE_ID_CCD_BNE1D, 0, 0, H(22)}, /* BNE1 (Dual) */
5156
5157         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5158                 PCI_DEVICE_ID_CCD_HFCE1, 0, 0, H(23)}, /* Old Eval */
5159         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5160                 PCI_SUBDEVICE_ID_CCD_IOB1E1, 0, 0, H(24)}, /* IOB1E1 */
5161         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5162                 PCI_SUBDEVICE_ID_CCD_HFCE1, 0, 0, H(25)}, /* E1 */
5163
5164         { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_CCD,
5165                 PCI_SUBDEVICE_ID_CCD_SPD4S, 0, 0, H(26)}, /* PLX PCI Bridge */
5166         { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_CCD,
5167                 PCI_SUBDEVICE_ID_CCD_SPDE1, 0, 0, H(27)}, /* PLX PCI Bridge */
5168         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_ANY_ID, PCI_ANY_ID,
5169                 0, 0, 0},
5170         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_ANY_ID, PCI_ANY_ID,
5171                 0, 0, 0},
5172         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_ANY_ID, PCI_ANY_ID,
5173                 0, 0, 0},
5174         {0, }
5175 };
5176 #undef H
5177
5178 MODULE_DEVICE_TABLE(pci, hfmultipci_ids);
5179
5180 static int
5181 hfcmulti_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
5182 {
5183         struct hm_map   *m = (struct hm_map *)ent->driver_data;
5184         int             ret;
5185
5186         if (m == NULL) {
5187                 if (ent->vendor == PCI_VENDOR_ID_CCD)
5188                         if (ent->device == PCI_DEVICE_ID_CCD_HFC4S ||
5189                             ent->device == PCI_DEVICE_ID_CCD_HFC8S ||
5190                             ent->device == PCI_DEVICE_ID_CCD_HFCE1)
5191                                 printk(KERN_ERR
5192                                     "unknown HFC multiport controller "
5193                                     "(vendor:%x device:%x subvendor:%x "
5194                                     "subdevice:%x) Please contact the "
5195                                     "driver maintainer for support.\n",
5196                                     ent->vendor, ent->device,
5197                                     ent->subvendor, ent->subdevice);
5198                 return -ENODEV;
5199         }
5200         ret = hfcmulti_init(pdev, ent);
5201         if (ret)
5202                 return ret;
5203         HFC_cnt++;
5204         printk(KERN_INFO "%d devices registered\n", HFC_cnt);
5205         return 0;
5206 }
5207
5208 static struct pci_driver hfcmultipci_driver = {
5209         .name           = "hfc_multi",
5210         .probe          = hfcmulti_probe,
5211         .remove         = __devexit_p(hfc_remove_pci),
5212         .id_table       = hfmultipci_ids,
5213 };
5214
5215 static void __exit
5216 HFCmulti_cleanup(void)
5217 {
5218         struct hfc_multi *card, *next;
5219
5220         /* unload interrupt function symbol */
5221         if (hfc_interrupt)
5222                 symbol_put(ztdummy_extern_interrupt);
5223         if (register_interrupt)
5224                 symbol_put(ztdummy_register_interrupt);
5225         if (unregister_interrupt) {
5226                 if (interrupt_registered) {
5227                         interrupt_registered = 0;
5228                         unregister_interrupt();
5229                 }
5230                 symbol_put(ztdummy_unregister_interrupt);
5231         }
5232
5233         list_for_each_entry_safe(card, next, &HFClist, list)
5234                 release_card(card);
5235         /* get rid of all devices of this driver */
5236         pci_unregister_driver(&hfcmultipci_driver);
5237 }
5238
5239 static int __init
5240 HFCmulti_init(void)
5241 {
5242         int err;
5243
5244 #ifdef IRQ_DEBUG
5245         printk(KERN_ERR "%s: IRQ_DEBUG IS ENABLED!\n", __func__);
5246 #endif
5247
5248         spin_lock_init(&HFClock);
5249         spin_lock_init(&plx_lock);
5250
5251         if (debug & DEBUG_HFCMULTI_INIT)
5252                 printk(KERN_DEBUG "%s: init entered\n", __func__);
5253
5254 #ifdef __BIG_ENDIAN
5255 #error "not running on big endian machines now"
5256 #endif
5257         hfc_interrupt = symbol_get(ztdummy_extern_interrupt);
5258         register_interrupt = symbol_get(ztdummy_register_interrupt);
5259         unregister_interrupt = symbol_get(ztdummy_unregister_interrupt);
5260         printk(KERN_INFO "mISDN: HFC-multi driver %s\n",
5261             hfcmulti_revision);
5262
5263         switch (poll) {
5264         case 0:
5265                 poll_timer = 6;
5266                 poll = 128;
5267                 break;
5268                 /*
5269                  * wenn dieses break nochmal verschwindet,
5270                  * gibt es heisse ohren :-)
5271                  * "without the break you will get hot ears ???"
5272                  */
5273         case 8:
5274                 poll_timer = 2;
5275                 break;
5276         case 16:
5277                 poll_timer = 3;
5278                 break;
5279         case 32:
5280                 poll_timer = 4;
5281                 break;
5282         case 64:
5283                 poll_timer = 5;
5284                 break;
5285         case 128:
5286                 poll_timer = 6;
5287                 break;
5288         case 256:
5289                 poll_timer = 7;
5290                 break;
5291         default:
5292                 printk(KERN_ERR
5293                     "%s: Wrong poll value (%d).\n", __func__, poll);
5294                 err = -EINVAL;
5295                 return err;
5296
5297         }
5298
5299         err = pci_register_driver(&hfcmultipci_driver);
5300         if (err < 0) {
5301                 printk(KERN_ERR "error registering pci driver: %x\n", err);
5302                 if (hfc_interrupt)
5303                         symbol_put(ztdummy_extern_interrupt);
5304                 if (register_interrupt)
5305                         symbol_put(ztdummy_register_interrupt);
5306                 if (unregister_interrupt) {
5307                         if (interrupt_registered) {
5308                                 interrupt_registered = 0;
5309                                 unregister_interrupt();
5310                         }
5311                         symbol_put(ztdummy_unregister_interrupt);
5312                 }
5313                 return err;
5314         }
5315         return 0;
5316 }
5317
5318
5319 module_init(HFCmulti_init);
5320 module_exit(HFCmulti_cleanup);