Merge branch 'linus' into core/generic-dma-coherent
[linux-2.6] / drivers / mtd / maps / dc21285.c
1 /*
2  * MTD map driver for flash on the DC21285 (the StrongARM-110 companion chip)
3  *
4  * (C) 2000  Nicolas Pitre <nico@cam.org>
5  *
6  * This code is GPL
7  */
8 #include <linux/module.h>
9 #include <linux/types.h>
10 #include <linux/kernel.h>
11 #include <linux/init.h>
12 #include <linux/delay.h>
13 #include <linux/slab.h>
14
15 #include <linux/mtd/mtd.h>
16 #include <linux/mtd/map.h>
17 #include <linux/mtd/partitions.h>
18
19 #include <asm/io.h>
20 #include <asm/hardware/dec21285.h>
21 #include <asm/mach-types.h>
22
23
24 static struct mtd_info *dc21285_mtd;
25
26 #ifdef CONFIG_ARCH_NETWINDER
27 /*
28  * This is really ugly, but it seams to be the only
29  * realiable way to do it, as the cpld state machine
30  * is unpredictible. So we have a 25us penalty per
31  * write access.
32  */
33 static void nw_en_write(void)
34 {
35         extern spinlock_t gpio_lock;
36         unsigned long flags;
37
38         /*
39          * we want to write a bit pattern XXX1 to Xilinx to enable
40          * the write gate, which will be open for about the next 2ms.
41          */
42         spin_lock_irqsave(&gpio_lock, flags);
43         cpld_modify(1, 1);
44         spin_unlock_irqrestore(&gpio_lock, flags);
45
46         /*
47          * let the ISA bus to catch on...
48          */
49         udelay(25);
50 }
51 #else
52 #define nw_en_write() do { } while (0)
53 #endif
54
55 static map_word dc21285_read8(struct map_info *map, unsigned long ofs)
56 {
57         map_word val;
58         val.x[0] = *(uint8_t*)(map->virt + ofs);
59         return val;
60 }
61
62 static map_word dc21285_read16(struct map_info *map, unsigned long ofs)
63 {
64         map_word val;
65         val.x[0] = *(uint16_t*)(map->virt + ofs);
66         return val;
67 }
68
69 static map_word dc21285_read32(struct map_info *map, unsigned long ofs)
70 {
71         map_word val;
72         val.x[0] = *(uint32_t*)(map->virt + ofs);
73         return val;
74 }
75
76 static void dc21285_copy_from(struct map_info *map, void *to, unsigned long from, ssize_t len)
77 {
78         memcpy(to, (void*)(map->virt + from), len);
79 }
80
81 static void dc21285_write8(struct map_info *map, const map_word d, unsigned long adr)
82 {
83         if (machine_is_netwinder())
84                 nw_en_write();
85         *CSR_ROMWRITEREG = adr & 3;
86         adr &= ~3;
87         *(uint8_t*)(map->virt + adr) = d.x[0];
88 }
89
90 static void dc21285_write16(struct map_info *map, const map_word d, unsigned long adr)
91 {
92         if (machine_is_netwinder())
93                 nw_en_write();
94         *CSR_ROMWRITEREG = adr & 3;
95         adr &= ~3;
96         *(uint16_t*)(map->virt + adr) = d.x[0];
97 }
98
99 static void dc21285_write32(struct map_info *map, const map_word d, unsigned long adr)
100 {
101         if (machine_is_netwinder())
102                 nw_en_write();
103         *(uint32_t*)(map->virt + adr) = d.x[0];
104 }
105
106 static void dc21285_copy_to_32(struct map_info *map, unsigned long to, const void *from, ssize_t len)
107 {
108         while (len > 0) {
109                 map_word d;
110                 d.x[0] = *((uint32_t*)from);
111                 dc21285_write32(map, d, to);
112                 from += 4;
113                 to += 4;
114                 len -= 4;
115         }
116 }
117
118 static void dc21285_copy_to_16(struct map_info *map, unsigned long to, const void *from, ssize_t len)
119 {
120         while (len > 0) {
121                 map_word d;
122                 d.x[0] = *((uint16_t*)from);
123                 dc21285_write16(map, d, to);
124                 from += 2;
125                 to += 2;
126                 len -= 2;
127         }
128 }
129
130 static void dc21285_copy_to_8(struct map_info *map, unsigned long to, const void *from, ssize_t len)
131 {
132         map_word d;
133         d.x[0] = *((uint8_t*)from);
134         dc21285_write8(map, d, to);
135         from++;
136         to++;
137         len--;
138 }
139
140 static struct map_info dc21285_map = {
141         .name = "DC21285 flash",
142         .phys = NO_XIP,
143         .size = 16*1024*1024,
144         .copy_from = dc21285_copy_from,
145 };
146
147
148 /* Partition stuff */
149 #ifdef CONFIG_MTD_PARTITIONS
150 static struct mtd_partition *dc21285_parts;
151 static const char *probes[] = { "RedBoot", "cmdlinepart", NULL };
152 #endif
153
154 static int __init init_dc21285(void)
155 {
156
157 #ifdef CONFIG_MTD_PARTITIONS
158         int nrparts;
159 #endif
160
161         /* Determine bankwidth */
162         switch (*CSR_SA110_CNTL & (3<<14)) {
163                 case SA110_CNTL_ROMWIDTH_8:
164                         dc21285_map.bankwidth = 1;
165                         dc21285_map.read = dc21285_read8;
166                         dc21285_map.write = dc21285_write8;
167                         dc21285_map.copy_to = dc21285_copy_to_8;
168                         break;
169                 case SA110_CNTL_ROMWIDTH_16:
170                         dc21285_map.bankwidth = 2;
171                         dc21285_map.read = dc21285_read16;
172                         dc21285_map.write = dc21285_write16;
173                         dc21285_map.copy_to = dc21285_copy_to_16;
174                         break;
175                 case SA110_CNTL_ROMWIDTH_32:
176                         dc21285_map.bankwidth = 4;
177                         dc21285_map.read = dc21285_read32;
178                         dc21285_map.write = dc21285_write32;
179                         dc21285_map.copy_to = dc21285_copy_to_32;
180                         break;
181                 default:
182                         printk (KERN_ERR "DC21285 flash: undefined bankwidth\n");
183                         return -ENXIO;
184         }
185         printk (KERN_NOTICE "DC21285 flash support (%d-bit bankwidth)\n",
186                 dc21285_map.bankwidth*8);
187
188         /* Let's map the flash area */
189         dc21285_map.virt = ioremap(DC21285_FLASH, 16*1024*1024);
190         if (!dc21285_map.virt) {
191                 printk("Failed to ioremap\n");
192                 return -EIO;
193         }
194
195         if (machine_is_ebsa285()) {
196                 dc21285_mtd = do_map_probe("cfi_probe", &dc21285_map);
197         } else {
198                 dc21285_mtd = do_map_probe("jedec_probe", &dc21285_map);
199         }
200
201         if (!dc21285_mtd) {
202                 iounmap(dc21285_map.virt);
203                 return -ENXIO;
204         }
205
206         dc21285_mtd->owner = THIS_MODULE;
207
208 #ifdef CONFIG_MTD_PARTITIONS
209         nrparts = parse_mtd_partitions(dc21285_mtd, probes, &dc21285_parts, 0);
210         if (nrparts > 0)
211                 add_mtd_partitions(dc21285_mtd, dc21285_parts, nrparts);
212         else
213 #endif
214                 add_mtd_device(dc21285_mtd);
215
216         if(machine_is_ebsa285()) {
217                 /*
218                  * Flash timing is determined with bits 19-16 of the
219                  * CSR_SA110_CNTL.  The value is the number of wait cycles, or
220                  * 0 for 16 cycles (the default).  Cycles are 20 ns.
221                  * Here we use 7 for 140 ns flash chips.
222                  */
223                 /* access time */
224                 *CSR_SA110_CNTL = ((*CSR_SA110_CNTL & ~0x000f0000) | (7 << 16));
225                 /* burst time */
226                 *CSR_SA110_CNTL = ((*CSR_SA110_CNTL & ~0x00f00000) | (7 << 20));
227                 /* tristate time */
228                 *CSR_SA110_CNTL = ((*CSR_SA110_CNTL & ~0x0f000000) | (7 << 24));
229         }
230
231         return 0;
232 }
233
234 static void __exit cleanup_dc21285(void)
235 {
236 #ifdef CONFIG_MTD_PARTITIONS
237         if (dc21285_parts) {
238                 del_mtd_partitions(dc21285_mtd);
239                 kfree(dc21285_parts);
240         } else
241 #endif
242                 del_mtd_device(dc21285_mtd);
243
244         map_destroy(dc21285_mtd);
245         iounmap(dc21285_map.virt);
246 }
247
248 module_init(init_dc21285);
249 module_exit(cleanup_dc21285);
250
251
252 MODULE_LICENSE("GPL");
253 MODULE_AUTHOR("Nicolas Pitre <nico@cam.org>");
254 MODULE_DESCRIPTION("MTD map driver for DC21285 boards");