git.oblomov.eu Git - linux-2.6/blob - drivers/net/wireless/ath5k/base.c

   1 /*-
   2  * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
   3  * Copyright (c) 2004-2005 Atheros Communications, Inc.
   4  * Copyright (c) 2006 Devicescape Software, Inc.
   5  * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
   6  * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
   7  *
   8  * All rights reserved.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer,
  15  *    without modification.
  16  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  17  *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
  18  *    redistribution must be conditioned upon including a substantially
  19  *    similar Disclaimer requirement for further binary redistribution.
  20  * 3. Neither the names of the above-listed copyright holders nor the names
  21  *    of any contributors may be used to endorse or promote products derived
  22  *    from this software without specific prior written permission.
  23  *
  24  * Alternatively, this software may be distributed under the terms of the
  25  * GNU General Public License ("GPL") version 2 as published by the Free
  26  * Software Foundation.
  27  *
  28  * NO WARRANTY
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
  32  * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
  33  * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
  34  * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  35  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  36  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
  37  * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  38  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  39  * THE POSSIBILITY OF SUCH DAMAGES.
  40  *
  41  */
  42
  43 #include <linux/module.h>
  44 #include <linux/delay.h>
  45 #include <linux/hardirq.h>
  46 #include <linux/if.h>
  47 #include <linux/io.h>
  48 #include <linux/netdevice.h>
  49 #include <linux/cache.h>
  50 #include <linux/pci.h>
  51 #include <linux/ethtool.h>
  52 #include <linux/uaccess.h>
  53
  54 #include <net/ieee80211_radiotap.h>
  55
  56 #include <asm/unaligned.h>
  57
  58 #include "base.h"
  59 #include "reg.h"
  60 #include "debug.h"
  61
  62 static int ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
  63 static int modparam_nohwcrypt;
  64 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
  65 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  66
  67
  68 /******************\
  69 * Internal defines *
  70 \******************/
  71
  72 /* Module info */
  73 MODULE_AUTHOR("Jiri Slaby");
  74 MODULE_AUTHOR("Nick Kossifidis");
  75 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
  76 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
  77 MODULE_LICENSE("Dual BSD/GPL");
  78 MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
  79
  80
  81 /* Known PCI ids */
  82 static struct pci_device_id ath5k_pci_id_table[] __devinitdata = {
  83         { PCI_VDEVICE(ATHEROS, 0x0207), .driver_data = AR5K_AR5210 }, /* 5210 early */
  84         { PCI_VDEVICE(ATHEROS, 0x0007), .driver_data = AR5K_AR5210 }, /* 5210 */
  85         { PCI_VDEVICE(ATHEROS, 0x0011), .driver_data = AR5K_AR5211 }, /* 5311 - this is on AHB bus !*/
  86         { PCI_VDEVICE(ATHEROS, 0x0012), .driver_data = AR5K_AR5211 }, /* 5211 */
  87         { PCI_VDEVICE(ATHEROS, 0x0013), .driver_data = AR5K_AR5212 }, /* 5212 */
  88         { PCI_VDEVICE(3COM_2,  0x0013), .driver_data = AR5K_AR5212 }, /* 3com 5212 */
  89         { PCI_VDEVICE(3COM,    0x0013), .driver_data = AR5K_AR5212 }, /* 3com 3CRDAG675 5212 */
  90         { PCI_VDEVICE(ATHEROS, 0x1014), .driver_data = AR5K_AR5212 }, /* IBM minipci 5212 */
  91         { PCI_VDEVICE(ATHEROS, 0x0014), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
  92         { PCI_VDEVICE(ATHEROS, 0x0015), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
  93         { PCI_VDEVICE(ATHEROS, 0x0016), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
  94         { PCI_VDEVICE(ATHEROS, 0x0017), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
  95         { PCI_VDEVICE(ATHEROS, 0x0018), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
  96         { PCI_VDEVICE(ATHEROS, 0x0019), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
  97         { PCI_VDEVICE(ATHEROS, 0x001a), .driver_data = AR5K_AR5212 }, /* 2413 Griffin-lite */
  98         { PCI_VDEVICE(ATHEROS, 0x001b), .driver_data = AR5K_AR5212 }, /* 5413 Eagle */
  99         { PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* PCI-E cards */
 100         { PCI_VDEVICE(ATHEROS, 0x001d), .driver_data = AR5K_AR5212 }, /* 2417 Nala */
 101         { 0 }
 102 };
 103 MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
 104
 105 /* Known SREVs */
 106 static struct ath5k_srev_name srev_names[] = {
 107         { "5210",       AR5K_VERSION_MAC,       AR5K_SREV_AR5210 },
 108         { "5311",       AR5K_VERSION_MAC,       AR5K_SREV_AR5311 },
 109         { "5311A",      AR5K_VERSION_MAC,       AR5K_SREV_AR5311A },
 110         { "5311B",      AR5K_VERSION_MAC,       AR5K_SREV_AR5311B },
 111         { "5211",       AR5K_VERSION_MAC,       AR5K_SREV_AR5211 },
 112         { "5212",       AR5K_VERSION_MAC,       AR5K_SREV_AR5212 },
 113         { "5213",       AR5K_VERSION_MAC,       AR5K_SREV_AR5213 },
 114         { "5213A",      AR5K_VERSION_MAC,       AR5K_SREV_AR5213A },
 115         { "2413",       AR5K_VERSION_MAC,       AR5K_SREV_AR2413 },
 116         { "2414",       AR5K_VERSION_MAC,       AR5K_SREV_AR2414 },
 117         { "5424",       AR5K_VERSION_MAC,       AR5K_SREV_AR5424 },
 118         { "5413",       AR5K_VERSION_MAC,       AR5K_SREV_AR5413 },
 119         { "5414",       AR5K_VERSION_MAC,       AR5K_SREV_AR5414 },
 120         { "2415",       AR5K_VERSION_MAC,       AR5K_SREV_AR2415 },
 121         { "5416",       AR5K_VERSION_MAC,       AR5K_SREV_AR5416 },
 122         { "5418",       AR5K_VERSION_MAC,       AR5K_SREV_AR5418 },
 123         { "2425",       AR5K_VERSION_MAC,       AR5K_SREV_AR2425 },
 124         { "2417",       AR5K_VERSION_MAC,       AR5K_SREV_AR2417 },
 125         { "xxxxx",      AR5K_VERSION_MAC,       AR5K_SREV_UNKNOWN },
 126         { "5110",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_5110 },
 127         { "5111",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_5111 },
 128         { "5111A",      AR5K_VERSION_RAD,       AR5K_SREV_RAD_5111A },
 129         { "2111",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_2111 },
 130         { "5112",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_5112 },
 131         { "5112A",      AR5K_VERSION_RAD,       AR5K_SREV_RAD_5112A },
 132         { "5112B",      AR5K_VERSION_RAD,       AR5K_SREV_RAD_5112B },
 133         { "2112",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_2112 },
 134         { "2112A",      AR5K_VERSION_RAD,       AR5K_SREV_RAD_2112A },
 135         { "2112B",      AR5K_VERSION_RAD,       AR5K_SREV_RAD_2112B },
 136         { "2413",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_2413 },
 137         { "5413",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_5413 },
 138         { "2316",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_2316 },
 139         { "2317",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_2317 },
 140         { "5424",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_5424 },
 141         { "5133",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_5133 },
 142         { "xxxxx",      AR5K_VERSION_RAD,       AR5K_SREV_UNKNOWN },
 143 };
 144
 145 static struct ieee80211_rate ath5k_rates[] = {
 146         { .bitrate = 10,
 147           .hw_value = ATH5K_RATE_CODE_1M, },
 148         { .bitrate = 20,
 149           .hw_value = ATH5K_RATE_CODE_2M,
 150           .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
 151           .flags = IEEE80211_RATE_SHORT_PREAMBLE },
 152         { .bitrate = 55,
 153           .hw_value = ATH5K_RATE_CODE_5_5M,
 154           .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
 155           .flags = IEEE80211_RATE_SHORT_PREAMBLE },
 156         { .bitrate = 110,
 157           .hw_value = ATH5K_RATE_CODE_11M,
 158           .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
 159           .flags = IEEE80211_RATE_SHORT_PREAMBLE },
 160         { .bitrate = 60,
 161           .hw_value = ATH5K_RATE_CODE_6M,
 162           .flags = 0 },
 163         { .bitrate = 90,
 164           .hw_value = ATH5K_RATE_CODE_9M,
 165           .flags = 0 },
 166         { .bitrate = 120,
 167           .hw_value = ATH5K_RATE_CODE_12M,
 168           .flags = 0 },
 169         { .bitrate = 180,
 170           .hw_value = ATH5K_RATE_CODE_18M,
 171           .flags = 0 },
 172         { .bitrate = 240,
 173           .hw_value = ATH5K_RATE_CODE_24M,
 174           .flags = 0 },
 175         { .bitrate = 360,
 176           .hw_value = ATH5K_RATE_CODE_36M,
 177           .flags = 0 },
 178         { .bitrate = 480,
 179           .hw_value = ATH5K_RATE_CODE_48M,
 180           .flags = 0 },
 181         { .bitrate = 540,
 182           .hw_value = ATH5K_RATE_CODE_54M,
 183           .flags = 0 },
 184         /* XR missing */
 185 };
 186
 187 /*
 188  * Prototypes - PCI stack related functions
 189  */
 190 static int __devinit    ath5k_pci_probe(struct pci_dev *pdev,
 191                                 const struct pci_device_id *id);
 192 static void __devexit   ath5k_pci_remove(struct pci_dev *pdev);
 193 #ifdef CONFIG_PM
 194 static int              ath5k_pci_suspend(struct pci_dev *pdev,
 195                                         pm_message_t state);
 196 static int              ath5k_pci_resume(struct pci_dev *pdev);
 197 #else
 198 #define ath5k_pci_suspend NULL
 199 #define ath5k_pci_resume NULL
 200 #endif /* CONFIG_PM */
 201
 202 static struct pci_driver ath5k_pci_driver = {
 203         .name           = KBUILD_MODNAME,
 204         .id_table       = ath5k_pci_id_table,
 205         .probe          = ath5k_pci_probe,
 206         .remove         = __devexit_p(ath5k_pci_remove),
 207         .suspend        = ath5k_pci_suspend,
 208         .resume         = ath5k_pci_resume,
 209 };
 210
 211
 212
 213 /*
 214  * Prototypes - MAC 802.11 stack related functions
 215  */
 216 static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
 217 static int ath5k_reset(struct ath5k_softc *sc, bool stop, bool change_channel);
 218 static int ath5k_reset_wake(struct ath5k_softc *sc);
 219 static int ath5k_start(struct ieee80211_hw *hw);
 220 static void ath5k_stop(struct ieee80211_hw *hw);
 221 static int ath5k_add_interface(struct ieee80211_hw *hw,
 222                 struct ieee80211_if_init_conf *conf);
 223 static void ath5k_remove_interface(struct ieee80211_hw *hw,
 224                 struct ieee80211_if_init_conf *conf);
 225 static int ath5k_config(struct ieee80211_hw *hw, u32 changed);
 226 static int ath5k_config_interface(struct ieee80211_hw *hw,
 227                 struct ieee80211_vif *vif,
 228                 struct ieee80211_if_conf *conf);
 229 static void ath5k_configure_filter(struct ieee80211_hw *hw,
 230                 unsigned int changed_flags,
 231                 unsigned int *new_flags,
 232                 int mc_count, struct dev_mc_list *mclist);
 233 static int ath5k_set_key(struct ieee80211_hw *hw,
 234                 enum set_key_cmd cmd,
 235                 const u8 *local_addr, const u8 *addr,
 236                 struct ieee80211_key_conf *key);
 237 static int ath5k_get_stats(struct ieee80211_hw *hw,
 238                 struct ieee80211_low_level_stats *stats);
 239 static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
 240                 struct ieee80211_tx_queue_stats *stats);
 241 static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
 242 static void ath5k_reset_tsf(struct ieee80211_hw *hw);
 243 static int ath5k_beacon_update(struct ath5k_softc *sc, struct sk_buff *skb);
 244
 245 static struct ieee80211_ops ath5k_hw_ops = {
 246         .tx             = ath5k_tx,
 247         .start          = ath5k_start,
 248         .stop           = ath5k_stop,
 249         .add_interface  = ath5k_add_interface,
 250         .remove_interface = ath5k_remove_interface,
 251         .config         = ath5k_config,
 252         .config_interface = ath5k_config_interface,
 253         .configure_filter = ath5k_configure_filter,
 254         .set_key        = ath5k_set_key,
 255         .get_stats      = ath5k_get_stats,
 256         .conf_tx        = NULL,
 257         .get_tx_stats   = ath5k_get_tx_stats,
 258         .get_tsf        = ath5k_get_tsf,
 259         .reset_tsf      = ath5k_reset_tsf,
 260 };
 261
 262 /*
 263  * Prototypes - Internal functions
 264  */
 265 /* Attach detach */
 266 static int      ath5k_attach(struct pci_dev *pdev,
 267                         struct ieee80211_hw *hw);
 268 static void     ath5k_detach(struct pci_dev *pdev,
 269                         struct ieee80211_hw *hw);
 270 /* Channel/mode setup */
 271 static inline short ath5k_ieee2mhz(short chan);
 272 static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
 273                                 struct ieee80211_channel *channels,
 274                                 unsigned int mode,
 275                                 unsigned int max);
 276 static int      ath5k_setup_bands(struct ieee80211_hw *hw);
 277 static int      ath5k_chan_set(struct ath5k_softc *sc,
 278                                 struct ieee80211_channel *chan);
 279 static void     ath5k_setcurmode(struct ath5k_softc *sc,
 280                                 unsigned int mode);
 281 static void     ath5k_mode_setup(struct ath5k_softc *sc);
 282
 283 /* Descriptor setup */
 284 static int      ath5k_desc_alloc(struct ath5k_softc *sc,
 285                                 struct pci_dev *pdev);
 286 static void     ath5k_desc_free(struct ath5k_softc *sc,
 287                                 struct pci_dev *pdev);
 288 /* Buffers setup */
 289 static int      ath5k_rxbuf_setup(struct ath5k_softc *sc,
 290                                 struct ath5k_buf *bf);
 291 static int      ath5k_txbuf_setup(struct ath5k_softc *sc,
 292                                 struct ath5k_buf *bf);
 293 static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
 294                                 struct ath5k_buf *bf)
 295 {
 296         BUG_ON(!bf);
 297         if (!bf->skb)
 298                 return;
 299         pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
 300                         PCI_DMA_TODEVICE);
 301         dev_kfree_skb_any(bf->skb);
 302         bf->skb = NULL;
 303 }
 304
 305 /* Queues setup */
 306 static struct   ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
 307                                 int qtype, int subtype);
 308 static int      ath5k_beaconq_setup(struct ath5k_hw *ah);
 309 static int      ath5k_beaconq_config(struct ath5k_softc *sc);
 310 static void     ath5k_txq_drainq(struct ath5k_softc *sc,
 311                                 struct ath5k_txq *txq);
 312 static void     ath5k_txq_cleanup(struct ath5k_softc *sc);
 313 static void     ath5k_txq_release(struct ath5k_softc *sc);
 314 /* Rx handling */
 315 static int      ath5k_rx_start(struct ath5k_softc *sc);
 316 static void     ath5k_rx_stop(struct ath5k_softc *sc);
 317 static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
 318                                         struct ath5k_desc *ds,
 319                                         struct sk_buff *skb,
 320                                         struct ath5k_rx_status *rs);
 321 static void     ath5k_tasklet_rx(unsigned long data);
 322 /* Tx handling */
 323 static void     ath5k_tx_processq(struct ath5k_softc *sc,
 324                                 struct ath5k_txq *txq);
 325 static void     ath5k_tasklet_tx(unsigned long data);
 326 /* Beacon handling */
 327 static int      ath5k_beacon_setup(struct ath5k_softc *sc,
 328                                         struct ath5k_buf *bf);
 329 static void     ath5k_beacon_send(struct ath5k_softc *sc);
 330 static void     ath5k_beacon_config(struct ath5k_softc *sc);
 331 static void     ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
 332
 333 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
 334 {
 335         u64 tsf = ath5k_hw_get_tsf64(ah);
 336
 337         if ((tsf & 0x7fff) < rstamp)
 338                 tsf -= 0x8000;
 339
 340         return (tsf & ~0x7fff) | rstamp;
 341 }
 342
 343 /* Interrupt handling */
 344 static int      ath5k_init(struct ath5k_softc *sc, bool is_resume);
 345 static int      ath5k_stop_locked(struct ath5k_softc *sc);
 346 static int      ath5k_stop_hw(struct ath5k_softc *sc, bool is_suspend);
 347 static irqreturn_t ath5k_intr(int irq, void *dev_id);
 348 static void     ath5k_tasklet_reset(unsigned long data);
 349
 350 static void     ath5k_calibrate(unsigned long data);
 351 /* LED functions */
 352 static int      ath5k_init_leds(struct ath5k_softc *sc);
 353 static void     ath5k_led_enable(struct ath5k_softc *sc);
 354 static void     ath5k_led_off(struct ath5k_softc *sc);
 355 static void     ath5k_unregister_leds(struct ath5k_softc *sc);
 356
 357 /*
 358  * Module init/exit functions
 359  */
 360 static int __init
 361 init_ath5k_pci(void)
 362 {
 363         int ret;
 364
 365         ath5k_debug_init();
 366
 367         ret = pci_register_driver(&ath5k_pci_driver);
 368         if (ret) {
 369                 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
 370                 return ret;
 371         }
 372
 373         return 0;
 374 }
 375
 376 static void __exit
 377 exit_ath5k_pci(void)
 378 {
 379         pci_unregister_driver(&ath5k_pci_driver);
 380
 381         ath5k_debug_finish();
 382 }
 383
 384 module_init(init_ath5k_pci);
 385 module_exit(exit_ath5k_pci);
 386
 387
 388 /********************\
 389 * PCI Initialization *
 390 \********************/
 391
 392 static const char *
 393 ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
 394 {
 395         const char *name = "xxxxx";
 396         unsigned int i;
 397
 398         for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
 399                 if (srev_names[i].sr_type != type)
 400                         continue;
 401
 402                 if ((val & 0xf0) == srev_names[i].sr_val)
 403                         name = srev_names[i].sr_name;
 404
 405                 if ((val & 0xff) == srev_names[i].sr_val) {
 406                         name = srev_names[i].sr_name;
 407                         break;
 408                 }
 409         }
 410
 411         return name;
 412 }
 413
 414 static int __devinit
 415 ath5k_pci_probe(struct pci_dev *pdev,
 416                 const struct pci_device_id *id)
 417 {
 418         void __iomem *mem;
 419         struct ath5k_softc *sc;
 420         struct ieee80211_hw *hw;
 421         int ret;
 422         u8 csz;
 423
 424         ret = pci_enable_device(pdev);
 425         if (ret) {
 426                 dev_err(&pdev->dev, "can't enable device\n");
 427                 goto err;
 428         }
 429
 430         /* XXX 32-bit addressing only */
 431         ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
 432         if (ret) {
 433                 dev_err(&pdev->dev, "32-bit DMA not available\n");
 434                 goto err_dis;
 435         }
 436
 437         /*
 438          * Cache line size is used to size and align various
 439          * structures used to communicate with the hardware.
 440          */
 441         pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
 442         if (csz == 0) {
 443                 /*
 444                  * Linux 2.4.18 (at least) writes the cache line size
 445                  * register as a 16-bit wide register which is wrong.
 446                  * We must have this setup properly for rx buffer
 447                  * DMA to work so force a reasonable value here if it
 448                  * comes up zero.
 449                  */
 450                 csz = L1_CACHE_BYTES / sizeof(u32);
 451                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
 452         }
 453         /*
 454          * The default setting of latency timer yields poor results,
 455          * set it to the value used by other systems.  It may be worth
 456          * tweaking this setting more.
 457          */
 458         pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
 459
 460         /* Enable bus mastering */
 461         pci_set_master(pdev);
 462
 463         /*
 464          * Disable the RETRY_TIMEOUT register (0x41) to keep
 465          * PCI Tx retries from interfering with C3 CPU state.
 466          */
 467         pci_write_config_byte(pdev, 0x41, 0);
 468
 469         ret = pci_request_region(pdev, 0, "ath5k");
 470         if (ret) {
 471                 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
 472                 goto err_dis;
 473         }
 474
 475         mem = pci_iomap(pdev, 0, 0);
 476         if (!mem) {
 477                 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
 478                 ret = -EIO;
 479                 goto err_reg;
 480         }
 481
 482         /*
 483          * Allocate hw (mac80211 main struct)
 484          * and hw->priv (driver private data)
 485          */
 486         hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
 487         if (hw == NULL) {
 488                 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
 489                 ret = -ENOMEM;
 490                 goto err_map;
 491         }
 492
 493         dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
 494
 495         /* Initialize driver private data */
 496         SET_IEEE80211_DEV(hw, &pdev->dev);
 497         hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
 498                     IEEE80211_HW_SIGNAL_DBM |
 499                     IEEE80211_HW_NOISE_DBM;
 500
 501         hw->wiphy->interface_modes =
 502                 BIT(NL80211_IFTYPE_STATION) |
 503                 BIT(NL80211_IFTYPE_ADHOC) |
 504                 BIT(NL80211_IFTYPE_MESH_POINT);
 505
 506         hw->extra_tx_headroom = 2;
 507         hw->channel_change_time = 5000;
 508         sc = hw->priv;
 509         sc->hw = hw;
 510         sc->pdev = pdev;
 511
 512         ath5k_debug_init_device(sc);
 513
 514         /*
 515          * Mark the device as detached to avoid processing
 516          * interrupts until setup is complete.
 517          */
 518         __set_bit(ATH_STAT_INVALID, sc->status);
 519
 520         sc->iobase = mem; /* So we can unmap it on detach */
 521         sc->cachelsz = csz * sizeof(u32); /* convert to bytes */
 522         sc->opmode = NL80211_IFTYPE_STATION;
 523         mutex_init(&sc->lock);
 524         spin_lock_init(&sc->rxbuflock);
 525         spin_lock_init(&sc->txbuflock);
 526         spin_lock_init(&sc->block);
 527
 528         /* Set private data */
 529         pci_set_drvdata(pdev, hw);
 530
 531         /* Setup interrupt handler */
 532         ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
 533         if (ret) {
 534                 ATH5K_ERR(sc, "request_irq failed\n");
 535                 goto err_free;
 536         }
 537
 538         /* Initialize device */
 539         sc->ah = ath5k_hw_attach(sc, id->driver_data);
 540         if (IS_ERR(sc->ah)) {
 541                 ret = PTR_ERR(sc->ah);
 542                 goto err_irq;
 543         }
 544
 545         /* set up multi-rate retry capabilities */
 546         if (sc->ah->ah_version == AR5K_AR5212) {
 547                 hw->max_rates = 4;
 548                 hw->max_rate_tries = 11;
 549         }
 550
 551         /* Finish private driver data initialization */
 552         ret = ath5k_attach(pdev, hw);
 553         if (ret)
 554                 goto err_ah;
 555
 556         ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
 557                         ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
 558                                         sc->ah->ah_mac_srev,
 559                                         sc->ah->ah_phy_revision);
 560
 561         if (!sc->ah->ah_single_chip) {
 562                 /* Single chip radio (!RF5111) */
 563                 if (sc->ah->ah_radio_5ghz_revision &&
 564                         !sc->ah->ah_radio_2ghz_revision) {
 565                         /* No 5GHz support -> report 2GHz radio */
 566                         if (!test_bit(AR5K_MODE_11A,
 567                                 sc->ah->ah_capabilities.cap_mode)) {
 568                                 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
 569                                         ath5k_chip_name(AR5K_VERSION_RAD,
 570                                                 sc->ah->ah_radio_5ghz_revision),
 571                                                 sc->ah->ah_radio_5ghz_revision);
 572                         /* No 2GHz support (5110 and some
 573                          * 5Ghz only cards) -> report 5Ghz radio */
 574                         } else if (!test_bit(AR5K_MODE_11B,
 575                                 sc->ah->ah_capabilities.cap_mode)) {
 576                                 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
 577                                         ath5k_chip_name(AR5K_VERSION_RAD,
 578                                                 sc->ah->ah_radio_5ghz_revision),
 579                                                 sc->ah->ah_radio_5ghz_revision);
 580                         /* Multiband radio */
 581                         } else {
 582                                 ATH5K_INFO(sc, "RF%s multiband radio found"
 583                                         " (0x%x)\n",
 584                                         ath5k_chip_name(AR5K_VERSION_RAD,
 585                                                 sc->ah->ah_radio_5ghz_revision),
 586                                                 sc->ah->ah_radio_5ghz_revision);
 587                         }
 588                 }
 589                 /* Multi chip radio (RF5111 - RF2111) ->
 590                  * report both 2GHz/5GHz radios */
 591                 else if (sc->ah->ah_radio_5ghz_revision &&
 592                                 sc->ah->ah_radio_2ghz_revision){
 593                         ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
 594                                 ath5k_chip_name(AR5K_VERSION_RAD,
 595                                         sc->ah->ah_radio_5ghz_revision),
 596                                         sc->ah->ah_radio_5ghz_revision);
 597                         ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
 598                                 ath5k_chip_name(AR5K_VERSION_RAD,
 599                                         sc->ah->ah_radio_2ghz_revision),
 600                                         sc->ah->ah_radio_2ghz_revision);
 601                 }
 602         }
 603
 604
 605         /* ready to process interrupts */
 606         __clear_bit(ATH_STAT_INVALID, sc->status);
 607
 608         return 0;
 609 err_ah:
 610         ath5k_hw_detach(sc->ah);
 611 err_irq:
 612         free_irq(pdev->irq, sc);
 613 err_free:
 614         ieee80211_free_hw(hw);
 615 err_map:
 616         pci_iounmap(pdev, mem);
 617 err_reg:
 618         pci_release_region(pdev, 0);
 619 err_dis:
 620         pci_disable_device(pdev);
 621 err:
 622         return ret;
 623 }
 624
 625 static void __devexit
 626 ath5k_pci_remove(struct pci_dev *pdev)
 627 {
 628         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
 629         struct ath5k_softc *sc = hw->priv;
 630
 631         ath5k_debug_finish_device(sc);
 632         ath5k_detach(pdev, hw);
 633         ath5k_hw_detach(sc->ah);
 634         free_irq(pdev->irq, sc);
 635         pci_iounmap(pdev, sc->iobase);
 636         pci_release_region(pdev, 0);
 637         pci_disable_device(pdev);
 638         ieee80211_free_hw(hw);
 639 }
 640
 641 #ifdef CONFIG_PM
 642 static int
 643 ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state)
 644 {
 645         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
 646         struct ath5k_softc *sc = hw->priv;
 647
 648         ath5k_led_off(sc);
 649
 650         ath5k_stop_hw(sc, true);
 651
 652         free_irq(pdev->irq, sc);
 653         pci_save_state(pdev);
 654         pci_disable_device(pdev);
 655         pci_set_power_state(pdev, PCI_D3hot);
 656
 657         return 0;
 658 }
 659
 660 static int
 661 ath5k_pci_resume(struct pci_dev *pdev)
 662 {
 663         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
 664         struct ath5k_softc *sc = hw->priv;
 665         int err;
 666
 667         pci_restore_state(pdev);
 668
 669         err = pci_enable_device(pdev);
 670         if (err)
 671                 return err;
 672
 673         /*
 674          * Suspend/Resume resets the PCI configuration space, so we have to
 675          * re-disable the RETRY_TIMEOUT register (0x41) to keep
 676          * PCI Tx retries from interfering with C3 CPU state
 677          */
 678         pci_write_config_byte(pdev, 0x41, 0);
 679
 680         err = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
 681         if (err) {
 682                 ATH5K_ERR(sc, "request_irq failed\n");
 683                 goto err_no_irq;
 684         }
 685
 686         err = ath5k_init(sc, true);
 687         if (err)
 688                 goto err_irq;
 689         ath5k_led_enable(sc);
 690
 691         return 0;
 692 err_irq:
 693         free_irq(pdev->irq, sc);
 694 err_no_irq:
 695         pci_disable_device(pdev);
 696         return err;
 697 }
 698 #endif /* CONFIG_PM */
 699
 700
 701 /***********************\
 702 * Driver Initialization *
 703 \***********************/
 704
 705 static int
 706 ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
 707 {
 708         struct ath5k_softc *sc = hw->priv;
 709         struct ath5k_hw *ah = sc->ah;
 710         u8 mac[ETH_ALEN] = {};
 711         int ret;
 712
 713         ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
 714
 715         /*
 716          * Check if the MAC has multi-rate retry support.
 717          * We do this by trying to setup a fake extended
 718          * descriptor.  MAC's that don't have support will
 719          * return false w/o doing anything.  MAC's that do
 720          * support it will return true w/o doing anything.
 721          */
 722         ret = ah->ah_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
 723         if (ret < 0)
 724                 goto err;
 725         if (ret > 0)
 726                 __set_bit(ATH_STAT_MRRETRY, sc->status);
 727
 728         /*
 729          * Collect the channel list.  The 802.11 layer
 730          * is resposible for filtering this list based
 731          * on settings like the phy mode and regulatory
 732          * domain restrictions.
 733          */
 734         ret = ath5k_setup_bands(hw);
 735         if (ret) {
 736                 ATH5K_ERR(sc, "can't get channels\n");
 737                 goto err;
 738         }
 739
 740         /* NB: setup here so ath5k_rate_update is happy */
 741         if (test_bit(AR5K_MODE_11A, ah->ah_modes))
 742                 ath5k_setcurmode(sc, AR5K_MODE_11A);
 743         else
 744                 ath5k_setcurmode(sc, AR5K_MODE_11B);
 745
 746         /*
 747          * Allocate tx+rx descriptors and populate the lists.
 748          */
 749         ret = ath5k_desc_alloc(sc, pdev);
 750         if (ret) {
 751                 ATH5K_ERR(sc, "can't allocate descriptors\n");
 752                 goto err;
 753         }
 754
 755         /*
 756          * Allocate hardware transmit queues: one queue for
 757          * beacon frames and one data queue for each QoS
 758          * priority.  Note that hw functions handle reseting
 759          * these queues at the needed time.
 760          */
 761         ret = ath5k_beaconq_setup(ah);
 762         if (ret < 0) {
 763                 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
 764                 goto err_desc;
 765         }
 766         sc->bhalq = ret;
 767
 768         sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
 769         if (IS_ERR(sc->txq)) {
 770                 ATH5K_ERR(sc, "can't setup xmit queue\n");
 771                 ret = PTR_ERR(sc->txq);
 772                 goto err_bhal;
 773         }
 774
 775         tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
 776         tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
 777         tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
 778         setup_timer(&sc->calib_tim, ath5k_calibrate, (unsigned long)sc);
 779
 780         ret = ath5k_eeprom_read_mac(ah, mac);
 781         if (ret) {
 782                 ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
 783                         sc->pdev->device);
 784                 goto err_queues;
 785         }
 786
 787         SET_IEEE80211_PERM_ADDR(hw, mac);
 788         /* All MAC address bits matter for ACKs */
 789         memset(sc->bssidmask, 0xff, ETH_ALEN);
 790         ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
 791
 792         ret = ieee80211_register_hw(hw);
 793         if (ret) {
 794                 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
 795                 goto err_queues;
 796         }
 797
 798         ath5k_init_leds(sc);
 799
 800         return 0;
 801 err_queues:
 802         ath5k_txq_release(sc);
 803 err_bhal:
 804         ath5k_hw_release_tx_queue(ah, sc->bhalq);
 805 err_desc:
 806         ath5k_desc_free(sc, pdev);
 807 err:
 808         return ret;
 809 }
 810
 811 static void
 812 ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
 813 {
 814         struct ath5k_softc *sc = hw->priv;
 815
 816         /*
 817          * NB: the order of these is important:
 818          * o call the 802.11 layer before detaching ath5k_hw to
 819          *   insure callbacks into the driver to delete global
 820          *   key cache entries can be handled
 821          * o reclaim the tx queue data structures after calling
 822          *   the 802.11 layer as we'll get called back to reclaim
 823          *   node state and potentially want to use them
 824          * o to cleanup the tx queues the hal is called, so detach
 825          *   it last
 826          * XXX: ??? detach ath5k_hw ???
 827          * Other than that, it's straightforward...
 828          */
 829         ieee80211_unregister_hw(hw);
 830         ath5k_desc_free(sc, pdev);
 831         ath5k_txq_release(sc);
 832         ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
 833         ath5k_unregister_leds(sc);
 834
 835         /*
 836          * NB: can't reclaim these until after ieee80211_ifdetach
 837          * returns because we'll get called back to reclaim node
 838          * state and potentially want to use them.
 839          */
 840 }
 841
 842
 843
 844
 845 /********************\
 846 * Channel/mode setup *
 847 \********************/
 848
 849 /*
 850  * Convert IEEE channel number to MHz frequency.
 851  */
 852 static inline short
 853 ath5k_ieee2mhz(short chan)
 854 {
 855         if (chan <= 14 || chan >= 27)
 856                 return ieee80211chan2mhz(chan);
 857         else
 858                 return 2212 + chan * 20;
 859 }
 860
 861 static unsigned int
 862 ath5k_copy_channels(struct ath5k_hw *ah,
 863                 struct ieee80211_channel *channels,
 864                 unsigned int mode,
 865                 unsigned int max)
 866 {
 867         unsigned int i, count, size, chfreq, freq, ch;
 868
 869         if (!test_bit(mode, ah->ah_modes))
 870                 return 0;
 871
 872         switch (mode) {
 873         case AR5K_MODE_11A:
 874         case AR5K_MODE_11A_TURBO:
 875                 /* 1..220, but 2GHz frequencies are filtered by check_channel */
 876                 size = 220 ;
 877                 chfreq = CHANNEL_5GHZ;
 878                 break;
 879         case AR5K_MODE_11B:
 880         case AR5K_MODE_11G:
 881         case AR5K_MODE_11G_TURBO:
 882                 size = 26;
 883                 chfreq = CHANNEL_2GHZ;
 884                 break;
 885         default:
 886                 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
 887                 return 0;
 888         }
 889
 890         for (i = 0, count = 0; i < size && max > 0; i++) {
 891                 ch = i + 1 ;
 892                 freq = ath5k_ieee2mhz(ch);
 893
 894                 /* Check if channel is supported by the chipset */
 895                 if (!ath5k_channel_ok(ah, freq, chfreq))
 896                         continue;
 897
 898                 /* Write channel info and increment counter */
 899                 channels[count].center_freq = freq;
 900                 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
 901                         IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
 902                 switch (mode) {
 903                 case AR5K_MODE_11A:
 904                 case AR5K_MODE_11G:
 905                         channels[count].hw_value = chfreq | CHANNEL_OFDM;
 906                         break;
 907                 case AR5K_MODE_11A_TURBO:
 908                 case AR5K_MODE_11G_TURBO:
 909                         channels[count].hw_value = chfreq |
 910                                 CHANNEL_OFDM | CHANNEL_TURBO;
 911                         break;
 912                 case AR5K_MODE_11B:
 913                         channels[count].hw_value = CHANNEL_B;
 914                 }
 915
 916                 count++;
 917                 max--;
 918         }
 919
 920         return count;
 921 }
 922
 923 static void
 924 ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
 925 {
 926         u8 i;
 927
 928         for (i = 0; i < AR5K_MAX_RATES; i++)
 929                 sc->rate_idx[b->band][i] = -1;
 930
 931         for (i = 0; i < b->n_bitrates; i++) {
 932                 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
 933                 if (b->bitrates[i].hw_value_short)
 934                         sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
 935         }
 936 }
 937
 938 static int
 939 ath5k_setup_bands(struct ieee80211_hw *hw)
 940 {
 941         struct ath5k_softc *sc = hw->priv;
 942         struct ath5k_hw *ah = sc->ah;
 943         struct ieee80211_supported_band *sband;
 944         int max_c, count_c = 0;
 945         int i;
 946
 947         BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
 948         max_c = ARRAY_SIZE(sc->channels);
 949
 950         /* 2GHz band */
 951         sband = &sc->sbands[IEEE80211_BAND_2GHZ];
 952         sband->band = IEEE80211_BAND_2GHZ;
 953         sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
 954
 955         if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
 956                 /* G mode */
 957                 memcpy(sband->bitrates, &ath5k_rates[0],
 958                        sizeof(struct ieee80211_rate) * 12);
 959                 sband->n_bitrates = 12;
 960
 961                 sband->channels = sc->channels;
 962                 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
 963                                         AR5K_MODE_11G, max_c);
 964
 965                 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
 966                 count_c = sband->n_channels;
 967                 max_c -= count_c;
 968         } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
 969                 /* B mode */
 970                 memcpy(sband->bitrates, &ath5k_rates[0],
 971                        sizeof(struct ieee80211_rate) * 4);
 972                 sband->n_bitrates = 4;
 973
 974                 /* 5211 only supports B rates and uses 4bit rate codes
 975                  * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
 976                  * fix them up here:
 977                  */
 978                 if (ah->ah_version == AR5K_AR5211) {
 979                         for (i = 0; i < 4; i++) {
 980                                 sband->bitrates[i].hw_value =
 981                                         sband->bitrates[i].hw_value & 0xF;
 982                                 sband->bitrates[i].hw_value_short =
 983                                         sband->bitrates[i].hw_value_short & 0xF;
 984                         }
 985                 }
 986
 987                 sband->channels = sc->channels;
 988                 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
 989                                         AR5K_MODE_11B, max_c);
 990
 991                 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
 992                 count_c = sband->n_channels;
 993                 max_c -= count_c;
 994         }
 995         ath5k_setup_rate_idx(sc, sband);
 996
 997         /* 5GHz band, A mode */
 998         if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
 999                 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
1000                 sband->band = IEEE80211_BAND_5GHZ;
1001                 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
1002
1003                 memcpy(sband->bitrates, &ath5k_rates[4],
1004                        sizeof(struct ieee80211_rate) * 8);
1005                 sband->n_bitrates = 8;
1006
1007                 sband->channels = &sc->channels[count_c];
1008                 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1009                                         AR5K_MODE_11A, max_c);
1010
1011                 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
1012         }
1013         ath5k_setup_rate_idx(sc, sband);
1014
1015         ath5k_debug_dump_bands(sc);
1016
1017         return 0;
1018 }
1019
1020 /*
1021  * Set/change channels.  If the channel is really being changed,
1022  * it's done by reseting the chip.  To accomplish this we must
1023  * first cleanup any pending DMA, then restart stuff after a la
1024  * ath5k_init.
1025  */
1026 static int
1027 ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1028 {
1029         ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
1030                 sc->curchan->center_freq, chan->center_freq);
1031
1032         if (chan->center_freq != sc->curchan->center_freq ||
1033                 chan->hw_value != sc->curchan->hw_value) {
1034
1035                 sc->curchan = chan;
1036                 sc->curband = &sc->sbands[chan->band];
1037
1038                 /*
1039                  * To switch channels clear any pending DMA operations;
1040                  * wait long enough for the RX fifo to drain, reset the
1041                  * hardware at the new frequency, and then re-enable
1042                  * the relevant bits of the h/w.
1043                  */
1044                 return ath5k_reset(sc, true, true);
1045         }
1046
1047         return 0;
1048 }
1049
1050 static void
1051 ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1052 {
1053         sc->curmode = mode;
1054
1055         if (mode == AR5K_MODE_11A) {
1056                 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1057         } else {
1058                 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1059         }
1060 }
1061
1062 static void
1063 ath5k_mode_setup(struct ath5k_softc *sc)
1064 {
1065         struct ath5k_hw *ah = sc->ah;
1066         u32 rfilt;
1067
1068         /* configure rx filter */
1069         rfilt = sc->filter_flags;
1070         ath5k_hw_set_rx_filter(ah, rfilt);
1071
1072         if (ath5k_hw_hasbssidmask(ah))
1073                 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1074
1075         /* configure operational mode */
1076         ath5k_hw_set_opmode(ah);
1077
1078         ath5k_hw_set_mcast_filter(ah, 0, 0);
1079         ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1080 }
1081
1082 static inline int
1083 ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
1084 {
1085         WARN_ON(hw_rix < 0 || hw_rix > AR5K_MAX_RATES);
1086         return sc->rate_idx[sc->curband->band][hw_rix];
1087 }
1088
1089 /***************\
1090 * Buffers setup *
1091 \***************/
1092
1093 static int
1094 ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1095 {
1096         struct ath5k_hw *ah = sc->ah;
1097         struct sk_buff *skb = bf->skb;
1098         struct ath5k_desc *ds;
1099
1100         if (likely(skb == NULL)) {
1101                 unsigned int off;
1102
1103                 /*
1104                  * Allocate buffer with headroom_needed space for the
1105                  * fake physical layer header at the start.
1106                  */
1107                 skb = dev_alloc_skb(sc->rxbufsize + sc->cachelsz - 1);
1108                 if (unlikely(skb == NULL)) {
1109                         ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1110                                         sc->rxbufsize + sc->cachelsz - 1);
1111                         return -ENOMEM;
1112                 }
1113                 /*
1114                  * Cache-line-align.  This is important (for the
1115                  * 5210 at least) as not doing so causes bogus data
1116                  * in rx'd frames.
1117                  */
1118                 off = ((unsigned long)skb->data) % sc->cachelsz;
1119                 if (off != 0)
1120                         skb_reserve(skb, sc->cachelsz - off);
1121
1122                 bf->skb = skb;
1123                 bf->skbaddr = pci_map_single(sc->pdev,
1124                         skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE);
1125                 if (unlikely(pci_dma_mapping_error(sc->pdev, bf->skbaddr))) {
1126                         ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1127                         dev_kfree_skb(skb);
1128                         bf->skb = NULL;
1129                         return -ENOMEM;
1130                 }
1131         }
1132
1133         /*
1134          * Setup descriptors.  For receive we always terminate
1135          * the descriptor list with a self-linked entry so we'll
1136          * not get overrun under high load (as can happen with a
1137          * 5212 when ANI processing enables PHY error frames).
1138          *
1139          * To insure the last descriptor is self-linked we create
1140          * each descriptor as self-linked and add it to the end.  As
1141          * each additional descriptor is added the previous self-linked
1142          * entry is ``fixed'' naturally.  This should be safe even
1143          * if DMA is happening.  When processing RX interrupts we
1144          * never remove/process the last, self-linked, entry on the
1145          * descriptor list.  This insures the hardware always has
1146          * someplace to write a new frame.
1147          */
1148         ds = bf->desc;
1149         ds->ds_link = bf->daddr;        /* link to self */
1150         ds->ds_data = bf->skbaddr;
1151         ah->ah_setup_rx_desc(ah, ds,
1152                 skb_tailroom(skb),      /* buffer size */
1153                 0);
1154
1155         if (sc->rxlink != NULL)
1156                 *sc->rxlink = bf->daddr;
1157         sc->rxlink = &ds->ds_link;
1158         return 0;
1159 }
1160
1161 static int
1162 ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1163 {
1164         struct ath5k_hw *ah = sc->ah;
1165         struct ath5k_txq *txq = sc->txq;
1166         struct ath5k_desc *ds = bf->desc;
1167         struct sk_buff *skb = bf->skb;
1168         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1169         unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
1170         struct ieee80211_rate *rate;
1171         unsigned int mrr_rate[3], mrr_tries[3];
1172         int i, ret;
1173
1174         flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
1175
1176         /* XXX endianness */
1177         bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1178                         PCI_DMA_TODEVICE);
1179
1180         if (info->flags & IEEE80211_TX_CTL_NO_ACK)
1181                 flags |= AR5K_TXDESC_NOACK;
1182
1183         pktlen = skb->len;
1184
1185         if (info->control.hw_key) {
1186                 keyidx = info->control.hw_key->hw_key_idx;
1187                 pktlen += info->control.hw_key->icv_len;
1188         }
1189         ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1190                 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
1191                 (sc->power_level * 2),
1192                 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
1193                 info->control.rates[0].count, keyidx, 0, flags, 0, 0);
1194         if (ret)
1195                 goto err_unmap;
1196
1197         memset(mrr_rate, 0, sizeof(mrr_rate));
1198         memset(mrr_tries, 0, sizeof(mrr_tries));
1199         for (i = 0; i < 3; i++) {
1200                 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
1201                 if (!rate)
1202                         break;
1203
1204                 mrr_rate[i] = rate->hw_value;
1205                 mrr_tries[i] = info->control.rates[i + 1].count;
1206         }
1207
1208         ah->ah_setup_mrr_tx_desc(ah, ds,
1209                 mrr_rate[0], mrr_tries[0],
1210                 mrr_rate[1], mrr_tries[1],
1211                 mrr_rate[2], mrr_tries[2]);
1212
1213         ds->ds_link = 0;
1214         ds->ds_data = bf->skbaddr;
1215
1216         spin_lock_bh(&txq->lock);
1217         list_add_tail(&bf->list, &txq->q);
1218         sc->tx_stats[txq->qnum].len++;
1219         if (txq->link == NULL) /* is this first packet? */
1220                 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
1221         else /* no, so only link it */
1222                 *txq->link = bf->daddr;
1223
1224         txq->link = &ds->ds_link;
1225         ath5k_hw_start_tx_dma(ah, txq->qnum);
1226         mmiowb();
1227         spin_unlock_bh(&txq->lock);
1228
1229         return 0;
1230 err_unmap:
1231         pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1232         return ret;
1233 }
1234
1235 /*******************\
1236 * Descriptors setup *
1237 \*******************/
1238
1239 static int
1240 ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1241 {
1242         struct ath5k_desc *ds;
1243         struct ath5k_buf *bf;
1244         dma_addr_t da;
1245         unsigned int i;
1246         int ret;
1247
1248         /* allocate descriptors */
1249         sc->desc_len = sizeof(struct ath5k_desc) *
1250                         (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1251         sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1252         if (sc->desc == NULL) {
1253                 ATH5K_ERR(sc, "can't allocate descriptors\n");
1254                 ret = -ENOMEM;
1255                 goto err;
1256         }
1257         ds = sc->desc;
1258         da = sc->desc_daddr;
1259         ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1260                 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1261
1262         bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1263                         sizeof(struct ath5k_buf), GFP_KERNEL);
1264         if (bf == NULL) {
1265                 ATH5K_ERR(sc, "can't allocate bufptr\n");
1266                 ret = -ENOMEM;
1267                 goto err_free;
1268         }
1269         sc->bufptr = bf;
1270
1271         INIT_LIST_HEAD(&sc->rxbuf);
1272         for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1273                 bf->desc = ds;
1274                 bf->daddr = da;
1275                 list_add_tail(&bf->list, &sc->rxbuf);
1276         }
1277
1278         INIT_LIST_HEAD(&sc->txbuf);
1279         sc->txbuf_len = ATH_TXBUF;
1280         for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1281                         da += sizeof(*ds)) {
1282                 bf->desc = ds;
1283                 bf->daddr = da;
1284                 list_add_tail(&bf->list, &sc->txbuf);
1285         }
1286
1287         /* beacon buffer */
1288         bf->desc = ds;
1289         bf->daddr = da;
1290         sc->bbuf = bf;
1291
1292         return 0;
1293 err_free:
1294         pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1295 err:
1296         sc->desc = NULL;
1297         return ret;
1298 }
1299
1300 static void
1301 ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1302 {
1303         struct ath5k_buf *bf;
1304
1305         ath5k_txbuf_free(sc, sc->bbuf);
1306         list_for_each_entry(bf, &sc->txbuf, list)
1307                 ath5k_txbuf_free(sc, bf);
1308         list_for_each_entry(bf, &sc->rxbuf, list)
1309                 ath5k_txbuf_free(sc, bf);
1310
1311         /* Free memory associated with all descriptors */
1312         pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1313
1314         kfree(sc->bufptr);
1315         sc->bufptr = NULL;
1316 }
1317
1318
1319
1320
1321
1322 /**************\
1323 * Queues setup *
1324 \**************/
1325
1326 static struct ath5k_txq *
1327 ath5k_txq_setup(struct ath5k_softc *sc,
1328                 int qtype, int subtype)
1329 {
1330         struct ath5k_hw *ah = sc->ah;
1331         struct ath5k_txq *txq;
1332         struct ath5k_txq_info qi = {
1333                 .tqi_subtype = subtype,
1334                 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1335                 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1336                 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1337         };
1338         int qnum;
1339
1340         /*
1341          * Enable interrupts only for EOL and DESC conditions.
1342          * We mark tx descriptors to receive a DESC interrupt
1343          * when a tx queue gets deep; otherwise waiting for the
1344          * EOL to reap descriptors.  Note that this is done to
1345          * reduce interrupt load and this only defers reaping
1346          * descriptors, never transmitting frames.  Aside from
1347          * reducing interrupts this also permits more concurrency.
1348          * The only potential downside is if the tx queue backs
1349          * up in which case the top half of the kernel may backup
1350          * due to a lack of tx descriptors.
1351          */
1352         qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1353                                 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1354         qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1355         if (qnum < 0) {
1356                 /*
1357                  * NB: don't print a message, this happens
1358                  * normally on parts with too few tx queues
1359                  */
1360                 return ERR_PTR(qnum);
1361         }
1362         if (qnum >= ARRAY_SIZE(sc->txqs)) {
1363                 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1364                         qnum, ARRAY_SIZE(sc->txqs));
1365                 ath5k_hw_release_tx_queue(ah, qnum);
1366                 return ERR_PTR(-EINVAL);
1367         }
1368         txq = &sc->txqs[qnum];
1369         if (!txq->setup) {
1370                 txq->qnum = qnum;
1371                 txq->link = NULL;
1372                 INIT_LIST_HEAD(&txq->q);
1373                 spin_lock_init(&txq->lock);
1374                 txq->setup = true;
1375         }
1376         return &sc->txqs[qnum];
1377 }
1378
1379 static int
1380 ath5k_beaconq_setup(struct ath5k_hw *ah)
1381 {
1382         struct ath5k_txq_info qi = {
1383                 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1384                 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1385                 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1386                 /* NB: for dynamic turbo, don't enable any other interrupts */
1387                 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1388         };
1389
1390         return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1391 }
1392
1393 static int
1394 ath5k_beaconq_config(struct ath5k_softc *sc)
1395 {
1396         struct ath5k_hw *ah = sc->ah;
1397         struct ath5k_txq_info qi;
1398         int ret;
1399
1400         ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1401         if (ret)
1402                 return ret;
1403         if (sc->opmode == NL80211_IFTYPE_AP ||
1404                 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
1405                 /*
1406                  * Always burst out beacon and CAB traffic
1407                  * (aifs = cwmin = cwmax = 0)
1408                  */
1409                 qi.tqi_aifs = 0;
1410                 qi.tqi_cw_min = 0;
1411                 qi.tqi_cw_max = 0;
1412         } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
1413                 /*
1414                  * Adhoc mode; backoff between 0 and (2 * cw_min).
1415                  */
1416                 qi.tqi_aifs = 0;
1417                 qi.tqi_cw_min = 0;
1418                 qi.tqi_cw_max = 2 * ah->ah_cw_min;
1419         }
1420
1421         ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1422                 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1423                 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1424
1425         ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
1426         if (ret) {
1427                 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1428                         "hardware queue!\n", __func__);
1429                 return ret;
1430         }
1431
1432         return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */;
1433 }
1434
1435 static void
1436 ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1437 {
1438         struct ath5k_buf *bf, *bf0;
1439
1440         /*
1441          * NB: this assumes output has been stopped and
1442          *     we do not need to block ath5k_tx_tasklet
1443          */
1444         spin_lock_bh(&txq->lock);
1445         list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1446                 ath5k_debug_printtxbuf(sc, bf);
1447
1448                 ath5k_txbuf_free(sc, bf);
1449
1450                 spin_lock_bh(&sc->txbuflock);
1451                 sc->tx_stats[txq->qnum].len--;
1452                 list_move_tail(&bf->list, &sc->txbuf);
1453                 sc->txbuf_len++;
1454                 spin_unlock_bh(&sc->txbuflock);
1455         }
1456         txq->link = NULL;
1457         spin_unlock_bh(&txq->lock);
1458 }
1459
1460 /*
1461  * Drain the transmit queues and reclaim resources.
1462  */
1463 static void
1464 ath5k_txq_cleanup(struct ath5k_softc *sc)
1465 {
1466         struct ath5k_hw *ah = sc->ah;
1467         unsigned int i;
1468
1469         /* XXX return value */
1470         if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1471                 /* don't touch the hardware if marked invalid */
1472                 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1473                 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
1474                         ath5k_hw_get_txdp(ah, sc->bhalq));
1475                 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1476                         if (sc->txqs[i].setup) {
1477                                 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1478                                 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1479                                         "link %p\n",
1480                                         sc->txqs[i].qnum,
1481                                         ath5k_hw_get_txdp(ah,
1482                                                         sc->txqs[i].qnum),
1483                                         sc->txqs[i].link);
1484                         }
1485         }
1486         ieee80211_wake_queues(sc->hw); /* XXX move to callers */
1487
1488         for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1489                 if (sc->txqs[i].setup)
1490                         ath5k_txq_drainq(sc, &sc->txqs[i]);
1491 }
1492
1493 static void
1494 ath5k_txq_release(struct ath5k_softc *sc)
1495 {
1496         struct ath5k_txq *txq = sc->txqs;
1497         unsigned int i;
1498
1499         for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1500                 if (txq->setup) {
1501                         ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1502                         txq->setup = false;
1503                 }
1504 }
1505
1506
1507
1508
1509 /*************\
1510 * RX Handling *
1511 \*************/
1512
1513 /*
1514  * Enable the receive h/w following a reset.
1515  */
1516 static int
1517 ath5k_rx_start(struct ath5k_softc *sc)
1518 {
1519         struct ath5k_hw *ah = sc->ah;
1520         struct ath5k_buf *bf;
1521         int ret;
1522
1523         sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->cachelsz);
1524
1525         ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rxbufsize %u\n",
1526                 sc->cachelsz, sc->rxbufsize);
1527
1528         sc->rxlink = NULL;
1529
1530         spin_lock_bh(&sc->rxbuflock);
1531         list_for_each_entry(bf, &sc->rxbuf, list) {
1532                 ret = ath5k_rxbuf_setup(sc, bf);
1533                 if (ret != 0) {
1534                         spin_unlock_bh(&sc->rxbuflock);
1535                         goto err;
1536                 }
1537         }
1538         bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1539         spin_unlock_bh(&sc->rxbuflock);
1540
1541         ath5k_hw_set_rxdp(ah, bf->daddr);
1542         ath5k_hw_start_rx_dma(ah);      /* enable recv descriptors */
1543         ath5k_mode_setup(sc);           /* set filters, etc. */
1544         ath5k_hw_start_rx_pcu(ah);      /* re-enable PCU/DMA engine */
1545
1546         return 0;
1547 err:
1548         return ret;
1549 }
1550
1551 /*
1552  * Disable the receive h/w in preparation for a reset.
1553  */
1554 static void
1555 ath5k_rx_stop(struct ath5k_softc *sc)
1556 {
1557         struct ath5k_hw *ah = sc->ah;
1558
1559         ath5k_hw_stop_rx_pcu(ah);       /* disable PCU */
1560         ath5k_hw_set_rx_filter(ah, 0);  /* clear recv filter */
1561         ath5k_hw_stop_rx_dma(ah);       /* disable DMA engine */
1562
1563         ath5k_debug_printrxbuffs(sc, ah);
1564
1565         sc->rxlink = NULL;              /* just in case */
1566 }
1567
1568 static unsigned int
1569 ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
1570                 struct sk_buff *skb, struct ath5k_rx_status *rs)
1571 {
1572         struct ieee80211_hdr *hdr = (void *)skb->data;
1573         unsigned int keyix, hlen;
1574
1575         if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1576                         rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1577                 return RX_FLAG_DECRYPTED;
1578
1579         /* Apparently when a default key is used to decrypt the packet
1580            the hw does not set the index used to decrypt.  In such cases
1581            get the index from the packet. */
1582         hlen = ieee80211_hdrlen(hdr->frame_control);
1583         if (ieee80211_has_protected(hdr->frame_control) &&
1584             !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1585             skb->len >= hlen + 4) {
1586                 keyix = skb->data[hlen + 3] >> 6;
1587
1588                 if (test_bit(keyix, sc->keymap))
1589                         return RX_FLAG_DECRYPTED;
1590         }
1591
1592         return 0;
1593 }
1594
1595
1596 static void
1597 ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1598                      struct ieee80211_rx_status *rxs)
1599 {
1600         u64 tsf, bc_tstamp;
1601         u32 hw_tu;
1602         struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1603
1604         if (ieee80211_is_beacon(mgmt->frame_control) &&
1605             le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
1606             memcmp(mgmt->bssid, sc->ah->ah_bssid, ETH_ALEN) == 0) {
1607                 /*
1608                  * Received an IBSS beacon with the same BSSID. Hardware *must*
1609                  * have updated the local TSF. We have to work around various
1610                  * hardware bugs, though...
1611                  */
1612                 tsf = ath5k_hw_get_tsf64(sc->ah);
1613                 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1614                 hw_tu = TSF_TO_TU(tsf);
1615
1616                 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1617                         "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1618                         (unsigned long long)bc_tstamp,
1619                         (unsigned long long)rxs->mactime,
1620                         (unsigned long long)(rxs->mactime - bc_tstamp),
1621                         (unsigned long long)tsf);
1622
1623                 /*
1624                  * Sometimes the HW will give us a wrong tstamp in the rx
1625                  * status, causing the timestamp extension to go wrong.
1626                  * (This seems to happen especially with beacon frames bigger
1627                  * than 78 byte (incl. FCS))
1628                  * But we know that the receive timestamp must be later than the
1629                  * timestamp of the beacon since HW must have synced to that.
1630                  *
1631                  * NOTE: here we assume mactime to be after the frame was
1632                  * received, not like mac80211 which defines it at the start.
1633                  */
1634                 if (bc_tstamp > rxs->mactime) {
1635                         ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1636                                 "fixing mactime from %llx to %llx\n",
1637                                 (unsigned long long)rxs->mactime,
1638                                 (unsigned long long)tsf);
1639                         rxs->mactime = tsf;
1640                 }
1641
1642                 /*
1643                  * Local TSF might have moved higher than our beacon timers,
1644                  * in that case we have to update them to continue sending
1645                  * beacons. This also takes care of synchronizing beacon sending
1646                  * times with other stations.
1647                  */
1648                 if (hw_tu >= sc->nexttbtt)
1649                         ath5k_beacon_update_timers(sc, bc_tstamp);
1650         }
1651 }
1652
1653
1654 static void
1655 ath5k_tasklet_rx(unsigned long data)
1656 {
1657         struct ieee80211_rx_status rxs = {};
1658         struct ath5k_rx_status rs = {};
1659         struct sk_buff *skb;
1660         struct ath5k_softc *sc = (void *)data;
1661         struct ath5k_buf *bf, *bf_last;
1662         struct ath5k_desc *ds;
1663         int ret;
1664         int hdrlen;
1665         int pad;
1666
1667         spin_lock(&sc->rxbuflock);
1668         if (list_empty(&sc->rxbuf)) {
1669                 ATH5K_WARN(sc, "empty rx buf pool\n");
1670                 goto unlock;
1671         }
1672         bf_last = list_entry(sc->rxbuf.prev, struct ath5k_buf, list);
1673         do {
1674                 rxs.flag = 0;
1675
1676                 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1677                 BUG_ON(bf->skb == NULL);
1678                 skb = bf->skb;
1679                 ds = bf->desc;
1680
1681                 /*
1682                  * last buffer must not be freed to ensure proper hardware
1683                  * function. When the hardware finishes also a packet next to
1684                  * it, we are sure, it doesn't use it anymore and we can go on.
1685                  */
1686                 if (bf_last == bf)
1687                         bf->flags |= 1;
1688                 if (bf->flags) {
1689                         struct ath5k_buf *bf_next = list_entry(bf->list.next,
1690                                         struct ath5k_buf, list);
1691                         ret = sc->ah->ah_proc_rx_desc(sc->ah, bf_next->desc,
1692                                         &rs);
1693                         if (ret)
1694                                 break;
1695                         bf->flags &= ~1;
1696                         /* skip the overwritten one (even status is martian) */
1697                         goto next;
1698                 }
1699
1700                 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
1701                 if (unlikely(ret == -EINPROGRESS))
1702                         break;
1703                 else if (unlikely(ret)) {
1704                         ATH5K_ERR(sc, "error in processing rx descriptor\n");
1705                         spin_unlock(&sc->rxbuflock);
1706                         return;
1707                 }
1708
1709                 if (unlikely(rs.rs_more)) {
1710                         ATH5K_WARN(sc, "unsupported jumbo\n");
1711                         goto next;
1712                 }
1713
1714                 if (unlikely(rs.rs_status)) {
1715                         if (rs.rs_status & AR5K_RXERR_PHY)
1716                                 goto next;
1717                         if (rs.rs_status & AR5K_RXERR_DECRYPT) {
1718                                 /*
1719                                  * Decrypt error.  If the error occurred
1720                                  * because there was no hardware key, then
1721                                  * let the frame through so the upper layers
1722                                  * can process it.  This is necessary for 5210
1723                                  * parts which have no way to setup a ``clear''
1724                                  * key cache entry.
1725                                  *
1726                                  * XXX do key cache faulting
1727                                  */
1728                                 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1729                                     !(rs.rs_status & AR5K_RXERR_CRC))
1730                                         goto accept;
1731                         }
1732                         if (rs.rs_status & AR5K_RXERR_MIC) {
1733                                 rxs.flag |= RX_FLAG_MMIC_ERROR;
1734                                 goto accept;
1735                         }
1736
1737                         /* let crypto-error packets fall through in MNTR */
1738                         if ((rs.rs_status &
1739                                 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
1740                                         sc->opmode != NL80211_IFTYPE_MONITOR)
1741                                 goto next;
1742                 }
1743 accept:
1744                 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
1745                                 PCI_DMA_FROMDEVICE);
1746                 bf->skb = NULL;
1747
1748                 skb_put(skb, rs.rs_datalen);
1749
1750                 /*
1751                  * the hardware adds a padding to 4 byte boundaries between
1752                  * the header and the payload data if the header length is
1753                  * not multiples of 4 - remove it
1754                  */
1755                 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1756                 if (hdrlen & 3) {
1757                         pad = hdrlen % 4;
1758                         memmove(skb->data + pad, skb->data, hdrlen);
1759                         skb_pull(skb, pad);
1760                 }
1761
1762                 /*
1763                  * always extend the mac timestamp, since this information is
1764                  * also needed for proper IBSS merging.
1765                  *
1766                  * XXX: it might be too late to do it here, since rs_tstamp is
1767                  * 15bit only. that means TSF extension has to be done within
1768                  * 32768usec (about 32ms). it might be necessary to move this to
1769                  * the interrupt handler, like it is done in madwifi.
1770                  *
1771                  * Unfortunately we don't know when the hardware takes the rx
1772                  * timestamp (beginning of phy frame, data frame, end of rx?).
1773                  * The only thing we know is that it is hardware specific...
1774                  * On AR5213 it seems the rx timestamp is at the end of the
1775                  * frame, but i'm not sure.
1776                  *
1777                  * NOTE: mac80211 defines mactime at the beginning of the first
1778                  * data symbol. Since we don't have any time references it's
1779                  * impossible to comply to that. This affects IBSS merge only
1780                  * right now, so it's not too bad...
1781                  */
1782                 rxs.mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
1783                 rxs.flag |= RX_FLAG_TSFT;
1784
1785                 rxs.freq = sc->curchan->center_freq;
1786                 rxs.band = sc->curband->band;
1787
1788                 rxs.noise = sc->ah->ah_noise_floor;
1789                 rxs.signal = rxs.noise + rs.rs_rssi;
1790
1791                 /* An rssi of 35 indicates you should be able use
1792                  * 54 Mbps reliably. A more elaborate scheme can be used
1793                  * here but it requires a map of SNR/throughput for each
1794                  * possible mode used */
1795                 rxs.qual = rs.rs_rssi * 100 / 35;
1796
1797                 /* rssi can be more than 35 though, anything above that
1798                  * should be considered at 100% */
1799                 if (rxs.qual > 100)
1800                         rxs.qual = 100;
1801
1802                 rxs.antenna = rs.rs_antenna;
1803                 rxs.rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
1804                 rxs.flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
1805
1806                 if (rxs.rate_idx >= 0 && rs.rs_rate ==
1807                     sc->curband->bitrates[rxs.rate_idx].hw_value_short)
1808                         rxs.flag |= RX_FLAG_SHORTPRE;
1809
1810                 ath5k_debug_dump_skb(sc, skb, "RX  ", 0);
1811
1812                 /* check beacons in IBSS mode */
1813                 if (sc->opmode == NL80211_IFTYPE_ADHOC)
1814                         ath5k_check_ibss_tsf(sc, skb, &rxs);
1815
1816                 __ieee80211_rx(sc->hw, skb, &rxs);
1817 next:
1818                 list_move_tail(&bf->list, &sc->rxbuf);
1819         } while (ath5k_rxbuf_setup(sc, bf) == 0);
1820 unlock:
1821         spin_unlock(&sc->rxbuflock);
1822 }
1823
1824
1825
1826
1827 /*************\
1828 * TX Handling *
1829 \*************/
1830
1831 static void
1832 ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1833 {
1834         struct ath5k_tx_status ts = {};
1835         struct ath5k_buf *bf, *bf0;
1836         struct ath5k_desc *ds;
1837         struct sk_buff *skb;
1838         struct ieee80211_tx_info *info;
1839         int i, ret;
1840
1841         spin_lock(&txq->lock);
1842         list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1843                 ds = bf->desc;
1844
1845                 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
1846                 if (unlikely(ret == -EINPROGRESS))
1847                         break;
1848                 else if (unlikely(ret)) {
1849                         ATH5K_ERR(sc, "error %d while processing queue %u\n",
1850                                 ret, txq->qnum);
1851                         break;
1852                 }
1853
1854                 skb = bf->skb;
1855                 info = IEEE80211_SKB_CB(skb);
1856                 bf->skb = NULL;
1857
1858                 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1859                                 PCI_DMA_TODEVICE);
1860
1861                 ieee80211_tx_info_clear_status(info);
1862                 for (i = 0; i < 4; i++) {
1863                         struct ieee80211_tx_rate *r =
1864                                 &info->status.rates[i];
1865
1866                         if (ts.ts_rate[i]) {
1867                                 r->idx = ath5k_hw_to_driver_rix(sc, ts.ts_rate[i]);
1868                                 r->count = ts.ts_retry[i];
1869                         } else {
1870                                 r->idx = -1;
1871                                 r->count = 0;
1872                         }
1873                 }
1874
1875                 /* count the successful attempt as well */
1876                 info->status.rates[ts.ts_final_idx].count++;
1877
1878                 if (unlikely(ts.ts_status)) {
1879                         sc->ll_stats.dot11ACKFailureCount++;
1880                         if (ts.ts_status & AR5K_TXERR_FILT)
1881                                 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1882                 } else {
1883                         info->flags |= IEEE80211_TX_STAT_ACK;
1884                         info->status.ack_signal = ts.ts_rssi;
1885                 }
1886
1887                 ieee80211_tx_status(sc->hw, skb);
1888                 sc->tx_stats[txq->qnum].count++;
1889
1890                 spin_lock(&sc->txbuflock);
1891                 sc->tx_stats[txq->qnum].len--;
1892                 list_move_tail(&bf->list, &sc->txbuf);
1893                 sc->txbuf_len++;
1894                 spin_unlock(&sc->txbuflock);
1895         }
1896         if (likely(list_empty(&txq->q)))
1897                 txq->link = NULL;
1898         spin_unlock(&txq->lock);
1899         if (sc->txbuf_len > ATH_TXBUF / 5)
1900                 ieee80211_wake_queues(sc->hw);
1901 }
1902
1903 static void
1904 ath5k_tasklet_tx(unsigned long data)
1905 {
1906         struct ath5k_softc *sc = (void *)data;
1907
1908         ath5k_tx_processq(sc, sc->txq);
1909 }
1910
1911
1912 /*****************\
1913 * Beacon handling *
1914 \*****************/
1915
1916 /*
1917  * Setup the beacon frame for transmit.
1918  */
1919 static int
1920 ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1921 {
1922         struct sk_buff *skb = bf->skb;
1923         struct  ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1924         struct ath5k_hw *ah = sc->ah;
1925         struct ath5k_desc *ds;
1926         int ret, antenna = 0;
1927         u32 flags;
1928
1929         bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1930                         PCI_DMA_TODEVICE);
1931         ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1932                         "skbaddr %llx\n", skb, skb->data, skb->len,
1933                         (unsigned long long)bf->skbaddr);
1934         if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
1935                 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
1936                 return -EIO;
1937         }
1938
1939         ds = bf->desc;
1940
1941         flags = AR5K_TXDESC_NOACK;
1942         if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
1943                 ds->ds_link = bf->daddr;        /* self-linked */
1944                 flags |= AR5K_TXDESC_VEOL;
1945                 /*
1946                  * Let hardware handle antenna switching if txantenna is not set
1947                  */
1948         } else {
1949                 ds->ds_link = 0;
1950                 /*
1951                  * Switch antenna every 4 beacons if txantenna is not set
1952                  * XXX assumes two antennas
1953                  */
1954                 if (antenna == 0)
1955                         antenna = sc->bsent & 4 ? 2 : 1;
1956         }
1957
1958         ds->ds_data = bf->skbaddr;
1959         ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
1960                         ieee80211_get_hdrlen_from_skb(skb),
1961                         AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
1962                         ieee80211_get_tx_rate(sc->hw, info)->hw_value,
1963                         1, AR5K_TXKEYIX_INVALID,
1964                         antenna, flags, 0, 0);
1965         if (ret)
1966                 goto err_unmap;
1967
1968         return 0;
1969 err_unmap:
1970         pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1971         return ret;
1972 }
1973
1974 /*
1975  * Transmit a beacon frame at SWBA.  Dynamic updates to the
1976  * frame contents are done as needed and the slot time is
1977  * also adjusted based on current state.
1978  *
1979  * this is usually called from interrupt context (ath5k_intr())
1980  * but also from ath5k_beacon_config() in IBSS mode which in turn
1981  * can be called from a tasklet and user context
1982  */
1983 static void
1984 ath5k_beacon_send(struct ath5k_softc *sc)
1985 {
1986         struct ath5k_buf *bf = sc->bbuf;
1987         struct ath5k_hw *ah = sc->ah;
1988
1989         ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
1990
1991         if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
1992                         sc->opmode == NL80211_IFTYPE_MONITOR)) {
1993                 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
1994                 return;
1995         }
1996         /*
1997          * Check if the previous beacon has gone out.  If
1998          * not don't don't try to post another, skip this
1999          * period and wait for the next.  Missed beacons
2000          * indicate a problem and should not occur.  If we
2001          * miss too many consecutive beacons reset the device.
2002          */
2003         if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
2004                 sc->bmisscount++;
2005                 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2006                         "missed %u consecutive beacons\n", sc->bmisscount);
2007                 if (sc->bmisscount > 3) {               /* NB: 3 is a guess */
2008                         ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2009                                 "stuck beacon time (%u missed)\n",
2010                                 sc->bmisscount);
2011                         tasklet_schedule(&sc->restq);
2012                 }
2013                 return;
2014         }
2015         if (unlikely(sc->bmisscount != 0)) {
2016                 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2017                         "resume beacon xmit after %u misses\n",
2018                         sc->bmisscount);
2019                 sc->bmisscount = 0;
2020         }
2021
2022         /*
2023          * Stop any current dma and put the new frame on the queue.
2024          * This should never fail since we check above that no frames
2025          * are still pending on the queue.
2026          */
2027         if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
2028                 ATH5K_WARN(sc, "beacon queue %u didn't stop?\n", sc->bhalq);
2029                 /* NB: hw still stops DMA, so proceed */
2030         }
2031
2032         ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
2033         ath5k_hw_start_tx_dma(ah, sc->bhalq);
2034         ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
2035                 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2036
2037         sc->bsent++;
2038 }
2039
2040
2041 /**
2042  * ath5k_beacon_update_timers - update beacon timers
2043  *
2044  * @sc: struct ath5k_softc pointer we are operating on
2045  * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2046  *          beacon timer update based on the current HW TSF.
2047  *
2048  * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2049  * of a received beacon or the current local hardware TSF and write it to the
2050  * beacon timer registers.
2051  *
2052  * This is called in a variety of situations, e.g. when a beacon is received,
2053  * when a TSF update has been detected, but also when an new IBSS is created or
2054  * when we otherwise know we have to update the timers, but we keep it in this
2055  * function to have it all together in one place.
2056  */
2057 static void
2058 ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
2059 {
2060         struct ath5k_hw *ah = sc->ah;
2061         u32 nexttbtt, intval, hw_tu, bc_tu;
2062         u64 hw_tsf;
2063
2064         intval = sc->bintval & AR5K_BEACON_PERIOD;
2065         if (WARN_ON(!intval))
2066                 return;
2067
2068         /* beacon TSF converted to TU */
2069         bc_tu = TSF_TO_TU(bc_tsf);
2070
2071         /* current TSF converted to TU */
2072         hw_tsf = ath5k_hw_get_tsf64(ah);
2073         hw_tu = TSF_TO_TU(hw_tsf);
2074
2075 #define FUDGE 3
2076         /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2077         if (bc_tsf == -1) {
2078                 /*
2079                  * no beacons received, called internally.
2080                  * just need to refresh timers based on HW TSF.
2081                  */
2082                 nexttbtt = roundup(hw_tu + FUDGE, intval);
2083         } else if (bc_tsf == 0) {
2084                 /*
2085                  * no beacon received, probably called by ath5k_reset_tsf().
2086                  * reset TSF to start with 0.
2087                  */
2088                 nexttbtt = intval;
2089                 intval |= AR5K_BEACON_RESET_TSF;
2090         } else if (bc_tsf > hw_tsf) {
2091                 /*
2092                  * beacon received, SW merge happend but HW TSF not yet updated.
2093                  * not possible to reconfigure timers yet, but next time we
2094                  * receive a beacon with the same BSSID, the hardware will
2095                  * automatically update the TSF and then we need to reconfigure
2096                  * the timers.
2097                  */
2098                 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2099                         "need to wait for HW TSF sync\n");
2100                 return;
2101         } else {
2102                 /*
2103                  * most important case for beacon synchronization between STA.
2104                  *
2105                  * beacon received and HW TSF has been already updated by HW.
2106                  * update next TBTT based on the TSF of the beacon, but make
2107                  * sure it is ahead of our local TSF timer.
2108                  */
2109                 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2110         }
2111 #undef FUDGE
2112
2113         sc->nexttbtt = nexttbtt;
2114
2115         intval |= AR5K_BEACON_ENA;
2116         ath5k_hw_init_beacon(ah, nexttbtt, intval);
2117
2118         /*
2119          * debugging output last in order to preserve the time critical aspect
2120          * of this function
2121          */
2122         if (bc_tsf == -1)
2123                 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2124                         "reconfigured timers based on HW TSF\n");
2125         else if (bc_tsf == 0)
2126                 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2127                         "reset HW TSF and timers\n");
2128         else
2129                 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2130                         "updated timers based on beacon TSF\n");
2131
2132         ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2133                           "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2134                           (unsigned long long) bc_tsf,
2135                           (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
2136         ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2137                 intval & AR5K_BEACON_PERIOD,
2138                 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2139                 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
2140 }
2141
2142
2143 /**
2144  * ath5k_beacon_config - Configure the beacon queues and interrupts
2145  *
2146  * @sc: struct ath5k_softc pointer we are operating on
2147  *
2148  * When operating in station mode we want to receive a BMISS interrupt when we
2149  * stop seeing beacons from the AP we've associated with so we can look for
2150  * another AP to associate with.
2151  *
2152  * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2153  * interrupts to detect TSF updates only.
2154  */
2155 static void
2156 ath5k_beacon_config(struct ath5k_softc *sc)
2157 {
2158         struct ath5k_hw *ah = sc->ah;
2159
2160         ath5k_hw_set_imr(ah, 0);
2161         sc->bmisscount = 0;
2162         sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
2163
2164         if (sc->opmode == NL80211_IFTYPE_STATION) {
2165                 sc->imask |= AR5K_INT_BMISS;
2166         } else if (sc->opmode == NL80211_IFTYPE_ADHOC ||
2167                         sc->opmode == NL80211_IFTYPE_MESH_POINT ||
2168                         sc->opmode == NL80211_IFTYPE_AP) {
2169                 /*
2170                  * In IBSS mode we use a self-linked tx descriptor and let the
2171                  * hardware send the beacons automatically. We have to load it
2172                  * only once here.
2173                  * We use the SWBA interrupt only to keep track of the beacon
2174                  * timers in order to detect automatic TSF updates.
2175                  */
2176                 ath5k_beaconq_config(sc);
2177
2178                 sc->imask |= AR5K_INT_SWBA;
2179
2180                 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2181                         if (ath5k_hw_hasveol(ah)) {
2182                                 spin_lock(&sc->block);
2183                                 ath5k_beacon_send(sc);
2184                                 spin_unlock(&sc->block);
2185                         }
2186                 } else
2187                         ath5k_beacon_update_timers(sc, -1);
2188         }
2189
2190         ath5k_hw_set_imr(ah, sc->imask);
2191 }
2192
2193
2194 /********************\
2195 * Interrupt handling *
2196 \********************/
2197
2198 static int
2199 ath5k_init(struct ath5k_softc *sc, bool is_resume)
2200 {
2201         struct ath5k_hw *ah = sc->ah;
2202         int ret, i;
2203
2204         mutex_lock(&sc->lock);
2205
2206         if (is_resume && !test_bit(ATH_STAT_STARTED, sc->status))
2207                 goto out_ok;
2208
2209         __clear_bit(ATH_STAT_STARTED, sc->status);
2210
2211         ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2212
2213         /*
2214          * Stop anything previously setup.  This is safe
2215          * no matter this is the first time through or not.
2216          */
2217         ath5k_stop_locked(sc);
2218
2219         /*
2220          * The basic interface to setting the hardware in a good
2221          * state is ``reset''.  On return the hardware is known to
2222          * be powered up and with interrupts disabled.  This must
2223          * be followed by initialization of the appropriate bits
2224          * and then setup of the interrupt mask.
2225          */
2226         sc->curchan = sc->hw->conf.channel;
2227         sc->curband = &sc->sbands[sc->curchan->band];
2228         sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2229                 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
2230                 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_MIB;
2231         ret = ath5k_reset(sc, false, false);
2232         if (ret)
2233                 goto done;
2234
2235         /*
2236          * Reset the key cache since some parts do not reset the
2237          * contents on initial power up or resume from suspend.
2238          */
2239         for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
2240                 ath5k_hw_reset_key(ah, i);
2241
2242         __set_bit(ATH_STAT_STARTED, sc->status);
2243
2244         /* Set ack to be sent at low bit-rates */
2245         ath5k_hw_set_ack_bitrate_high(ah, false);
2246
2247         mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2248                         msecs_to_jiffies(ath5k_calinterval * 1000)));
2249
2250 out_ok:
2251         ret = 0;
2252 done:
2253         mmiowb();
2254         mutex_unlock(&sc->lock);
2255         return ret;
2256 }
2257
2258 static int
2259 ath5k_stop_locked(struct ath5k_softc *sc)
2260 {
2261         struct ath5k_hw *ah = sc->ah;
2262
2263         ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2264                         test_bit(ATH_STAT_INVALID, sc->status));
2265
2266         /*
2267          * Shutdown the hardware and driver:
2268          *    stop output from above
2269          *    disable interrupts
2270          *    turn off timers
2271          *    turn off the radio
2272          *    clear transmit machinery
2273          *    clear receive machinery
2274          *    drain and release tx queues
2275          *    reclaim beacon resources
2276          *    power down hardware
2277          *
2278          * Note that some of this work is not possible if the
2279          * hardware is gone (invalid).
2280          */
2281         ieee80211_stop_queues(sc->hw);
2282
2283         if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2284                 ath5k_led_off(sc);
2285                 ath5k_hw_set_imr(ah, 0);
2286                 synchronize_irq(sc->pdev->irq);
2287         }
2288         ath5k_txq_cleanup(sc);
2289         if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2290                 ath5k_rx_stop(sc);
2291                 ath5k_hw_phy_disable(ah);
2292         } else
2293                 sc->rxlink = NULL;
2294
2295         return 0;
2296 }
2297
2298 /*
2299  * Stop the device, grabbing the top-level lock to protect
2300  * against concurrent entry through ath5k_init (which can happen
2301  * if another thread does a system call and the thread doing the
2302  * stop is preempted).
2303  */
2304 static int
2305 ath5k_stop_hw(struct ath5k_softc *sc, bool is_suspend)
2306 {
2307         int ret;
2308
2309         mutex_lock(&sc->lock);
2310         ret = ath5k_stop_locked(sc);
2311         if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2312                 /*
2313                  * Set the chip in full sleep mode.  Note that we are
2314                  * careful to do this only when bringing the interface
2315                  * completely to a stop.  When the chip is in this state
2316                  * it must be carefully woken up or references to
2317                  * registers in the PCI clock domain may freeze the bus
2318                  * (and system).  This varies by chip and is mostly an
2319                  * issue with newer parts that go to sleep more quickly.
2320                  */
2321                 if (sc->ah->ah_mac_srev >= 0x78) {
2322                         /*
2323                          * XXX
2324                          * don't put newer MAC revisions > 7.8 to sleep because
2325                          * of the above mentioned problems
2326                          */
2327                         ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mac version > 7.8, "
2328                                 "not putting device to sleep\n");
2329                 } else {
2330                         ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2331                                 "putting device to full sleep\n");
2332                         ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0);
2333                 }
2334         }
2335         ath5k_txbuf_free(sc, sc->bbuf);
2336         if (!is_suspend)
2337                 __clear_bit(ATH_STAT_STARTED, sc->status);
2338
2339         mmiowb();
2340         mutex_unlock(&sc->lock);
2341
2342         del_timer_sync(&sc->calib_tim);
2343         tasklet_kill(&sc->rxtq);
2344         tasklet_kill(&sc->txtq);
2345         tasklet_kill(&sc->restq);
2346
2347         return ret;
2348 }
2349
2350 static irqreturn_t
2351 ath5k_intr(int irq, void *dev_id)
2352 {
2353         struct ath5k_softc *sc = dev_id;
2354         struct ath5k_hw *ah = sc->ah;
2355         enum ath5k_int status;
2356         unsigned int counter = 1000;
2357
2358         if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2359                                 !ath5k_hw_is_intr_pending(ah)))
2360                 return IRQ_NONE;
2361
2362         do {
2363                 /*
2364                  * Figure out the reason(s) for the interrupt.  Note
2365                  * that get_isr returns a pseudo-ISR that may include
2366                  * bits we haven't explicitly enabled so we mask the
2367                  * value to insure we only process bits we requested.
2368                  */
2369                 ath5k_hw_get_isr(ah, &status);          /* NB: clears IRQ too */
2370                 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2371                                 status, sc->imask);
2372                 status &= sc->imask; /* discard unasked for bits */
2373                 if (unlikely(status & AR5K_INT_FATAL)) {
2374                         /*
2375                          * Fatal errors are unrecoverable.
2376                          * Typically these are caused by DMA errors.
2377                          */
2378                         tasklet_schedule(&sc->restq);
2379                 } else if (unlikely(status & AR5K_INT_RXORN)) {
2380                         tasklet_schedule(&sc->restq);
2381                 } else {
2382                         if (status & AR5K_INT_SWBA) {
2383                                 /*
2384                                 * Software beacon alert--time to send a beacon.
2385                                 * Handle beacon transmission directly; deferring
2386                                 * this is too slow to meet timing constraints
2387                                 * under load.
2388                                 *
2389                                 * In IBSS mode we use this interrupt just to
2390                                 * keep track of the next TBTT (target beacon
2391                                 * transmission time) in order to detect wether
2392                                 * automatic TSF updates happened.
2393                                 */
2394                                 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2395                                          /* XXX: only if VEOL suppported */
2396                                         u64 tsf = ath5k_hw_get_tsf64(ah);
2397                                         sc->nexttbtt += sc->bintval;
2398                                         ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2399                                                   "SWBA nexttbtt: %x hw_tu: %x "
2400                                                   "TSF: %llx\n",
2401                                                   sc->nexttbtt,
2402                                                   TSF_TO_TU(tsf),
2403                                                   (unsigned long long) tsf);
2404                                 } else {
2405                                         spin_lock(&sc->block);
2406                                         ath5k_beacon_send(sc);
2407                                         spin_unlock(&sc->block);
2408                                 }
2409                         }
2410                         if (status & AR5K_INT_RXEOL) {
2411                                 /*
2412                                 * NB: the hardware should re-read the link when
2413                                 *     RXE bit is written, but it doesn't work at
2414                                 *     least on older hardware revs.
2415                                 */
2416                                 sc->rxlink = NULL;
2417                         }
2418                         if (status & AR5K_INT_TXURN) {
2419                                 /* bump tx trigger level */
2420                                 ath5k_hw_update_tx_triglevel(ah, true);
2421                         }
2422                         if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
2423                                 tasklet_schedule(&sc->rxtq);
2424                         if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2425                                         | AR5K_INT_TXERR | AR5K_INT_TXEOL))
2426                                 tasklet_schedule(&sc->txtq);
2427                         if (status & AR5K_INT_BMISS) {
2428                         }
2429                         if (status & AR5K_INT_MIB) {
2430                                 /*
2431                                  * These stats are also used for ANI i think
2432                                  * so how about updating them more often ?
2433                                  */
2434                                 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
2435                         }
2436                 }
2437         } while (ath5k_hw_is_intr_pending(ah) && counter-- > 0);
2438
2439         if (unlikely(!counter))
2440                 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2441
2442         return IRQ_HANDLED;
2443 }
2444
2445 static void
2446 ath5k_tasklet_reset(unsigned long data)
2447 {
2448         struct ath5k_softc *sc = (void *)data;
2449
2450         ath5k_reset_wake(sc);
2451 }
2452
2453 /*
2454  * Periodically recalibrate the PHY to account
2455  * for temperature/environment changes.
2456  */
2457 static void
2458 ath5k_calibrate(unsigned long data)
2459 {
2460         struct ath5k_softc *sc = (void *)data;
2461         struct ath5k_hw *ah = sc->ah;
2462
2463         ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
2464                 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2465                 sc->curchan->hw_value);
2466
2467         if (ath5k_hw_get_rf_gain(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2468                 /*
2469                  * Rfgain is out of bounds, reset the chip
2470                  * to load new gain values.
2471                  */
2472                 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
2473                 ath5k_reset_wake(sc);
2474         }
2475         if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2476                 ATH5K_ERR(sc, "calibration of channel %u failed\n",
2477                         ieee80211_frequency_to_channel(
2478                                 sc->curchan->center_freq));
2479
2480         mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2481                         msecs_to_jiffies(ath5k_calinterval * 1000)));
2482 }
2483
2484
2485
2486 /***************\
2487 * LED functions *
2488 \***************/
2489
2490 static void
2491 ath5k_led_enable(struct ath5k_softc *sc)
2492 {
2493         if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
2494                 ath5k_hw_set_gpio_output(sc->ah, sc->led_pin);
2495                 ath5k_led_off(sc);
2496         }
2497 }
2498
2499 static void
2500 ath5k_led_on(struct ath5k_softc *sc)
2501 {
2502         if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2503                 return;
2504         ath5k_hw_set_gpio(sc->ah, sc->led_pin, sc->led_on);
2505 }
2506
2507 static void
2508 ath5k_led_off(struct ath5k_softc *sc)
2509 {
2510         if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2511                 return;
2512         ath5k_hw_set_gpio(sc->ah, sc->led_pin, !sc->led_on);
2513 }
2514
2515 static void
2516 ath5k_led_brightness_set(struct led_classdev *led_dev,
2517         enum led_brightness brightness)
2518 {
2519         struct ath5k_led *led = container_of(led_dev, struct ath5k_led,
2520                 led_dev);
2521
2522         if (brightness == LED_OFF)
2523                 ath5k_led_off(led->sc);
2524         else
2525                 ath5k_led_on(led->sc);
2526 }
2527
2528 static int
2529 ath5k_register_led(struct ath5k_softc *sc, struct ath5k_led *led,
2530                    const char *name, char *trigger)
2531 {
2532         int err;
2533
2534         led->sc = sc;
2535         strncpy(led->name, name, sizeof(led->name));
2536         led->led_dev.name = led->name;
2537         led->led_dev.default_trigger = trigger;
2538         led->led_dev.brightness_set = ath5k_led_brightness_set;
2539
2540         err = led_classdev_register(&sc->pdev->dev, &led->led_dev);
2541         if (err) {
2542                 ATH5K_WARN(sc, "could not register LED %s\n", name);
2543                 led->sc = NULL;
2544         }
2545         return err;
2546 }
2547
2548 static void
2549 ath5k_unregister_led(struct ath5k_led *led)
2550 {
2551         if (!led->sc)
2552                 return;
2553         led_classdev_unregister(&led->led_dev);
2554         ath5k_led_off(led->sc);
2555         led->sc = NULL;
2556 }
2557
2558 static void
2559 ath5k_unregister_leds(struct ath5k_softc *sc)
2560 {
2561         ath5k_unregister_led(&sc->rx_led);
2562         ath5k_unregister_led(&sc->tx_led);
2563 }
2564
2565
2566 static int
2567 ath5k_init_leds(struct ath5k_softc *sc)
2568 {
2569         int ret = 0;
2570         struct ieee80211_hw *hw = sc->hw;
2571         struct pci_dev *pdev = sc->pdev;
2572         char name[ATH5K_LED_MAX_NAME_LEN + 1];
2573
2574         /*
2575          * Auto-enable soft led processing for IBM cards and for
2576          * 5211 minipci cards.
2577          */
2578         if (pdev->device == PCI_DEVICE_ID_ATHEROS_AR5212_IBM ||
2579             pdev->device == PCI_DEVICE_ID_ATHEROS_AR5211) {
2580                 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2581                 sc->led_pin = 0;
2582                 sc->led_on = 0;  /* active low */
2583         }
2584         /* Enable softled on PIN1 on HP Compaq nc6xx, nc4000 & nx5000 laptops */
2585         if (pdev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ) {
2586                 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2587                 sc->led_pin = 1;
2588                 sc->led_on = 1;  /* active high */
2589         }
2590         if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2591                 goto out;
2592
2593         ath5k_led_enable(sc);
2594
2595         snprintf(name, sizeof(name), "ath5k-%s::rx", wiphy_name(hw->wiphy));
2596         ret = ath5k_register_led(sc, &sc->rx_led, name,
2597                 ieee80211_get_rx_led_name(hw));
2598         if (ret)
2599                 goto out;
2600
2601         snprintf(name, sizeof(name), "ath5k-%s::tx", wiphy_name(hw->wiphy));
2602         ret = ath5k_register_led(sc, &sc->tx_led, name,
2603                 ieee80211_get_tx_led_name(hw));
2604 out:
2605         return ret;
2606 }
2607
2608
2609 /********************\
2610 * Mac80211 functions *
2611 \********************/
2612
2613 static int
2614 ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2615 {
2616         struct ath5k_softc *sc = hw->priv;
2617         struct ath5k_buf *bf;
2618         unsigned long flags;
2619         int hdrlen;
2620         int pad;
2621
2622         ath5k_debug_dump_skb(sc, skb, "TX  ", 1);
2623
2624         if (sc->opmode == NL80211_IFTYPE_MONITOR)
2625                 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2626
2627         /*
2628          * the hardware expects the header padded to 4 byte boundaries
2629          * if this is not the case we add the padding after the header
2630          */
2631         hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2632         if (hdrlen & 3) {
2633                 pad = hdrlen % 4;
2634                 if (skb_headroom(skb) < pad) {
2635                         ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
2636                                 " headroom to pad %d\n", hdrlen, pad);
2637                         return -1;
2638                 }
2639                 skb_push(skb, pad);
2640                 memmove(skb->data, skb->data+pad, hdrlen);
2641         }
2642
2643         spin_lock_irqsave(&sc->txbuflock, flags);
2644         if (list_empty(&sc->txbuf)) {
2645                 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2646                 spin_unlock_irqrestore(&sc->txbuflock, flags);
2647                 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
2648                 return -1;
2649         }
2650         bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2651         list_del(&bf->list);
2652         sc->txbuf_len--;
2653         if (list_empty(&sc->txbuf))
2654                 ieee80211_stop_queues(hw);
2655         spin_unlock_irqrestore(&sc->txbuflock, flags);
2656
2657         bf->skb = skb;
2658
2659         if (ath5k_txbuf_setup(sc, bf)) {
2660                 bf->skb = NULL;
2661                 spin_lock_irqsave(&sc->txbuflock, flags);
2662                 list_add_tail(&bf->list, &sc->txbuf);
2663                 sc->txbuf_len++;
2664                 spin_unlock_irqrestore(&sc->txbuflock, flags);
2665                 dev_kfree_skb_any(skb);
2666                 return 0;
2667         }
2668
2669         return 0;
2670 }
2671
2672 static int
2673 ath5k_reset(struct ath5k_softc *sc, bool stop, bool change_channel)
2674 {
2675         struct ath5k_hw *ah = sc->ah;
2676         int ret;
2677
2678         ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
2679
2680         if (stop) {
2681                 ath5k_hw_set_imr(ah, 0);
2682                 ath5k_txq_cleanup(sc);
2683                 ath5k_rx_stop(sc);
2684         }
2685         ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
2686         if (ret) {
2687                 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2688                 goto err;
2689         }
2690
2691         /*
2692          * This is needed only to setup initial state
2693          * but it's best done after a reset.
2694          */
2695         ath5k_hw_set_txpower_limit(sc->ah, 0);
2696
2697         ret = ath5k_rx_start(sc);
2698         if (ret) {
2699                 ATH5K_ERR(sc, "can't start recv logic\n");
2700                 goto err;
2701         }
2702
2703         /*
2704          * Change channels and update the h/w rate map if we're switching;
2705          * e.g. 11a to 11b/g.
2706          *
2707          * We may be doing a reset in response to an ioctl that changes the
2708          * channel so update any state that might change as a result.
2709          *
2710          * XXX needed?
2711          */
2712 /*      ath5k_chan_change(sc, c); */
2713
2714         ath5k_beacon_config(sc);
2715         /* intrs are enabled by ath5k_beacon_config */
2716
2717         return 0;
2718 err:
2719         return ret;
2720 }
2721
2722 static int
2723 ath5k_reset_wake(struct ath5k_softc *sc)
2724 {
2725         int ret;
2726
2727         ret = ath5k_reset(sc, true, true);
2728         if (!ret)
2729                 ieee80211_wake_queues(sc->hw);
2730
2731         return ret;
2732 }
2733
2734 static int ath5k_start(struct ieee80211_hw *hw)
2735 {
2736         return ath5k_init(hw->priv, false);
2737 }
2738
2739 static void ath5k_stop(struct ieee80211_hw *hw)
2740 {
2741         ath5k_stop_hw(hw->priv, false);
2742 }
2743
2744 static int ath5k_add_interface(struct ieee80211_hw *hw,
2745                 struct ieee80211_if_init_conf *conf)
2746 {
2747         struct ath5k_softc *sc = hw->priv;
2748         int ret;
2749
2750         mutex_lock(&sc->lock);
2751         if (sc->vif) {
2752                 ret = 0;
2753                 goto end;
2754         }
2755
2756         sc->vif = conf->vif;
2757
2758         switch (conf->type) {
2759         case NL80211_IFTYPE_AP:
2760         case NL80211_IFTYPE_STATION:
2761         case NL80211_IFTYPE_ADHOC:
2762         case NL80211_IFTYPE_MESH_POINT:
2763         case NL80211_IFTYPE_MONITOR:
2764                 sc->opmode = conf->type;
2765                 break;
2766         default:
2767                 ret = -EOPNOTSUPP;
2768                 goto end;
2769         }
2770
2771         /* Set to a reasonable value. Note that this will
2772          * be set to mac80211's value at ath5k_config(). */
2773         sc->bintval = 1000;
2774         ath5k_hw_set_lladdr(sc->ah, conf->mac_addr);
2775
2776         ret = 0;
2777 end:
2778         mutex_unlock(&sc->lock);
2779         return ret;
2780 }
2781
2782 static void
2783 ath5k_remove_interface(struct ieee80211_hw *hw,
2784                         struct ieee80211_if_init_conf *conf)
2785 {
2786         struct ath5k_softc *sc = hw->priv;
2787         u8 mac[ETH_ALEN] = {};
2788
2789         mutex_lock(&sc->lock);
2790         if (sc->vif != conf->vif)
2791                 goto end;
2792
2793         ath5k_hw_set_lladdr(sc->ah, mac);
2794         sc->vif = NULL;
2795 end:
2796         mutex_unlock(&sc->lock);
2797 }
2798
2799 /*
2800  * TODO: Phy disable/diversity etc
2801  */
2802 static int
2803 ath5k_config(struct ieee80211_hw *hw, u32 changed)
2804 {
2805         struct ath5k_softc *sc = hw->priv;
2806         struct ieee80211_conf *conf = &hw->conf;
2807
2808         sc->bintval = conf->beacon_int;
2809         sc->power_level = conf->power_level;
2810
2811         return ath5k_chan_set(sc, conf->channel);
2812 }
2813
2814 static int
2815 ath5k_config_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2816                         struct ieee80211_if_conf *conf)
2817 {
2818         struct ath5k_softc *sc = hw->priv;
2819         struct ath5k_hw *ah = sc->ah;
2820         int ret;
2821
2822         mutex_lock(&sc->lock);
2823         if (sc->vif != vif) {
2824                 ret = -EIO;
2825                 goto unlock;
2826         }
2827         if (conf->changed & IEEE80211_IFCC_BSSID && conf->bssid) {
2828                 /* Cache for later use during resets */
2829                 memcpy(ah->ah_bssid, conf->bssid, ETH_ALEN);
2830                 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
2831                  * a clean way of letting us retrieve this yet. */
2832                 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
2833                 mmiowb();
2834         }
2835         if (conf->changed & IEEE80211_IFCC_BEACON &&
2836                         (vif->type == NL80211_IFTYPE_ADHOC ||
2837                          vif->type == NL80211_IFTYPE_MESH_POINT ||
2838                          vif->type == NL80211_IFTYPE_AP)) {
2839                 struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
2840                 if (!beacon) {
2841                         ret = -ENOMEM;
2842                         goto unlock;
2843                 }
2844                 ath5k_beacon_update(sc, beacon);
2845         }
2846         mutex_unlock(&sc->lock);
2847
2848         return ath5k_reset_wake(sc);
2849 unlock:
2850         mutex_unlock(&sc->lock);
2851         return ret;
2852 }
2853
2854 #define SUPPORTED_FIF_FLAGS \
2855         FIF_PROMISC_IN_BSS |  FIF_ALLMULTI | FIF_FCSFAIL | \
2856         FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2857         FIF_BCN_PRBRESP_PROMISC
2858 /*
2859  * o always accept unicast, broadcast, and multicast traffic
2860  * o multicast traffic for all BSSIDs will be enabled if mac80211
2861  *   says it should be
2862  * o maintain current state of phy ofdm or phy cck error reception.
2863  *   If the hardware detects any of these type of errors then
2864  *   ath5k_hw_get_rx_filter() will pass to us the respective
2865  *   hardware filters to be able to receive these type of frames.
2866  * o probe request frames are accepted only when operating in
2867  *   hostap, adhoc, or monitor modes
2868  * o enable promiscuous mode according to the interface state
2869  * o accept beacons:
2870  *   - when operating in adhoc mode so the 802.11 layer creates
2871  *     node table entries for peers,
2872  *   - when operating in station mode for collecting rssi data when
2873  *     the station is otherwise quiet, or
2874  *   - when scanning
2875  */
2876 static void ath5k_configure_filter(struct ieee80211_hw *hw,
2877                 unsigned int changed_flags,
2878                 unsigned int *new_flags,
2879                 int mc_count, struct dev_mc_list *mclist)
2880 {
2881         struct ath5k_softc *sc = hw->priv;
2882         struct ath5k_hw *ah = sc->ah;
2883         u32 mfilt[2], val, rfilt;
2884         u8 pos;
2885         int i;
2886
2887         mfilt[0] = 0;
2888         mfilt[1] = 0;
2889
2890         /* Only deal with supported flags */
2891         changed_flags &= SUPPORTED_FIF_FLAGS;
2892         *new_flags &= SUPPORTED_FIF_FLAGS;
2893
2894         /* If HW detects any phy or radar errors, leave those filters on.
2895          * Also, always enable Unicast, Broadcasts and Multicast
2896          * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2897         rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2898                 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2899                 AR5K_RX_FILTER_MCAST);
2900
2901         if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2902                 if (*new_flags & FIF_PROMISC_IN_BSS) {
2903                         rfilt |= AR5K_RX_FILTER_PROM;
2904                         __set_bit(ATH_STAT_PROMISC, sc->status);
2905                 } else {
2906                         __clear_bit(ATH_STAT_PROMISC, sc->status);
2907                 }
2908         }
2909
2910         /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2911         if (*new_flags & FIF_ALLMULTI) {
2912                 mfilt[0] =  ~0;
2913                 mfilt[1] =  ~0;
2914         } else {
2915                 for (i = 0; i < mc_count; i++) {
2916                         if (!mclist)
2917                                 break;
2918                         /* calculate XOR of eight 6-bit values */
2919                         val = get_unaligned_le32(mclist->dmi_addr + 0);
2920                         pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2921                         val = get_unaligned_le32(mclist->dmi_addr + 3);
2922                         pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2923                         pos &= 0x3f;
2924                         mfilt[pos / 32] |= (1 << (pos % 32));
2925                         /* XXX: we might be able to just do this instead,
2926                         * but not sure, needs testing, if we do use this we'd
2927                         * neet to inform below to not reset the mcast */
2928                         /* ath5k_hw_set_mcast_filterindex(ah,
2929                          *      mclist->dmi_addr[5]); */
2930                         mclist = mclist->next;
2931                 }
2932         }
2933
2934         /* This is the best we can do */
2935         if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
2936                 rfilt |= AR5K_RX_FILTER_PHYERR;
2937
2938         /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2939         * and probes for any BSSID, this needs testing */
2940         if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
2941                 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
2942
2943         /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2944          * set we should only pass on control frames for this
2945          * station. This needs testing. I believe right now this
2946          * enables *all* control frames, which is OK.. but
2947          * but we should see if we can improve on granularity */
2948         if (*new_flags & FIF_CONTROL)
2949                 rfilt |= AR5K_RX_FILTER_CONTROL;
2950
2951         /* Additional settings per mode -- this is per ath5k */
2952
2953         /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2954
2955         if (sc->opmode == NL80211_IFTYPE_MONITOR)
2956                 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2957                         AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
2958         if (sc->opmode != NL80211_IFTYPE_STATION)
2959                 rfilt |= AR5K_RX_FILTER_PROBEREQ;
2960         if (sc->opmode != NL80211_IFTYPE_AP &&
2961                 sc->opmode != NL80211_IFTYPE_MESH_POINT &&
2962                 test_bit(ATH_STAT_PROMISC, sc->status))
2963                 rfilt |= AR5K_RX_FILTER_PROM;
2964         if (sc->opmode == NL80211_IFTYPE_STATION ||
2965                 sc->opmode == NL80211_IFTYPE_ADHOC ||
2966                 sc->opmode == NL80211_IFTYPE_AP)
2967                 rfilt |= AR5K_RX_FILTER_BEACON;
2968         if (sc->opmode == NL80211_IFTYPE_MESH_POINT)
2969                 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2970                         AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
2971
2972         /* Set filters */
2973         ath5k_hw_set_rx_filter(ah, rfilt);
2974
2975         /* Set multicast bits */
2976         ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
2977         /* Set the cached hw filter flags, this will alter actually
2978          * be set in HW */
2979         sc->filter_flags = rfilt;
2980 }
2981
2982 static int
2983 ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2984                 const u8 *local_addr, const u8 *addr,
2985                 struct ieee80211_key_conf *key)
2986 {
2987         struct ath5k_softc *sc = hw->priv;
2988         int ret = 0;
2989
2990         if (modparam_nohwcrypt)
2991                 return -EOPNOTSUPP;
2992
2993         switch (key->alg) {
2994         case ALG_WEP:
2995         case ALG_TKIP:
2996                 break;
2997         case ALG_CCMP:
2998                 return -EOPNOTSUPP;
2999         default:
3000                 WARN_ON(1);
3001                 return -EINVAL;
3002         }
3003
3004         mutex_lock(&sc->lock);
3005
3006         switch (cmd) {
3007         case SET_KEY:
3008                 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key, addr);
3009                 if (ret) {
3010                         ATH5K_ERR(sc, "can't set the key\n");
3011                         goto unlock;
3012                 }
3013                 __set_bit(key->keyidx, sc->keymap);
3014                 key->hw_key_idx = key->keyidx;
3015                 key->flags |= (IEEE80211_KEY_FLAG_GENERATE_IV |
3016                                IEEE80211_KEY_FLAG_GENERATE_MMIC);
3017                 break;
3018         case DISABLE_KEY:
3019                 ath5k_hw_reset_key(sc->ah, key->keyidx);
3020                 __clear_bit(key->keyidx, sc->keymap);
3021                 break;
3022         default:
3023                 ret = -EINVAL;
3024                 goto unlock;
3025         }
3026
3027 unlock:
3028         mmiowb();
3029         mutex_unlock(&sc->lock);
3030         return ret;
3031 }
3032
3033 static int
3034 ath5k_get_stats(struct ieee80211_hw *hw,
3035                 struct ieee80211_low_level_stats *stats)
3036 {
3037         struct ath5k_softc *sc = hw->priv;
3038         struct ath5k_hw *ah = sc->ah;
3039
3040         /* Force update */
3041         ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
3042
3043         memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
3044
3045         return 0;
3046 }
3047
3048 static int
3049 ath5k_get_tx_stats(struct ieee80211_hw *hw,
3050                 struct ieee80211_tx_queue_stats *stats)
3051 {
3052         struct ath5k_softc *sc = hw->priv;
3053
3054         memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats));
3055
3056         return 0;
3057 }
3058
3059 static u64
3060 ath5k_get_tsf(struct ieee80211_hw *hw)
3061 {
3062         struct ath5k_softc *sc = hw->priv;
3063
3064         return ath5k_hw_get_tsf64(sc->ah);
3065 }
3066
3067 static void
3068 ath5k_reset_tsf(struct ieee80211_hw *hw)
3069 {
3070         struct ath5k_softc *sc = hw->priv;
3071
3072         /*
3073          * in IBSS mode we need to update the beacon timers too.
3074          * this will also reset the TSF if we call it with 0
3075          */
3076         if (sc->opmode == NL80211_IFTYPE_ADHOC)
3077                 ath5k_beacon_update_timers(sc, 0);
3078         else
3079                 ath5k_hw_reset_tsf(sc->ah);
3080 }
3081
3082 static int
3083 ath5k_beacon_update(struct ath5k_softc *sc, struct sk_buff *skb)
3084 {
3085         unsigned long flags;
3086         int ret;
3087
3088         ath5k_debug_dump_skb(sc, skb, "BC  ", 1);
3089
3090         spin_lock_irqsave(&sc->block, flags);
3091         ath5k_txbuf_free(sc, sc->bbuf);
3092         sc->bbuf->skb = skb;
3093         ret = ath5k_beacon_setup(sc, sc->bbuf);
3094         if (ret)
3095                 sc->bbuf->skb = NULL;
3096         spin_unlock_irqrestore(&sc->block, flags);
3097         if (!ret) {
3098                 ath5k_beacon_config(sc);
3099                 mmiowb();
3100         }
3101
3102         return ret;
3103 }
3104