1 /* winbond-840.c: A Linux PCI network adapter device driver. */
3 Written 1998-2001 by Donald Becker.
5 This software may be used and distributed according to the terms of
6 the GNU General Public License (GPL), incorporated herein by reference.
7 Drivers based on or derived from this code fall under the GPL and must
8 retain the authorship, copyright and license notice. This file is not
9 a complete program and may only be used when the entire operating
10 system is licensed under the GPL.
12 The author may be reached as becker@scyld.com, or C/O
13 Scyld Computing Corporation
14 410 Severn Ave., Suite 210
17 Support and updates available at
18 http://www.scyld.com/network/drivers.html
20 Do not remove the copyright information.
21 Do not change the version information unless an improvement has been made.
22 Merely removing my name, as Compex has done in the past, does not count
28 * spin lock update, memory barriers, new style dma mappings
29 limit each tx buffer to < 1024 bytes
30 remove DescIntr from Rx descriptors (that's an Tx flag)
31 remove next pointer from Tx descriptors
32 synchronize tx_q_bytes
33 software reset in tx_timeout
34 Copyright (C) 2000 Manfred Spraul
37 support for big endian descriptors
38 Copyright (C) 2001 Manfred Spraul
39 * ethtool support (jgarzik)
40 * Replace some MII-related magic numbers with constants (jgarzik)
43 * enable pci_power_off
47 #define DRV_NAME "winbond-840"
48 #define DRV_VERSION "1.01-e"
49 #define DRV_RELDATE "Sep-11-2006"
52 /* Automatically extracted configuration info:
53 probe-func: winbond840_probe
54 config-in: tristate 'Winbond W89c840 Ethernet support' CONFIG_WINBOND_840
56 c-help-name: Winbond W89c840 PCI Ethernet support
57 c-help-symbol: CONFIG_WINBOND_840
58 c-help: This driver is for the Winbond W89c840 chip. It also works with
59 c-help: the TX9882 chip on the Compex RL100-ATX board.
60 c-help: More specific information and updates are available from
61 c-help: http://www.scyld.com/network/drivers.html
64 /* The user-configurable values.
65 These may be modified when a driver module is loaded.*/
67 static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
68 static int max_interrupt_work = 20;
69 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
70 The '840 uses a 64 element hash table based on the Ethernet CRC. */
71 static int multicast_filter_limit = 32;
73 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
74 Setting to > 1518 effectively disables this feature. */
75 static int rx_copybreak;
77 /* Used to pass the media type, etc.
78 Both 'options[]' and 'full_duplex[]' should exist for driver
80 The media type is usually passed in 'options[]'.
82 #define MAX_UNITS 8 /* More are supported, limit only on options */
83 static int options[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
84 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
86 /* Operational parameters that are set at compile time. */
88 /* Keep the ring sizes a power of two for compile efficiency.
89 The compiler will convert <unsigned>'%'<2^N> into a bit mask.
90 Making the Tx ring too large decreases the effectiveness of channel
91 bonding and packet priority.
92 There are no ill effects from too-large receive rings. */
93 #define TX_QUEUE_LEN 10 /* Limit ring entries actually used. */
94 #define TX_QUEUE_LEN_RESTART 5
96 #define TX_BUFLIMIT (1024-128)
98 /* The presumed FIFO size for working around the Tx-FIFO-overflow bug.
99 To avoid overflowing we don't queue again until we have room for a
102 #define TX_FIFO_SIZE (2048)
103 #define TX_BUG_FIFO_LIMIT (TX_FIFO_SIZE-1514-16)
106 /* Operational parameters that usually are not changed. */
107 /* Time in jiffies before concluding the transmitter is hung. */
108 #define TX_TIMEOUT (2*HZ)
110 /* Include files, designed to support most kernel versions 2.0.0 and later. */
111 #include <linux/module.h>
112 #include <linux/kernel.h>
113 #include <linux/string.h>
114 #include <linux/timer.h>
115 #include <linux/errno.h>
116 #include <linux/ioport.h>
117 #include <linux/slab.h>
118 #include <linux/interrupt.h>
119 #include <linux/pci.h>
120 #include <linux/dma-mapping.h>
121 #include <linux/netdevice.h>
122 #include <linux/etherdevice.h>
123 #include <linux/skbuff.h>
124 #include <linux/init.h>
125 #include <linux/delay.h>
126 #include <linux/ethtool.h>
127 #include <linux/mii.h>
128 #include <linux/rtnetlink.h>
129 #include <linux/crc32.h>
130 #include <linux/bitops.h>
131 #include <asm/uaccess.h>
132 #include <asm/processor.h> /* Processor type for cache alignment. */
138 #undef PKT_BUF_SZ /* tulip.h also defines this */
139 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
141 /* These identify the driver base version and may not be removed. */
142 static char version[] =
143 KERN_INFO DRV_NAME ".c:v" DRV_VERSION " (2.4 port) " DRV_RELDATE " Donald Becker <becker@scyld.com>\n"
144 KERN_INFO " http://www.scyld.com/network/drivers.html\n";
146 MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
147 MODULE_DESCRIPTION("Winbond W89c840 Ethernet driver");
148 MODULE_LICENSE("GPL");
149 MODULE_VERSION(DRV_VERSION);
151 module_param(max_interrupt_work, int, 0);
152 module_param(debug, int, 0);
153 module_param(rx_copybreak, int, 0);
154 module_param(multicast_filter_limit, int, 0);
155 module_param_array(options, int, NULL, 0);
156 module_param_array(full_duplex, int, NULL, 0);
157 MODULE_PARM_DESC(max_interrupt_work, "winbond-840 maximum events handled per interrupt");
158 MODULE_PARM_DESC(debug, "winbond-840 debug level (0-6)");
159 MODULE_PARM_DESC(rx_copybreak, "winbond-840 copy breakpoint for copy-only-tiny-frames");
160 MODULE_PARM_DESC(multicast_filter_limit, "winbond-840 maximum number of filtered multicast addresses");
161 MODULE_PARM_DESC(options, "winbond-840: Bits 0-3: media type, bit 17: full duplex");
162 MODULE_PARM_DESC(full_duplex, "winbond-840 full duplex setting(s) (1)");
167 I. Board Compatibility
169 This driver is for the Winbond w89c840 chip.
171 II. Board-specific settings
175 III. Driver operation
177 This chip is very similar to the Digital 21*4* "Tulip" family. The first
178 twelve registers and the descriptor format are nearly identical. Read a
179 Tulip manual for operational details.
181 A significant difference is that the multicast filter and station address are
182 stored in registers rather than loaded through a pseudo-transmit packet.
184 Unlike the Tulip, transmit buffers are limited to 1KB. To transmit a
185 full-sized packet we must use both data buffers in a descriptor. Thus the
186 driver uses ring mode where descriptors are implicitly sequential in memory,
187 rather than using the second descriptor address as a chain pointer to
188 subsequent descriptors.
192 If you are going to almost clone a Tulip, why not go all the way and avoid
193 the need for a new driver?
197 http://www.scyld.com/expert/100mbps.html
198 http://www.scyld.com/expert/NWay.html
199 http://www.winbond.com.tw/
203 A horrible bug exists in the transmit FIFO. Apparently the chip doesn't
204 correctly detect a full FIFO, and queuing more than 2048 bytes may result in
205 silent data corruption.
207 Test with 'ping -s 10000' on a fast computer.
216 enum chip_capability_flags {
217 CanHaveMII=1, HasBrokenTx=2, AlwaysFDX=4, FDXOnNoMII=8,
220 static const struct pci_device_id w840_pci_tbl[] = {
221 { 0x1050, 0x0840, PCI_ANY_ID, 0x8153, 0, 0, 0 },
222 { 0x1050, 0x0840, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
223 { 0x11f6, 0x2011, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 },
226 MODULE_DEVICE_TABLE(pci, w840_pci_tbl);
229 netdev_res_size = 128, /* size of PCI BAR resource */
234 int drv_flags; /* Driver use, intended as capability flags. */
237 static const struct pci_id_info pci_id_tbl[] __devinitdata = {
238 { /* Sometime a Level-One switch card. */
239 "Winbond W89c840", CanHaveMII | HasBrokenTx | FDXOnNoMII},
240 { "Winbond W89c840", CanHaveMII | HasBrokenTx},
241 { "Compex RL100-ATX", CanHaveMII | HasBrokenTx},
242 { } /* terminate list. */
245 /* This driver was written to use PCI memory space, however some x86 systems
246 work only with I/O space accesses. See CONFIG_TULIP_MMIO in .config
249 /* Offsets to the Command and Status Registers, "CSRs".
250 While similar to the Tulip, these registers are longword aligned.
251 Note: It's not useful to define symbolic names for every register bit in
252 the device. The name can only partially document the semantics and make
253 the driver longer and more difficult to read.
256 PCIBusCfg=0x00, TxStartDemand=0x04, RxStartDemand=0x08,
257 RxRingPtr=0x0C, TxRingPtr=0x10,
258 IntrStatus=0x14, NetworkConfig=0x18, IntrEnable=0x1C,
259 RxMissed=0x20, EECtrl=0x24, MIICtrl=0x24, BootRom=0x28, GPTimer=0x2C,
260 CurRxDescAddr=0x30, CurRxBufAddr=0x34, /* Debug use */
261 MulticastFilter0=0x38, MulticastFilter1=0x3C, StationAddr=0x40,
262 CurTxDescAddr=0x4C, CurTxBufAddr=0x50,
265 /* Bits in the NetworkConfig register. */
268 RxAcceptBroadcast=0x20, AcceptMulticast=0x10,
269 RxAcceptAllPhys=0x08, AcceptMyPhys=0x02,
273 MDIO_ShiftClk=0x10000, MDIO_DataIn=0x80000, MDIO_DataOut=0x20000,
274 MDIO_EnbOutput=0x40000, MDIO_EnbIn = 0x00000,
277 /* The Tulip Rx and Tx buffer descriptors. */
278 struct w840_rx_desc {
285 struct w840_tx_desc {
288 u32 buffer1, buffer2;
291 #define MII_CNT 1 /* winbond only supports one MII */
292 struct netdev_private {
293 struct w840_rx_desc *rx_ring;
294 dma_addr_t rx_addr[RX_RING_SIZE];
295 struct w840_tx_desc *tx_ring;
296 dma_addr_t tx_addr[TX_RING_SIZE];
297 dma_addr_t ring_dma_addr;
298 /* The addresses of receive-in-place skbuffs. */
299 struct sk_buff* rx_skbuff[RX_RING_SIZE];
300 /* The saved address of a sent-in-place packet/buffer, for later free(). */
301 struct sk_buff* tx_skbuff[TX_RING_SIZE];
302 struct net_device_stats stats;
303 struct timer_list timer; /* Media monitoring timer. */
304 /* Frequently used values: keep some adjacent for cache effect. */
306 int chip_id, drv_flags;
307 struct pci_dev *pci_dev;
309 struct w840_rx_desc *rx_head_desc;
310 unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */
311 unsigned int rx_buf_sz; /* Based on MTU+slack. */
312 unsigned int cur_tx, dirty_tx;
313 unsigned int tx_q_bytes;
314 unsigned int tx_full; /* The Tx queue is full. */
315 /* MII transceiver section. */
316 int mii_cnt; /* MII device addresses. */
317 unsigned char phys[MII_CNT]; /* MII device addresses, but only the first is used */
319 struct mii_if_info mii_if;
320 void __iomem *base_addr;
323 static int eeprom_read(void __iomem *ioaddr, int location);
324 static int mdio_read(struct net_device *dev, int phy_id, int location);
325 static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
326 static int netdev_open(struct net_device *dev);
327 static int update_link(struct net_device *dev);
328 static void netdev_timer(unsigned long data);
329 static void init_rxtx_rings(struct net_device *dev);
330 static void free_rxtx_rings(struct netdev_private *np);
331 static void init_registers(struct net_device *dev);
332 static void tx_timeout(struct net_device *dev);
333 static int alloc_ringdesc(struct net_device *dev);
334 static void free_ringdesc(struct netdev_private *np);
335 static int start_tx(struct sk_buff *skb, struct net_device *dev);
336 static irqreturn_t intr_handler(int irq, void *dev_instance);
337 static void netdev_error(struct net_device *dev, int intr_status);
338 static int netdev_rx(struct net_device *dev);
339 static u32 __set_rx_mode(struct net_device *dev);
340 static void set_rx_mode(struct net_device *dev);
341 static struct net_device_stats *get_stats(struct net_device *dev);
342 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
343 static const struct ethtool_ops netdev_ethtool_ops;
344 static int netdev_close(struct net_device *dev);
346 static const struct net_device_ops netdev_ops = {
347 .ndo_open = netdev_open,
348 .ndo_stop = netdev_close,
349 .ndo_start_xmit = start_tx,
350 .ndo_get_stats = get_stats,
351 .ndo_set_multicast_list = set_rx_mode,
352 .ndo_do_ioctl = netdev_ioctl,
353 .ndo_tx_timeout = tx_timeout,
354 .ndo_change_mtu = eth_change_mtu,
355 .ndo_set_mac_address = eth_mac_addr,
356 .ndo_validate_addr = eth_validate_addr,
359 static int __devinit w840_probe1 (struct pci_dev *pdev,
360 const struct pci_device_id *ent)
362 struct net_device *dev;
363 struct netdev_private *np;
365 int chip_idx = ent->driver_data;
367 int i, option = find_cnt < MAX_UNITS ? options[find_cnt] : 0;
368 void __iomem *ioaddr;
370 i = pci_enable_device(pdev);
373 pci_set_master(pdev);
377 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
378 printk(KERN_WARNING "Winbond-840: Device %s disabled due to DMA limitations.\n",
382 dev = alloc_etherdev(sizeof(*np));
385 SET_NETDEV_DEV(dev, &pdev->dev);
387 if (pci_request_regions(pdev, DRV_NAME))
390 ioaddr = pci_iomap(pdev, TULIP_BAR, netdev_res_size);
392 goto err_out_free_res;
394 for (i = 0; i < 3; i++)
395 ((__le16 *)dev->dev_addr)[i] = cpu_to_le16(eeprom_read(ioaddr, i));
397 /* Reset the chip to erase previous misconfiguration.
398 No hold time required! */
399 iowrite32(0x00000001, ioaddr + PCIBusCfg);
401 dev->base_addr = (unsigned long)ioaddr;
404 np = netdev_priv(dev);
406 np->chip_id = chip_idx;
407 np->drv_flags = pci_id_tbl[chip_idx].drv_flags;
408 spin_lock_init(&np->lock);
409 np->mii_if.dev = dev;
410 np->mii_if.mdio_read = mdio_read;
411 np->mii_if.mdio_write = mdio_write;
412 np->base_addr = ioaddr;
414 pci_set_drvdata(pdev, dev);
417 option = dev->mem_start;
419 /* The lower four bits are the media type. */
422 np->mii_if.full_duplex = 1;
424 printk(KERN_INFO "%s: ignoring user supplied media type %d",
425 dev->name, option & 15);
427 if (find_cnt < MAX_UNITS && full_duplex[find_cnt] > 0)
428 np->mii_if.full_duplex = 1;
430 if (np->mii_if.full_duplex)
431 np->mii_if.force_media = 1;
433 /* The chip-specific entries in the device structure. */
434 dev->netdev_ops = &netdev_ops;
435 dev->ethtool_ops = &netdev_ethtool_ops;
436 dev->watchdog_timeo = TX_TIMEOUT;
438 i = register_netdev(dev);
440 goto err_out_cleardev;
442 printk(KERN_INFO "%s: %s at %p, %pM, IRQ %d.\n",
443 dev->name, pci_id_tbl[chip_idx].name, ioaddr,
446 if (np->drv_flags & CanHaveMII) {
447 int phy, phy_idx = 0;
448 for (phy = 1; phy < 32 && phy_idx < MII_CNT; phy++) {
449 int mii_status = mdio_read(dev, phy, MII_BMSR);
450 if (mii_status != 0xffff && mii_status != 0x0000) {
451 np->phys[phy_idx++] = phy;
452 np->mii_if.advertising = mdio_read(dev, phy, MII_ADVERTISE);
453 np->mii = (mdio_read(dev, phy, MII_PHYSID1) << 16)+
454 mdio_read(dev, phy, MII_PHYSID2);
455 printk(KERN_INFO "%s: MII PHY %8.8xh found at address %d, status "
456 "0x%4.4x advertising %4.4x.\n",
457 dev->name, np->mii, phy, mii_status, np->mii_if.advertising);
460 np->mii_cnt = phy_idx;
461 np->mii_if.phy_id = np->phys[0];
463 printk(KERN_WARNING "%s: MII PHY not found -- this device may "
464 "not operate correctly.\n", dev->name);
472 pci_set_drvdata(pdev, NULL);
473 pci_iounmap(pdev, ioaddr);
475 pci_release_regions(pdev);
482 /* Read the EEPROM and MII Management Data I/O (MDIO) interfaces. These are
483 often serial bit streams generated by the host processor.
484 The example below is for the common 93c46 EEPROM, 64 16 bit words. */
486 /* Delay between EEPROM clock transitions.
487 No extra delay is needed with 33Mhz PCI, but future 66Mhz access may need
488 a delay. Note that pre-2.0.34 kernels had a cache-alignment bug that
489 made udelay() unreliable.
490 The old method of using an ISA access as a delay, __SLOW_DOWN_IO__, is
493 #define eeprom_delay(ee_addr) ioread32(ee_addr)
495 enum EEPROM_Ctrl_Bits {
496 EE_ShiftClk=0x02, EE_Write0=0x801, EE_Write1=0x805,
497 EE_ChipSelect=0x801, EE_DataIn=0x08,
500 /* The EEPROM commands include the alway-set leading bit. */
502 EE_WriteCmd=(5 << 6), EE_ReadCmd=(6 << 6), EE_EraseCmd=(7 << 6),
505 static int eeprom_read(void __iomem *addr, int location)
509 void __iomem *ee_addr = addr + EECtrl;
510 int read_cmd = location | EE_ReadCmd;
511 iowrite32(EE_ChipSelect, ee_addr);
513 /* Shift the read command bits out. */
514 for (i = 10; i >= 0; i--) {
515 short dataval = (read_cmd & (1 << i)) ? EE_Write1 : EE_Write0;
516 iowrite32(dataval, ee_addr);
517 eeprom_delay(ee_addr);
518 iowrite32(dataval | EE_ShiftClk, ee_addr);
519 eeprom_delay(ee_addr);
521 iowrite32(EE_ChipSelect, ee_addr);
522 eeprom_delay(ee_addr);
524 for (i = 16; i > 0; i--) {
525 iowrite32(EE_ChipSelect | EE_ShiftClk, ee_addr);
526 eeprom_delay(ee_addr);
527 retval = (retval << 1) | ((ioread32(ee_addr) & EE_DataIn) ? 1 : 0);
528 iowrite32(EE_ChipSelect, ee_addr);
529 eeprom_delay(ee_addr);
532 /* Terminate the EEPROM access. */
533 iowrite32(0, ee_addr);
537 /* MII transceiver control section.
538 Read and write the MII registers using software-generated serial
539 MDIO protocol. See the MII specifications or DP83840A data sheet
542 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
543 met by back-to-back 33Mhz PCI cycles. */
544 #define mdio_delay(mdio_addr) ioread32(mdio_addr)
546 /* Set iff a MII transceiver on any interface requires mdio preamble.
547 This only set with older transceivers, so the extra
548 code size of a per-interface flag is not worthwhile. */
549 static char mii_preamble_required = 1;
551 #define MDIO_WRITE0 (MDIO_EnbOutput)
552 #define MDIO_WRITE1 (MDIO_DataOut | MDIO_EnbOutput)
554 /* Generate the preamble required for initial synchronization and
555 a few older transceivers. */
556 static void mdio_sync(void __iomem *mdio_addr)
560 /* Establish sync by sending at least 32 logic ones. */
561 while (--bits >= 0) {
562 iowrite32(MDIO_WRITE1, mdio_addr);
563 mdio_delay(mdio_addr);
564 iowrite32(MDIO_WRITE1 | MDIO_ShiftClk, mdio_addr);
565 mdio_delay(mdio_addr);
569 static int mdio_read(struct net_device *dev, int phy_id, int location)
571 struct netdev_private *np = netdev_priv(dev);
572 void __iomem *mdio_addr = np->base_addr + MIICtrl;
573 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
576 if (mii_preamble_required)
577 mdio_sync(mdio_addr);
579 /* Shift the read command bits out. */
580 for (i = 15; i >= 0; i--) {
581 int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
583 iowrite32(dataval, mdio_addr);
584 mdio_delay(mdio_addr);
585 iowrite32(dataval | MDIO_ShiftClk, mdio_addr);
586 mdio_delay(mdio_addr);
588 /* Read the two transition, 16 data, and wire-idle bits. */
589 for (i = 20; i > 0; i--) {
590 iowrite32(MDIO_EnbIn, mdio_addr);
591 mdio_delay(mdio_addr);
592 retval = (retval << 1) | ((ioread32(mdio_addr) & MDIO_DataIn) ? 1 : 0);
593 iowrite32(MDIO_EnbIn | MDIO_ShiftClk, mdio_addr);
594 mdio_delay(mdio_addr);
596 return (retval>>1) & 0xffff;
599 static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
601 struct netdev_private *np = netdev_priv(dev);
602 void __iomem *mdio_addr = np->base_addr + MIICtrl;
603 int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location<<18) | value;
606 if (location == 4 && phy_id == np->phys[0])
607 np->mii_if.advertising = value;
609 if (mii_preamble_required)
610 mdio_sync(mdio_addr);
612 /* Shift the command bits out. */
613 for (i = 31; i >= 0; i--) {
614 int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
616 iowrite32(dataval, mdio_addr);
617 mdio_delay(mdio_addr);
618 iowrite32(dataval | MDIO_ShiftClk, mdio_addr);
619 mdio_delay(mdio_addr);
621 /* Clear out extra bits. */
622 for (i = 2; i > 0; i--) {
623 iowrite32(MDIO_EnbIn, mdio_addr);
624 mdio_delay(mdio_addr);
625 iowrite32(MDIO_EnbIn | MDIO_ShiftClk, mdio_addr);
626 mdio_delay(mdio_addr);
632 static int netdev_open(struct net_device *dev)
634 struct netdev_private *np = netdev_priv(dev);
635 void __iomem *ioaddr = np->base_addr;
638 iowrite32(0x00000001, ioaddr + PCIBusCfg); /* Reset */
640 netif_device_detach(dev);
641 i = request_irq(dev->irq, &intr_handler, IRQF_SHARED, dev->name, dev);
646 printk(KERN_DEBUG "%s: w89c840_open() irq %d.\n",
647 dev->name, dev->irq);
649 if((i=alloc_ringdesc(dev)))
652 spin_lock_irq(&np->lock);
653 netif_device_attach(dev);
655 spin_unlock_irq(&np->lock);
657 netif_start_queue(dev);
659 printk(KERN_DEBUG "%s: Done netdev_open().\n", dev->name);
661 /* Set the timer to check for link beat. */
662 init_timer(&np->timer);
663 np->timer.expires = jiffies + 1*HZ;
664 np->timer.data = (unsigned long)dev;
665 np->timer.function = &netdev_timer; /* timer handler */
666 add_timer(&np->timer);
669 netif_device_attach(dev);
673 #define MII_DAVICOM_DM9101 0x0181b800
675 static int update_link(struct net_device *dev)
677 struct netdev_private *np = netdev_priv(dev);
678 int duplex, fasteth, result, mii_reg;
681 mii_reg = mdio_read(dev, np->phys[0], MII_BMSR);
683 if (mii_reg == 0xffff)
685 /* reread: the link status bit is sticky */
686 mii_reg = mdio_read(dev, np->phys[0], MII_BMSR);
687 if (!(mii_reg & 0x4)) {
688 if (netif_carrier_ok(dev)) {
690 printk(KERN_INFO "%s: MII #%d reports no link. Disabling watchdog.\n",
691 dev->name, np->phys[0]);
692 netif_carrier_off(dev);
696 if (!netif_carrier_ok(dev)) {
698 printk(KERN_INFO "%s: MII #%d link is back. Enabling watchdog.\n",
699 dev->name, np->phys[0]);
700 netif_carrier_on(dev);
703 if ((np->mii & ~0xf) == MII_DAVICOM_DM9101) {
704 /* If the link partner doesn't support autonegotiation
705 * the MII detects it's abilities with the "parallel detection".
706 * Some MIIs update the LPA register to the result of the parallel
707 * detection, some don't.
708 * The Davicom PHY [at least 0181b800] doesn't.
709 * Instead bit 9 and 13 of the BMCR are updated to the result
710 * of the negotiation..
712 mii_reg = mdio_read(dev, np->phys[0], MII_BMCR);
713 duplex = mii_reg & BMCR_FULLDPLX;
714 fasteth = mii_reg & BMCR_SPEED100;
717 mii_reg = mdio_read(dev, np->phys[0], MII_LPA);
718 negotiated = mii_reg & np->mii_if.advertising;
720 duplex = (negotiated & LPA_100FULL) || ((negotiated & 0x02C0) == LPA_10FULL);
721 fasteth = negotiated & 0x380;
723 duplex |= np->mii_if.force_media;
724 /* remove fastether and fullduplex */
725 result = np->csr6 & ~0x20000200;
729 result |= 0x20000000;
730 if (result != np->csr6 && debug)
731 printk(KERN_INFO "%s: Setting %dMBit-%s-duplex based on MII#%d\n",
732 dev->name, fasteth ? 100 : 10,
733 duplex ? "full" : "half", np->phys[0]);
737 #define RXTX_TIMEOUT 2000
738 static inline void update_csr6(struct net_device *dev, int new)
740 struct netdev_private *np = netdev_priv(dev);
741 void __iomem *ioaddr = np->base_addr;
742 int limit = RXTX_TIMEOUT;
744 if (!netif_device_present(dev))
748 /* stop both Tx and Rx processes */
749 iowrite32(np->csr6 & ~0x2002, ioaddr + NetworkConfig);
750 /* wait until they have really stopped */
752 int csr5 = ioread32(ioaddr + IntrStatus);
755 t = (csr5 >> 17) & 0x07;
758 t = (csr5 >> 20) & 0x07;
765 printk(KERN_INFO "%s: couldn't stop rxtx, IntrStatus %xh.\n",
772 /* and restart them with the new configuration */
773 iowrite32(np->csr6, ioaddr + NetworkConfig);
775 np->mii_if.full_duplex = 1;
778 static void netdev_timer(unsigned long data)
780 struct net_device *dev = (struct net_device *)data;
781 struct netdev_private *np = netdev_priv(dev);
782 void __iomem *ioaddr = np->base_addr;
785 printk(KERN_DEBUG "%s: Media selection timer tick, status %8.8x "
787 dev->name, ioread32(ioaddr + IntrStatus),
788 ioread32(ioaddr + NetworkConfig));
789 spin_lock_irq(&np->lock);
790 update_csr6(dev, update_link(dev));
791 spin_unlock_irq(&np->lock);
792 np->timer.expires = jiffies + 10*HZ;
793 add_timer(&np->timer);
796 static void init_rxtx_rings(struct net_device *dev)
798 struct netdev_private *np = netdev_priv(dev);
801 np->rx_head_desc = &np->rx_ring[0];
802 np->tx_ring = (struct w840_tx_desc*)&np->rx_ring[RX_RING_SIZE];
804 /* Initial all Rx descriptors. */
805 for (i = 0; i < RX_RING_SIZE; i++) {
806 np->rx_ring[i].length = np->rx_buf_sz;
807 np->rx_ring[i].status = 0;
808 np->rx_skbuff[i] = NULL;
810 /* Mark the last entry as wrapping the ring. */
811 np->rx_ring[i-1].length |= DescEndRing;
813 /* Fill in the Rx buffers. Handle allocation failure gracefully. */
814 for (i = 0; i < RX_RING_SIZE; i++) {
815 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz);
816 np->rx_skbuff[i] = skb;
819 np->rx_addr[i] = pci_map_single(np->pci_dev,skb->data,
820 np->rx_buf_sz,PCI_DMA_FROMDEVICE);
822 np->rx_ring[i].buffer1 = np->rx_addr[i];
823 np->rx_ring[i].status = DescOwned;
827 np->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
829 /* Initialize the Tx descriptors */
830 for (i = 0; i < TX_RING_SIZE; i++) {
831 np->tx_skbuff[i] = NULL;
832 np->tx_ring[i].status = 0;
835 np->tx_q_bytes = np->dirty_tx = np->cur_tx = 0;
837 iowrite32(np->ring_dma_addr, np->base_addr + RxRingPtr);
838 iowrite32(np->ring_dma_addr+sizeof(struct w840_rx_desc)*RX_RING_SIZE,
839 np->base_addr + TxRingPtr);
843 static void free_rxtx_rings(struct netdev_private* np)
846 /* Free all the skbuffs in the Rx queue. */
847 for (i = 0; i < RX_RING_SIZE; i++) {
848 np->rx_ring[i].status = 0;
849 if (np->rx_skbuff[i]) {
850 pci_unmap_single(np->pci_dev,
852 np->rx_skbuff[i]->len,
854 dev_kfree_skb(np->rx_skbuff[i]);
856 np->rx_skbuff[i] = NULL;
858 for (i = 0; i < TX_RING_SIZE; i++) {
859 if (np->tx_skbuff[i]) {
860 pci_unmap_single(np->pci_dev,
862 np->tx_skbuff[i]->len,
864 dev_kfree_skb(np->tx_skbuff[i]);
866 np->tx_skbuff[i] = NULL;
870 static void init_registers(struct net_device *dev)
872 struct netdev_private *np = netdev_priv(dev);
873 void __iomem *ioaddr = np->base_addr;
876 for (i = 0; i < 6; i++)
877 iowrite8(dev->dev_addr[i], ioaddr + StationAddr + i);
879 /* Initialize other registers. */
881 i = (1<<20); /* Big-endian descriptors */
885 i |= (0x04<<2); /* skip length 4 u32 */
886 i |= 0x02; /* give Rx priority */
888 /* Configure the PCI bus bursts and FIFO thresholds.
889 486: Set 8 longword cache alignment, 8 longword burst.
890 586: Set 16 longword cache alignment, no burst limit.
891 Cache alignment bits 15:14 Burst length 13:8
892 0000 <not allowed> 0000 align to cache 0800 8 longwords
893 4000 8 longwords 0100 1 longword 1000 16 longwords
894 8000 16 longwords 0200 2 longwords 2000 32 longwords
895 C000 32 longwords 0400 4 longwords */
897 #if defined (__i386__) && !defined(MODULE)
898 /* When not a module we can work around broken '486 PCI boards. */
899 if (boot_cpu_data.x86 <= 4) {
901 printk(KERN_INFO "%s: This is a 386/486 PCI system, setting cache "
902 "alignment to 8 longwords.\n", dev->name);
906 #elif defined(__powerpc__) || defined(__i386__) || defined(__alpha__) || defined(__ia64__) || defined(__x86_64__)
908 #elif defined(CONFIG_SPARC) || defined (CONFIG_PARISC)
911 #warning Processor architecture undefined
914 iowrite32(i, ioaddr + PCIBusCfg);
917 /* 128 byte Tx threshold;
918 Transmit on; Receive on; */
919 update_csr6(dev, 0x00022002 | update_link(dev) | __set_rx_mode(dev));
921 /* Clear and Enable interrupts by setting the interrupt mask. */
922 iowrite32(0x1A0F5, ioaddr + IntrStatus);
923 iowrite32(0x1A0F5, ioaddr + IntrEnable);
925 iowrite32(0, ioaddr + RxStartDemand);
928 static void tx_timeout(struct net_device *dev)
930 struct netdev_private *np = netdev_priv(dev);
931 void __iomem *ioaddr = np->base_addr;
933 printk(KERN_WARNING "%s: Transmit timed out, status %8.8x,"
934 " resetting...\n", dev->name, ioread32(ioaddr + IntrStatus));
938 printk(KERN_DEBUG " Rx ring %p: ", np->rx_ring);
939 for (i = 0; i < RX_RING_SIZE; i++)
940 printk(" %8.8x", (unsigned int)np->rx_ring[i].status);
941 printk("\n"KERN_DEBUG" Tx ring %p: ", np->tx_ring);
942 for (i = 0; i < TX_RING_SIZE; i++)
943 printk(" %8.8x", np->tx_ring[i].status);
946 printk(KERN_DEBUG "Tx cur %d Tx dirty %d Tx Full %d, q bytes %d.\n",
947 np->cur_tx, np->dirty_tx, np->tx_full, np->tx_q_bytes);
948 printk(KERN_DEBUG "Tx Descriptor addr %xh.\n",ioread32(ioaddr+0x4C));
950 disable_irq(dev->irq);
951 spin_lock_irq(&np->lock);
953 * Under high load dirty_tx and the internal tx descriptor pointer
954 * come out of sync, thus perform a software reset and reinitialize
958 iowrite32(1, np->base_addr+PCIBusCfg);
962 init_rxtx_rings(dev);
964 spin_unlock_irq(&np->lock);
965 enable_irq(dev->irq);
967 netif_wake_queue(dev);
968 dev->trans_start = jiffies;
969 np->stats.tx_errors++;
973 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
974 static int alloc_ringdesc(struct net_device *dev)
976 struct netdev_private *np = netdev_priv(dev);
978 np->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
980 np->rx_ring = pci_alloc_consistent(np->pci_dev,
981 sizeof(struct w840_rx_desc)*RX_RING_SIZE +
982 sizeof(struct w840_tx_desc)*TX_RING_SIZE,
986 init_rxtx_rings(dev);
990 static void free_ringdesc(struct netdev_private *np)
992 pci_free_consistent(np->pci_dev,
993 sizeof(struct w840_rx_desc)*RX_RING_SIZE +
994 sizeof(struct w840_tx_desc)*TX_RING_SIZE,
995 np->rx_ring, np->ring_dma_addr);
999 static int start_tx(struct sk_buff *skb, struct net_device *dev)
1001 struct netdev_private *np = netdev_priv(dev);
1004 /* Caution: the write order is important here, set the field
1005 with the "ownership" bits last. */
1007 /* Calculate the next Tx descriptor entry. */
1008 entry = np->cur_tx % TX_RING_SIZE;
1010 np->tx_addr[entry] = pci_map_single(np->pci_dev,
1011 skb->data,skb->len, PCI_DMA_TODEVICE);
1012 np->tx_skbuff[entry] = skb;
1014 np->tx_ring[entry].buffer1 = np->tx_addr[entry];
1015 if (skb->len < TX_BUFLIMIT) {
1016 np->tx_ring[entry].length = DescWholePkt | skb->len;
1018 int len = skb->len - TX_BUFLIMIT;
1020 np->tx_ring[entry].buffer2 = np->tx_addr[entry]+TX_BUFLIMIT;
1021 np->tx_ring[entry].length = DescWholePkt | (len << 11) | TX_BUFLIMIT;
1023 if(entry == TX_RING_SIZE-1)
1024 np->tx_ring[entry].length |= DescEndRing;
1026 /* Now acquire the irq spinlock.
1027 * The difficult race is the ordering between
1028 * increasing np->cur_tx and setting DescOwned:
1029 * - if np->cur_tx is increased first the interrupt
1030 * handler could consider the packet as transmitted
1031 * since DescOwned is cleared.
1032 * - If DescOwned is set first the NIC could report the
1033 * packet as sent, but the interrupt handler would ignore it
1034 * since the np->cur_tx was not yet increased.
1036 spin_lock_irq(&np->lock);
1039 wmb(); /* flush length, buffer1, buffer2 */
1040 np->tx_ring[entry].status = DescOwned;
1041 wmb(); /* flush status and kick the hardware */
1042 iowrite32(0, np->base_addr + TxStartDemand);
1043 np->tx_q_bytes += skb->len;
1044 /* Work around horrible bug in the chip by marking the queue as full
1045 when we do not have FIFO room for a maximum sized packet. */
1046 if (np->cur_tx - np->dirty_tx > TX_QUEUE_LEN ||
1047 ((np->drv_flags & HasBrokenTx) && np->tx_q_bytes > TX_BUG_FIFO_LIMIT)) {
1048 netif_stop_queue(dev);
1052 spin_unlock_irq(&np->lock);
1054 dev->trans_start = jiffies;
1057 printk(KERN_DEBUG "%s: Transmit frame #%d queued in slot %d.\n",
1058 dev->name, np->cur_tx, entry);
1063 static void netdev_tx_done(struct net_device *dev)
1065 struct netdev_private *np = netdev_priv(dev);
1066 for (; np->cur_tx - np->dirty_tx > 0; np->dirty_tx++) {
1067 int entry = np->dirty_tx % TX_RING_SIZE;
1068 int tx_status = np->tx_ring[entry].status;
1072 if (tx_status & 0x8000) { /* There was an error, log it. */
1073 #ifndef final_version
1075 printk(KERN_DEBUG "%s: Transmit error, Tx status %8.8x.\n",
1076 dev->name, tx_status);
1078 np->stats.tx_errors++;
1079 if (tx_status & 0x0104) np->stats.tx_aborted_errors++;
1080 if (tx_status & 0x0C80) np->stats.tx_carrier_errors++;
1081 if (tx_status & 0x0200) np->stats.tx_window_errors++;
1082 if (tx_status & 0x0002) np->stats.tx_fifo_errors++;
1083 if ((tx_status & 0x0080) && np->mii_if.full_duplex == 0)
1084 np->stats.tx_heartbeat_errors++;
1086 #ifndef final_version
1088 printk(KERN_DEBUG "%s: Transmit slot %d ok, Tx status %8.8x.\n",
1089 dev->name, entry, tx_status);
1091 np->stats.tx_bytes += np->tx_skbuff[entry]->len;
1092 np->stats.collisions += (tx_status >> 3) & 15;
1093 np->stats.tx_packets++;
1095 /* Free the original skb. */
1096 pci_unmap_single(np->pci_dev,np->tx_addr[entry],
1097 np->tx_skbuff[entry]->len,
1099 np->tx_q_bytes -= np->tx_skbuff[entry]->len;
1100 dev_kfree_skb_irq(np->tx_skbuff[entry]);
1101 np->tx_skbuff[entry] = NULL;
1104 np->cur_tx - np->dirty_tx < TX_QUEUE_LEN_RESTART &&
1105 np->tx_q_bytes < TX_BUG_FIFO_LIMIT) {
1106 /* The ring is no longer full, clear tbusy. */
1109 netif_wake_queue(dev);
1113 /* The interrupt handler does all of the Rx thread work and cleans up
1114 after the Tx thread. */
1115 static irqreturn_t intr_handler(int irq, void *dev_instance)
1117 struct net_device *dev = (struct net_device *)dev_instance;
1118 struct netdev_private *np = netdev_priv(dev);
1119 void __iomem *ioaddr = np->base_addr;
1120 int work_limit = max_interrupt_work;
1123 if (!netif_device_present(dev))
1126 u32 intr_status = ioread32(ioaddr + IntrStatus);
1128 /* Acknowledge all of the current interrupt sources ASAP. */
1129 iowrite32(intr_status & 0x001ffff, ioaddr + IntrStatus);
1132 printk(KERN_DEBUG "%s: Interrupt, status %4.4x.\n",
1133 dev->name, intr_status);
1135 if ((intr_status & (NormalIntr|AbnormalIntr)) == 0)
1140 if (intr_status & (RxIntr | RxNoBuf))
1142 if (intr_status & RxNoBuf)
1143 iowrite32(0, ioaddr + RxStartDemand);
1145 if (intr_status & (TxNoBuf | TxIntr) &&
1146 np->cur_tx != np->dirty_tx) {
1147 spin_lock(&np->lock);
1148 netdev_tx_done(dev);
1149 spin_unlock(&np->lock);
1152 /* Abnormal error summary/uncommon events handlers. */
1153 if (intr_status & (AbnormalIntr | TxFIFOUnderflow | SystemError |
1155 netdev_error(dev, intr_status);
1157 if (--work_limit < 0) {
1158 printk(KERN_WARNING "%s: Too much work at interrupt, "
1159 "status=0x%4.4x.\n", dev->name, intr_status);
1160 /* Set the timer to re-enable the other interrupts after
1162 spin_lock(&np->lock);
1163 if (netif_device_present(dev)) {
1164 iowrite32(AbnormalIntr | TimerInt, ioaddr + IntrEnable);
1165 iowrite32(10, ioaddr + GPTimer);
1167 spin_unlock(&np->lock);
1173 printk(KERN_DEBUG "%s: exiting interrupt, status=%#4.4x.\n",
1174 dev->name, ioread32(ioaddr + IntrStatus));
1175 return IRQ_RETVAL(handled);
1178 /* This routine is logically part of the interrupt handler, but separated
1179 for clarity and better register allocation. */
1180 static int netdev_rx(struct net_device *dev)
1182 struct netdev_private *np = netdev_priv(dev);
1183 int entry = np->cur_rx % RX_RING_SIZE;
1184 int work_limit = np->dirty_rx + RX_RING_SIZE - np->cur_rx;
1187 printk(KERN_DEBUG " In netdev_rx(), entry %d status %4.4x.\n",
1188 entry, np->rx_ring[entry].status);
1191 /* If EOP is set on the next entry, it's a new packet. Send it up. */
1192 while (--work_limit >= 0) {
1193 struct w840_rx_desc *desc = np->rx_head_desc;
1194 s32 status = desc->status;
1197 printk(KERN_DEBUG " netdev_rx() status was %8.8x.\n",
1201 if ((status & 0x38008300) != 0x0300) {
1202 if ((status & 0x38000300) != 0x0300) {
1203 /* Ingore earlier buffers. */
1204 if ((status & 0xffff) != 0x7fff) {
1205 printk(KERN_WARNING "%s: Oversized Ethernet frame spanned "
1206 "multiple buffers, entry %#x status %4.4x!\n",
1207 dev->name, np->cur_rx, status);
1208 np->stats.rx_length_errors++;
1210 } else if (status & 0x8000) {
1211 /* There was a fatal error. */
1213 printk(KERN_DEBUG "%s: Receive error, Rx status %8.8x.\n",
1215 np->stats.rx_errors++; /* end of a packet.*/
1216 if (status & 0x0890) np->stats.rx_length_errors++;
1217 if (status & 0x004C) np->stats.rx_frame_errors++;
1218 if (status & 0x0002) np->stats.rx_crc_errors++;
1221 struct sk_buff *skb;
1222 /* Omit the four octet CRC from the length. */
1223 int pkt_len = ((status >> 16) & 0x7ff) - 4;
1225 #ifndef final_version
1227 printk(KERN_DEBUG " netdev_rx() normal Rx pkt length %d"
1228 " status %x.\n", pkt_len, status);
1230 /* Check if the packet is long enough to accept without copying
1231 to a minimally-sized skbuff. */
1232 if (pkt_len < rx_copybreak
1233 && (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1234 skb_reserve(skb, 2); /* 16 byte align the IP header */
1235 pci_dma_sync_single_for_cpu(np->pci_dev,np->rx_addr[entry],
1236 np->rx_skbuff[entry]->len,
1237 PCI_DMA_FROMDEVICE);
1238 skb_copy_to_linear_data(skb, np->rx_skbuff[entry]->data, pkt_len);
1239 skb_put(skb, pkt_len);
1240 pci_dma_sync_single_for_device(np->pci_dev,np->rx_addr[entry],
1241 np->rx_skbuff[entry]->len,
1242 PCI_DMA_FROMDEVICE);
1244 pci_unmap_single(np->pci_dev,np->rx_addr[entry],
1245 np->rx_skbuff[entry]->len,
1246 PCI_DMA_FROMDEVICE);
1247 skb_put(skb = np->rx_skbuff[entry], pkt_len);
1248 np->rx_skbuff[entry] = NULL;
1250 #ifndef final_version /* Remove after testing. */
1251 /* You will want this info for the initial debug. */
1253 printk(KERN_DEBUG " Rx data %pM %pM"
1254 " %2.2x%2.2x %d.%d.%d.%d.\n",
1255 &skb->data[0], &skb->data[6],
1256 skb->data[12], skb->data[13],
1257 skb->data[14], skb->data[15], skb->data[16], skb->data[17]);
1259 skb->protocol = eth_type_trans(skb, dev);
1261 np->stats.rx_packets++;
1262 np->stats.rx_bytes += pkt_len;
1264 entry = (++np->cur_rx) % RX_RING_SIZE;
1265 np->rx_head_desc = &np->rx_ring[entry];
1268 /* Refill the Rx ring buffers. */
1269 for (; np->cur_rx - np->dirty_rx > 0; np->dirty_rx++) {
1270 struct sk_buff *skb;
1271 entry = np->dirty_rx % RX_RING_SIZE;
1272 if (np->rx_skbuff[entry] == NULL) {
1273 skb = dev_alloc_skb(np->rx_buf_sz);
1274 np->rx_skbuff[entry] = skb;
1276 break; /* Better luck next round. */
1277 np->rx_addr[entry] = pci_map_single(np->pci_dev,
1279 np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1280 np->rx_ring[entry].buffer1 = np->rx_addr[entry];
1283 np->rx_ring[entry].status = DescOwned;
1289 static void netdev_error(struct net_device *dev, int intr_status)
1291 struct netdev_private *np = netdev_priv(dev);
1292 void __iomem *ioaddr = np->base_addr;
1295 printk(KERN_DEBUG "%s: Abnormal event, %8.8x.\n",
1296 dev->name, intr_status);
1297 if (intr_status == 0xffffffff)
1299 spin_lock(&np->lock);
1300 if (intr_status & TxFIFOUnderflow) {
1302 /* Bump up the Tx threshold */
1304 /* This causes lots of dropped packets,
1305 * and under high load even tx_timeouts
1307 new = np->csr6 + 0x4000;
1309 new = (np->csr6 >> 14)&0x7f;
1313 new = 127; /* load full packet before starting */
1314 new = (np->csr6 & ~(0x7F << 14)) | (new<<14);
1316 printk(KERN_DEBUG "%s: Tx underflow, new csr6 %8.8x.\n",
1318 update_csr6(dev, new);
1320 if (intr_status & RxDied) { /* Missed a Rx frame. */
1321 np->stats.rx_errors++;
1323 if (intr_status & TimerInt) {
1324 /* Re-enable other interrupts. */
1325 if (netif_device_present(dev))
1326 iowrite32(0x1A0F5, ioaddr + IntrEnable);
1328 np->stats.rx_missed_errors += ioread32(ioaddr + RxMissed) & 0xffff;
1329 iowrite32(0, ioaddr + RxStartDemand);
1330 spin_unlock(&np->lock);
1333 static struct net_device_stats *get_stats(struct net_device *dev)
1335 struct netdev_private *np = netdev_priv(dev);
1336 void __iomem *ioaddr = np->base_addr;
1338 /* The chip only need report frame silently dropped. */
1339 spin_lock_irq(&np->lock);
1340 if (netif_running(dev) && netif_device_present(dev))
1341 np->stats.rx_missed_errors += ioread32(ioaddr + RxMissed) & 0xffff;
1342 spin_unlock_irq(&np->lock);
1348 static u32 __set_rx_mode(struct net_device *dev)
1350 struct netdev_private *np = netdev_priv(dev);
1351 void __iomem *ioaddr = np->base_addr;
1352 u32 mc_filter[2]; /* Multicast hash filter */
1355 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1356 memset(mc_filter, 0xff, sizeof(mc_filter));
1357 rx_mode = RxAcceptBroadcast | AcceptMulticast | RxAcceptAllPhys
1359 } else if ((dev->mc_count > multicast_filter_limit)
1360 || (dev->flags & IFF_ALLMULTI)) {
1361 /* Too many to match, or accept all multicasts. */
1362 memset(mc_filter, 0xff, sizeof(mc_filter));
1363 rx_mode = RxAcceptBroadcast | AcceptMulticast | AcceptMyPhys;
1365 struct dev_mc_list *mclist;
1367 memset(mc_filter, 0, sizeof(mc_filter));
1368 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1369 i++, mclist = mclist->next) {
1370 int filterbit = (ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26) ^ 0x3F;
1372 mc_filter[filterbit >> 5] |= 1 << (filterbit & 31);
1374 rx_mode = RxAcceptBroadcast | AcceptMulticast | AcceptMyPhys;
1376 iowrite32(mc_filter[0], ioaddr + MulticastFilter0);
1377 iowrite32(mc_filter[1], ioaddr + MulticastFilter1);
1381 static void set_rx_mode(struct net_device *dev)
1383 struct netdev_private *np = netdev_priv(dev);
1384 u32 rx_mode = __set_rx_mode(dev);
1385 spin_lock_irq(&np->lock);
1386 update_csr6(dev, (np->csr6 & ~0x00F8) | rx_mode);
1387 spin_unlock_irq(&np->lock);
1390 static void netdev_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1392 struct netdev_private *np = netdev_priv(dev);
1394 strcpy (info->driver, DRV_NAME);
1395 strcpy (info->version, DRV_VERSION);
1396 strcpy (info->bus_info, pci_name(np->pci_dev));
1399 static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1401 struct netdev_private *np = netdev_priv(dev);
1404 spin_lock_irq(&np->lock);
1405 rc = mii_ethtool_gset(&np->mii_if, cmd);
1406 spin_unlock_irq(&np->lock);
1411 static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1413 struct netdev_private *np = netdev_priv(dev);
1416 spin_lock_irq(&np->lock);
1417 rc = mii_ethtool_sset(&np->mii_if, cmd);
1418 spin_unlock_irq(&np->lock);
1423 static int netdev_nway_reset(struct net_device *dev)
1425 struct netdev_private *np = netdev_priv(dev);
1426 return mii_nway_restart(&np->mii_if);
1429 static u32 netdev_get_link(struct net_device *dev)
1431 struct netdev_private *np = netdev_priv(dev);
1432 return mii_link_ok(&np->mii_if);
1435 static u32 netdev_get_msglevel(struct net_device *dev)
1440 static void netdev_set_msglevel(struct net_device *dev, u32 value)
1445 static const struct ethtool_ops netdev_ethtool_ops = {
1446 .get_drvinfo = netdev_get_drvinfo,
1447 .get_settings = netdev_get_settings,
1448 .set_settings = netdev_set_settings,
1449 .nway_reset = netdev_nway_reset,
1450 .get_link = netdev_get_link,
1451 .get_msglevel = netdev_get_msglevel,
1452 .set_msglevel = netdev_set_msglevel,
1455 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1457 struct mii_ioctl_data *data = if_mii(rq);
1458 struct netdev_private *np = netdev_priv(dev);
1461 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
1462 data->phy_id = ((struct netdev_private *)netdev_priv(dev))->phys[0] & 0x1f;
1465 case SIOCGMIIREG: /* Read MII PHY register. */
1466 spin_lock_irq(&np->lock);
1467 data->val_out = mdio_read(dev, data->phy_id & 0x1f, data->reg_num & 0x1f);
1468 spin_unlock_irq(&np->lock);
1471 case SIOCSMIIREG: /* Write MII PHY register. */
1472 if (!capable(CAP_NET_ADMIN))
1474 spin_lock_irq(&np->lock);
1475 mdio_write(dev, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
1476 spin_unlock_irq(&np->lock);
1483 static int netdev_close(struct net_device *dev)
1485 struct netdev_private *np = netdev_priv(dev);
1486 void __iomem *ioaddr = np->base_addr;
1488 netif_stop_queue(dev);
1491 printk(KERN_DEBUG "%s: Shutting down ethercard, status was %8.8x "
1492 "Config %8.8x.\n", dev->name, ioread32(ioaddr + IntrStatus),
1493 ioread32(ioaddr + NetworkConfig));
1494 printk(KERN_DEBUG "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n",
1495 dev->name, np->cur_tx, np->dirty_tx, np->cur_rx, np->dirty_rx);
1498 /* Stop the chip's Tx and Rx processes. */
1499 spin_lock_irq(&np->lock);
1500 netif_device_detach(dev);
1501 update_csr6(dev, 0);
1502 iowrite32(0x0000, ioaddr + IntrEnable);
1503 spin_unlock_irq(&np->lock);
1505 free_irq(dev->irq, dev);
1507 netif_device_attach(dev);
1509 if (ioread32(ioaddr + NetworkConfig) != 0xffffffff)
1510 np->stats.rx_missed_errors += ioread32(ioaddr + RxMissed) & 0xffff;
1516 printk(KERN_DEBUG" Tx ring at %8.8x:\n",
1518 for (i = 0; i < TX_RING_SIZE; i++)
1519 printk(KERN_DEBUG " #%d desc. %4.4x %4.4x %8.8x.\n",
1520 i, np->tx_ring[i].length,
1521 np->tx_ring[i].status, np->tx_ring[i].buffer1);
1522 printk("\n"KERN_DEBUG " Rx ring %8.8x:\n",
1524 for (i = 0; i < RX_RING_SIZE; i++) {
1525 printk(KERN_DEBUG " #%d desc. %4.4x %4.4x %8.8x\n",
1526 i, np->rx_ring[i].length,
1527 np->rx_ring[i].status, np->rx_ring[i].buffer1);
1530 #endif /* __i386__ debugging only */
1532 del_timer_sync(&np->timer);
1534 free_rxtx_rings(np);
1540 static void __devexit w840_remove1 (struct pci_dev *pdev)
1542 struct net_device *dev = pci_get_drvdata(pdev);
1545 struct netdev_private *np = netdev_priv(dev);
1546 unregister_netdev(dev);
1547 pci_release_regions(pdev);
1548 pci_iounmap(pdev, np->base_addr);
1552 pci_set_drvdata(pdev, NULL);
1558 * suspend/resume synchronization:
1559 * - open, close, do_ioctl:
1560 * rtnl_lock, & netif_device_detach after the rtnl_unlock.
1562 * spin_lock_irq(np->lock), doesn't touch hw if not present
1564 * synchronize_irq + netif_tx_disable;
1566 * netif_device_detach + netif_tx_disable;
1567 * - set_multicast_list
1568 * netif_device_detach + netif_tx_disable;
1569 * - interrupt handler
1570 * doesn't touch hw if not present, synchronize_irq waits for
1571 * running instances of the interrupt handler.
1573 * Disabling hw requires clearing csr6 & IntrEnable.
1574 * update_csr6 & all function that write IntrEnable check netif_device_present
1575 * before settings any bits.
1577 * Detach must occur under spin_unlock_irq(), interrupts from a detached
1578 * device would cause an irq storm.
1580 static int w840_suspend (struct pci_dev *pdev, pm_message_t state)
1582 struct net_device *dev = pci_get_drvdata (pdev);
1583 struct netdev_private *np = netdev_priv(dev);
1584 void __iomem *ioaddr = np->base_addr;
1587 if (netif_running (dev)) {
1588 del_timer_sync(&np->timer);
1590 spin_lock_irq(&np->lock);
1591 netif_device_detach(dev);
1592 update_csr6(dev, 0);
1593 iowrite32(0, ioaddr + IntrEnable);
1594 spin_unlock_irq(&np->lock);
1596 synchronize_irq(dev->irq);
1597 netif_tx_disable(dev);
1599 np->stats.rx_missed_errors += ioread32(ioaddr + RxMissed) & 0xffff;
1601 /* no more hardware accesses behind this line. */
1604 if (ioread32(ioaddr + IntrEnable)) BUG();
1606 /* pci_power_off(pdev, -1); */
1608 free_rxtx_rings(np);
1610 netif_device_detach(dev);
1616 static int w840_resume (struct pci_dev *pdev)
1618 struct net_device *dev = pci_get_drvdata (pdev);
1619 struct netdev_private *np = netdev_priv(dev);
1623 if (netif_device_present(dev))
1624 goto out; /* device not suspended */
1625 if (netif_running(dev)) {
1626 if ((retval = pci_enable_device(pdev))) {
1628 "%s: pci_enable_device failed in resume\n",
1632 spin_lock_irq(&np->lock);
1633 iowrite32(1, np->base_addr+PCIBusCfg);
1634 ioread32(np->base_addr+PCIBusCfg);
1636 netif_device_attach(dev);
1637 init_rxtx_rings(dev);
1638 init_registers(dev);
1639 spin_unlock_irq(&np->lock);
1641 netif_wake_queue(dev);
1643 mod_timer(&np->timer, jiffies + 1*HZ);
1645 netif_device_attach(dev);
1653 static struct pci_driver w840_driver = {
1655 .id_table = w840_pci_tbl,
1656 .probe = w840_probe1,
1657 .remove = __devexit_p(w840_remove1),
1659 .suspend = w840_suspend,
1660 .resume = w840_resume,
1664 static int __init w840_init(void)
1667 return pci_register_driver(&w840_driver);
1670 static void __exit w840_exit(void)
1672 pci_unregister_driver(&w840_driver);
1675 module_init(w840_init);
1676 module_exit(w840_exit);