x86, apic: refactor ->phys_pkg_id()
[linux-2.6] / arch / x86 / kernel / cpu / intel.c
1 #include <linux/init.h>
2 #include <linux/kernel.h>
3
4 #include <linux/string.h>
5 #include <linux/bitops.h>
6 #include <linux/smp.h>
7 #include <linux/thread_info.h>
8 #include <linux/module.h>
9
10 #include <asm/processor.h>
11 #include <asm/pgtable.h>
12 #include <asm/msr.h>
13 #include <asm/uaccess.h>
14 #include <asm/ds.h>
15 #include <asm/bugs.h>
16
17 #ifdef CONFIG_X86_64
18 #include <asm/topology.h>
19 #include <asm/numa_64.h>
20 #endif
21
22 #include "cpu.h"
23
24 #ifdef CONFIG_X86_LOCAL_APIC
25 #include <asm/mpspec.h>
26 #include <asm/apic.h>
27 #include <mach_apic.h>
28 #endif
29
30 static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
31 {
32         /* Unmask CPUID levels if masked: */
33         if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
34                 u64 misc_enable;
35
36                 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
37
38                 if (misc_enable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID) {
39                         misc_enable &= ~MSR_IA32_MISC_ENABLE_LIMIT_CPUID;
40                         wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
41                         c->cpuid_level = cpuid_eax(0);
42                 }
43         }
44
45         if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
46                 (c->x86 == 0x6 && c->x86_model >= 0x0e))
47                 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
48
49 #ifdef CONFIG_X86_64
50         set_cpu_cap(c, X86_FEATURE_SYSENTER32);
51 #else
52         /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
53         if (c->x86 == 15 && c->x86_cache_alignment == 64)
54                 c->x86_cache_alignment = 128;
55 #endif
56
57         /*
58          * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
59          * with P/T states and does not stop in deep C-states
60          */
61         if (c->x86_power & (1 << 8)) {
62                 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
63                 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
64         }
65
66         /*
67          * There is a known erratum on Pentium III and Core Solo
68          * and Core Duo CPUs.
69          * " Page with PAT set to WC while associated MTRR is UC
70          *   may consolidate to UC "
71          * Because of this erratum, it is better to stick with
72          * setting WC in MTRR rather than using PAT on these CPUs.
73          *
74          * Enable PAT WC only on P4, Core 2 or later CPUs.
75          */
76         if (c->x86 == 6 && c->x86_model < 15)
77                 clear_cpu_cap(c, X86_FEATURE_PAT);
78 }
79
80 #ifdef CONFIG_X86_32
81 /*
82  *      Early probe support logic for ppro memory erratum #50
83  *
84  *      This is called before we do cpu ident work
85  */
86
87 int __cpuinit ppro_with_ram_bug(void)
88 {
89         /* Uses data from early_cpu_detect now */
90         if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
91             boot_cpu_data.x86 == 6 &&
92             boot_cpu_data.x86_model == 1 &&
93             boot_cpu_data.x86_mask < 8) {
94                 printk(KERN_INFO "Pentium Pro with Errata#50 detected. Taking evasive action.\n");
95                 return 1;
96         }
97         return 0;
98 }
99
100 #ifdef CONFIG_X86_F00F_BUG
101 static void __cpuinit trap_init_f00f_bug(void)
102 {
103         __set_fixmap(FIX_F00F_IDT, __pa(&idt_table), PAGE_KERNEL_RO);
104
105         /*
106          * Update the IDT descriptor and reload the IDT so that
107          * it uses the read-only mapped virtual address.
108          */
109         idt_descr.address = fix_to_virt(FIX_F00F_IDT);
110         load_idt(&idt_descr);
111 }
112 #endif
113
114 static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
115 {
116         unsigned long lo, hi;
117
118 #ifdef CONFIG_X86_F00F_BUG
119         /*
120          * All current models of Pentium and Pentium with MMX technology CPUs
121          * have the F0 0F bug, which lets nonprivileged users lock up the system.
122          * Note that the workaround only should be initialized once...
123          */
124         c->f00f_bug = 0;
125         if (!paravirt_enabled() && c->x86 == 5) {
126                 static int f00f_workaround_enabled;
127
128                 c->f00f_bug = 1;
129                 if (!f00f_workaround_enabled) {
130                         trap_init_f00f_bug();
131                         printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n");
132                         f00f_workaround_enabled = 1;
133                 }
134         }
135 #endif
136
137         /*
138          * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until
139          * model 3 mask 3
140          */
141         if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
142                 clear_cpu_cap(c, X86_FEATURE_SEP);
143
144         /*
145          * P4 Xeon errata 037 workaround.
146          * Hardware prefetcher may cause stale data to be loaded into the cache.
147          */
148         if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
149                 rdmsr(MSR_IA32_MISC_ENABLE, lo, hi);
150                 if ((lo & (1<<9)) == 0) {
151                         printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");
152                         printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n");
153                         lo |= (1<<9);   /* Disable hw prefetching */
154                         wrmsr (MSR_IA32_MISC_ENABLE, lo, hi);
155                 }
156         }
157
158         /*
159          * See if we have a good local APIC by checking for buggy Pentia,
160          * i.e. all B steppings and the C2 stepping of P54C when using their
161          * integrated APIC (see 11AP erratum in "Pentium Processor
162          * Specification Update").
163          */
164         if (cpu_has_apic && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
165             (c->x86_mask < 0x6 || c->x86_mask == 0xb))
166                 set_cpu_cap(c, X86_FEATURE_11AP);
167
168
169 #ifdef CONFIG_X86_INTEL_USERCOPY
170         /*
171          * Set up the preferred alignment for movsl bulk memory moves
172          */
173         switch (c->x86) {
174         case 4:         /* 486: untested */
175                 break;
176         case 5:         /* Old Pentia: untested */
177                 break;
178         case 6:         /* PII/PIII only like movsl with 8-byte alignment */
179                 movsl_mask.mask = 7;
180                 break;
181         case 15:        /* P4 is OK down to 8-byte alignment */
182                 movsl_mask.mask = 7;
183                 break;
184         }
185 #endif
186
187 #ifdef CONFIG_X86_NUMAQ
188         numaq_tsc_disable();
189 #endif
190 }
191 #else
192 static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
193 {
194 }
195 #endif
196
197 static void __cpuinit srat_detect_node(void)
198 {
199 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64)
200         unsigned node;
201         int cpu = smp_processor_id();
202         int apicid = hard_smp_processor_id();
203
204         /* Don't do the funky fallback heuristics the AMD version employs
205            for now. */
206         node = apicid_to_node[apicid];
207         if (node == NUMA_NO_NODE || !node_online(node))
208                 node = first_node(node_online_map);
209         numa_set_node(cpu, node);
210
211         printk(KERN_INFO "CPU %d/0x%x -> Node %d\n", cpu, apicid, node);
212 #endif
213 }
214
215 /*
216  * find out the number of processor cores on the die
217  */
218 static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
219 {
220         unsigned int eax, ebx, ecx, edx;
221
222         if (c->cpuid_level < 4)
223                 return 1;
224
225         /* Intel has a non-standard dependency on %ecx for this CPUID level. */
226         cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
227         if (eax & 0x1f)
228                 return ((eax >> 26) + 1);
229         else
230                 return 1;
231 }
232
233 static void __cpuinit detect_vmx_virtcap(struct cpuinfo_x86 *c)
234 {
235         /* Intel VMX MSR indicated features */
236 #define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW    0x00200000
237 #define X86_VMX_FEATURE_PROC_CTLS_VNMI          0x00400000
238 #define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS      0x80000000
239 #define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC    0x00000001
240 #define X86_VMX_FEATURE_PROC_CTLS2_EPT          0x00000002
241 #define X86_VMX_FEATURE_PROC_CTLS2_VPID         0x00000020
242
243         u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2;
244
245         clear_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
246         clear_cpu_cap(c, X86_FEATURE_VNMI);
247         clear_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
248         clear_cpu_cap(c, X86_FEATURE_EPT);
249         clear_cpu_cap(c, X86_FEATURE_VPID);
250
251         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high);
252         msr_ctl = vmx_msr_high | vmx_msr_low;
253         if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)
254                 set_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
255         if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI)
256                 set_cpu_cap(c, X86_FEATURE_VNMI);
257         if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) {
258                 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
259                       vmx_msr_low, vmx_msr_high);
260                 msr_ctl2 = vmx_msr_high | vmx_msr_low;
261                 if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) &&
262                     (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW))
263                         set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
264                 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT)
265                         set_cpu_cap(c, X86_FEATURE_EPT);
266                 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID)
267                         set_cpu_cap(c, X86_FEATURE_VPID);
268         }
269 }
270
271 static void __cpuinit init_intel(struct cpuinfo_x86 *c)
272 {
273         unsigned int l2 = 0;
274
275         early_init_intel(c);
276
277         intel_workarounds(c);
278
279         /*
280          * Detect the extended topology information if available. This
281          * will reinitialise the initial_apicid which will be used
282          * in init_intel_cacheinfo()
283          */
284         detect_extended_topology(c);
285
286         l2 = init_intel_cacheinfo(c);
287         if (c->cpuid_level > 9) {
288                 unsigned eax = cpuid_eax(10);
289                 /* Check for version and the number of counters */
290                 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
291                         set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
292         }
293
294         if (cpu_has_xmm2)
295                 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
296         if (cpu_has_ds) {
297                 unsigned int l1;
298                 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
299                 if (!(l1 & (1<<11)))
300                         set_cpu_cap(c, X86_FEATURE_BTS);
301                 if (!(l1 & (1<<12)))
302                         set_cpu_cap(c, X86_FEATURE_PEBS);
303                 ds_init_intel(c);
304         }
305
306 #ifdef CONFIG_X86_64
307         if (c->x86 == 15)
308                 c->x86_cache_alignment = c->x86_clflush_size * 2;
309         if (c->x86 == 6)
310                 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
311 #else
312         /*
313          * Names for the Pentium II/Celeron processors
314          * detectable only by also checking the cache size.
315          * Dixon is NOT a Celeron.
316          */
317         if (c->x86 == 6) {
318                 char *p = NULL;
319
320                 switch (c->x86_model) {
321                 case 5:
322                         if (c->x86_mask == 0) {
323                                 if (l2 == 0)
324                                         p = "Celeron (Covington)";
325                                 else if (l2 == 256)
326                                         p = "Mobile Pentium II (Dixon)";
327                         }
328                         break;
329
330                 case 6:
331                         if (l2 == 128)
332                                 p = "Celeron (Mendocino)";
333                         else if (c->x86_mask == 0 || c->x86_mask == 5)
334                                 p = "Celeron-A";
335                         break;
336
337                 case 8:
338                         if (l2 == 128)
339                                 p = "Celeron (Coppermine)";
340                         break;
341                 }
342
343                 if (p)
344                         strcpy(c->x86_model_id, p);
345         }
346
347         if (c->x86 == 15)
348                 set_cpu_cap(c, X86_FEATURE_P4);
349         if (c->x86 == 6)
350                 set_cpu_cap(c, X86_FEATURE_P3);
351 #endif
352
353         if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
354                 /*
355                  * let's use the legacy cpuid vector 0x1 and 0x4 for topology
356                  * detection.
357                  */
358                 c->x86_max_cores = intel_num_cpu_cores(c);
359 #ifdef CONFIG_X86_32
360                 detect_ht(c);
361 #endif
362         }
363
364         /* Work around errata */
365         srat_detect_node();
366
367         if (cpu_has(c, X86_FEATURE_VMX))
368                 detect_vmx_virtcap(c);
369 }
370
371 #ifdef CONFIG_X86_32
372 static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
373 {
374         /*
375          * Intel PIII Tualatin. This comes in two flavours.
376          * One has 256kb of cache, the other 512. We have no way
377          * to determine which, so we use a boottime override
378          * for the 512kb model, and assume 256 otherwise.
379          */
380         if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
381                 size = 256;
382         return size;
383 }
384 #endif
385
386 static struct cpu_dev intel_cpu_dev __cpuinitdata = {
387         .c_vendor       = "Intel",
388         .c_ident        = { "GenuineIntel" },
389 #ifdef CONFIG_X86_32
390         .c_models = {
391                 { .vendor = X86_VENDOR_INTEL, .family = 4, .model_names =
392                   {
393                           [0] = "486 DX-25/33",
394                           [1] = "486 DX-50",
395                           [2] = "486 SX",
396                           [3] = "486 DX/2",
397                           [4] = "486 SL",
398                           [5] = "486 SX/2",
399                           [7] = "486 DX/2-WB",
400                           [8] = "486 DX/4",
401                           [9] = "486 DX/4-WB"
402                   }
403                 },
404                 { .vendor = X86_VENDOR_INTEL, .family = 5, .model_names =
405                   {
406                           [0] = "Pentium 60/66 A-step",
407                           [1] = "Pentium 60/66",
408                           [2] = "Pentium 75 - 200",
409                           [3] = "OverDrive PODP5V83",
410                           [4] = "Pentium MMX",
411                           [7] = "Mobile Pentium 75 - 200",
412                           [8] = "Mobile Pentium MMX"
413                   }
414                 },
415                 { .vendor = X86_VENDOR_INTEL, .family = 6, .model_names =
416                   {
417                           [0] = "Pentium Pro A-step",
418                           [1] = "Pentium Pro",
419                           [3] = "Pentium II (Klamath)",
420                           [4] = "Pentium II (Deschutes)",
421                           [5] = "Pentium II (Deschutes)",
422                           [6] = "Mobile Pentium II",
423                           [7] = "Pentium III (Katmai)",
424                           [8] = "Pentium III (Coppermine)",
425                           [10] = "Pentium III (Cascades)",
426                           [11] = "Pentium III (Tualatin)",
427                   }
428                 },
429                 { .vendor = X86_VENDOR_INTEL, .family = 15, .model_names =
430                   {
431                           [0] = "Pentium 4 (Unknown)",
432                           [1] = "Pentium 4 (Willamette)",
433                           [2] = "Pentium 4 (Northwood)",
434                           [4] = "Pentium 4 (Foster)",
435                           [5] = "Pentium 4 (Foster)",
436                   }
437                 },
438         },
439         .c_size_cache   = intel_size_cache,
440 #endif
441         .c_early_init   = early_init_intel,
442         .c_init         = init_intel,
443         .c_x86_vendor   = X86_VENDOR_INTEL,
444 };
445
446 cpu_dev_register(intel_cpu_dev);
447