Merge branch 'devel' into for-linus
[linux-2.6] / drivers / i2c / busses / i2c-omap.c
1 /*
2  * TI OMAP I2C master mode driver
3  *
4  * Copyright (C) 2003 MontaVista Software, Inc.
5  * Copyright (C) 2005 Nokia Corporation
6  * Copyright (C) 2004 - 2007 Texas Instruments.
7  *
8  * Originally written by MontaVista Software, Inc.
9  * Additional contributions by:
10  *      Tony Lindgren <tony@atomide.com>
11  *      Imre Deak <imre.deak@nokia.com>
12  *      Juha Yrjölä <juha.yrjola@solidboot.com>
13  *      Syed Khasim <x0khasim@ti.com>
14  *      Nishant Menon <nm@ti.com>
15  *
16  * This program is free software; you can redistribute it and/or modify
17  * it under the terms of the GNU General Public License as published by
18  * the Free Software Foundation; either version 2 of the License, or
19  * (at your option) any later version.
20  *
21  * This program is distributed in the hope that it will be useful,
22  * but WITHOUT ANY WARRANTY; without even the implied warranty of
23  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24  * GNU General Public License for more details.
25  *
26  * You should have received a copy of the GNU General Public License
27  * along with this program; if not, write to the Free Software
28  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
29  */
30
31 #include <linux/module.h>
32 #include <linux/delay.h>
33 #include <linux/i2c.h>
34 #include <linux/err.h>
35 #include <linux/interrupt.h>
36 #include <linux/completion.h>
37 #include <linux/platform_device.h>
38 #include <linux/clk.h>
39 #include <linux/io.h>
40
41 /* I2C controller revisions */
42 #define OMAP_I2C_REV_2                  0x20
43
44 /* I2C controller revisions present on specific hardware */
45 #define OMAP_I2C_REV_ON_2430            0x36
46 #define OMAP_I2C_REV_ON_3430            0x3C
47
48 /* timeout waiting for the controller to respond */
49 #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
50
51 #define OMAP_I2C_REV_REG                0x00
52 #define OMAP_I2C_IE_REG                 0x04
53 #define OMAP_I2C_STAT_REG               0x08
54 #define OMAP_I2C_IV_REG                 0x0c
55 /* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */
56 #define OMAP_I2C_WE_REG                 0x0c
57 #define OMAP_I2C_SYSS_REG               0x10
58 #define OMAP_I2C_BUF_REG                0x14
59 #define OMAP_I2C_CNT_REG                0x18
60 #define OMAP_I2C_DATA_REG               0x1c
61 #define OMAP_I2C_SYSC_REG               0x20
62 #define OMAP_I2C_CON_REG                0x24
63 #define OMAP_I2C_OA_REG                 0x28
64 #define OMAP_I2C_SA_REG                 0x2c
65 #define OMAP_I2C_PSC_REG                0x30
66 #define OMAP_I2C_SCLL_REG               0x34
67 #define OMAP_I2C_SCLH_REG               0x38
68 #define OMAP_I2C_SYSTEST_REG            0x3c
69 #define OMAP_I2C_BUFSTAT_REG            0x40
70
71 /* I2C Interrupt Enable Register (OMAP_I2C_IE): */
72 #define OMAP_I2C_IE_XDR         (1 << 14)       /* TX Buffer drain int enable */
73 #define OMAP_I2C_IE_RDR         (1 << 13)       /* RX Buffer drain int enable */
74 #define OMAP_I2C_IE_XRDY        (1 << 4)        /* TX data ready int enable */
75 #define OMAP_I2C_IE_RRDY        (1 << 3)        /* RX data ready int enable */
76 #define OMAP_I2C_IE_ARDY        (1 << 2)        /* Access ready int enable */
77 #define OMAP_I2C_IE_NACK        (1 << 1)        /* No ack interrupt enable */
78 #define OMAP_I2C_IE_AL          (1 << 0)        /* Arbitration lost int ena */
79
80 /* I2C Status Register (OMAP_I2C_STAT): */
81 #define OMAP_I2C_STAT_XDR       (1 << 14)       /* TX Buffer draining */
82 #define OMAP_I2C_STAT_RDR       (1 << 13)       /* RX Buffer draining */
83 #define OMAP_I2C_STAT_BB        (1 << 12)       /* Bus busy */
84 #define OMAP_I2C_STAT_ROVR      (1 << 11)       /* Receive overrun */
85 #define OMAP_I2C_STAT_XUDF      (1 << 10)       /* Transmit underflow */
86 #define OMAP_I2C_STAT_AAS       (1 << 9)        /* Address as slave */
87 #define OMAP_I2C_STAT_AD0       (1 << 8)        /* Address zero */
88 #define OMAP_I2C_STAT_XRDY      (1 << 4)        /* Transmit data ready */
89 #define OMAP_I2C_STAT_RRDY      (1 << 3)        /* Receive data ready */
90 #define OMAP_I2C_STAT_ARDY      (1 << 2)        /* Register access ready */
91 #define OMAP_I2C_STAT_NACK      (1 << 1)        /* No ack interrupt enable */
92 #define OMAP_I2C_STAT_AL        (1 << 0)        /* Arbitration lost int ena */
93
94 /* I2C WE wakeup enable register */
95 #define OMAP_I2C_WE_XDR_WE      (1 << 14)       /* TX drain wakup */
96 #define OMAP_I2C_WE_RDR_WE      (1 << 13)       /* RX drain wakeup */
97 #define OMAP_I2C_WE_AAS_WE      (1 << 9)        /* Address as slave wakeup*/
98 #define OMAP_I2C_WE_BF_WE       (1 << 8)        /* Bus free wakeup */
99 #define OMAP_I2C_WE_STC_WE      (1 << 6)        /* Start condition wakeup */
100 #define OMAP_I2C_WE_GC_WE       (1 << 5)        /* General call wakeup */
101 #define OMAP_I2C_WE_DRDY_WE     (1 << 3)        /* TX/RX data ready wakeup */
102 #define OMAP_I2C_WE_ARDY_WE     (1 << 2)        /* Reg access ready wakeup */
103 #define OMAP_I2C_WE_NACK_WE     (1 << 1)        /* No acknowledgment wakeup */
104 #define OMAP_I2C_WE_AL_WE       (1 << 0)        /* Arbitration lost wakeup */
105
106 #define OMAP_I2C_WE_ALL         (OMAP_I2C_WE_XDR_WE | OMAP_I2C_WE_RDR_WE | \
107                                 OMAP_I2C_WE_AAS_WE | OMAP_I2C_WE_BF_WE | \
108                                 OMAP_I2C_WE_STC_WE | OMAP_I2C_WE_GC_WE | \
109                                 OMAP_I2C_WE_DRDY_WE | OMAP_I2C_WE_ARDY_WE | \
110                                 OMAP_I2C_WE_NACK_WE | OMAP_I2C_WE_AL_WE)
111
112 /* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
113 #define OMAP_I2C_BUF_RDMA_EN    (1 << 15)       /* RX DMA channel enable */
114 #define OMAP_I2C_BUF_RXFIF_CLR  (1 << 14)       /* RX FIFO Clear */
115 #define OMAP_I2C_BUF_XDMA_EN    (1 << 7)        /* TX DMA channel enable */
116 #define OMAP_I2C_BUF_TXFIF_CLR  (1 << 6)        /* TX FIFO Clear */
117
118 /* I2C Configuration Register (OMAP_I2C_CON): */
119 #define OMAP_I2C_CON_EN         (1 << 15)       /* I2C module enable */
120 #define OMAP_I2C_CON_BE         (1 << 14)       /* Big endian mode */
121 #define OMAP_I2C_CON_OPMODE_HS  (1 << 12)       /* High Speed support */
122 #define OMAP_I2C_CON_STB        (1 << 11)       /* Start byte mode (master) */
123 #define OMAP_I2C_CON_MST        (1 << 10)       /* Master/slave mode */
124 #define OMAP_I2C_CON_TRX        (1 << 9)        /* TX/RX mode (master only) */
125 #define OMAP_I2C_CON_XA         (1 << 8)        /* Expand address */
126 #define OMAP_I2C_CON_RM         (1 << 2)        /* Repeat mode (master only) */
127 #define OMAP_I2C_CON_STP        (1 << 1)        /* Stop cond (master only) */
128 #define OMAP_I2C_CON_STT        (1 << 0)        /* Start condition (master) */
129
130 /* I2C SCL time value when Master */
131 #define OMAP_I2C_SCLL_HSSCLL    8
132 #define OMAP_I2C_SCLH_HSSCLH    8
133
134 /* I2C System Test Register (OMAP_I2C_SYSTEST): */
135 #ifdef DEBUG
136 #define OMAP_I2C_SYSTEST_ST_EN          (1 << 15)       /* System test enable */
137 #define OMAP_I2C_SYSTEST_FREE           (1 << 14)       /* Free running mode */
138 #define OMAP_I2C_SYSTEST_TMODE_MASK     (3 << 12)       /* Test mode select */
139 #define OMAP_I2C_SYSTEST_TMODE_SHIFT    (12)            /* Test mode select */
140 #define OMAP_I2C_SYSTEST_SCL_I          (1 << 3)        /* SCL line sense in */
141 #define OMAP_I2C_SYSTEST_SCL_O          (1 << 2)        /* SCL line drive out */
142 #define OMAP_I2C_SYSTEST_SDA_I          (1 << 1)        /* SDA line sense in */
143 #define OMAP_I2C_SYSTEST_SDA_O          (1 << 0)        /* SDA line drive out */
144 #endif
145
146 /* OCP_SYSSTATUS bit definitions */
147 #define SYSS_RESETDONE_MASK             (1 << 0)
148
149 /* OCP_SYSCONFIG bit definitions */
150 #define SYSC_CLOCKACTIVITY_MASK         (0x3 << 8)
151 #define SYSC_SIDLEMODE_MASK             (0x3 << 3)
152 #define SYSC_ENAWAKEUP_MASK             (1 << 2)
153 #define SYSC_SOFTRESET_MASK             (1 << 1)
154 #define SYSC_AUTOIDLE_MASK              (1 << 0)
155
156 #define SYSC_IDLEMODE_SMART             0x2
157 #define SYSC_CLOCKACTIVITY_FCLK         0x2
158
159
160 struct omap_i2c_dev {
161         struct device           *dev;
162         void __iomem            *base;          /* virtual */
163         int                     irq;
164         struct clk              *iclk;          /* Interface clock */
165         struct clk              *fclk;          /* Functional clock */
166         struct completion       cmd_complete;
167         struct resource         *ioarea;
168         u32                     speed;          /* Speed of bus in Khz */
169         u16                     cmd_err;
170         u8                      *buf;
171         size_t                  buf_len;
172         struct i2c_adapter      adapter;
173         u8                      fifo_size;      /* use as flag and value
174                                                  * fifo_size==0 implies no fifo
175                                                  * if set, should be trsh+1
176                                                  */
177         u8                      rev;
178         unsigned                b_hw:1;         /* bad h/w fixes */
179         unsigned                idle:1;
180         u16                     iestate;        /* Saved interrupt register */
181 };
182
183 static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev,
184                                       int reg, u16 val)
185 {
186         __raw_writew(val, i2c_dev->base + reg);
187 }
188
189 static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
190 {
191         return __raw_readw(i2c_dev->base + reg);
192 }
193
194 static int __init omap_i2c_get_clocks(struct omap_i2c_dev *dev)
195 {
196         int ret;
197
198         dev->iclk = clk_get(dev->dev, "ick");
199         if (IS_ERR(dev->iclk)) {
200                 ret = PTR_ERR(dev->iclk);
201                 dev->iclk = NULL;
202                 return ret;
203         }
204
205         dev->fclk = clk_get(dev->dev, "fck");
206         if (IS_ERR(dev->fclk)) {
207                 ret = PTR_ERR(dev->fclk);
208                 if (dev->iclk != NULL) {
209                         clk_put(dev->iclk);
210                         dev->iclk = NULL;
211                 }
212                 dev->fclk = NULL;
213                 return ret;
214         }
215
216         return 0;
217 }
218
219 static void omap_i2c_put_clocks(struct omap_i2c_dev *dev)
220 {
221         clk_put(dev->fclk);
222         dev->fclk = NULL;
223         clk_put(dev->iclk);
224         dev->iclk = NULL;
225 }
226
227 static void omap_i2c_unidle(struct omap_i2c_dev *dev)
228 {
229         WARN_ON(!dev->idle);
230
231         clk_enable(dev->iclk);
232         clk_enable(dev->fclk);
233         dev->idle = 0;
234         if (dev->iestate)
235                 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
236 }
237
238 static void omap_i2c_idle(struct omap_i2c_dev *dev)
239 {
240         u16 iv;
241
242         WARN_ON(dev->idle);
243
244         dev->iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
245         omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, 0);
246         if (dev->rev < OMAP_I2C_REV_2) {
247                 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG); /* Read clears */
248         } else {
249                 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, dev->iestate);
250
251                 /* Flush posted write before the dev->idle store occurs */
252                 omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
253         }
254         dev->idle = 1;
255         clk_disable(dev->fclk);
256         clk_disable(dev->iclk);
257 }
258
259 static int omap_i2c_init(struct omap_i2c_dev *dev)
260 {
261         u16 psc = 0, scll = 0, sclh = 0;
262         u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
263         unsigned long fclk_rate = 12000000;
264         unsigned long timeout;
265         unsigned long internal_clk = 0;
266
267         if (dev->rev >= OMAP_I2C_REV_2) {
268                 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK);
269                 /* For some reason we need to set the EN bit before the
270                  * reset done bit gets set. */
271                 timeout = jiffies + OMAP_I2C_TIMEOUT;
272                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
273                 while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) &
274                          SYSS_RESETDONE_MASK)) {
275                         if (time_after(jiffies, timeout)) {
276                                 dev_warn(dev->dev, "timeout waiting "
277                                                 "for controller reset\n");
278                                 return -ETIMEDOUT;
279                         }
280                         msleep(1);
281                 }
282
283                 /* SYSC register is cleared by the reset; rewrite it */
284                 if (dev->rev == OMAP_I2C_REV_ON_2430) {
285
286                         omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG,
287                                            SYSC_AUTOIDLE_MASK);
288
289                 } else if (dev->rev >= OMAP_I2C_REV_ON_3430) {
290                         u32 v;
291
292                         v = SYSC_AUTOIDLE_MASK;
293                         v |= SYSC_ENAWAKEUP_MASK;
294                         v |= (SYSC_IDLEMODE_SMART <<
295                               __ffs(SYSC_SIDLEMODE_MASK));
296                         v |= (SYSC_CLOCKACTIVITY_FCLK <<
297                               __ffs(SYSC_CLOCKACTIVITY_MASK));
298
299                         omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, v);
300                         /*
301                          * Enabling all wakup sources to stop I2C freezing on
302                          * WFI instruction.
303                          * REVISIT: Some wkup sources might not be needed.
304                          */
305                         omap_i2c_write_reg(dev, OMAP_I2C_WE_REG,
306                                                         OMAP_I2C_WE_ALL);
307
308                 }
309         }
310         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
311
312         if (cpu_class_is_omap1()) {
313                 /*
314                  * The I2C functional clock is the armxor_ck, so there's
315                  * no need to get "armxor_ck" separately.  Now, if OMAP2420
316                  * always returns 12MHz for the functional clock, we can
317                  * do this bit unconditionally.
318                  */
319                 fclk_rate = clk_get_rate(dev->fclk);
320
321                 /* TRM for 5912 says the I2C clock must be prescaled to be
322                  * between 7 - 12 MHz. The XOR input clock is typically
323                  * 12, 13 or 19.2 MHz. So we should have code that produces:
324                  *
325                  * XOR MHz      Divider         Prescaler
326                  * 12           1               0
327                  * 13           2               1
328                  * 19.2         2               1
329                  */
330                 if (fclk_rate > 12000000)
331                         psc = fclk_rate / 12000000;
332         }
333
334         if (cpu_is_omap2430() || cpu_is_omap34xx()) {
335
336                 /* HSI2C controller internal clk rate should be 19.2 Mhz */
337                 internal_clk = 19200;
338                 fclk_rate = clk_get_rate(dev->fclk) / 1000;
339
340                 /* Compute prescaler divisor */
341                 psc = fclk_rate / internal_clk;
342                 psc = psc - 1;
343
344                 /* If configured for High Speed */
345                 if (dev->speed > 400) {
346                         /* For first phase of HS mode */
347                         fsscll = internal_clk / (400 * 2) - 6;
348                         fssclh = internal_clk / (400 * 2) - 6;
349
350                         /* For second phase of HS mode */
351                         hsscll = fclk_rate / (dev->speed * 2) - 6;
352                         hssclh = fclk_rate / (dev->speed * 2) - 6;
353                 } else {
354                         /* To handle F/S modes */
355                         fsscll = internal_clk / (dev->speed * 2) - 6;
356                         fssclh = internal_clk / (dev->speed * 2) - 6;
357                 }
358                 scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
359                 sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
360         } else {
361                 /* Program desired operating rate */
362                 fclk_rate /= (psc + 1) * 1000;
363                 if (psc > 2)
364                         psc = 2;
365                 scll = fclk_rate / (dev->speed * 2) - 7 + psc;
366                 sclh = fclk_rate / (dev->speed * 2) - 7 + psc;
367         }
368
369         /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
370         omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc);
371
372         /* SCL low and high time values */
373         omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, scll);
374         omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, sclh);
375
376         if (dev->fifo_size)
377                 /* Note: setup required fifo size - 1 */
378                 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG,
379                                         (dev->fifo_size - 1) << 8 | /* RTRSH */
380                                         OMAP_I2C_BUF_RXFIF_CLR |
381                                         (dev->fifo_size - 1) | /* XTRSH */
382                                         OMAP_I2C_BUF_TXFIF_CLR);
383
384         /* Take the I2C module out of reset: */
385         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
386
387         /* Enable interrupts */
388         omap_i2c_write_reg(dev, OMAP_I2C_IE_REG,
389                         (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
390                         OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
391                         OMAP_I2C_IE_AL)  | ((dev->fifo_size) ?
392                                 (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0));
393         return 0;
394 }
395
396 /*
397  * Waiting on Bus Busy
398  */
399 static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev)
400 {
401         unsigned long timeout;
402
403         timeout = jiffies + OMAP_I2C_TIMEOUT;
404         while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
405                 if (time_after(jiffies, timeout)) {
406                         dev_warn(dev->dev, "timeout waiting for bus ready\n");
407                         return -ETIMEDOUT;
408                 }
409                 msleep(1);
410         }
411
412         return 0;
413 }
414
415 /*
416  * Low level master read/write transaction.
417  */
418 static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
419                              struct i2c_msg *msg, int stop)
420 {
421         struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
422         int r;
423         u16 w;
424
425         dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
426                 msg->addr, msg->len, msg->flags, stop);
427
428         if (msg->len == 0)
429                 return -EINVAL;
430
431         omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);
432
433         /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
434         dev->buf = msg->buf;
435         dev->buf_len = msg->len;
436
437         omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len);
438
439         /* Clear the FIFO Buffers */
440         w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
441         w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR;
442         omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w);
443
444         init_completion(&dev->cmd_complete);
445         dev->cmd_err = 0;
446
447         w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
448
449         /* High speed configuration */
450         if (dev->speed > 400)
451                 w |= OMAP_I2C_CON_OPMODE_HS;
452
453         if (msg->flags & I2C_M_TEN)
454                 w |= OMAP_I2C_CON_XA;
455         if (!(msg->flags & I2C_M_RD))
456                 w |= OMAP_I2C_CON_TRX;
457
458         if (!dev->b_hw && stop)
459                 w |= OMAP_I2C_CON_STP;
460
461         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
462
463         /*
464          * Don't write stt and stp together on some hardware.
465          */
466         if (dev->b_hw && stop) {
467                 unsigned long delay = jiffies + OMAP_I2C_TIMEOUT;
468                 u16 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
469                 while (con & OMAP_I2C_CON_STT) {
470                         con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
471
472                         /* Let the user know if i2c is in a bad state */
473                         if (time_after(jiffies, delay)) {
474                                 dev_err(dev->dev, "controller timed out "
475                                 "waiting for start condition to finish\n");
476                                 return -ETIMEDOUT;
477                         }
478                         cpu_relax();
479                 }
480
481                 w |= OMAP_I2C_CON_STP;
482                 w &= ~OMAP_I2C_CON_STT;
483                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
484         }
485
486         /*
487          * REVISIT: We should abort the transfer on signals, but the bus goes
488          * into arbitration and we're currently unable to recover from it.
489          */
490         r = wait_for_completion_timeout(&dev->cmd_complete,
491                                         OMAP_I2C_TIMEOUT);
492         dev->buf_len = 0;
493         if (r < 0)
494                 return r;
495         if (r == 0) {
496                 dev_err(dev->dev, "controller timed out\n");
497                 omap_i2c_init(dev);
498                 return -ETIMEDOUT;
499         }
500
501         if (likely(!dev->cmd_err))
502                 return 0;
503
504         /* We have an error */
505         if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR |
506                             OMAP_I2C_STAT_XUDF)) {
507                 omap_i2c_init(dev);
508                 return -EIO;
509         }
510
511         if (dev->cmd_err & OMAP_I2C_STAT_NACK) {
512                 if (msg->flags & I2C_M_IGNORE_NAK)
513                         return 0;
514                 if (stop) {
515                         w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
516                         w |= OMAP_I2C_CON_STP;
517                         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
518                 }
519                 return -EREMOTEIO;
520         }
521         return -EIO;
522 }
523
524
525 /*
526  * Prepare controller for a transaction and call omap_i2c_xfer_msg
527  * to do the work during IRQ processing.
528  */
529 static int
530 omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
531 {
532         struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
533         int i;
534         int r;
535
536         omap_i2c_unidle(dev);
537
538         r = omap_i2c_wait_for_bb(dev);
539         if (r < 0)
540                 goto out;
541
542         for (i = 0; i < num; i++) {
543                 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
544                 if (r != 0)
545                         break;
546         }
547
548         if (r == 0)
549                 r = num;
550 out:
551         omap_i2c_idle(dev);
552         return r;
553 }
554
555 static u32
556 omap_i2c_func(struct i2c_adapter *adap)
557 {
558         return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
559 }
560
561 static inline void
562 omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err)
563 {
564         dev->cmd_err |= err;
565         complete(&dev->cmd_complete);
566 }
567
568 static inline void
569 omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat)
570 {
571         omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
572 }
573
574 /* rev1 devices are apparently only on some 15xx */
575 #ifdef CONFIG_ARCH_OMAP15XX
576
577 static irqreturn_t
578 omap_i2c_rev1_isr(int this_irq, void *dev_id)
579 {
580         struct omap_i2c_dev *dev = dev_id;
581         u16 iv, w;
582
583         if (dev->idle)
584                 return IRQ_NONE;
585
586         iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
587         switch (iv) {
588         case 0x00:      /* None */
589                 break;
590         case 0x01:      /* Arbitration lost */
591                 dev_err(dev->dev, "Arbitration lost\n");
592                 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
593                 break;
594         case 0x02:      /* No acknowledgement */
595                 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
596                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
597                 break;
598         case 0x03:      /* Register access ready */
599                 omap_i2c_complete_cmd(dev, 0);
600                 break;
601         case 0x04:      /* Receive data ready */
602                 if (dev->buf_len) {
603                         w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
604                         *dev->buf++ = w;
605                         dev->buf_len--;
606                         if (dev->buf_len) {
607                                 *dev->buf++ = w >> 8;
608                                 dev->buf_len--;
609                         }
610                 } else
611                         dev_err(dev->dev, "RRDY IRQ while no data requested\n");
612                 break;
613         case 0x05:      /* Transmit data ready */
614                 if (dev->buf_len) {
615                         w = *dev->buf++;
616                         dev->buf_len--;
617                         if (dev->buf_len) {
618                                 w |= *dev->buf++ << 8;
619                                 dev->buf_len--;
620                         }
621                         omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
622                 } else
623                         dev_err(dev->dev, "XRDY IRQ while no data to send\n");
624                 break;
625         default:
626                 return IRQ_NONE;
627         }
628
629         return IRQ_HANDLED;
630 }
631 #else
632 #define omap_i2c_rev1_isr               NULL
633 #endif
634
635 static irqreturn_t
636 omap_i2c_isr(int this_irq, void *dev_id)
637 {
638         struct omap_i2c_dev *dev = dev_id;
639         u16 bits;
640         u16 stat, w;
641         int err, count = 0;
642
643         if (dev->idle)
644                 return IRQ_NONE;
645
646         bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
647         while ((stat = (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG))) & bits) {
648                 dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat);
649                 if (count++ == 100) {
650                         dev_warn(dev->dev, "Too much work in one IRQ\n");
651                         break;
652                 }
653
654                 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
655
656                 err = 0;
657                 if (stat & OMAP_I2C_STAT_NACK) {
658                         err |= OMAP_I2C_STAT_NACK;
659                         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
660                                            OMAP_I2C_CON_STP);
661                 }
662                 if (stat & OMAP_I2C_STAT_AL) {
663                         dev_err(dev->dev, "Arbitration lost\n");
664                         err |= OMAP_I2C_STAT_AL;
665                 }
666                 if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
667                                         OMAP_I2C_STAT_AL))
668                         omap_i2c_complete_cmd(dev, err);
669                 if (stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR)) {
670                         u8 num_bytes = 1;
671                         if (dev->fifo_size) {
672                                 if (stat & OMAP_I2C_STAT_RRDY)
673                                         num_bytes = dev->fifo_size;
674                                 else
675                                         num_bytes = omap_i2c_read_reg(dev,
676                                                         OMAP_I2C_BUFSTAT_REG);
677                         }
678                         while (num_bytes) {
679                                 num_bytes--;
680                                 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
681                                 if (dev->buf_len) {
682                                         *dev->buf++ = w;
683                                         dev->buf_len--;
684                                         /* Data reg from 2430 is 8 bit wide */
685                                         if (!cpu_is_omap2430() &&
686                                                         !cpu_is_omap34xx()) {
687                                                 if (dev->buf_len) {
688                                                         *dev->buf++ = w >> 8;
689                                                         dev->buf_len--;
690                                                 }
691                                         }
692                                 } else {
693                                         if (stat & OMAP_I2C_STAT_RRDY)
694                                                 dev_err(dev->dev,
695                                                         "RRDY IRQ while no data"
696                                                                 " requested\n");
697                                         if (stat & OMAP_I2C_STAT_RDR)
698                                                 dev_err(dev->dev,
699                                                         "RDR IRQ while no data"
700                                                                 " requested\n");
701                                         break;
702                                 }
703                         }
704                         omap_i2c_ack_stat(dev,
705                                 stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR));
706                         continue;
707                 }
708                 if (stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)) {
709                         u8 num_bytes = 1;
710                         if (dev->fifo_size) {
711                                 if (stat & OMAP_I2C_STAT_XRDY)
712                                         num_bytes = dev->fifo_size;
713                                 else
714                                         num_bytes = omap_i2c_read_reg(dev,
715                                                         OMAP_I2C_BUFSTAT_REG);
716                         }
717                         while (num_bytes) {
718                                 num_bytes--;
719                                 w = 0;
720                                 if (dev->buf_len) {
721                                         w = *dev->buf++;
722                                         dev->buf_len--;
723                                         /* Data reg from  2430 is 8 bit wide */
724                                         if (!cpu_is_omap2430() &&
725                                                         !cpu_is_omap34xx()) {
726                                                 if (dev->buf_len) {
727                                                         w |= *dev->buf++ << 8;
728                                                         dev->buf_len--;
729                                                 }
730                                         }
731                                 } else {
732                                         if (stat & OMAP_I2C_STAT_XRDY)
733                                                 dev_err(dev->dev,
734                                                         "XRDY IRQ while no "
735                                                         "data to send\n");
736                                         if (stat & OMAP_I2C_STAT_XDR)
737                                                 dev_err(dev->dev,
738                                                         "XDR IRQ while no "
739                                                         "data to send\n");
740                                         break;
741                                 }
742                                 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
743                         }
744                         omap_i2c_ack_stat(dev,
745                                 stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
746                         continue;
747                 }
748                 if (stat & OMAP_I2C_STAT_ROVR) {
749                         dev_err(dev->dev, "Receive overrun\n");
750                         dev->cmd_err |= OMAP_I2C_STAT_ROVR;
751                 }
752                 if (stat & OMAP_I2C_STAT_XUDF) {
753                         dev_err(dev->dev, "Transmit underflow\n");
754                         dev->cmd_err |= OMAP_I2C_STAT_XUDF;
755                 }
756         }
757
758         return count ? IRQ_HANDLED : IRQ_NONE;
759 }
760
761 static const struct i2c_algorithm omap_i2c_algo = {
762         .master_xfer    = omap_i2c_xfer,
763         .functionality  = omap_i2c_func,
764 };
765
766 static int __init
767 omap_i2c_probe(struct platform_device *pdev)
768 {
769         struct omap_i2c_dev     *dev;
770         struct i2c_adapter      *adap;
771         struct resource         *mem, *irq, *ioarea;
772         irq_handler_t isr;
773         int r;
774         u32 speed = 0;
775
776         /* NOTE: driver uses the static register mapping */
777         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
778         if (!mem) {
779                 dev_err(&pdev->dev, "no mem resource?\n");
780                 return -ENODEV;
781         }
782         irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
783         if (!irq) {
784                 dev_err(&pdev->dev, "no irq resource?\n");
785                 return -ENODEV;
786         }
787
788         ioarea = request_mem_region(mem->start, (mem->end - mem->start) + 1,
789                         pdev->name);
790         if (!ioarea) {
791                 dev_err(&pdev->dev, "I2C region already claimed\n");
792                 return -EBUSY;
793         }
794
795         dev = kzalloc(sizeof(struct omap_i2c_dev), GFP_KERNEL);
796         if (!dev) {
797                 r = -ENOMEM;
798                 goto err_release_region;
799         }
800
801         if (pdev->dev.platform_data != NULL)
802                 speed = *(u32 *)pdev->dev.platform_data;
803         else
804                 speed = 100;    /* Defualt speed */
805
806         dev->speed = speed;
807         dev->idle = 1;
808         dev->dev = &pdev->dev;
809         dev->irq = irq->start;
810         dev->base = ioremap(mem->start, mem->end - mem->start + 1);
811         if (!dev->base) {
812                 r = -ENOMEM;
813                 goto err_free_mem;
814         }
815
816         platform_set_drvdata(pdev, dev);
817
818         if ((r = omap_i2c_get_clocks(dev)) != 0)
819                 goto err_iounmap;
820
821         omap_i2c_unidle(dev);
822
823         dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff;
824
825         if (cpu_is_omap2430() || cpu_is_omap34xx()) {
826                 u16 s;
827
828                 /* Set up the fifo size - Get total size */
829                 s = (omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3;
830                 dev->fifo_size = 0x8 << s;
831
832                 /*
833                  * Set up notification threshold as half the total available
834                  * size. This is to ensure that we can handle the status on int
835                  * call back latencies.
836                  */
837                 dev->fifo_size = (dev->fifo_size / 2);
838                 dev->b_hw = 1; /* Enable hardware fixes */
839         }
840
841         /* reset ASAP, clearing any IRQs */
842         omap_i2c_init(dev);
843
844         isr = (dev->rev < OMAP_I2C_REV_2) ? omap_i2c_rev1_isr : omap_i2c_isr;
845         r = request_irq(dev->irq, isr, 0, pdev->name, dev);
846
847         if (r) {
848                 dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
849                 goto err_unuse_clocks;
850         }
851
852         dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n",
853                  pdev->id, dev->rev >> 4, dev->rev & 0xf, dev->speed);
854
855         omap_i2c_idle(dev);
856
857         adap = &dev->adapter;
858         i2c_set_adapdata(adap, dev);
859         adap->owner = THIS_MODULE;
860         adap->class = I2C_CLASS_HWMON;
861         strncpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
862         adap->algo = &omap_i2c_algo;
863         adap->dev.parent = &pdev->dev;
864
865         /* i2c device drivers may be active on return from add_adapter() */
866         adap->nr = pdev->id;
867         r = i2c_add_numbered_adapter(adap);
868         if (r) {
869                 dev_err(dev->dev, "failure adding adapter\n");
870                 goto err_free_irq;
871         }
872
873         return 0;
874
875 err_free_irq:
876         free_irq(dev->irq, dev);
877 err_unuse_clocks:
878         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
879         omap_i2c_idle(dev);
880         omap_i2c_put_clocks(dev);
881 err_iounmap:
882         iounmap(dev->base);
883 err_free_mem:
884         platform_set_drvdata(pdev, NULL);
885         kfree(dev);
886 err_release_region:
887         release_mem_region(mem->start, (mem->end - mem->start) + 1);
888
889         return r;
890 }
891
892 static int
893 omap_i2c_remove(struct platform_device *pdev)
894 {
895         struct omap_i2c_dev     *dev = platform_get_drvdata(pdev);
896         struct resource         *mem;
897
898         platform_set_drvdata(pdev, NULL);
899
900         free_irq(dev->irq, dev);
901         i2c_del_adapter(&dev->adapter);
902         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
903         omap_i2c_put_clocks(dev);
904         iounmap(dev->base);
905         kfree(dev);
906         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
907         release_mem_region(mem->start, (mem->end - mem->start) + 1);
908         return 0;
909 }
910
911 static struct platform_driver omap_i2c_driver = {
912         .probe          = omap_i2c_probe,
913         .remove         = omap_i2c_remove,
914         .driver         = {
915                 .name   = "i2c_omap",
916                 .owner  = THIS_MODULE,
917         },
918 };
919
920 /* I2C may be needed to bring up other drivers */
921 static int __init
922 omap_i2c_init_driver(void)
923 {
924         return platform_driver_register(&omap_i2c_driver);
925 }
926 subsys_initcall(omap_i2c_init_driver);
927
928 static void __exit omap_i2c_exit_driver(void)
929 {
930         platform_driver_unregister(&omap_i2c_driver);
931 }
932 module_exit(omap_i2c_exit_driver);
933
934 MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
935 MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
936 MODULE_LICENSE("GPL");
937 MODULE_ALIAS("platform:i2c_omap");