Merge master.kernel.org:/home/rmk/linux-2.6-serial
[linux-2.6] / include / asm-ppc / mpc52xx.h
1 /*
2  * include/asm-ppc/mpc52xx.h
3  * 
4  * Prototypes, etc. for the Freescale MPC52xx embedded cpu chips
5  * May need to be cleaned as the port goes on ...
6  *
7  *
8  * Maintainer : Sylvain Munaut <tnt@246tNt.com>
9  *
10  * Originally written by Dale Farnsworth <dfarnsworth@mvista.com> 
11  * for the 2.4 kernel.
12  *
13  * Copyright (C) 2004-2005 Sylvain Munaut <tnt@246tNt.com>
14  * Copyright (C) 2003 MontaVista, Software, Inc.
15  *
16  * This file is licensed under the terms of the GNU General Public License
17  * version 2. This program is licensed "as is" without any warranty of any
18  * kind, whether express or implied.
19  */
20
21 #ifndef __ASM_MPC52xx_H__
22 #define __ASM_MPC52xx_H__
23
24 #ifndef __ASSEMBLY__
25 #include <asm/ppcboot.h>
26 #include <asm/types.h>
27
28 struct pt_regs;
29 #endif /* __ASSEMBLY__ */
30
31
32 #ifdef CONFIG_PCI
33 #define _IO_BASE        isa_io_base
34 #define _ISA_MEM_BASE   isa_mem_base
35 #define PCI_DRAM_OFFSET pci_dram_offset
36 #else
37 #define _IO_BASE        0
38 #define _ISA_MEM_BASE   0
39 #define PCI_DRAM_OFFSET 0
40 #endif
41
42
43 /* ======================================================================== */
44 /* PPC Sys devices definition                                               */
45 /* ======================================================================== */
46
47 enum ppc_sys_devices {
48         MPC52xx_MSCAN1,
49         MPC52xx_MSCAN2,
50         MPC52xx_SPI,
51         MPC52xx_USB,
52         MPC52xx_BDLC,
53         MPC52xx_PSC1,
54         MPC52xx_PSC2,
55         MPC52xx_PSC3,
56         MPC52xx_PSC4,
57         MPC52xx_PSC5,
58         MPC52xx_PSC6,
59         MPC52xx_FEC,
60         MPC52xx_ATA,
61         MPC52xx_I2C1,
62         MPC52xx_I2C2,
63 };
64
65
66 /* ======================================================================== */
67 /* Main registers/struct addresses                                          */
68 /* ======================================================================== */
69
70 /* MBAR position */
71 #define MPC52xx_MBAR            0xf0000000      /* Phys address */
72 #define MPC52xx_MBAR_VIRT       0xf0000000      /* Virt address */
73 #define MPC52xx_MBAR_SIZE       0x00010000
74
75 #define MPC52xx_PA(x)           ((phys_addr_t)(MPC52xx_MBAR + (x)))
76 #define MPC52xx_VA(x)           ((void __iomem *)(MPC52xx_MBAR_VIRT + (x)))
77
78 /* Registers zone offset/size  */
79 #define MPC52xx_MMAP_CTL_OFFSET         0x0000
80 #define MPC52xx_MMAP_CTL_SIZE           0x068
81 #define MPC52xx_SDRAM_OFFSET            0x0100
82 #define MPC52xx_SDRAM_SIZE              0x010
83 #define MPC52xx_CDM_OFFSET              0x0200
84 #define MPC52xx_CDM_SIZE                0x038
85 #define MPC52xx_INTR_OFFSET             0x0500
86 #define MPC52xx_INTR_SIZE               0x04c
87 #define MPC52xx_GPTx_OFFSET(x)          (0x0600 + ((x)<<4))
88 #define MPC52xx_GPT_SIZE                0x010
89 #define MPC52xx_RTC_OFFSET              0x0800
90 #define MPC52xx_RTC_SIZE                0x024
91 #define MPC52xx_GPIO_OFFSET             0x0b00
92 #define MPC52xx_GPIO_SIZE               0x040
93 #define MPC52xx_GPIO_WKUP_OFFSET        0x0c00
94 #define MPC52xx_GPIO_WKUP_SIZE          0x028
95 #define MPC52xx_PCI_OFFSET              0x0d00
96 #define MPC52xx_PCI_SIZE                0x100
97 #define MPC52xx_SDMA_OFFSET             0x1200
98 #define MPC52xx_SDMA_SIZE               0x100
99 #define MPC52xx_XLB_OFFSET              0x1f00
100 #define MPC52xx_XLB_SIZE                0x100
101 #define MPC52xx_PSCx_OFFSET(x)          (((x)!=6)?(0x1e00+((x)<<9)):0x2c00)
102 #define MPC52xx_PSC_SIZE                0x0a0
103
104 /* SRAM used for SDMA */
105 #define MPC52xx_SRAM_OFFSET             0x8000
106 #define MPC52xx_SRAM_SIZE               0x4000
107
108
109 /* ======================================================================== */
110 /* IRQ mapping                                                              */
111 /* ======================================================================== */
112 /* Be sure to look at mpc52xx_pic.h if you wish for whatever reason to change
113  * this
114  */
115
116 #define MPC52xx_CRIT_IRQ_NUM    4
117 #define MPC52xx_MAIN_IRQ_NUM    17
118 #define MPC52xx_SDMA_IRQ_NUM    17
119 #define MPC52xx_PERP_IRQ_NUM    23
120
121 #define MPC52xx_CRIT_IRQ_BASE   1
122 #define MPC52xx_MAIN_IRQ_BASE   (MPC52xx_CRIT_IRQ_BASE + MPC52xx_CRIT_IRQ_NUM)
123 #define MPC52xx_SDMA_IRQ_BASE   (MPC52xx_MAIN_IRQ_BASE + MPC52xx_MAIN_IRQ_NUM)
124 #define MPC52xx_PERP_IRQ_BASE   (MPC52xx_SDMA_IRQ_BASE + MPC52xx_SDMA_IRQ_NUM)
125
126 #define MPC52xx_IRQ0                    (MPC52xx_CRIT_IRQ_BASE + 0)
127 #define MPC52xx_SLICE_TIMER_0_IRQ       (MPC52xx_CRIT_IRQ_BASE + 1)
128 #define MPC52xx_HI_INT_IRQ              (MPC52xx_CRIT_IRQ_BASE + 2)
129 #define MPC52xx_CCS_IRQ                 (MPC52xx_CRIT_IRQ_BASE + 3)
130
131 #define MPC52xx_IRQ1                    (MPC52xx_MAIN_IRQ_BASE + 1)
132 #define MPC52xx_IRQ2                    (MPC52xx_MAIN_IRQ_BASE + 2)
133 #define MPC52xx_IRQ3                    (MPC52xx_MAIN_IRQ_BASE + 3)
134
135 #define MPC52xx_SDMA_IRQ                (MPC52xx_PERP_IRQ_BASE + 0)
136 #define MPC52xx_PSC1_IRQ                (MPC52xx_PERP_IRQ_BASE + 1)
137 #define MPC52xx_PSC2_IRQ                (MPC52xx_PERP_IRQ_BASE + 2)
138 #define MPC52xx_PSC3_IRQ                (MPC52xx_PERP_IRQ_BASE + 3)
139 #define MPC52xx_PSC6_IRQ                (MPC52xx_PERP_IRQ_BASE + 4)
140 #define MPC52xx_IRDA_IRQ                (MPC52xx_PERP_IRQ_BASE + 4)
141 #define MPC52xx_FEC_IRQ                 (MPC52xx_PERP_IRQ_BASE + 5)
142 #define MPC52xx_USB_IRQ                 (MPC52xx_PERP_IRQ_BASE + 6)
143 #define MPC52xx_ATA_IRQ                 (MPC52xx_PERP_IRQ_BASE + 7)
144 #define MPC52xx_PCI_CNTRL_IRQ           (MPC52xx_PERP_IRQ_BASE + 8)
145 #define MPC52xx_PCI_SCIRX_IRQ           (MPC52xx_PERP_IRQ_BASE + 9)
146 #define MPC52xx_PCI_SCITX_IRQ           (MPC52xx_PERP_IRQ_BASE + 10)
147 #define MPC52xx_PSC4_IRQ                (MPC52xx_PERP_IRQ_BASE + 11)
148 #define MPC52xx_PSC5_IRQ                (MPC52xx_PERP_IRQ_BASE + 12)
149 #define MPC52xx_SPI_MODF_IRQ            (MPC52xx_PERP_IRQ_BASE + 13)
150 #define MPC52xx_SPI_SPIF_IRQ            (MPC52xx_PERP_IRQ_BASE + 14)
151 #define MPC52xx_I2C1_IRQ                (MPC52xx_PERP_IRQ_BASE + 15)
152 #define MPC52xx_I2C2_IRQ                (MPC52xx_PERP_IRQ_BASE + 16)
153 #define MPC52xx_MSCAN1_IRQ              (MPC52xx_PERP_IRQ_BASE + 17)
154 #define MPC52xx_MSCAN2_IRQ              (MPC52xx_PERP_IRQ_BASE + 18)
155 #define MPC52xx_IR_RX_IRQ               (MPC52xx_PERP_IRQ_BASE + 19)
156 #define MPC52xx_IR_TX_IRQ               (MPC52xx_PERP_IRQ_BASE + 20)
157 #define MPC52xx_XLB_ARB_IRQ             (MPC52xx_PERP_IRQ_BASE + 21)
158 #define MPC52xx_BDLC_IRQ                (MPC52xx_PERP_IRQ_BASE + 22)
159
160
161
162 /* ======================================================================== */
163 /* Structures mapping of some unit register set                             */
164 /* ======================================================================== */
165
166 #ifndef __ASSEMBLY__
167
168 /* Memory Mapping Control */
169 struct mpc52xx_mmap_ctl {
170         u32     mbar;           /* MMAP_CTRL + 0x00 */
171
172         u32     cs0_start;      /* MMAP_CTRL + 0x04 */
173         u32     cs0_stop;       /* MMAP_CTRL + 0x08 */
174         u32     cs1_start;      /* MMAP_CTRL + 0x0c */
175         u32     cs1_stop;       /* MMAP_CTRL + 0x10 */
176         u32     cs2_start;      /* MMAP_CTRL + 0x14 */
177         u32     cs2_stop;       /* MMAP_CTRL + 0x18 */
178         u32     cs3_start;      /* MMAP_CTRL + 0x1c */
179         u32     cs3_stop;       /* MMAP_CTRL + 0x20 */
180         u32     cs4_start;      /* MMAP_CTRL + 0x24 */
181         u32     cs4_stop;       /* MMAP_CTRL + 0x28 */
182         u32     cs5_start;      /* MMAP_CTRL + 0x2c */
183         u32     cs5_stop;       /* MMAP_CTRL + 0x30 */
184
185         u32     sdram0;         /* MMAP_CTRL + 0x34 */
186         u32     sdram1;         /* MMAP_CTRL + 0X38 */
187
188         u32     reserved[4];    /* MMAP_CTRL + 0x3c .. 0x48 */
189
190         u32     boot_start;     /* MMAP_CTRL + 0x4c */
191         u32     boot_stop;      /* MMAP_CTRL + 0x50 */
192
193         u32     ipbi_ws_ctrl;   /* MMAP_CTRL + 0x54 */
194
195         u32     cs6_start;      /* MMAP_CTRL + 0x58 */
196         u32     cs6_stop;       /* MMAP_CTRL + 0x5c */
197         u32     cs7_start;      /* MMAP_CTRL + 0x60 */
198         u32     cs7_stop;       /* MMAP_CTRL + 0x64 */
199 };
200
201 /* SDRAM control */
202 struct mpc52xx_sdram {
203         u32     mode;           /* SDRAM + 0x00 */
204         u32     ctrl;           /* SDRAM + 0x04 */
205         u32     config1;        /* SDRAM + 0x08 */
206         u32     config2;        /* SDRAM + 0x0c */
207 };
208
209 /* Interrupt controller */
210 struct mpc52xx_intr {
211         u32     per_mask;       /* INTR + 0x00 */
212         u32     per_pri1;       /* INTR + 0x04 */
213         u32     per_pri2;       /* INTR + 0x08 */
214         u32     per_pri3;       /* INTR + 0x0c */
215         u32     ctrl;           /* INTR + 0x10 */
216         u32     main_mask;      /* INTR + 0x14 */
217         u32     main_pri1;      /* INTR + 0x18 */
218         u32     main_pri2;      /* INTR + 0x1c */
219         u32     reserved1;      /* INTR + 0x20 */
220         u32     enc_status;     /* INTR + 0x24 */
221         u32     crit_status;    /* INTR + 0x28 */
222         u32     main_status;    /* INTR + 0x2c */
223         u32     per_status;     /* INTR + 0x30 */
224         u32     reserved2;      /* INTR + 0x34 */
225         u32     per_error;      /* INTR + 0x38 */
226 };
227
228 /* SDMA */
229 struct mpc52xx_sdma {
230         u32     taskBar;        /* SDMA + 0x00 */
231         u32     currentPointer; /* SDMA + 0x04 */
232         u32     endPointer;     /* SDMA + 0x08 */
233         u32     variablePointer;/* SDMA + 0x0c */
234
235         u8      IntVect1;       /* SDMA + 0x10 */
236         u8      IntVect2;       /* SDMA + 0x11 */
237         u16     PtdCntrl;       /* SDMA + 0x12 */
238
239         u32     IntPend;        /* SDMA + 0x14 */
240         u32     IntMask;        /* SDMA + 0x18 */
241
242         u16     tcr[16];        /* SDMA + 0x1c .. 0x3a */
243
244         u8      ipr[32];        /* SDMA + 0x3c .. 0x5b */
245
246         u32     cReqSelect;     /* SDMA + 0x5c */
247         u32     task_size0;     /* SDMA + 0x60 */
248         u32     task_size1;     /* SDMA + 0x64 */
249         u32     MDEDebug;       /* SDMA + 0x68 */
250         u32     ADSDebug;       /* SDMA + 0x6c */
251         u32     Value1;         /* SDMA + 0x70 */
252         u32     Value2;         /* SDMA + 0x74 */
253         u32     Control;        /* SDMA + 0x78 */
254         u32     Status;         /* SDMA + 0x7c */
255         u32     PTDDebug;       /* SDMA + 0x80 */
256 };
257
258 /* GPT */
259 struct mpc52xx_gpt {
260         u32     mode;           /* GPTx + 0x00 */
261         u32     count;          /* GPTx + 0x04 */
262         u32     pwm;            /* GPTx + 0x08 */
263         u32     status;         /* GPTx + 0X0c */
264 };
265
266 /* RTC */
267 struct mpc52xx_rtc {
268         u32     time_set;       /* RTC + 0x00 */
269         u32     date_set;       /* RTC + 0x04 */
270         u32     stopwatch;      /* RTC + 0x08 */
271         u32     int_enable;     /* RTC + 0x0c */
272         u32     time;           /* RTC + 0x10 */
273         u32     date;           /* RTC + 0x14 */
274         u32     stopwatch_intr; /* RTC + 0x18 */
275         u32     bus_error;      /* RTC + 0x1c */
276         u32     dividers;       /* RTC + 0x20 */
277 };
278
279 /* GPIO */
280 struct mpc52xx_gpio {
281         u32     port_config;    /* GPIO + 0x00 */
282         u32     simple_gpioe;   /* GPIO + 0x04 */
283         u32     simple_ode;     /* GPIO + 0x08 */
284         u32     simple_ddr;     /* GPIO + 0x0c */
285         u32     simple_dvo;     /* GPIO + 0x10 */
286         u32     simple_ival;    /* GPIO + 0x14 */
287         u8      outo_gpioe;     /* GPIO + 0x18 */
288         u8      reserved1[3];   /* GPIO + 0x19 */
289         u8      outo_dvo;       /* GPIO + 0x1c */
290         u8      reserved2[3];   /* GPIO + 0x1d */
291         u8      sint_gpioe;     /* GPIO + 0x20 */
292         u8      reserved3[3];   /* GPIO + 0x21 */
293         u8      sint_ode;       /* GPIO + 0x24 */
294         u8      reserved4[3];   /* GPIO + 0x25 */
295         u8      sint_ddr;       /* GPIO + 0x28 */
296         u8      reserved5[3];   /* GPIO + 0x29 */
297         u8      sint_dvo;       /* GPIO + 0x2c */
298         u8      reserved6[3];   /* GPIO + 0x2d */
299         u8      sint_inten;     /* GPIO + 0x30 */
300         u8      reserved7[3];   /* GPIO + 0x31 */
301         u16     sint_itype;     /* GPIO + 0x34 */
302         u16     reserved8;      /* GPIO + 0x36 */
303         u8      gpio_control;   /* GPIO + 0x38 */
304         u8      reserved9[3];   /* GPIO + 0x39 */
305         u8      sint_istat;     /* GPIO + 0x3c */
306         u8      sint_ival;      /* GPIO + 0x3d */
307         u8      bus_errs;       /* GPIO + 0x3e */
308         u8      reserved10;     /* GPIO + 0x3f */
309 };
310
311 #define MPC52xx_GPIO_PSC_CONFIG_UART_WITHOUT_CD 4
312 #define MPC52xx_GPIO_PSC_CONFIG_UART_WITH_CD    5
313 #define MPC52xx_GPIO_PCI_DIS                    (1<<15)
314
315 /* GPIO with WakeUp*/
316 struct mpc52xx_gpio_wkup {
317         u8      wkup_gpioe;     /* GPIO_WKUP + 0x00 */
318         u8      reserved1[3];   /* GPIO_WKUP + 0x03 */
319         u8      wkup_ode;       /* GPIO_WKUP + 0x04 */
320         u8      reserved2[3];   /* GPIO_WKUP + 0x05 */
321         u8      wkup_ddr;       /* GPIO_WKUP + 0x08 */
322         u8      reserved3[3];   /* GPIO_WKUP + 0x09 */
323         u8      wkup_dvo;       /* GPIO_WKUP + 0x0C */
324         u8      reserved4[3];   /* GPIO_WKUP + 0x0D */
325         u8      wkup_inten;     /* GPIO_WKUP + 0x10 */
326         u8      reserved5[3];   /* GPIO_WKUP + 0x11 */
327         u8      wkup_iinten;    /* GPIO_WKUP + 0x14 */
328         u8      reserved6[3];   /* GPIO_WKUP + 0x15 */
329         u16     wkup_itype;     /* GPIO_WKUP + 0x18 */
330         u8      reserved7[2];   /* GPIO_WKUP + 0x1A */
331         u8      wkup_maste;     /* GPIO_WKUP + 0x1C */
332         u8      reserved8[3];   /* GPIO_WKUP + 0x1D */
333         u8      wkup_ival;      /* GPIO_WKUP + 0x20 */
334         u8      reserved9[3];   /* GPIO_WKUP + 0x21 */
335         u8      wkup_istat;     /* GPIO_WKUP + 0x24 */
336         u8      reserved10[3];  /* GPIO_WKUP + 0x25 */
337 };
338
339 /* XLB Bus control */
340 struct mpc52xx_xlb {
341         u8      reserved[0x40];
342         u32     config;                 /* XLB + 0x40 */
343         u32     version;                /* XLB + 0x44 */
344         u32     status;                 /* XLB + 0x48 */
345         u32     int_enable;             /* XLB + 0x4c */
346         u32     addr_capture;           /* XLB + 0x50 */
347         u32     bus_sig_capture;        /* XLB + 0x54 */
348         u32     addr_timeout;           /* XLB + 0x58 */
349         u32     data_timeout;           /* XLB + 0x5c */
350         u32     bus_act_timeout;        /* XLB + 0x60 */
351         u32     master_pri_enable;      /* XLB + 0x64 */
352         u32     master_priority;        /* XLB + 0x68 */
353         u32     base_address;           /* XLB + 0x6c */
354         u32     snoop_window;           /* XLB + 0x70 */
355 };
356
357 #define MPC52xx_XLB_CFG_SNOOP           (1 << 15)
358
359 /* Clock Distribution control */
360 struct mpc52xx_cdm {
361         u32     jtag_id;                /* CDM + 0x00  reg0 read only */
362         u32     rstcfg;                 /* CDM + 0x04  reg1 read only */
363         u32     breadcrumb;             /* CDM + 0x08  reg2 */
364
365         u8      mem_clk_sel;            /* CDM + 0x0c  reg3 byte0 */
366         u8      xlb_clk_sel;            /* CDM + 0x0d  reg3 byte1 read only */
367         u8      ipb_clk_sel;            /* CDM + 0x0e  reg3 byte2 */
368         u8      pci_clk_sel;            /* CDM + 0x0f  reg3 byte3 */
369
370         u8      ext_48mhz_en;           /* CDM + 0x10  reg4 byte0 */
371         u8      fd_enable;              /* CDM + 0x11  reg4 byte1 */
372         u16     fd_counters;            /* CDM + 0x12  reg4 byte2,3 */
373
374         u32     clk_enables;            /* CDM + 0x14  reg5 */
375
376         u8      osc_disable;            /* CDM + 0x18  reg6 byte0 */
377         u8      reserved0[3];           /* CDM + 0x19  reg6 byte1,2,3 */
378
379         u8      ccs_sleep_enable;       /* CDM + 0x1c  reg7 byte0 */
380         u8      osc_sleep_enable;       /* CDM + 0x1d  reg7 byte1 */
381         u8      reserved1;              /* CDM + 0x1e  reg7 byte2 */
382         u8      ccs_qreq_test;          /* CDM + 0x1f  reg7 byte3 */
383
384         u8      soft_reset;             /* CDM + 0x20  u8 byte0 */
385         u8      no_ckstp;               /* CDM + 0x21  u8 byte0 */
386         u8      reserved2[2];           /* CDM + 0x22  u8 byte1,2,3 */
387
388         u8      pll_lock;               /* CDM + 0x24  reg9 byte0 */
389         u8      pll_looselock;          /* CDM + 0x25  reg9 byte1 */
390         u8      pll_sm_lockwin;         /* CDM + 0x26  reg9 byte2 */
391         u8      reserved3;              /* CDM + 0x27  reg9 byte3 */
392
393         u16     reserved4;              /* CDM + 0x28  reg10 byte0,1 */
394         u16     mclken_div_psc1;        /* CDM + 0x2a  reg10 byte2,3 */
395
396         u16     reserved5;              /* CDM + 0x2c  reg11 byte0,1 */
397         u16     mclken_div_psc2;        /* CDM + 0x2e  reg11 byte2,3 */
398
399         u16     reserved6;              /* CDM + 0x30  reg12 byte0,1 */
400         u16     mclken_div_psc3;        /* CDM + 0x32  reg12 byte2,3 */
401
402         u16     reserved7;              /* CDM + 0x34  reg13 byte0,1 */
403         u16     mclken_div_psc6;        /* CDM + 0x36  reg13 byte2,3 */
404 };
405
406 #endif /* __ASSEMBLY__ */
407
408
409 /* ========================================================================= */
410 /* Prototypes for MPC52xx syslib                                             */
411 /* ========================================================================= */
412
413 #ifndef __ASSEMBLY__
414
415 extern void mpc52xx_init_irq(void);
416 extern int mpc52xx_get_irq(struct pt_regs *regs);
417
418 extern unsigned long mpc52xx_find_end_of_memory(void);
419 extern void mpc52xx_set_bat(void);
420 extern void mpc52xx_map_io(void);
421 extern void mpc52xx_restart(char *cmd);
422 extern void mpc52xx_halt(void);
423 extern void mpc52xx_power_off(void);
424 extern void mpc52xx_progress(char *s, unsigned short hex);
425 extern void mpc52xx_calibrate_decr(void);
426
427 extern void mpc52xx_find_bridges(void);
428
429
430         /* Matching of PSC function */
431 struct mpc52xx_psc_func {
432         int id;
433         char *func;
434 };
435
436 extern int mpc52xx_match_psc_function(int psc_idx, const char *func);
437 extern struct  mpc52xx_psc_func mpc52xx_psc_functions[];
438         /* This array is to be defined in platform file */
439
440 #endif /* __ASSEMBLY__ */
441
442
443 /* ========================================================================= */
444 /* Platform configuration                                                    */
445 /* ========================================================================= */
446
447 /* The U-Boot platform information struct */
448 extern bd_t __res;
449
450 /* Platform options */
451 #if defined(CONFIG_LITE5200)
452 #include <platforms/lite5200.h>
453 #endif
454
455
456 #endif /* __ASM_MPC52xx_H__ */