2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
43 #include <linux/version.h>
44 #include <linux/module.h>
45 #include <linux/delay.h>
47 #include <linux/netdevice.h>
48 #include <linux/cache.h>
49 #include <linux/pci.h>
50 #include <linux/ethtool.h>
51 #include <linux/uaccess.h>
53 #include <net/ieee80211_radiotap.h>
55 #include <asm/unaligned.h>
66 static int ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
74 MODULE_AUTHOR("Jiri Slaby");
75 MODULE_AUTHOR("Nick Kossifidis");
76 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
77 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
78 MODULE_LICENSE("Dual BSD/GPL");
79 MODULE_VERSION("0.5.0 (EXPERIMENTAL)");
83 static struct pci_device_id ath5k_pci_id_table[] __devinitdata = {
84 { PCI_VDEVICE(ATHEROS, 0x0207), .driver_data = AR5K_AR5210 }, /* 5210 early */
85 { PCI_VDEVICE(ATHEROS, 0x0007), .driver_data = AR5K_AR5210 }, /* 5210 */
86 { PCI_VDEVICE(ATHEROS, 0x0011), .driver_data = AR5K_AR5211 }, /* 5311 - this is on AHB bus !*/
87 { PCI_VDEVICE(ATHEROS, 0x0012), .driver_data = AR5K_AR5211 }, /* 5211 */
88 { PCI_VDEVICE(ATHEROS, 0x0013), .driver_data = AR5K_AR5212 }, /* 5212 */
89 { PCI_VDEVICE(3COM_2, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 5212 */
90 { PCI_VDEVICE(3COM, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 3CRDAG675 5212 */
91 { PCI_VDEVICE(ATHEROS, 0x1014), .driver_data = AR5K_AR5212 }, /* IBM minipci 5212 */
92 { PCI_VDEVICE(ATHEROS, 0x0014), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
93 { PCI_VDEVICE(ATHEROS, 0x0015), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
94 { PCI_VDEVICE(ATHEROS, 0x0016), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
95 { PCI_VDEVICE(ATHEROS, 0x0017), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
96 { PCI_VDEVICE(ATHEROS, 0x0018), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
97 { PCI_VDEVICE(ATHEROS, 0x0019), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
98 { PCI_VDEVICE(ATHEROS, 0x001a), .driver_data = AR5K_AR5212 }, /* 2413 Griffin-lite */
99 { PCI_VDEVICE(ATHEROS, 0x001b), .driver_data = AR5K_AR5212 }, /* 5413 Eagle */
100 { PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* 5424 Condor (PCI-E)*/
101 { PCI_VDEVICE(ATHEROS, 0x0023), .driver_data = AR5K_AR5212 }, /* 5416 */
102 { PCI_VDEVICE(ATHEROS, 0x0024), .driver_data = AR5K_AR5212 }, /* 5418 */
105 MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
108 static struct ath5k_srev_name srev_names[] = {
109 { "5210", AR5K_VERSION_VER, AR5K_SREV_VER_AR5210 },
110 { "5311", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311 },
111 { "5311A", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311A },
112 { "5311B", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311B },
113 { "5211", AR5K_VERSION_VER, AR5K_SREV_VER_AR5211 },
114 { "5212", AR5K_VERSION_VER, AR5K_SREV_VER_AR5212 },
115 { "5213", AR5K_VERSION_VER, AR5K_SREV_VER_AR5213 },
116 { "5213A", AR5K_VERSION_VER, AR5K_SREV_VER_AR5213A },
117 { "2413", AR5K_VERSION_VER, AR5K_SREV_VER_AR2413 },
118 { "2414", AR5K_VERSION_VER, AR5K_SREV_VER_AR2414 },
119 { "2424", AR5K_VERSION_VER, AR5K_SREV_VER_AR2424 },
120 { "5424", AR5K_VERSION_VER, AR5K_SREV_VER_AR5424 },
121 { "5413", AR5K_VERSION_VER, AR5K_SREV_VER_AR5413 },
122 { "5414", AR5K_VERSION_VER, AR5K_SREV_VER_AR5414 },
123 { "5416", AR5K_VERSION_VER, AR5K_SREV_VER_AR5416 },
124 { "5418", AR5K_VERSION_VER, AR5K_SREV_VER_AR5418 },
125 { "2425", AR5K_VERSION_VER, AR5K_SREV_VER_AR2425 },
126 { "xxxxx", AR5K_VERSION_VER, AR5K_SREV_UNKNOWN },
127 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
128 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
129 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
130 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
131 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
132 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
133 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
134 { "SChip", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC0 },
135 { "SChip", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC1 },
136 { "SChip", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC2 },
137 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
138 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
142 * Prototypes - PCI stack related functions
144 static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
145 const struct pci_device_id *id);
146 static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
148 static int ath5k_pci_suspend(struct pci_dev *pdev,
150 static int ath5k_pci_resume(struct pci_dev *pdev);
152 #define ath5k_pci_suspend NULL
153 #define ath5k_pci_resume NULL
154 #endif /* CONFIG_PM */
156 static struct pci_driver ath5k_pci_driver = {
158 .id_table = ath5k_pci_id_table,
159 .probe = ath5k_pci_probe,
160 .remove = __devexit_p(ath5k_pci_remove),
161 .suspend = ath5k_pci_suspend,
162 .resume = ath5k_pci_resume,
168 * Prototypes - MAC 802.11 stack related functions
170 static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
171 struct ieee80211_tx_control *ctl);
172 static int ath5k_reset(struct ieee80211_hw *hw);
173 static int ath5k_start(struct ieee80211_hw *hw);
174 static void ath5k_stop(struct ieee80211_hw *hw);
175 static int ath5k_add_interface(struct ieee80211_hw *hw,
176 struct ieee80211_if_init_conf *conf);
177 static void ath5k_remove_interface(struct ieee80211_hw *hw,
178 struct ieee80211_if_init_conf *conf);
179 static int ath5k_config(struct ieee80211_hw *hw,
180 struct ieee80211_conf *conf);
181 static int ath5k_config_interface(struct ieee80211_hw *hw,
182 struct ieee80211_vif *vif,
183 struct ieee80211_if_conf *conf);
184 static void ath5k_configure_filter(struct ieee80211_hw *hw,
185 unsigned int changed_flags,
186 unsigned int *new_flags,
187 int mc_count, struct dev_mc_list *mclist);
188 static int ath5k_set_key(struct ieee80211_hw *hw,
189 enum set_key_cmd cmd,
190 const u8 *local_addr, const u8 *addr,
191 struct ieee80211_key_conf *key);
192 static int ath5k_get_stats(struct ieee80211_hw *hw,
193 struct ieee80211_low_level_stats *stats);
194 static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
195 struct ieee80211_tx_queue_stats *stats);
196 static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
197 static void ath5k_reset_tsf(struct ieee80211_hw *hw);
198 static int ath5k_beacon_update(struct ieee80211_hw *hw,
200 struct ieee80211_tx_control *ctl);
202 static struct ieee80211_ops ath5k_hw_ops = {
204 .start = ath5k_start,
206 .add_interface = ath5k_add_interface,
207 .remove_interface = ath5k_remove_interface,
208 .config = ath5k_config,
209 .config_interface = ath5k_config_interface,
210 .configure_filter = ath5k_configure_filter,
211 .set_key = ath5k_set_key,
212 .get_stats = ath5k_get_stats,
214 .get_tx_stats = ath5k_get_tx_stats,
215 .get_tsf = ath5k_get_tsf,
216 .reset_tsf = ath5k_reset_tsf,
217 .beacon_update = ath5k_beacon_update,
221 * Prototypes - Internal functions
224 static int ath5k_attach(struct pci_dev *pdev,
225 struct ieee80211_hw *hw);
226 static void ath5k_detach(struct pci_dev *pdev,
227 struct ieee80211_hw *hw);
228 /* Channel/mode setup */
229 static inline short ath5k_ieee2mhz(short chan);
230 static unsigned int ath5k_copy_rates(struct ieee80211_rate *rates,
231 const struct ath5k_rate_table *rt,
233 static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
234 struct ieee80211_channel *channels,
237 static int ath5k_getchannels(struct ieee80211_hw *hw);
238 static int ath5k_chan_set(struct ath5k_softc *sc,
239 struct ieee80211_channel *chan);
240 static void ath5k_setcurmode(struct ath5k_softc *sc,
242 static void ath5k_mode_setup(struct ath5k_softc *sc);
243 static void ath5k_set_total_hw_rates(struct ath5k_softc *sc);
245 /* Descriptor setup */
246 static int ath5k_desc_alloc(struct ath5k_softc *sc,
247 struct pci_dev *pdev);
248 static void ath5k_desc_free(struct ath5k_softc *sc,
249 struct pci_dev *pdev);
251 static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
252 struct ath5k_buf *bf);
253 static int ath5k_txbuf_setup(struct ath5k_softc *sc,
254 struct ath5k_buf *bf,
255 struct ieee80211_tx_control *ctl);
257 static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
258 struct ath5k_buf *bf)
263 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
265 dev_kfree_skb(bf->skb);
270 static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
271 int qtype, int subtype);
272 static int ath5k_beaconq_setup(struct ath5k_hw *ah);
273 static int ath5k_beaconq_config(struct ath5k_softc *sc);
274 static void ath5k_txq_drainq(struct ath5k_softc *sc,
275 struct ath5k_txq *txq);
276 static void ath5k_txq_cleanup(struct ath5k_softc *sc);
277 static void ath5k_txq_release(struct ath5k_softc *sc);
279 static int ath5k_rx_start(struct ath5k_softc *sc);
280 static void ath5k_rx_stop(struct ath5k_softc *sc);
281 static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
282 struct ath5k_desc *ds,
284 struct ath5k_rx_status *rs);
285 static void ath5k_tasklet_rx(unsigned long data);
287 static void ath5k_tx_processq(struct ath5k_softc *sc,
288 struct ath5k_txq *txq);
289 static void ath5k_tasklet_tx(unsigned long data);
290 /* Beacon handling */
291 static int ath5k_beacon_setup(struct ath5k_softc *sc,
292 struct ath5k_buf *bf,
293 struct ieee80211_tx_control *ctl);
294 static void ath5k_beacon_send(struct ath5k_softc *sc);
295 static void ath5k_beacon_config(struct ath5k_softc *sc);
296 static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
298 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
300 u64 tsf = ath5k_hw_get_tsf64(ah);
302 if ((tsf & 0x7fff) < rstamp)
305 return (tsf & ~0x7fff) | rstamp;
308 /* Interrupt handling */
309 static int ath5k_init(struct ath5k_softc *sc);
310 static int ath5k_stop_locked(struct ath5k_softc *sc);
311 static int ath5k_stop_hw(struct ath5k_softc *sc);
312 static irqreturn_t ath5k_intr(int irq, void *dev_id);
313 static void ath5k_tasklet_reset(unsigned long data);
315 static void ath5k_calibrate(unsigned long data);
317 static void ath5k_led_off(unsigned long data);
318 static void ath5k_led_blink(struct ath5k_softc *sc,
321 static void ath5k_led_event(struct ath5k_softc *sc,
326 * Module init/exit functions
335 ret = pci_register_driver(&ath5k_pci_driver);
337 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
347 pci_unregister_driver(&ath5k_pci_driver);
349 ath5k_debug_finish();
352 module_init(init_ath5k_pci);
353 module_exit(exit_ath5k_pci);
356 /********************\
357 * PCI Initialization *
358 \********************/
361 ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
363 const char *name = "xxxxx";
366 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
367 if (srev_names[i].sr_type != type)
369 if ((val & 0xff) < srev_names[i + 1].sr_val) {
370 name = srev_names[i].sr_name;
379 ath5k_pci_probe(struct pci_dev *pdev,
380 const struct pci_device_id *id)
383 struct ath5k_softc *sc;
384 struct ieee80211_hw *hw;
388 ret = pci_enable_device(pdev);
390 dev_err(&pdev->dev, "can't enable device\n");
394 /* XXX 32-bit addressing only */
395 ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
397 dev_err(&pdev->dev, "32-bit DMA not available\n");
402 * Cache line size is used to size and align various
403 * structures used to communicate with the hardware.
405 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
408 * Linux 2.4.18 (at least) writes the cache line size
409 * register as a 16-bit wide register which is wrong.
410 * We must have this setup properly for rx buffer
411 * DMA to work so force a reasonable value here if it
414 csz = L1_CACHE_BYTES / sizeof(u32);
415 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
418 * The default setting of latency timer yields poor results,
419 * set it to the value used by other systems. It may be worth
420 * tweaking this setting more.
422 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
424 /* Enable bus mastering */
425 pci_set_master(pdev);
428 * Disable the RETRY_TIMEOUT register (0x41) to keep
429 * PCI Tx retries from interfering with C3 CPU state.
431 pci_write_config_byte(pdev, 0x41, 0);
433 ret = pci_request_region(pdev, 0, "ath5k");
435 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
439 mem = pci_iomap(pdev, 0, 0);
441 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
447 * Allocate hw (mac80211 main struct)
448 * and hw->priv (driver private data)
450 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
452 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
457 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
459 /* Initialize driver private data */
460 SET_IEEE80211_DEV(hw, &pdev->dev);
461 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS;
462 hw->extra_tx_headroom = 2;
463 hw->channel_change_time = 5000;
464 /* these names are misleading */
465 hw->max_rssi = -110; /* signal in dBm */
466 hw->max_noise = -110; /* noise in dBm */
467 hw->max_signal = 100; /* we will provide a percentage based on rssi */
472 ath5k_debug_init_device(sc);
475 * Mark the device as detached to avoid processing
476 * interrupts until setup is complete.
478 __set_bit(ATH_STAT_INVALID, sc->status);
480 sc->iobase = mem; /* So we can unmap it on detach */
481 sc->cachelsz = csz * sizeof(u32); /* convert to bytes */
482 sc->opmode = IEEE80211_IF_TYPE_STA;
483 mutex_init(&sc->lock);
484 spin_lock_init(&sc->rxbuflock);
485 spin_lock_init(&sc->txbuflock);
487 /* Set private data */
488 pci_set_drvdata(pdev, hw);
490 /* Enable msi for devices that support it */
491 pci_enable_msi(pdev);
493 /* Setup interrupt handler */
494 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
496 ATH5K_ERR(sc, "request_irq failed\n");
500 /* Initialize device */
501 sc->ah = ath5k_hw_attach(sc, id->driver_data);
502 if (IS_ERR(sc->ah)) {
503 ret = PTR_ERR(sc->ah);
507 /* Finish private driver data initialization */
508 ret = ath5k_attach(pdev, hw);
512 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
513 ath5k_chip_name(AR5K_VERSION_VER,sc->ah->ah_mac_srev),
515 sc->ah->ah_phy_revision);
517 if (!sc->ah->ah_single_chip) {
518 /* Single chip radio (!RF5111) */
519 if (sc->ah->ah_radio_5ghz_revision &&
520 !sc->ah->ah_radio_2ghz_revision) {
521 /* No 5GHz support -> report 2GHz radio */
522 if (!test_bit(AR5K_MODE_11A,
523 sc->ah->ah_capabilities.cap_mode)) {
524 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
525 ath5k_chip_name(AR5K_VERSION_RAD,
526 sc->ah->ah_radio_5ghz_revision),
527 sc->ah->ah_radio_5ghz_revision);
528 /* No 2GHz support (5110 and some
529 * 5Ghz only cards) -> report 5Ghz radio */
530 } else if (!test_bit(AR5K_MODE_11B,
531 sc->ah->ah_capabilities.cap_mode)) {
532 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
533 ath5k_chip_name(AR5K_VERSION_RAD,
534 sc->ah->ah_radio_5ghz_revision),
535 sc->ah->ah_radio_5ghz_revision);
536 /* Multiband radio */
538 ATH5K_INFO(sc, "RF%s multiband radio found"
540 ath5k_chip_name(AR5K_VERSION_RAD,
541 sc->ah->ah_radio_5ghz_revision),
542 sc->ah->ah_radio_5ghz_revision);
545 /* Multi chip radio (RF5111 - RF2111) ->
546 * report both 2GHz/5GHz radios */
547 else if (sc->ah->ah_radio_5ghz_revision &&
548 sc->ah->ah_radio_2ghz_revision){
549 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
550 ath5k_chip_name(AR5K_VERSION_RAD,
551 sc->ah->ah_radio_5ghz_revision),
552 sc->ah->ah_radio_5ghz_revision);
553 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
554 ath5k_chip_name(AR5K_VERSION_RAD,
555 sc->ah->ah_radio_2ghz_revision),
556 sc->ah->ah_radio_2ghz_revision);
561 /* ready to process interrupts */
562 __clear_bit(ATH_STAT_INVALID, sc->status);
566 ath5k_hw_detach(sc->ah);
568 free_irq(pdev->irq, sc);
570 pci_disable_msi(pdev);
571 ieee80211_free_hw(hw);
573 pci_iounmap(pdev, mem);
575 pci_release_region(pdev, 0);
577 pci_disable_device(pdev);
582 static void __devexit
583 ath5k_pci_remove(struct pci_dev *pdev)
585 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
586 struct ath5k_softc *sc = hw->priv;
588 ath5k_debug_finish_device(sc);
589 ath5k_detach(pdev, hw);
590 ath5k_hw_detach(sc->ah);
591 free_irq(pdev->irq, sc);
592 pci_disable_msi(pdev);
593 pci_iounmap(pdev, sc->iobase);
594 pci_release_region(pdev, 0);
595 pci_disable_device(pdev);
596 ieee80211_free_hw(hw);
601 ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state)
603 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
604 struct ath5k_softc *sc = hw->priv;
606 if (test_bit(ATH_STAT_LEDSOFT, sc->status))
607 ath5k_hw_set_gpio(sc->ah, sc->led_pin, 1);
610 pci_save_state(pdev);
611 pci_disable_device(pdev);
612 pci_set_power_state(pdev, PCI_D3hot);
618 ath5k_pci_resume(struct pci_dev *pdev)
620 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
621 struct ath5k_softc *sc = hw->priv;
622 struct ath5k_hw *ah = sc->ah;
625 err = pci_set_power_state(pdev, PCI_D0);
629 err = pci_enable_device(pdev);
633 pci_restore_state(pdev);
635 * Suspend/Resume resets the PCI configuration space, so we have to
636 * re-disable the RETRY_TIMEOUT register (0x41) to keep
637 * PCI Tx retries from interfering with C3 CPU state
639 pci_write_config_byte(pdev, 0x41, 0);
642 if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
643 ath5k_hw_set_gpio_output(ah, sc->led_pin);
644 ath5k_hw_set_gpio(ah, sc->led_pin, 0);
648 * Reset the key cache since some parts do not
649 * reset the contents on initial power up or resume.
651 * FIXME: This may need to be revisited when mac80211 becomes
652 * aware of suspend/resume.
654 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
655 ath5k_hw_reset_key(ah, i);
659 #endif /* CONFIG_PM */
663 /***********************\
664 * Driver Initialization *
665 \***********************/
668 ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
670 struct ath5k_softc *sc = hw->priv;
671 struct ath5k_hw *ah = sc->ah;
676 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
679 * Check if the MAC has multi-rate retry support.
680 * We do this by trying to setup a fake extended
681 * descriptor. MAC's that don't have support will
682 * return false w/o doing anything. MAC's that do
683 * support it will return true w/o doing anything.
685 ret = ah->ah_setup_xtx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
689 __set_bit(ATH_STAT_MRRETRY, sc->status);
692 * Reset the key cache since some parts do not
693 * reset the contents on initial power up.
695 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
696 ath5k_hw_reset_key(ah, i);
699 * Collect the channel list. The 802.11 layer
700 * is resposible for filtering this list based
701 * on settings like the phy mode and regulatory
702 * domain restrictions.
704 ret = ath5k_getchannels(hw);
706 ATH5K_ERR(sc, "can't get channels\n");
710 /* Set *_rates so we can map hw rate index */
711 ath5k_set_total_hw_rates(sc);
713 /* NB: setup here so ath5k_rate_update is happy */
714 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
715 ath5k_setcurmode(sc, AR5K_MODE_11A);
717 ath5k_setcurmode(sc, AR5K_MODE_11B);
720 * Allocate tx+rx descriptors and populate the lists.
722 ret = ath5k_desc_alloc(sc, pdev);
724 ATH5K_ERR(sc, "can't allocate descriptors\n");
729 * Allocate hardware transmit queues: one queue for
730 * beacon frames and one data queue for each QoS
731 * priority. Note that hw functions handle reseting
732 * these queues at the needed time.
734 ret = ath5k_beaconq_setup(ah);
736 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
741 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
742 if (IS_ERR(sc->txq)) {
743 ATH5K_ERR(sc, "can't setup xmit queue\n");
744 ret = PTR_ERR(sc->txq);
748 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
749 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
750 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
751 setup_timer(&sc->calib_tim, ath5k_calibrate, (unsigned long)sc);
752 setup_timer(&sc->led_tim, ath5k_led_off, (unsigned long)sc);
754 sc->led_on = 0; /* low true */
756 * Auto-enable soft led processing for IBM cards and for
757 * 5211 minipci cards.
759 if (pdev->device == PCI_DEVICE_ID_ATHEROS_AR5212_IBM ||
760 pdev->device == PCI_DEVICE_ID_ATHEROS_AR5211) {
761 __set_bit(ATH_STAT_LEDSOFT, sc->status);
764 /* Enable softled on PIN1 on HP Compaq nc6xx, nc4000 & nx5000 laptops */
765 if (pdev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ) {
766 __set_bit(ATH_STAT_LEDSOFT, sc->status);
769 if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
770 ath5k_hw_set_gpio_output(ah, sc->led_pin);
771 ath5k_hw_set_gpio(ah, sc->led_pin, !sc->led_on);
774 ath5k_hw_get_lladdr(ah, mac);
775 SET_IEEE80211_PERM_ADDR(hw, mac);
776 /* All MAC address bits matter for ACKs */
777 memset(sc->bssidmask, 0xff, ETH_ALEN);
778 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
780 ret = ieee80211_register_hw(hw);
782 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
788 ath5k_txq_release(sc);
790 ath5k_hw_release_tx_queue(ah, sc->bhalq);
792 ath5k_desc_free(sc, pdev);
798 ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
800 struct ath5k_softc *sc = hw->priv;
803 * NB: the order of these is important:
804 * o call the 802.11 layer before detaching ath5k_hw to
805 * insure callbacks into the driver to delete global
806 * key cache entries can be handled
807 * o reclaim the tx queue data structures after calling
808 * the 802.11 layer as we'll get called back to reclaim
809 * node state and potentially want to use them
810 * o to cleanup the tx queues the hal is called, so detach
812 * XXX: ??? detach ath5k_hw ???
813 * Other than that, it's straightforward...
815 ieee80211_unregister_hw(hw);
816 ath5k_desc_free(sc, pdev);
817 ath5k_txq_release(sc);
818 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
821 * NB: can't reclaim these until after ieee80211_ifdetach
822 * returns because we'll get called back to reclaim node
823 * state and potentially want to use them.
830 /********************\
831 * Channel/mode setup *
832 \********************/
835 * Convert IEEE channel number to MHz frequency.
838 ath5k_ieee2mhz(short chan)
840 if (chan <= 14 || chan >= 27)
841 return ieee80211chan2mhz(chan);
843 return 2212 + chan * 20;
847 ath5k_copy_rates(struct ieee80211_rate *rates,
848 const struct ath5k_rate_table *rt,
851 unsigned int i, count;
856 for (i = 0, count = 0; i < rt->rate_count && max > 0; i++) {
857 rates[count].bitrate = rt->rates[i].rate_kbps / 100;
858 rates[count].hw_value = rt->rates[i].rate_code;
859 rates[count].flags = rt->rates[i].modulation;
868 ath5k_copy_channels(struct ath5k_hw *ah,
869 struct ieee80211_channel *channels,
873 unsigned int i, count, size, chfreq, freq, ch;
875 if (!test_bit(mode, ah->ah_modes))
880 case AR5K_MODE_11A_TURBO:
881 /* 1..220, but 2GHz frequencies are filtered by check_channel */
883 chfreq = CHANNEL_5GHZ;
887 case AR5K_MODE_11G_TURBO:
889 chfreq = CHANNEL_2GHZ;
892 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
896 for (i = 0, count = 0; i < size && max > 0; i++) {
898 freq = ath5k_ieee2mhz(ch);
900 /* Check if channel is supported by the chipset */
901 if (!ath5k_channel_ok(ah, freq, chfreq))
904 /* Write channel info and increment counter */
905 channels[count].center_freq = freq;
906 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
907 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
911 channels[count].hw_value = chfreq | CHANNEL_OFDM;
913 case AR5K_MODE_11A_TURBO:
914 case AR5K_MODE_11G_TURBO:
915 channels[count].hw_value = chfreq |
916 CHANNEL_OFDM | CHANNEL_TURBO;
919 channels[count].hw_value = CHANNEL_B;
930 ath5k_getchannels(struct ieee80211_hw *hw)
932 struct ath5k_softc *sc = hw->priv;
933 struct ath5k_hw *ah = sc->ah;
934 struct ieee80211_supported_band *sbands = sc->sbands;
935 const struct ath5k_rate_table *hw_rates;
936 unsigned int max_r, max_c, count_r, count_c;
937 int mode2g = AR5K_MODE_11G;
939 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
941 max_r = ARRAY_SIZE(sc->rates);
942 max_c = ARRAY_SIZE(sc->channels);
943 count_r = count_c = 0;
946 if (!test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
947 mode2g = AR5K_MODE_11B;
948 if (!test_bit(AR5K_MODE_11B,
949 sc->ah->ah_capabilities.cap_mode))
954 struct ieee80211_supported_band *sband =
955 &sbands[IEEE80211_BAND_2GHZ];
957 sband->bitrates = sc->rates;
958 sband->channels = sc->channels;
960 sband->band = IEEE80211_BAND_2GHZ;
961 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
964 hw_rates = ath5k_hw_get_rate_table(ah, mode2g);
965 sband->n_bitrates = ath5k_copy_rates(sband->bitrates,
968 count_c = sband->n_channels;
969 count_r = sband->n_bitrates;
971 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
980 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
981 struct ieee80211_supported_band *sband =
982 &sbands[IEEE80211_BAND_5GHZ];
984 sband->bitrates = &sc->rates[count_r];
985 sband->channels = &sc->channels[count_c];
987 sband->band = IEEE80211_BAND_5GHZ;
988 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
989 AR5K_MODE_11A, max_c);
991 hw_rates = ath5k_hw_get_rate_table(ah, AR5K_MODE_11A);
992 sband->n_bitrates = ath5k_copy_rates(sband->bitrates,
995 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
998 ath5k_debug_dump_bands(sc);
1004 * Set/change channels. If the channel is really being changed,
1005 * it's done by reseting the chip. To accomplish this we must
1006 * first cleanup any pending DMA, then restart stuff after a la
1010 ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1012 struct ath5k_hw *ah = sc->ah;
1015 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
1016 sc->curchan->center_freq, chan->center_freq);
1018 if (chan->center_freq != sc->curchan->center_freq ||
1019 chan->hw_value != sc->curchan->hw_value) {
1022 sc->curband = &sc->sbands[chan->band];
1025 * To switch channels clear any pending DMA operations;
1026 * wait long enough for the RX fifo to drain, reset the
1027 * hardware at the new frequency, and then re-enable
1028 * the relevant bits of the h/w.
1030 ath5k_hw_set_intr(ah, 0); /* disable interrupts */
1031 ath5k_txq_cleanup(sc); /* clear pending tx frames */
1032 ath5k_rx_stop(sc); /* turn off frame recv */
1033 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
1035 ATH5K_ERR(sc, "%s: unable to reset channel "
1036 "(%u Mhz)\n", __func__, chan->center_freq);
1040 ath5k_hw_set_txpower_limit(sc->ah, 0);
1043 * Re-enable rx framework.
1045 ret = ath5k_rx_start(sc);
1047 ATH5K_ERR(sc, "%s: unable to restart recv logic\n",
1053 * Change channels and update the h/w rate map
1054 * if we're switching; e.g. 11a to 11b/g.
1058 /* ath5k_chan_change(sc, chan); */
1060 ath5k_beacon_config(sc);
1062 * Re-enable interrupts.
1064 ath5k_hw_set_intr(ah, sc->imask);
1071 * TODO: CLEAN THIS !!!
1074 ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1076 if (unlikely(test_bit(ATH_STAT_LEDSOFT, sc->status))) {
1077 /* from Atheros NDIS driver, w/ permission */
1078 static const struct {
1079 u16 rate; /* tx/rx 802.11 rate */
1080 u16 timeOn; /* LED on time (ms) */
1081 u16 timeOff; /* LED off time (ms) */
1098 const struct ath5k_rate_table *rt =
1099 ath5k_hw_get_rate_table(sc->ah, mode);
1104 memset(sc->hwmap, 0, sizeof(sc->hwmap));
1105 for (i = 0; i < 32; i++) {
1106 u8 ix = rt->rate_code_to_index[i];
1108 sc->hwmap[i].ledon = msecs_to_jiffies(500);
1109 sc->hwmap[i].ledoff = msecs_to_jiffies(130);
1112 sc->hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD;
1113 /* receive frames include FCS */
1114 sc->hwmap[i].rxflags = sc->hwmap[i].txflags |
1115 IEEE80211_RADIOTAP_F_FCS;
1116 /* setup blink rate table to avoid per-packet lookup */
1117 for (j = 0; j < ARRAY_SIZE(blinkrates) - 1; j++)
1118 if (blinkrates[j].rate == /* XXX why 7f? */
1119 (rt->rates[ix].dot11_rate&0x7f))
1122 sc->hwmap[i].ledon = msecs_to_jiffies(blinkrates[j].
1124 sc->hwmap[i].ledoff = msecs_to_jiffies(blinkrates[j].
1131 if (mode == AR5K_MODE_11A) {
1132 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1134 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1139 ath5k_mode_setup(struct ath5k_softc *sc)
1141 struct ath5k_hw *ah = sc->ah;
1144 /* configure rx filter */
1145 rfilt = sc->filter_flags;
1146 ath5k_hw_set_rx_filter(ah, rfilt);
1148 if (ath5k_hw_hasbssidmask(ah))
1149 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1151 /* configure operational mode */
1152 ath5k_hw_set_opmode(ah);
1154 ath5k_hw_set_mcast_filter(ah, 0, 0);
1155 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1159 * Match the hw provided rate index (through descriptors)
1160 * to an index for sc->curband->bitrates, so it can be used
1163 * This one is a little bit tricky but i think i'm right
1166 * We have 4 rate tables in the following order:
1170 * 802.11g (12 rates)
1171 * that make the hw rate table.
1173 * Lets take a 5211 for example that supports a and b modes only.
1174 * First comes the 802.11a table and then 802.11b (total 12 rates).
1175 * When hw returns eg. 11 it points to the last 802.11b rate (11Mbit),
1176 * if it returns 2 it points to the second 802.11a rate etc.
1178 * Same goes for 5212 who has xr/a/b/g support (total 28 rates).
1179 * First comes the XR table, then 802.11a, 802.11b and 802.11g.
1180 * When hw returns eg. 27 it points to the last 802.11g rate (54Mbits) etc
1183 ath5k_set_total_hw_rates(struct ath5k_softc *sc) {
1185 struct ath5k_hw *ah = sc->ah;
1187 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
1190 if (test_bit(AR5K_MODE_11B, ah->ah_modes))
1193 if (test_bit(AR5K_MODE_11G, ah->ah_modes))
1196 /* XXX: Need to see what what happens when
1197 xr disable bits in eeprom are set */
1198 if (ah->ah_version >= AR5K_AR5212)
1204 ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix) {
1208 if(sc->curband->band == IEEE80211_BAND_2GHZ) {
1209 /* We setup a g ratetable for both b/g modes */
1211 hw_rix - sc->b_rates - sc->a_rates - sc->xr_rates;
1213 mac80211_rix = hw_rix - sc->xr_rates;
1216 /* Something went wrong, fallback to basic rate for this band */
1217 if ((mac80211_rix >= sc->curband->n_bitrates) ||
1218 (mac80211_rix <= 0 ))
1221 return mac80211_rix;
1232 ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1234 struct ath5k_hw *ah = sc->ah;
1235 struct sk_buff *skb = bf->skb;
1236 struct ath5k_desc *ds;
1238 if (likely(skb == NULL)) {
1242 * Allocate buffer with headroom_needed space for the
1243 * fake physical layer header at the start.
1245 skb = dev_alloc_skb(sc->rxbufsize + sc->cachelsz - 1);
1246 if (unlikely(skb == NULL)) {
1247 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1248 sc->rxbufsize + sc->cachelsz - 1);
1252 * Cache-line-align. This is important (for the
1253 * 5210 at least) as not doing so causes bogus data
1256 off = ((unsigned long)skb->data) % sc->cachelsz;
1258 skb_reserve(skb, sc->cachelsz - off);
1261 bf->skbaddr = pci_map_single(sc->pdev,
1262 skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE);
1263 if (unlikely(pci_dma_mapping_error(bf->skbaddr))) {
1264 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1272 * Setup descriptors. For receive we always terminate
1273 * the descriptor list with a self-linked entry so we'll
1274 * not get overrun under high load (as can happen with a
1275 * 5212 when ANI processing enables PHY error frames).
1277 * To insure the last descriptor is self-linked we create
1278 * each descriptor as self-linked and add it to the end. As
1279 * each additional descriptor is added the previous self-linked
1280 * entry is ``fixed'' naturally. This should be safe even
1281 * if DMA is happening. When processing RX interrupts we
1282 * never remove/process the last, self-linked, entry on the
1283 * descriptor list. This insures the hardware always has
1284 * someplace to write a new frame.
1287 ds->ds_link = bf->daddr; /* link to self */
1288 ds->ds_data = bf->skbaddr;
1289 ath5k_hw_setup_rx_desc(ah, ds,
1290 skb_tailroom(skb), /* buffer size */
1293 if (sc->rxlink != NULL)
1294 *sc->rxlink = bf->daddr;
1295 sc->rxlink = &ds->ds_link;
1300 ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
1301 struct ieee80211_tx_control *ctl)
1303 struct ath5k_hw *ah = sc->ah;
1304 struct ath5k_txq *txq = sc->txq;
1305 struct ath5k_desc *ds = bf->desc;
1306 struct sk_buff *skb = bf->skb;
1307 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
1310 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
1312 /* XXX endianness */
1313 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1316 if (ctl->flags & IEEE80211_TXCTL_NO_ACK)
1317 flags |= AR5K_TXDESC_NOACK;
1321 if (!(ctl->flags & IEEE80211_TXCTL_DO_NOT_ENCRYPT)) {
1322 keyidx = ctl->key_idx;
1323 pktlen += ctl->icv_len;
1326 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1327 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
1328 (sc->power_level * 2), ctl->tx_rate->hw_value,
1329 ctl->retry_limit, keyidx, 0, flags, 0, 0);
1334 ds->ds_data = bf->skbaddr;
1336 spin_lock_bh(&txq->lock);
1337 list_add_tail(&bf->list, &txq->q);
1338 sc->tx_stats.data[txq->qnum].len++;
1339 if (txq->link == NULL) /* is this first packet? */
1340 ath5k_hw_put_tx_buf(ah, txq->qnum, bf->daddr);
1341 else /* no, so only link it */
1342 *txq->link = bf->daddr;
1344 txq->link = &ds->ds_link;
1345 ath5k_hw_tx_start(ah, txq->qnum);
1346 spin_unlock_bh(&txq->lock);
1350 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1354 /*******************\
1355 * Descriptors setup *
1356 \*******************/
1359 ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1361 struct ath5k_desc *ds;
1362 struct ath5k_buf *bf;
1367 /* allocate descriptors */
1368 sc->desc_len = sizeof(struct ath5k_desc) *
1369 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1370 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1371 if (sc->desc == NULL) {
1372 ATH5K_ERR(sc, "can't allocate descriptors\n");
1377 da = sc->desc_daddr;
1378 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1379 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1381 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1382 sizeof(struct ath5k_buf), GFP_KERNEL);
1384 ATH5K_ERR(sc, "can't allocate bufptr\n");
1390 INIT_LIST_HEAD(&sc->rxbuf);
1391 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1394 list_add_tail(&bf->list, &sc->rxbuf);
1397 INIT_LIST_HEAD(&sc->txbuf);
1398 sc->txbuf_len = ATH_TXBUF;
1399 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1400 da += sizeof(*ds)) {
1403 list_add_tail(&bf->list, &sc->txbuf);
1413 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1420 ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1422 struct ath5k_buf *bf;
1424 ath5k_txbuf_free(sc, sc->bbuf);
1425 list_for_each_entry(bf, &sc->txbuf, list)
1426 ath5k_txbuf_free(sc, bf);
1427 list_for_each_entry(bf, &sc->rxbuf, list)
1428 ath5k_txbuf_free(sc, bf);
1430 /* Free memory associated with all descriptors */
1431 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1445 static struct ath5k_txq *
1446 ath5k_txq_setup(struct ath5k_softc *sc,
1447 int qtype, int subtype)
1449 struct ath5k_hw *ah = sc->ah;
1450 struct ath5k_txq *txq;
1451 struct ath5k_txq_info qi = {
1452 .tqi_subtype = subtype,
1453 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1454 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1455 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1460 * Enable interrupts only for EOL and DESC conditions.
1461 * We mark tx descriptors to receive a DESC interrupt
1462 * when a tx queue gets deep; otherwise waiting for the
1463 * EOL to reap descriptors. Note that this is done to
1464 * reduce interrupt load and this only defers reaping
1465 * descriptors, never transmitting frames. Aside from
1466 * reducing interrupts this also permits more concurrency.
1467 * The only potential downside is if the tx queue backs
1468 * up in which case the top half of the kernel may backup
1469 * due to a lack of tx descriptors.
1471 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1472 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1473 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1476 * NB: don't print a message, this happens
1477 * normally on parts with too few tx queues
1479 return ERR_PTR(qnum);
1481 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1482 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1483 qnum, ARRAY_SIZE(sc->txqs));
1484 ath5k_hw_release_tx_queue(ah, qnum);
1485 return ERR_PTR(-EINVAL);
1487 txq = &sc->txqs[qnum];
1491 INIT_LIST_HEAD(&txq->q);
1492 spin_lock_init(&txq->lock);
1495 return &sc->txqs[qnum];
1499 ath5k_beaconq_setup(struct ath5k_hw *ah)
1501 struct ath5k_txq_info qi = {
1502 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1503 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1504 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1505 /* NB: for dynamic turbo, don't enable any other interrupts */
1506 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1509 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1513 ath5k_beaconq_config(struct ath5k_softc *sc)
1515 struct ath5k_hw *ah = sc->ah;
1516 struct ath5k_txq_info qi;
1519 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1522 if (sc->opmode == IEEE80211_IF_TYPE_AP) {
1524 * Always burst out beacon and CAB traffic
1525 * (aifs = cwmin = cwmax = 0)
1530 } else if (sc->opmode == IEEE80211_IF_TYPE_IBSS) {
1532 * Adhoc mode; backoff between 0 and (2 * cw_min).
1536 qi.tqi_cw_max = 2 * ah->ah_cw_min;
1539 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1540 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1541 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1543 ret = ath5k_hw_setup_tx_queueprops(ah, sc->bhalq, &qi);
1545 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1546 "hardware queue!\n", __func__);
1550 return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */;
1554 ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1556 struct ath5k_buf *bf, *bf0;
1559 * NB: this assumes output has been stopped and
1560 * we do not need to block ath5k_tx_tasklet
1562 spin_lock_bh(&txq->lock);
1563 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1564 ath5k_debug_printtxbuf(sc, bf);
1566 ath5k_txbuf_free(sc, bf);
1568 spin_lock_bh(&sc->txbuflock);
1569 sc->tx_stats.data[txq->qnum].len--;
1570 list_move_tail(&bf->list, &sc->txbuf);
1572 spin_unlock_bh(&sc->txbuflock);
1575 spin_unlock_bh(&txq->lock);
1579 * Drain the transmit queues and reclaim resources.
1582 ath5k_txq_cleanup(struct ath5k_softc *sc)
1584 struct ath5k_hw *ah = sc->ah;
1587 /* XXX return value */
1588 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1589 /* don't touch the hardware if marked invalid */
1590 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1591 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
1592 ath5k_hw_get_tx_buf(ah, sc->bhalq));
1593 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1594 if (sc->txqs[i].setup) {
1595 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1596 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1599 ath5k_hw_get_tx_buf(ah,
1604 ieee80211_start_queues(sc->hw); /* XXX move to callers */
1606 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1607 if (sc->txqs[i].setup)
1608 ath5k_txq_drainq(sc, &sc->txqs[i]);
1612 ath5k_txq_release(struct ath5k_softc *sc)
1614 struct ath5k_txq *txq = sc->txqs;
1617 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1619 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1632 * Enable the receive h/w following a reset.
1635 ath5k_rx_start(struct ath5k_softc *sc)
1637 struct ath5k_hw *ah = sc->ah;
1638 struct ath5k_buf *bf;
1641 sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->cachelsz);
1643 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rxbufsize %u\n",
1644 sc->cachelsz, sc->rxbufsize);
1648 spin_lock_bh(&sc->rxbuflock);
1649 list_for_each_entry(bf, &sc->rxbuf, list) {
1650 ret = ath5k_rxbuf_setup(sc, bf);
1652 spin_unlock_bh(&sc->rxbuflock);
1656 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1657 spin_unlock_bh(&sc->rxbuflock);
1659 ath5k_hw_put_rx_buf(ah, bf->daddr);
1660 ath5k_hw_start_rx(ah); /* enable recv descriptors */
1661 ath5k_mode_setup(sc); /* set filters, etc. */
1662 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1670 * Disable the receive h/w in preparation for a reset.
1673 ath5k_rx_stop(struct ath5k_softc *sc)
1675 struct ath5k_hw *ah = sc->ah;
1677 ath5k_hw_stop_pcu_recv(ah); /* disable PCU */
1678 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1679 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
1680 mdelay(3); /* 3ms is long enough for 1 frame */
1682 ath5k_debug_printrxbuffs(sc, ah);
1684 sc->rxlink = NULL; /* just in case */
1688 ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
1689 struct sk_buff *skb, struct ath5k_rx_status *rs)
1691 struct ieee80211_hdr *hdr = (void *)skb->data;
1692 unsigned int keyix, hlen = ieee80211_get_hdrlen_from_skb(skb);
1694 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1695 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1696 return RX_FLAG_DECRYPTED;
1698 /* Apparently when a default key is used to decrypt the packet
1699 the hw does not set the index used to decrypt. In such cases
1700 get the index from the packet. */
1701 if ((le16_to_cpu(hdr->frame_control) & IEEE80211_FCTL_PROTECTED) &&
1702 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1703 skb->len >= hlen + 4) {
1704 keyix = skb->data[hlen + 3] >> 6;
1706 if (test_bit(keyix, sc->keymap))
1707 return RX_FLAG_DECRYPTED;
1715 ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1716 struct ieee80211_rx_status *rxs)
1720 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1722 if ((le16_to_cpu(mgmt->frame_control) & IEEE80211_FCTL_FTYPE) ==
1723 IEEE80211_FTYPE_MGMT &&
1724 (le16_to_cpu(mgmt->frame_control) & IEEE80211_FCTL_STYPE) ==
1725 IEEE80211_STYPE_BEACON &&
1726 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
1727 memcmp(mgmt->bssid, sc->ah->ah_bssid, ETH_ALEN) == 0) {
1729 * Received an IBSS beacon with the same BSSID. Hardware *must*
1730 * have updated the local TSF. We have to work around various
1731 * hardware bugs, though...
1733 tsf = ath5k_hw_get_tsf64(sc->ah);
1734 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1735 hw_tu = TSF_TO_TU(tsf);
1737 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1738 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1739 (unsigned long long)bc_tstamp,
1740 (unsigned long long)rxs->mactime,
1741 (unsigned long long)(rxs->mactime - bc_tstamp),
1742 (unsigned long long)tsf);
1745 * Sometimes the HW will give us a wrong tstamp in the rx
1746 * status, causing the timestamp extension to go wrong.
1747 * (This seems to happen especially with beacon frames bigger
1748 * than 78 byte (incl. FCS))
1749 * But we know that the receive timestamp must be later than the
1750 * timestamp of the beacon since HW must have synced to that.
1752 * NOTE: here we assume mactime to be after the frame was
1753 * received, not like mac80211 which defines it at the start.
1755 if (bc_tstamp > rxs->mactime) {
1756 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1757 "fixing mactime from %llx to %llx\n",
1758 (unsigned long long)rxs->mactime,
1759 (unsigned long long)tsf);
1764 * Local TSF might have moved higher than our beacon timers,
1765 * in that case we have to update them to continue sending
1766 * beacons. This also takes care of synchronizing beacon sending
1767 * times with other stations.
1769 if (hw_tu >= sc->nexttbtt)
1770 ath5k_beacon_update_timers(sc, bc_tstamp);
1776 ath5k_tasklet_rx(unsigned long data)
1778 struct ieee80211_rx_status rxs = {};
1779 struct ath5k_rx_status rs = {};
1780 struct sk_buff *skb;
1781 struct ath5k_softc *sc = (void *)data;
1782 struct ath5k_buf *bf;
1783 struct ath5k_desc *ds;
1788 spin_lock(&sc->rxbuflock);
1790 if (unlikely(list_empty(&sc->rxbuf))) {
1791 ATH5K_WARN(sc, "empty rx buf pool\n");
1794 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1795 BUG_ON(bf->skb == NULL);
1799 /* TODO only one segment */
1800 pci_dma_sync_single_for_cpu(sc->pdev, sc->desc_daddr,
1801 sc->desc_len, PCI_DMA_FROMDEVICE);
1803 if (unlikely(ds->ds_link == bf->daddr)) /* this is the end */
1806 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
1807 if (unlikely(ret == -EINPROGRESS))
1809 else if (unlikely(ret)) {
1810 ATH5K_ERR(sc, "error in processing rx descriptor\n");
1811 spin_unlock(&sc->rxbuflock);
1815 if (unlikely(rs.rs_more)) {
1816 ATH5K_WARN(sc, "unsupported jumbo\n");
1820 if (unlikely(rs.rs_status)) {
1821 if (rs.rs_status & AR5K_RXERR_PHY)
1823 if (rs.rs_status & AR5K_RXERR_DECRYPT) {
1825 * Decrypt error. If the error occurred
1826 * because there was no hardware key, then
1827 * let the frame through so the upper layers
1828 * can process it. This is necessary for 5210
1829 * parts which have no way to setup a ``clear''
1832 * XXX do key cache faulting
1834 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1835 !(rs.rs_status & AR5K_RXERR_CRC))
1838 if (rs.rs_status & AR5K_RXERR_MIC) {
1839 rxs.flag |= RX_FLAG_MMIC_ERROR;
1843 /* let crypto-error packets fall through in MNTR */
1845 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
1846 sc->opmode != IEEE80211_IF_TYPE_MNTR)
1850 pci_dma_sync_single_for_cpu(sc->pdev, bf->skbaddr,
1851 rs.rs_datalen, PCI_DMA_FROMDEVICE);
1852 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
1853 PCI_DMA_FROMDEVICE);
1856 skb_put(skb, rs.rs_datalen);
1859 * the hardware adds a padding to 4 byte boundaries between
1860 * the header and the payload data if the header length is
1861 * not multiples of 4 - remove it
1863 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1866 memmove(skb->data + pad, skb->data, hdrlen);
1871 * always extend the mac timestamp, since this information is
1872 * also needed for proper IBSS merging.
1874 * XXX: it might be too late to do it here, since rs_tstamp is
1875 * 15bit only. that means TSF extension has to be done within
1876 * 32768usec (about 32ms). it might be necessary to move this to
1877 * the interrupt handler, like it is done in madwifi.
1879 * Unfortunately we don't know when the hardware takes the rx
1880 * timestamp (beginning of phy frame, data frame, end of rx?).
1881 * The only thing we know is that it is hardware specific...
1882 * On AR5213 it seems the rx timestamp is at the end of the
1883 * frame, but i'm not sure.
1885 * NOTE: mac80211 defines mactime at the beginning of the first
1886 * data symbol. Since we don't have any time references it's
1887 * impossible to comply to that. This affects IBSS merge only
1888 * right now, so it's not too bad...
1890 rxs.mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
1891 rxs.flag |= RX_FLAG_TSFT;
1893 rxs.freq = sc->curchan->center_freq;
1894 rxs.band = sc->curband->band;
1898 * the names here are misleading and the usage of these
1899 * values by iwconfig makes it even worse
1901 /* noise floor in dBm, from the last noise calibration */
1902 rxs.noise = sc->ah->ah_noise_floor;
1903 /* signal level in dBm */
1904 rxs.ssi = rxs.noise + rs.rs_rssi;
1906 * "signal" is actually displayed as Link Quality by iwconfig
1907 * we provide a percentage based on rssi (assuming max rssi 64)
1909 rxs.signal = rs.rs_rssi * 100 / 64;
1911 rxs.antenna = rs.rs_antenna;
1912 rxs.rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
1913 rxs.flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
1915 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1917 /* check beacons in IBSS mode */
1918 if (sc->opmode == IEEE80211_IF_TYPE_IBSS)
1919 ath5k_check_ibss_tsf(sc, skb, &rxs);
1921 __ieee80211_rx(sc->hw, skb, &rxs);
1922 sc->led_rxrate = rs.rs_rate;
1923 ath5k_led_event(sc, ATH_LED_RX);
1925 list_move_tail(&bf->list, &sc->rxbuf);
1926 } while (ath5k_rxbuf_setup(sc, bf) == 0);
1927 spin_unlock(&sc->rxbuflock);
1938 ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1940 struct ieee80211_tx_status txs = {};
1941 struct ath5k_tx_status ts = {};
1942 struct ath5k_buf *bf, *bf0;
1943 struct ath5k_desc *ds;
1944 struct sk_buff *skb;
1947 spin_lock(&txq->lock);
1948 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1951 /* TODO only one segment */
1952 pci_dma_sync_single_for_cpu(sc->pdev, sc->desc_daddr,
1953 sc->desc_len, PCI_DMA_FROMDEVICE);
1954 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
1955 if (unlikely(ret == -EINPROGRESS))
1957 else if (unlikely(ret)) {
1958 ATH5K_ERR(sc, "error %d while processing queue %u\n",
1965 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1968 txs.control = bf->ctl;
1969 txs.retry_count = ts.ts_shortretry + ts.ts_longretry / 6;
1970 if (unlikely(ts.ts_status)) {
1971 sc->ll_stats.dot11ACKFailureCount++;
1972 if (ts.ts_status & AR5K_TXERR_XRETRY)
1973 txs.excessive_retries = 1;
1974 else if (ts.ts_status & AR5K_TXERR_FILT)
1975 txs.flags |= IEEE80211_TX_STATUS_TX_FILTERED;
1977 txs.flags |= IEEE80211_TX_STATUS_ACK;
1978 txs.ack_signal = ts.ts_rssi;
1981 ieee80211_tx_status(sc->hw, skb, &txs);
1982 sc->tx_stats.data[txq->qnum].count++;
1984 spin_lock(&sc->txbuflock);
1985 sc->tx_stats.data[txq->qnum].len--;
1986 list_move_tail(&bf->list, &sc->txbuf);
1988 spin_unlock(&sc->txbuflock);
1990 if (likely(list_empty(&txq->q)))
1992 spin_unlock(&txq->lock);
1993 if (sc->txbuf_len > ATH_TXBUF / 5)
1994 ieee80211_wake_queues(sc->hw);
1998 ath5k_tasklet_tx(unsigned long data)
2000 struct ath5k_softc *sc = (void *)data;
2002 ath5k_tx_processq(sc, sc->txq);
2004 ath5k_led_event(sc, ATH_LED_TX);
2015 * Setup the beacon frame for transmit.
2018 ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
2019 struct ieee80211_tx_control *ctl)
2021 struct sk_buff *skb = bf->skb;
2022 struct ath5k_hw *ah = sc->ah;
2023 struct ath5k_desc *ds;
2024 int ret, antenna = 0;
2027 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
2029 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
2030 "skbaddr %llx\n", skb, skb->data, skb->len,
2031 (unsigned long long)bf->skbaddr);
2032 if (pci_dma_mapping_error(bf->skbaddr)) {
2033 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
2039 flags = AR5K_TXDESC_NOACK;
2040 if (sc->opmode == IEEE80211_IF_TYPE_IBSS && ath5k_hw_hasveol(ah)) {
2041 ds->ds_link = bf->daddr; /* self-linked */
2042 flags |= AR5K_TXDESC_VEOL;
2044 * Let hardware handle antenna switching if txantenna is not set
2049 * Switch antenna every 4 beacons if txantenna is not set
2050 * XXX assumes two antennas
2053 antenna = sc->bsent & 4 ? 2 : 1;
2056 ds->ds_data = bf->skbaddr;
2057 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
2058 ieee80211_get_hdrlen_from_skb(skb),
2059 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
2060 ctl->tx_rate->hw_value, 1, AR5K_TXKEYIX_INVALID,
2061 antenna, flags, 0, 0);
2067 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
2072 * Transmit a beacon frame at SWBA. Dynamic updates to the
2073 * frame contents are done as needed and the slot time is
2074 * also adjusted based on current state.
2076 * this is usually called from interrupt context (ath5k_intr())
2077 * but also from ath5k_beacon_config() in IBSS mode which in turn
2078 * can be called from a tasklet and user context
2081 ath5k_beacon_send(struct ath5k_softc *sc)
2083 struct ath5k_buf *bf = sc->bbuf;
2084 struct ath5k_hw *ah = sc->ah;
2086 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
2088 if (unlikely(bf->skb == NULL || sc->opmode == IEEE80211_IF_TYPE_STA ||
2089 sc->opmode == IEEE80211_IF_TYPE_MNTR)) {
2090 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
2094 * Check if the previous beacon has gone out. If
2095 * not don't don't try to post another, skip this
2096 * period and wait for the next. Missed beacons
2097 * indicate a problem and should not occur. If we
2098 * miss too many consecutive beacons reset the device.
2100 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
2102 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2103 "missed %u consecutive beacons\n", sc->bmisscount);
2104 if (sc->bmisscount > 3) { /* NB: 3 is a guess */
2105 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2106 "stuck beacon time (%u missed)\n",
2108 tasklet_schedule(&sc->restq);
2112 if (unlikely(sc->bmisscount != 0)) {
2113 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2114 "resume beacon xmit after %u misses\n",
2120 * Stop any current dma and put the new frame on the queue.
2121 * This should never fail since we check above that no frames
2122 * are still pending on the queue.
2124 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
2125 ATH5K_WARN(sc, "beacon queue %u didn't stop?\n", sc->bhalq);
2126 /* NB: hw still stops DMA, so proceed */
2128 pci_dma_sync_single_for_cpu(sc->pdev, bf->skbaddr, bf->skb->len,
2131 ath5k_hw_put_tx_buf(ah, sc->bhalq, bf->daddr);
2132 ath5k_hw_tx_start(ah, sc->bhalq);
2133 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
2134 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2141 * ath5k_beacon_update_timers - update beacon timers
2143 * @sc: struct ath5k_softc pointer we are operating on
2144 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2145 * beacon timer update based on the current HW TSF.
2147 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2148 * of a received beacon or the current local hardware TSF and write it to the
2149 * beacon timer registers.
2151 * This is called in a variety of situations, e.g. when a beacon is received,
2152 * when a TSF update has been detected, but also when an new IBSS is created or
2153 * when we otherwise know we have to update the timers, but we keep it in this
2154 * function to have it all together in one place.
2157 ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
2159 struct ath5k_hw *ah = sc->ah;
2160 u32 nexttbtt, intval, hw_tu, bc_tu;
2163 intval = sc->bintval & AR5K_BEACON_PERIOD;
2164 if (WARN_ON(!intval))
2167 /* beacon TSF converted to TU */
2168 bc_tu = TSF_TO_TU(bc_tsf);
2170 /* current TSF converted to TU */
2171 hw_tsf = ath5k_hw_get_tsf64(ah);
2172 hw_tu = TSF_TO_TU(hw_tsf);
2175 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2178 * no beacons received, called internally.
2179 * just need to refresh timers based on HW TSF.
2181 nexttbtt = roundup(hw_tu + FUDGE, intval);
2182 } else if (bc_tsf == 0) {
2184 * no beacon received, probably called by ath5k_reset_tsf().
2185 * reset TSF to start with 0.
2188 intval |= AR5K_BEACON_RESET_TSF;
2189 } else if (bc_tsf > hw_tsf) {
2191 * beacon received, SW merge happend but HW TSF not yet updated.
2192 * not possible to reconfigure timers yet, but next time we
2193 * receive a beacon with the same BSSID, the hardware will
2194 * automatically update the TSF and then we need to reconfigure
2197 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2198 "need to wait for HW TSF sync\n");
2202 * most important case for beacon synchronization between STA.
2204 * beacon received and HW TSF has been already updated by HW.
2205 * update next TBTT based on the TSF of the beacon, but make
2206 * sure it is ahead of our local TSF timer.
2208 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2212 sc->nexttbtt = nexttbtt;
2214 intval |= AR5K_BEACON_ENA;
2215 ath5k_hw_init_beacon(ah, nexttbtt, intval);
2218 * debugging output last in order to preserve the time critical aspect
2222 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2223 "reconfigured timers based on HW TSF\n");
2224 else if (bc_tsf == 0)
2225 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2226 "reset HW TSF and timers\n");
2228 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2229 "updated timers based on beacon TSF\n");
2231 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2232 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2233 (unsigned long long) bc_tsf,
2234 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
2235 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2236 intval & AR5K_BEACON_PERIOD,
2237 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2238 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
2243 * ath5k_beacon_config - Configure the beacon queues and interrupts
2245 * @sc: struct ath5k_softc pointer we are operating on
2247 * When operating in station mode we want to receive a BMISS interrupt when we
2248 * stop seeing beacons from the AP we've associated with so we can look for
2249 * another AP to associate with.
2251 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2252 * interrupts to detect TSF updates only.
2254 * AP mode is missing.
2257 ath5k_beacon_config(struct ath5k_softc *sc)
2259 struct ath5k_hw *ah = sc->ah;
2261 ath5k_hw_set_intr(ah, 0);
2264 if (sc->opmode == IEEE80211_IF_TYPE_STA) {
2265 sc->imask |= AR5K_INT_BMISS;
2266 } else if (sc->opmode == IEEE80211_IF_TYPE_IBSS) {
2268 * In IBSS mode we use a self-linked tx descriptor and let the
2269 * hardware send the beacons automatically. We have to load it
2271 * We use the SWBA interrupt only to keep track of the beacon
2272 * timers in order to detect automatic TSF updates.
2274 ath5k_beaconq_config(sc);
2276 sc->imask |= AR5K_INT_SWBA;
2278 if (ath5k_hw_hasveol(ah))
2279 ath5k_beacon_send(sc);
2283 ath5k_hw_set_intr(ah, sc->imask);
2287 /********************\
2288 * Interrupt handling *
2289 \********************/
2292 ath5k_init(struct ath5k_softc *sc)
2296 mutex_lock(&sc->lock);
2298 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2301 * Stop anything previously setup. This is safe
2302 * no matter this is the first time through or not.
2304 ath5k_stop_locked(sc);
2307 * The basic interface to setting the hardware in a good
2308 * state is ``reset''. On return the hardware is known to
2309 * be powered up and with interrupts disabled. This must
2310 * be followed by initialization of the appropriate bits
2311 * and then setup of the interrupt mask.
2313 sc->curchan = sc->hw->conf.channel;
2314 sc->curband = &sc->sbands[sc->curchan->band];
2315 ret = ath5k_hw_reset(sc->ah, sc->opmode, sc->curchan, false);
2317 ATH5K_ERR(sc, "unable to reset hardware: %d\n", ret);
2321 * This is needed only to setup initial state
2322 * but it's best done after a reset.
2324 ath5k_hw_set_txpower_limit(sc->ah, 0);
2327 * Setup the hardware after reset: the key cache
2328 * is filled as needed and the receive engine is
2329 * set going. Frame transmit is handled entirely
2330 * in the frame output path; there's nothing to do
2331 * here except setup the interrupt mask.
2333 ret = ath5k_rx_start(sc);
2338 * Enable interrupts.
2340 sc->imask = AR5K_INT_RX | AR5K_INT_TX | AR5K_INT_RXEOL |
2341 AR5K_INT_RXORN | AR5K_INT_FATAL | AR5K_INT_GLOBAL |
2344 ath5k_hw_set_intr(sc->ah, sc->imask);
2345 /* Set ack to be sent at low bit-rates */
2346 ath5k_hw_set_ack_bitrate_high(sc->ah, false);
2348 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2349 msecs_to_jiffies(ath5k_calinterval * 1000)));
2353 mutex_unlock(&sc->lock);
2358 ath5k_stop_locked(struct ath5k_softc *sc)
2360 struct ath5k_hw *ah = sc->ah;
2362 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2363 test_bit(ATH_STAT_INVALID, sc->status));
2366 * Shutdown the hardware and driver:
2367 * stop output from above
2368 * disable interrupts
2370 * turn off the radio
2371 * clear transmit machinery
2372 * clear receive machinery
2373 * drain and release tx queues
2374 * reclaim beacon resources
2375 * power down hardware
2377 * Note that some of this work is not possible if the
2378 * hardware is gone (invalid).
2380 ieee80211_stop_queues(sc->hw);
2382 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2383 if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
2384 del_timer_sync(&sc->led_tim);
2385 ath5k_hw_set_gpio(ah, sc->led_pin, !sc->led_on);
2386 __clear_bit(ATH_STAT_LEDBLINKING, sc->status);
2388 ath5k_hw_set_intr(ah, 0);
2390 ath5k_txq_cleanup(sc);
2391 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2393 ath5k_hw_phy_disable(ah);
2401 * Stop the device, grabbing the top-level lock to protect
2402 * against concurrent entry through ath5k_init (which can happen
2403 * if another thread does a system call and the thread doing the
2404 * stop is preempted).
2407 ath5k_stop_hw(struct ath5k_softc *sc)
2411 mutex_lock(&sc->lock);
2412 ret = ath5k_stop_locked(sc);
2413 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2415 * Set the chip in full sleep mode. Note that we are
2416 * careful to do this only when bringing the interface
2417 * completely to a stop. When the chip is in this state
2418 * it must be carefully woken up or references to
2419 * registers in the PCI clock domain may freeze the bus
2420 * (and system). This varies by chip and is mostly an
2421 * issue with newer parts that go to sleep more quickly.
2423 if (sc->ah->ah_mac_srev >= 0x78) {
2426 * don't put newer MAC revisions > 7.8 to sleep because
2427 * of the above mentioned problems
2429 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mac version > 7.8, "
2430 "not putting device to sleep\n");
2432 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2433 "putting device to full sleep\n");
2434 ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0);
2437 ath5k_txbuf_free(sc, sc->bbuf);
2438 mutex_unlock(&sc->lock);
2440 del_timer_sync(&sc->calib_tim);
2446 ath5k_intr(int irq, void *dev_id)
2448 struct ath5k_softc *sc = dev_id;
2449 struct ath5k_hw *ah = sc->ah;
2450 enum ath5k_int status;
2451 unsigned int counter = 1000;
2453 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2454 !ath5k_hw_is_intr_pending(ah)))
2459 * Figure out the reason(s) for the interrupt. Note
2460 * that get_isr returns a pseudo-ISR that may include
2461 * bits we haven't explicitly enabled so we mask the
2462 * value to insure we only process bits we requested.
2464 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2465 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2467 status &= sc->imask; /* discard unasked for bits */
2468 if (unlikely(status & AR5K_INT_FATAL)) {
2470 * Fatal errors are unrecoverable.
2471 * Typically these are caused by DMA errors.
2473 tasklet_schedule(&sc->restq);
2474 } else if (unlikely(status & AR5K_INT_RXORN)) {
2475 tasklet_schedule(&sc->restq);
2477 if (status & AR5K_INT_SWBA) {
2479 * Software beacon alert--time to send a beacon.
2480 * Handle beacon transmission directly; deferring
2481 * this is too slow to meet timing constraints
2484 * In IBSS mode we use this interrupt just to
2485 * keep track of the next TBTT (target beacon
2486 * transmission time) in order to detect wether
2487 * automatic TSF updates happened.
2489 if (sc->opmode == IEEE80211_IF_TYPE_IBSS) {
2490 /* XXX: only if VEOL suppported */
2491 u64 tsf = ath5k_hw_get_tsf64(ah);
2492 sc->nexttbtt += sc->bintval;
2493 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2494 "SWBA nexttbtt: %x hw_tu: %x "
2498 (unsigned long long) tsf);
2500 ath5k_beacon_send(sc);
2503 if (status & AR5K_INT_RXEOL) {
2505 * NB: the hardware should re-read the link when
2506 * RXE bit is written, but it doesn't work at
2507 * least on older hardware revs.
2511 if (status & AR5K_INT_TXURN) {
2512 /* bump tx trigger level */
2513 ath5k_hw_update_tx_triglevel(ah, true);
2515 if (status & AR5K_INT_RX)
2516 tasklet_schedule(&sc->rxtq);
2517 if (status & AR5K_INT_TX)
2518 tasklet_schedule(&sc->txtq);
2519 if (status & AR5K_INT_BMISS) {
2521 if (status & AR5K_INT_MIB) {
2523 * These stats are also used for ANI i think
2524 * so how about updating them more often ?
2526 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
2529 } while (ath5k_hw_is_intr_pending(ah) && counter-- > 0);
2531 if (unlikely(!counter))
2532 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2538 ath5k_tasklet_reset(unsigned long data)
2540 struct ath5k_softc *sc = (void *)data;
2542 ath5k_reset(sc->hw);
2546 * Periodically recalibrate the PHY to account
2547 * for temperature/environment changes.
2550 ath5k_calibrate(unsigned long data)
2552 struct ath5k_softc *sc = (void *)data;
2553 struct ath5k_hw *ah = sc->ah;
2555 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
2556 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2557 sc->curchan->hw_value);
2559 if (ath5k_hw_get_rf_gain(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2561 * Rfgain is out of bounds, reset the chip
2562 * to load new gain values.
2564 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
2565 ath5k_reset(sc->hw);
2567 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2568 ATH5K_ERR(sc, "calibration of channel %u failed\n",
2569 ieee80211_frequency_to_channel(
2570 sc->curchan->center_freq));
2572 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2573 msecs_to_jiffies(ath5k_calinterval * 1000)));
2583 ath5k_led_off(unsigned long data)
2585 struct ath5k_softc *sc = (void *)data;
2587 if (test_bit(ATH_STAT_LEDENDBLINK, sc->status))
2588 __clear_bit(ATH_STAT_LEDBLINKING, sc->status);
2590 __set_bit(ATH_STAT_LEDENDBLINK, sc->status);
2591 ath5k_hw_set_gpio(sc->ah, sc->led_pin, !sc->led_on);
2592 mod_timer(&sc->led_tim, jiffies + sc->led_off);
2597 * Blink the LED according to the specified on/off times.
2600 ath5k_led_blink(struct ath5k_softc *sc, unsigned int on,
2603 ATH5K_DBG(sc, ATH5K_DEBUG_LED, "on %u off %u\n", on, off);
2604 ath5k_hw_set_gpio(sc->ah, sc->led_pin, sc->led_on);
2605 __set_bit(ATH_STAT_LEDBLINKING, sc->status);
2606 __clear_bit(ATH_STAT_LEDENDBLINK, sc->status);
2608 mod_timer(&sc->led_tim, jiffies + on);
2612 ath5k_led_event(struct ath5k_softc *sc, int event)
2614 if (likely(!test_bit(ATH_STAT_LEDSOFT, sc->status)))
2616 if (unlikely(test_bit(ATH_STAT_LEDBLINKING, sc->status)))
2617 return; /* don't interrupt active blink */
2620 ath5k_led_blink(sc, sc->hwmap[sc->led_txrate].ledon,
2621 sc->hwmap[sc->led_txrate].ledoff);
2624 ath5k_led_blink(sc, sc->hwmap[sc->led_rxrate].ledon,
2625 sc->hwmap[sc->led_rxrate].ledoff);
2633 /********************\
2634 * Mac80211 functions *
2635 \********************/
2638 ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
2639 struct ieee80211_tx_control *ctl)
2641 struct ath5k_softc *sc = hw->priv;
2642 struct ath5k_buf *bf;
2643 unsigned long flags;
2647 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2649 if (sc->opmode == IEEE80211_IF_TYPE_MNTR)
2650 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2653 * the hardware expects the header padded to 4 byte boundaries
2654 * if this is not the case we add the padding after the header
2656 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2659 if (skb_headroom(skb) < pad) {
2660 ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
2661 " headroom to pad %d\n", hdrlen, pad);
2665 memmove(skb->data, skb->data+pad, hdrlen);
2668 sc->led_txrate = ctl->tx_rate->hw_value;
2670 spin_lock_irqsave(&sc->txbuflock, flags);
2671 if (list_empty(&sc->txbuf)) {
2672 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2673 spin_unlock_irqrestore(&sc->txbuflock, flags);
2674 ieee80211_stop_queue(hw, ctl->queue);
2677 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2678 list_del(&bf->list);
2680 if (list_empty(&sc->txbuf))
2681 ieee80211_stop_queues(hw);
2682 spin_unlock_irqrestore(&sc->txbuflock, flags);
2686 if (ath5k_txbuf_setup(sc, bf, ctl)) {
2688 spin_lock_irqsave(&sc->txbuflock, flags);
2689 list_add_tail(&bf->list, &sc->txbuf);
2691 spin_unlock_irqrestore(&sc->txbuflock, flags);
2692 dev_kfree_skb_any(skb);
2700 ath5k_reset(struct ieee80211_hw *hw)
2702 struct ath5k_softc *sc = hw->priv;
2703 struct ath5k_hw *ah = sc->ah;
2706 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
2708 ath5k_hw_set_intr(ah, 0);
2709 ath5k_txq_cleanup(sc);
2712 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
2713 if (unlikely(ret)) {
2714 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2717 ath5k_hw_set_txpower_limit(sc->ah, 0);
2719 ret = ath5k_rx_start(sc);
2720 if (unlikely(ret)) {
2721 ATH5K_ERR(sc, "can't start recv logic\n");
2725 * We may be doing a reset in response to an ioctl
2726 * that changes the channel so update any state that
2727 * might change as a result.
2731 /* ath5k_chan_change(sc, c); */
2732 ath5k_beacon_config(sc);
2733 /* intrs are started by ath5k_beacon_config */
2735 ieee80211_wake_queues(hw);
2742 static int ath5k_start(struct ieee80211_hw *hw)
2744 return ath5k_init(hw->priv);
2747 static void ath5k_stop(struct ieee80211_hw *hw)
2749 ath5k_stop_hw(hw->priv);
2752 static int ath5k_add_interface(struct ieee80211_hw *hw,
2753 struct ieee80211_if_init_conf *conf)
2755 struct ath5k_softc *sc = hw->priv;
2758 mutex_lock(&sc->lock);
2764 sc->vif = conf->vif;
2766 switch (conf->type) {
2767 case IEEE80211_IF_TYPE_STA:
2768 case IEEE80211_IF_TYPE_IBSS:
2769 case IEEE80211_IF_TYPE_MNTR:
2770 sc->opmode = conf->type;
2778 mutex_unlock(&sc->lock);
2783 ath5k_remove_interface(struct ieee80211_hw *hw,
2784 struct ieee80211_if_init_conf *conf)
2786 struct ath5k_softc *sc = hw->priv;
2788 mutex_lock(&sc->lock);
2789 if (sc->vif != conf->vif)
2794 mutex_unlock(&sc->lock);
2798 * TODO: Phy disable/diversity etc
2801 ath5k_config(struct ieee80211_hw *hw,
2802 struct ieee80211_conf *conf)
2804 struct ath5k_softc *sc = hw->priv;
2806 sc->bintval = conf->beacon_int;
2807 sc->power_level = conf->power_level;
2809 return ath5k_chan_set(sc, conf->channel);
2813 ath5k_config_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2814 struct ieee80211_if_conf *conf)
2816 struct ath5k_softc *sc = hw->priv;
2817 struct ath5k_hw *ah = sc->ah;
2820 /* Set to a reasonable value. Note that this will
2821 * be set to mac80211's value at ath5k_config(). */
2823 mutex_lock(&sc->lock);
2824 if (sc->vif != vif) {
2829 /* Cache for later use during resets */
2830 memcpy(ah->ah_bssid, conf->bssid, ETH_ALEN);
2831 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
2832 * a clean way of letting us retrieve this yet. */
2833 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
2835 mutex_unlock(&sc->lock);
2837 return ath5k_reset(hw);
2839 mutex_unlock(&sc->lock);
2843 #define SUPPORTED_FIF_FLAGS \
2844 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2845 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2846 FIF_BCN_PRBRESP_PROMISC
2848 * o always accept unicast, broadcast, and multicast traffic
2849 * o multicast traffic for all BSSIDs will be enabled if mac80211
2851 * o maintain current state of phy ofdm or phy cck error reception.
2852 * If the hardware detects any of these type of errors then
2853 * ath5k_hw_get_rx_filter() will pass to us the respective
2854 * hardware filters to be able to receive these type of frames.
2855 * o probe request frames are accepted only when operating in
2856 * hostap, adhoc, or monitor modes
2857 * o enable promiscuous mode according to the interface state
2859 * - when operating in adhoc mode so the 802.11 layer creates
2860 * node table entries for peers,
2861 * - when operating in station mode for collecting rssi data when
2862 * the station is otherwise quiet, or
2865 static void ath5k_configure_filter(struct ieee80211_hw *hw,
2866 unsigned int changed_flags,
2867 unsigned int *new_flags,
2868 int mc_count, struct dev_mc_list *mclist)
2870 struct ath5k_softc *sc = hw->priv;
2871 struct ath5k_hw *ah = sc->ah;
2872 u32 mfilt[2], val, rfilt;
2879 /* Only deal with supported flags */
2880 changed_flags &= SUPPORTED_FIF_FLAGS;
2881 *new_flags &= SUPPORTED_FIF_FLAGS;
2883 /* If HW detects any phy or radar errors, leave those filters on.
2884 * Also, always enable Unicast, Broadcasts and Multicast
2885 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2886 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2887 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2888 AR5K_RX_FILTER_MCAST);
2890 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2891 if (*new_flags & FIF_PROMISC_IN_BSS) {
2892 rfilt |= AR5K_RX_FILTER_PROM;
2893 __set_bit(ATH_STAT_PROMISC, sc->status);
2896 __clear_bit(ATH_STAT_PROMISC, sc->status);
2899 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2900 if (*new_flags & FIF_ALLMULTI) {
2904 for (i = 0; i < mc_count; i++) {
2907 /* calculate XOR of eight 6-bit values */
2908 val = get_unaligned_le32(mclist->dmi_addr + 0);
2909 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2910 val = get_unaligned_le32(mclist->dmi_addr + 3);
2911 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2913 mfilt[pos / 32] |= (1 << (pos % 32));
2914 /* XXX: we might be able to just do this instead,
2915 * but not sure, needs testing, if we do use this we'd
2916 * neet to inform below to not reset the mcast */
2917 /* ath5k_hw_set_mcast_filterindex(ah,
2918 * mclist->dmi_addr[5]); */
2919 mclist = mclist->next;
2923 /* This is the best we can do */
2924 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
2925 rfilt |= AR5K_RX_FILTER_PHYERR;
2927 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2928 * and probes for any BSSID, this needs testing */
2929 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
2930 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
2932 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2933 * set we should only pass on control frames for this
2934 * station. This needs testing. I believe right now this
2935 * enables *all* control frames, which is OK.. but
2936 * but we should see if we can improve on granularity */
2937 if (*new_flags & FIF_CONTROL)
2938 rfilt |= AR5K_RX_FILTER_CONTROL;
2940 /* Additional settings per mode -- this is per ath5k */
2942 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2944 if (sc->opmode == IEEE80211_IF_TYPE_MNTR)
2945 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2946 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
2947 if (sc->opmode != IEEE80211_IF_TYPE_STA)
2948 rfilt |= AR5K_RX_FILTER_PROBEREQ;
2949 if (sc->opmode != IEEE80211_IF_TYPE_AP &&
2950 test_bit(ATH_STAT_PROMISC, sc->status))
2951 rfilt |= AR5K_RX_FILTER_PROM;
2952 if (sc->opmode == IEEE80211_IF_TYPE_STA ||
2953 sc->opmode == IEEE80211_IF_TYPE_IBSS) {
2954 rfilt |= AR5K_RX_FILTER_BEACON;
2958 ath5k_hw_set_rx_filter(ah,rfilt);
2960 /* Set multicast bits */
2961 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
2962 /* Set the cached hw filter flags, this will alter actually
2964 sc->filter_flags = rfilt;
2968 ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2969 const u8 *local_addr, const u8 *addr,
2970 struct ieee80211_key_conf *key)
2972 struct ath5k_softc *sc = hw->priv;
2977 /* XXX: fix hardware encryption, its not working. For now
2978 * allow software encryption */
2988 mutex_lock(&sc->lock);
2992 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key, addr);
2994 ATH5K_ERR(sc, "can't set the key\n");
2997 __set_bit(key->keyidx, sc->keymap);
2998 key->hw_key_idx = key->keyidx;
3001 ath5k_hw_reset_key(sc->ah, key->keyidx);
3002 __clear_bit(key->keyidx, sc->keymap);
3010 mutex_unlock(&sc->lock);
3015 ath5k_get_stats(struct ieee80211_hw *hw,
3016 struct ieee80211_low_level_stats *stats)
3018 struct ath5k_softc *sc = hw->priv;
3019 struct ath5k_hw *ah = sc->ah;
3022 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
3024 memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
3030 ath5k_get_tx_stats(struct ieee80211_hw *hw,
3031 struct ieee80211_tx_queue_stats *stats)
3033 struct ath5k_softc *sc = hw->priv;
3035 memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats));
3041 ath5k_get_tsf(struct ieee80211_hw *hw)
3043 struct ath5k_softc *sc = hw->priv;
3045 return ath5k_hw_get_tsf64(sc->ah);
3049 ath5k_reset_tsf(struct ieee80211_hw *hw)
3051 struct ath5k_softc *sc = hw->priv;
3054 * in IBSS mode we need to update the beacon timers too.
3055 * this will also reset the TSF if we call it with 0
3057 if (sc->opmode == IEEE80211_IF_TYPE_IBSS)
3058 ath5k_beacon_update_timers(sc, 0);
3060 ath5k_hw_reset_tsf(sc->ah);
3064 ath5k_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
3065 struct ieee80211_tx_control *ctl)
3067 struct ath5k_softc *sc = hw->priv;
3070 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
3072 mutex_lock(&sc->lock);
3074 if (sc->opmode != IEEE80211_IF_TYPE_IBSS) {
3079 ath5k_txbuf_free(sc, sc->bbuf);
3080 sc->bbuf->skb = skb;
3081 ret = ath5k_beacon_setup(sc, sc->bbuf, ctl);
3083 sc->bbuf->skb = NULL;
3085 ath5k_beacon_config(sc);
3088 mutex_unlock(&sc->lock);
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