git.oblomov.eu Git - linux-2.6/blob - drivers/media/video/cx88/cx88-mpeg.c

   1 /*
   2  *
   3  *  Support for the mpeg transport stream transfers
   4  *  PCI function #2 of the cx2388x.
   5  *
   6  *    (c) 2004 Jelle Foks <jelle@foks.8m.com>
   7  *    (c) 2004 Chris Pascoe <c.pascoe@itee.uq.edu.au>
   8  *    (c) 2004 Gerd Knorr <kraxel@bytesex.org>
   9  *
  10  *  This program is free software; you can redistribute it and/or modify
  11  *  it under the terms of the GNU General Public License as published by
  12  *  the Free Software Foundation; either version 2 of the License, or
  13  *  (at your option) any later version.
  14  *
  15  *  This program is distributed in the hope that it will be useful,
  16  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *  GNU General Public License for more details.
  19  *
  20  *  You should have received a copy of the GNU General Public License
  21  *  along with this program; if not, write to the Free Software
  22  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  23  */
  24
  25 #include <linux/module.h>
  26 #include <linux/moduleparam.h>
  27 #include <linux/init.h>
  28 #include <linux/device.h>
  29 #include <linux/interrupt.h>
  30 #include <asm/delay.h>
  31
  32 #include "cx88.h"
  33
  34 /* ------------------------------------------------------------------ */
  35
  36 MODULE_DESCRIPTION("mpeg driver for cx2388x based TV cards");
  37 MODULE_AUTHOR("Jelle Foks <jelle@foks.8m.com>");
  38 MODULE_AUTHOR("Chris Pascoe <c.pascoe@itee.uq.edu.au>");
  39 MODULE_AUTHOR("Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]");
  40 MODULE_LICENSE("GPL");
  41
  42 static unsigned int debug = 0;
  43 module_param(debug,int,0644);
  44 MODULE_PARM_DESC(debug,"enable debug messages [mpeg]");
  45
  46 #define dprintk(level,fmt, arg...)      if (debug >= level) \
  47         printk(KERN_DEBUG "%s/2: " fmt, dev->core->name , ## arg)
  48
  49 /* ------------------------------------------------------------------ */
  50
  51 static int cx8802_start_dma(struct cx8802_dev    *dev,
  52                             struct cx88_dmaqueue *q,
  53                             struct cx88_buffer   *buf)
  54 {
  55         struct cx88_core *core = dev->core;
  56
  57         dprintk(0, "cx8802_start_dma w: %d, h: %d, f: %d\n", dev->width, dev->height, buf->vb.field);
  58
  59         /* setup fifo + format */
  60         cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH28],
  61                                 dev->ts_packet_size, buf->risc.dma);
  62
  63         /* write TS length to chip */
  64         cx_write(MO_TS_LNGTH, buf->vb.width);
  65
  66         /* FIXME: this needs a review.
  67          * also: move to cx88-blackbird + cx88-dvb source files? */
  68
  69         if (cx88_boards[core->board].dvb) {
  70                 /* negedge driven & software reset */
  71                 cx_write(TS_GEN_CNTRL, 0x0040 | dev->ts_gen_cntrl);
  72                 udelay(100);
  73                 cx_write(MO_PINMUX_IO, 0x00);
  74                 cx_write(TS_HW_SOP_CNTRL,0x47<<16|188<<4|0x01);
  75                 switch (core->board) {
  76                 case CX88_BOARD_DVICO_FUSIONHDTV_3_GOLD_Q:
  77                 case CX88_BOARD_DVICO_FUSIONHDTV_3_GOLD_T:
  78                 case CX88_BOARD_DVICO_FUSIONHDTV_5_GOLD:
  79                         cx_write(TS_SOP_STAT, 1<<13);
  80                         break;
  81                 default:
  82                         cx_write(TS_SOP_STAT, 0x00);
  83                         break;
  84                 }
  85                 cx_write(TS_GEN_CNTRL, dev->ts_gen_cntrl);
  86                 udelay(100);
  87         }
  88
  89         if (cx88_boards[core->board].blackbird) {
  90                 cx_write(MO_PINMUX_IO, 0x88); /* enable MPEG parallel IO */
  91
  92                 cx_write(TS_GEN_CNTRL, 0x46); /* punctured clock TS & posedge driven & software reset */
  93                 udelay(100);
  94
  95                 cx_write(TS_HW_SOP_CNTRL, 0x408); /* mpeg start byte */
  96                 cx_write(TS_VALERR_CNTRL, 0x2000);
  97
  98                 cx_write(TS_GEN_CNTRL, 0x06); /* punctured clock TS & posedge driven */
  99                 udelay(100);
 100         }
 101
 102         /* reset counter */
 103         cx_write(MO_TS_GPCNTRL, GP_COUNT_CONTROL_RESET);
 104         q->count = 1;
 105
 106         /* enable irqs */
 107         dprintk( 0, "setting the interrupt mask\n" );
 108         cx_set(MO_PCI_INTMSK, core->pci_irqmask | 0x04);
 109         cx_set(MO_TS_INTMSK,  0x1f0011);
 110
 111         /* start dma */
 112         cx_set(MO_DEV_CNTRL2, (1<<5));
 113         cx_set(MO_TS_DMACNTRL, 0x11);
 114         return 0;
 115 }
 116
 117 static int cx8802_stop_dma(struct cx8802_dev *dev)
 118 {
 119         struct cx88_core *core = dev->core;
 120         dprintk( 0, "cx8802_stop_dma\n" );
 121
 122         /* stop dma */
 123         cx_clear(MO_TS_DMACNTRL, 0x11);
 124
 125         /* disable irqs */
 126         cx_clear(MO_PCI_INTMSK, 0x000004);
 127         cx_clear(MO_TS_INTMSK, 0x1f0011);
 128
 129         /* Reset the controller */
 130         cx_write(TS_GEN_CNTRL, 0xcd);
 131         return 0;
 132 }
 133
 134 static int cx8802_restart_queue(struct cx8802_dev    *dev,
 135                                 struct cx88_dmaqueue *q)
 136 {
 137         struct cx88_buffer *buf;
 138         struct list_head *item;
 139
 140         dprintk( 0, "cx8802_restart_queue\n" );
 141         if (list_empty(&q->active))
 142         {
 143                 dprintk( 0, "cx8802_restart_queue: queue is empty\n" );
 144                 return 0;
 145         }
 146
 147         buf = list_entry(q->active.next, struct cx88_buffer, vb.queue);
 148         dprintk(2,"restart_queue [%p/%d]: restart dma\n",
 149                 buf, buf->vb.i);
 150         cx8802_start_dma(dev, q, buf);
 151         list_for_each(item,&q->active) {
 152                 buf = list_entry(item, struct cx88_buffer, vb.queue);
 153                 buf->count = q->count++;
 154         }
 155         mod_timer(&q->timeout, jiffies+BUFFER_TIMEOUT);
 156         return 0;
 157 }
 158
 159 /* ------------------------------------------------------------------ */
 160
 161 int cx8802_buf_prepare(struct cx8802_dev *dev, struct cx88_buffer *buf,
 162                         enum v4l2_field field)
 163 {
 164         int size = dev->ts_packet_size * dev->ts_packet_count;
 165         int rc;
 166
 167         dprintk(1, "%s: %p\n", __FUNCTION__, buf);
 168         if (0 != buf->vb.baddr  &&  buf->vb.bsize < size)
 169                 return -EINVAL;
 170
 171         if (STATE_NEEDS_INIT == buf->vb.state) {
 172                 buf->vb.width  = dev->ts_packet_size;
 173                 buf->vb.height = dev->ts_packet_count;
 174                 buf->vb.size   = size;
 175                 buf->vb.field  = field /*V4L2_FIELD_TOP*/;
 176
 177                 if (0 != (rc = videobuf_iolock(dev->pci,&buf->vb,NULL)))
 178                         goto fail;
 179                 cx88_risc_databuffer(dev->pci, &buf->risc,
 180                                      buf->vb.dma.sglist,
 181                                      buf->vb.width, buf->vb.height);
 182         }
 183         buf->vb.state = STATE_PREPARED;
 184         return 0;
 185
 186  fail:
 187         cx88_free_buffer(dev->pci,buf);
 188         return rc;
 189 }
 190
 191 void cx8802_buf_queue(struct cx8802_dev *dev, struct cx88_buffer *buf)
 192 {
 193         struct cx88_buffer    *prev;
 194         struct cx88_dmaqueue  *q    = &dev->mpegq;
 195
 196         dprintk( 1, "cx8802_buf_queue\n" );
 197         /* add jump to stopper */
 198         buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
 199         buf->risc.jmp[1] = cpu_to_le32(q->stopper.dma);
 200
 201         if (list_empty(&q->active)) {
 202                 dprintk( 0, "queue is empty - first active\n" );
 203                 list_add_tail(&buf->vb.queue,&q->active);
 204                 cx8802_start_dma(dev, q, buf);
 205                 buf->vb.state = STATE_ACTIVE;
 206                 buf->count    = q->count++;
 207                 mod_timer(&q->timeout, jiffies+BUFFER_TIMEOUT);
 208                 dprintk(0,"[%p/%d] %s - first active\n",
 209                         buf, buf->vb.i, __FUNCTION__);
 210
 211         } else {
 212                 dprintk( 1, "queue is not empty - append to active\n" );
 213                 prev = list_entry(q->active.prev, struct cx88_buffer, vb.queue);
 214                 list_add_tail(&buf->vb.queue,&q->active);
 215                 buf->vb.state = STATE_ACTIVE;
 216                 buf->count    = q->count++;
 217                 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
 218                 dprintk( 1, "[%p/%d] %s - append to active\n",
 219                         buf, buf->vb.i, __FUNCTION__);
 220         }
 221 }
 222
 223 /* ----------------------------------------------------------- */
 224
 225 static void do_cancel_buffers(struct cx8802_dev *dev, char *reason, int restart)
 226 {
 227         struct cx88_dmaqueue *q = &dev->mpegq;
 228         struct cx88_buffer *buf;
 229         unsigned long flags;
 230
 231         spin_lock_irqsave(&dev->slock,flags);
 232         while (!list_empty(&q->active)) {
 233                 buf = list_entry(q->active.next, struct cx88_buffer, vb.queue);
 234                 list_del(&buf->vb.queue);
 235                 buf->vb.state = STATE_ERROR;
 236                 wake_up(&buf->vb.done);
 237                 dprintk(1,"[%p/%d] %s - dma=0x%08lx\n",
 238                         buf, buf->vb.i, reason, (unsigned long)buf->risc.dma);
 239         }
 240         if (restart)
 241         {
 242                 dprintk(0, "restarting queue\n" );
 243                 cx8802_restart_queue(dev,q);
 244         }
 245         spin_unlock_irqrestore(&dev->slock,flags);
 246 }
 247
 248 void cx8802_cancel_buffers(struct cx8802_dev *dev)
 249 {
 250         struct cx88_dmaqueue *q = &dev->mpegq;
 251
 252         dprintk( 1, "cx8802_cancel_buffers" );
 253         del_timer_sync(&q->timeout);
 254         cx8802_stop_dma(dev);
 255         do_cancel_buffers(dev,"cancel",0);
 256 }
 257
 258 static void cx8802_timeout(unsigned long data)
 259 {
 260         struct cx8802_dev *dev = (struct cx8802_dev*)data;
 261
 262         dprintk(0, "%s\n",__FUNCTION__);
 263
 264         if (debug)
 265                 cx88_sram_channel_dump(dev->core, &cx88_sram_channels[SRAM_CH28]);
 266         cx8802_stop_dma(dev);
 267         do_cancel_buffers(dev,"timeout",1);
 268 }
 269
 270 static char *cx88_mpeg_irqs[32] = {
 271         "ts_risci1", NULL, NULL, NULL,
 272         "ts_risci2", NULL, NULL, NULL,
 273         "ts_oflow",  NULL, NULL, NULL,
 274         "ts_sync",   NULL, NULL, NULL,
 275         "opc_err", "par_err", "rip_err", "pci_abort",
 276         "ts_err?",
 277 };
 278
 279 static void cx8802_mpeg_irq(struct cx8802_dev *dev)
 280 {
 281         struct cx88_core *core = dev->core;
 282         u32 status, mask, count;
 283
 284         dprintk( 1, "cx8802_mpeg_irq\n" );
 285         status = cx_read(MO_TS_INTSTAT);
 286         mask   = cx_read(MO_TS_INTMSK);
 287         if (0 == (status & mask))
 288                 return;
 289
 290         cx_write(MO_TS_INTSTAT, status);
 291
 292         if (debug || (status & mask & ~0xff))
 293                 cx88_print_irqbits(core->name, "irq mpeg ",
 294                                    cx88_mpeg_irqs, status, mask);
 295
 296         /* risc op code error */
 297         if (status & (1 << 16)) {
 298                 printk(KERN_WARNING "%s: mpeg risc op code error\n",core->name);
 299                 cx_clear(MO_TS_DMACNTRL, 0x11);
 300                 cx88_sram_channel_dump(dev->core, &cx88_sram_channels[SRAM_CH28]);
 301         }
 302
 303         /* risc1 y */
 304         if (status & 0x01) {
 305                 dprintk( 1, "wake up\n" );
 306                 spin_lock(&dev->slock);
 307                 count = cx_read(MO_TS_GPCNT);
 308                 cx88_wakeup(dev->core, &dev->mpegq, count);
 309                 spin_unlock(&dev->slock);
 310         }
 311
 312         /* risc2 y */
 313         if (status & 0x10) {
 314                 spin_lock(&dev->slock);
 315                 cx8802_restart_queue(dev,&dev->mpegq);
 316                 spin_unlock(&dev->slock);
 317         }
 318
 319         /* other general errors */
 320         if (status & 0x1f0100) {
 321                 dprintk( 0, "general errors: 0x%08x\n", status & 0x1f0100 );
 322                 spin_lock(&dev->slock);
 323                 cx8802_stop_dma(dev);
 324                 cx8802_restart_queue(dev,&dev->mpegq);
 325                 spin_unlock(&dev->slock);
 326         }
 327 }
 328
 329 #define MAX_IRQ_LOOP 10
 330
 331 static irqreturn_t cx8802_irq(int irq, void *dev_id, struct pt_regs *regs)
 332 {
 333         struct cx8802_dev *dev = dev_id;
 334         struct cx88_core *core = dev->core;
 335         u32 status;
 336         int loop, handled = 0;
 337
 338         for (loop = 0; loop < MAX_IRQ_LOOP; loop++) {
 339                 status = cx_read(MO_PCI_INTSTAT) & (core->pci_irqmask | 0x04);
 340                 if (0 == status)
 341                         goto out;
 342                 dprintk( 1, "cx8802_irq\n" );
 343                 dprintk( 1, "    loop: %d/%d\n", loop, MAX_IRQ_LOOP );
 344                 dprintk( 1, "    status: %d\n", status );
 345                 handled = 1;
 346                 cx_write(MO_PCI_INTSTAT, status);
 347
 348                 if (status & core->pci_irqmask)
 349                         cx88_core_irq(core,status);
 350                 if (status & 0x04)
 351                         cx8802_mpeg_irq(dev);
 352         };
 353         if (MAX_IRQ_LOOP == loop) {
 354                 dprintk( 0, "clearing mask\n" );
 355                 printk(KERN_WARNING "%s/0: irq loop -- clearing mask\n",
 356                        core->name);
 357                 cx_write(MO_PCI_INTMSK,0);
 358         }
 359
 360  out:
 361         return IRQ_RETVAL(handled);
 362 }
 363
 364 /* ----------------------------------------------------------- */
 365 /* exported stuff                                              */
 366
 367 int cx8802_init_common(struct cx8802_dev *dev)
 368 {
 369         struct cx88_core *core = dev->core;
 370         int err;
 371
 372         /* pci init */
 373         if (pci_enable_device(dev->pci))
 374                 return -EIO;
 375         pci_set_master(dev->pci);
 376         if (!pci_dma_supported(dev->pci,0xffffffff)) {
 377                 printk("%s/2: Oops: no 32bit PCI DMA ???\n",dev->core->name);
 378                 return -EIO;
 379         }
 380
 381         pci_read_config_byte(dev->pci, PCI_CLASS_REVISION, &dev->pci_rev);
 382         pci_read_config_byte(dev->pci, PCI_LATENCY_TIMER,  &dev->pci_lat);
 383         printk(KERN_INFO "%s/2: found at %s, rev: %d, irq: %d, "
 384                "latency: %d, mmio: 0x%lx\n", dev->core->name,
 385                pci_name(dev->pci), dev->pci_rev, dev->pci->irq,
 386                dev->pci_lat,pci_resource_start(dev->pci,0));
 387
 388         /* initialize driver struct */
 389         spin_lock_init(&dev->slock);
 390
 391         /* init dma queue */
 392         INIT_LIST_HEAD(&dev->mpegq.active);
 393         INIT_LIST_HEAD(&dev->mpegq.queued);
 394         dev->mpegq.timeout.function = cx8802_timeout;
 395         dev->mpegq.timeout.data     = (unsigned long)dev;
 396         init_timer(&dev->mpegq.timeout);
 397         cx88_risc_stopper(dev->pci,&dev->mpegq.stopper,
 398                           MO_TS_DMACNTRL,0x11,0x00);
 399
 400         /* get irq */
 401         err = request_irq(dev->pci->irq, cx8802_irq,
 402                           SA_SHIRQ | SA_INTERRUPT, dev->core->name, dev);
 403         if (err < 0) {
 404                 printk(KERN_ERR "%s: can't get IRQ %d\n",
 405                        dev->core->name, dev->pci->irq);
 406                 return err;
 407         }
 408         cx_set(MO_PCI_INTMSK, core->pci_irqmask);
 409
 410         /* everything worked */
 411         pci_set_drvdata(dev->pci,dev);
 412         return 0;
 413 }
 414
 415 void cx8802_fini_common(struct cx8802_dev *dev)
 416 {
 417         dprintk( 2, "cx8802_fini_common\n" );
 418         cx8802_stop_dma(dev);
 419         pci_disable_device(dev->pci);
 420
 421         /* unregister stuff */
 422         free_irq(dev->pci->irq, dev);
 423         pci_set_drvdata(dev->pci, NULL);
 424
 425         /* free memory */
 426         btcx_riscmem_free(dev->pci,&dev->mpegq.stopper);
 427 }
 428
 429 /* ----------------------------------------------------------- */
 430
 431 int cx8802_suspend_common(struct pci_dev *pci_dev, pm_message_t state)
 432 {
 433         struct cx8802_dev *dev = pci_get_drvdata(pci_dev);
 434         struct cx88_core *core = dev->core;
 435
 436         /* stop mpeg dma */
 437         spin_lock(&dev->slock);
 438         if (!list_empty(&dev->mpegq.active)) {
 439                 dprintk( 2, "suspend\n" );
 440                 printk("%s: suspend mpeg\n", core->name);
 441                 cx8802_stop_dma(dev);
 442                 del_timer(&dev->mpegq.timeout);
 443         }
 444         spin_unlock(&dev->slock);
 445
 446         /* FIXME -- shutdown device */
 447         cx88_shutdown(dev->core);
 448
 449         pci_save_state(pci_dev);
 450         if (0 != pci_set_power_state(pci_dev, pci_choose_state(pci_dev, state))) {
 451                 pci_disable_device(pci_dev);
 452                 dev->state.disabled = 1;
 453         }
 454         return 0;
 455 }
 456
 457 int cx8802_resume_common(struct pci_dev *pci_dev)
 458 {
 459         struct cx8802_dev *dev = pci_get_drvdata(pci_dev);
 460         struct cx88_core *core = dev->core;
 461         int err;
 462
 463         if (dev->state.disabled) {
 464                 err=pci_enable_device(pci_dev);
 465                 if (err) {
 466                         printk(KERN_ERR "%s: can't enable device\n",
 467                                                dev->core->name);
 468                         return err;
 469                 }
 470                 dev->state.disabled = 0;
 471         }
 472         err=pci_set_power_state(pci_dev, PCI_D0);
 473         if (err) {
 474                 printk(KERN_ERR "%s: can't enable device\n",
 475                                                dev->core->name);
 476                 pci_disable_device(pci_dev);
 477                 dev->state.disabled = 1;
 478
 479                 return err;
 480         }
 481         pci_restore_state(pci_dev);
 482
 483         /* FIXME: re-initialize hardware */
 484         cx88_reset(dev->core);
 485
 486         /* restart video+vbi capture */
 487         spin_lock(&dev->slock);
 488         if (!list_empty(&dev->mpegq.active)) {
 489                 printk("%s: resume mpeg\n", core->name);
 490                 cx8802_restart_queue(dev,&dev->mpegq);
 491         }
 492         spin_unlock(&dev->slock);
 493
 494         return 0;
 495 }
 496
 497 /* ----------------------------------------------------------- */
 498
 499 EXPORT_SYMBOL(cx8802_buf_prepare);
 500 EXPORT_SYMBOL(cx8802_buf_queue);
 501 EXPORT_SYMBOL(cx8802_cancel_buffers);
 502
 503 EXPORT_SYMBOL(cx8802_init_common);
 504 EXPORT_SYMBOL(cx8802_fini_common);
 505
 506 EXPORT_SYMBOL(cx8802_suspend_common);
 507 EXPORT_SYMBOL(cx8802_resume_common);
 508
 509 /* ----------------------------------------------------------- */
 510 /*
 511  * Local variables:
 512  * c-basic-offset: 8
 513  * End:
 514  * kate: eol "unix"; indent-width 3; remove-trailing-space on; replace-trailing-space-save on; tab-width 8; replace-tabs off; space-indent off; mixed-indent off
 515  */