1 #ifndef __ASM_MACH_APIC_H
2 #define __ASM_MACH_APIC_H
5 extern u8 bios_cpu_apicid[];
7 #define xapic_phys_to_log_apicid(cpu) (bios_cpu_apicid[cpu])
8 #define esr_disable (1)
10 static inline int apic_id_registered(void)
15 /* Round robin the irqs amoung the online cpus */
16 static inline cpumask_t target_cpus(void)
18 static unsigned long cpu = NR_CPUS;
21 cpu = first_cpu(cpu_online_map);
23 cpu = next_cpu(cpu, cpu_online_map);
24 } while (cpu >= NR_CPUS);
25 return cpumask_of_cpu(cpu);
28 #undef APIC_DEST_LOGICAL
29 #define APIC_DEST_LOGICAL 0
30 #define TARGET_CPUS (target_cpus())
31 #define APIC_DFR_VALUE (APIC_DFR_FLAT)
32 #define INT_DELIVERY_MODE (dest_Fixed)
33 #define INT_DEST_MODE (0) /* phys delivery to target proc */
34 #define NO_BALANCE_IRQ (0)
35 #define WAKE_SECONDARY_VIA_INIT
38 static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid)
43 static inline unsigned long check_apicid_present(int bit)
48 static inline unsigned long calculate_ldr(int cpu)
50 unsigned long val, id;
51 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
52 id = xapic_phys_to_log_apicid(cpu);
53 val |= SET_APIC_LOGICAL_ID(id);
58 * Set up the logical destination ID.
60 * Intel recommends to set DFR, LDR and TPR before enabling
61 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
62 * document number 292116). So here it goes...
64 static inline void init_apic_ldr(void)
67 int cpu = smp_processor_id();
69 apic_write_around(APIC_DFR, APIC_DFR_VALUE);
70 val = calculate_ldr(cpu);
71 apic_write_around(APIC_LDR, val);
74 static inline void clustered_apic_check(void)
76 printk("Enabling APIC mode: %s. Using %d I/O APICs\n",
77 "Physflat", nr_ioapics);
80 static inline int multi_timer_check(int apic, int irq)
85 static inline int apicid_to_node(int logical_apicid)
90 static inline int cpu_present_to_apicid(int mps_cpu)
92 if (mps_cpu < NR_CPUS)
93 return (int) bios_cpu_apicid[mps_cpu];
98 static inline physid_mask_t apicid_to_cpu_present(int phys_apicid)
100 return physid_mask_of_physid(phys_apicid);
103 extern u8 cpu_2_logical_apicid[];
104 /* Mapping from cpu number to logical apicid */
105 static inline int cpu_to_logical_apicid(int cpu)
109 return cpu_physical_id(cpu);
112 static inline int mpc_apic_id(struct mpc_config_processor *m,
113 struct mpc_config_translation *translation_record)
115 printk("Processor #%d %ld:%ld APIC version %d\n",
117 (m->mpc_cpufeature & CPU_FAMILY_MASK) >> 8,
118 (m->mpc_cpufeature & CPU_MODEL_MASK) >> 4,
120 return m->mpc_apicid;
123 static inline physid_mask_t ioapic_phys_id_map(physid_mask_t phys_map)
125 /* For clustered we don't have a good way to do this yet - hack */
126 return physids_promote(0xFFL);
129 static inline void setup_portio_remap(void)
133 static inline void enable_apic_mode(void)
137 static inline int check_phys_apicid_present(int boot_cpu_physical_apicid)
142 /* As we are using single CPU as destination, pick only one CPU here */
143 static inline unsigned int cpu_mask_to_apicid(cpumask_t cpumask)
148 cpu = first_cpu(cpumask);
149 apicid = cpu_to_logical_apicid(cpu);
153 static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb)
155 return cpuid_apic >> index_msb;
158 #endif /* __ASM_MACH_APIC_H */