git.oblomov.eu Git - linux-2.6/blob - arch/powerpc/boot/dts/mpc8548cds.dts

   1 /*
   2  * MPC8555 CDS Device Tree Source
   3  *
   4  * Copyright 2006 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12
  13 / {
  14         model = "MPC8548CDS";
  15         compatible = "MPC8548CDS", "MPC85xxCDS";
  16         #address-cells = <1>;
  17         #size-cells = <1>;
  18
  19         cpus {
  20                 #address-cells = <1>;
  21                 #size-cells = <0>;
  22
  23                 PowerPC,8548@0 {
  24                         device_type = "cpu";
  25                         reg = <0>;
  26                         d-cache-line-size = <20>;       // 32 bytes
  27                         i-cache-line-size = <20>;       // 32 bytes
  28                         d-cache-size = <8000>;          // L1, 32K
  29                         i-cache-size = <8000>;          // L1, 32K
  30                         timebase-frequency = <0>;       //  33 MHz, from uboot
  31                         bus-frequency = <0>;    // 166 MHz
  32                         clock-frequency = <0>;  // 825 MHz, from uboot
  33                         32-bit;
  34                 };
  35         };
  36
  37         memory {
  38                 device_type = "memory";
  39                 reg = <00000000 08000000>;      // 128M at 0x0
  40         };
  41
  42         soc8548@e0000000 {
  43                 #address-cells = <1>;
  44                 #size-cells = <1>;
  45                 #interrupt-cells = <2>;
  46                 device_type = "soc";
  47                 ranges = <0 e0000000 00100000>;
  48                 reg = <e0000000 00100000>;      // CCSRBAR 1M
  49                 bus-frequency = <0>;
  50
  51                 i2c@3000 {
  52                         device_type = "i2c";
  53                         compatible = "fsl-i2c";
  54                         reg = <3000 100>;
  55                         interrupts = <1b 2>;
  56                         interrupt-parent = <&mpic>;
  57                         dfsrr;
  58                 };
  59
  60                 mdio@24520 {
  61                         #address-cells = <1>;
  62                         #size-cells = <0>;
  63                         device_type = "mdio";
  64                         compatible = "gianfar";
  65                         reg = <24520 20>;
  66                         phy0: ethernet-phy@0 {
  67                                 interrupt-parent = <&mpic>;
  68                                 interrupts = <35 0>;
  69                                 reg = <0>;
  70                                 device_type = "ethernet-phy";
  71                         };
  72                         phy1: ethernet-phy@1 {
  73                                 interrupt-parent = <&mpic>;
  74                                 interrupts = <35 0>;
  75                                 reg = <1>;
  76                                 device_type = "ethernet-phy";
  77                         };
  78                         phy2: ethernet-phy@2 {
  79                                 interrupt-parent = <&mpic>;
  80                                 interrupts = <35 0>;
  81                                 reg = <2>;
  82                                 device_type = "ethernet-phy";
  83                         };
  84                         phy3: ethernet-phy@3 {
  85                                 interrupt-parent = <&mpic>;
  86                                 interrupts = <35 0>;
  87                                 reg = <3>;
  88                                 device_type = "ethernet-phy";
  89                         };
  90                 };
  91
  92                 ethernet@24000 {
  93                         #address-cells = <1>;
  94                         #size-cells = <0>;
  95                         device_type = "network";
  96                         model = "eTSEC";
  97                         compatible = "gianfar";
  98                         reg = <24000 1000>;
  99                         local-mac-address = [ 00 E0 0C 00 73 00 ];
 100                         interrupts = <d 2 e 2 12 2>;
 101                         interrupt-parent = <&mpic>;
 102                         phy-handle = <&phy0>;
 103                 };
 104
 105                 ethernet@25000 {
 106                         #address-cells = <1>;
 107                         #size-cells = <0>;
 108                         device_type = "network";
 109                         model = "eTSEC";
 110                         compatible = "gianfar";
 111                         reg = <25000 1000>;
 112                         local-mac-address = [ 00 E0 0C 00 73 01 ];
 113                         interrupts = <13 2 14 2 18 2>;
 114                         interrupt-parent = <&mpic>;
 115                         phy-handle = <&phy1>;
 116                 };
 117
 118 /* eTSEC 3/4 are currently broken
 119                 ethernet@26000 {
 120                         #address-cells = <1>;
 121                         #size-cells = <0>;
 122                         device_type = "network";
 123                         model = "eTSEC";
 124                         compatible = "gianfar";
 125                         reg = <26000 1000>;
 126                         local-mac-address = [ 00 E0 0C 00 73 02 ];
 127                         interrupts = <f 2 10 2 11 2>;
 128                         interrupt-parent = <&mpic>;
 129                         phy-handle = <&phy2>;
 130                 };
 131
 132                 ethernet@27000 {
 133                         #address-cells = <1>;
 134                         #size-cells = <0>;
 135                         device_type = "network";
 136                         model = "eTSEC";
 137                         compatible = "gianfar";
 138                         reg = <27000 1000>;
 139                         local-mac-address = [ 00 E0 0C 00 73 03 ];
 140                         interrupts = <15 2 16 2 17 2>;
 141                         interrupt-parent = <&mpic>;
 142                         phy-handle = <&phy3>;
 143                 };
 144  */
 145
 146                 serial@4500 {
 147                         device_type = "serial";
 148                         compatible = "ns16550";
 149                         reg = <4500 100>;       // reg base, size
 150                         clock-frequency = <0>;  // should we fill in in uboot?
 151                         interrupts = <1a 2>;
 152                         interrupt-parent = <&mpic>;
 153                 };
 154
 155                 serial@4600 {
 156                         device_type = "serial";
 157                         compatible = "ns16550";
 158                         reg = <4600 100>;       // reg base, size
 159                         clock-frequency = <0>;  // should we fill in in uboot?
 160                         interrupts = <1a 2>;
 161                         interrupt-parent = <&mpic>;
 162                 };
 163
 164                 pci1: pci@8000 {
 165                         interrupt-map-mask = <1f800 0 0 7>;
 166                         interrupt-map = <
 167
 168                                 /* IDSEL 0x10 */
 169                                 08000 0 0 1 &mpic 30 1
 170                                 08000 0 0 2 &mpic 31 1
 171                                 08000 0 0 3 &mpic 32 1
 172                                 08000 0 0 4 &mpic 33 1
 173
 174                                 /* IDSEL 0x11 */
 175                                 08800 0 0 1 &mpic 30 1
 176                                 08800 0 0 2 &mpic 31 1
 177                                 08800 0 0 3 &mpic 32 1
 178                                 08800 0 0 4 &mpic 33 1
 179
 180                                 /* IDSEL 0x12 (Slot 1) */
 181                                 09000 0 0 1 &mpic 30 1
 182                                 09000 0 0 2 &mpic 31 1
 183                                 09000 0 0 3 &mpic 32 1
 184                                 09000 0 0 4 &mpic 33 1
 185
 186                                 /* IDSEL 0x13 (Slot 2) */
 187                                 09800 0 0 1 &mpic 31 1
 188                                 09800 0 0 2 &mpic 32 1
 189                                 09800 0 0 3 &mpic 33 1
 190                                 09800 0 0 4 &mpic 30 1
 191
 192                                 /* IDSEL 0x14 (Slot 3) */
 193                                 0a000 0 0 1 &mpic 32 1
 194                                 0a000 0 0 2 &mpic 33 1
 195                                 0a000 0 0 3 &mpic 30 1
 196                                 0a000 0 0 4 &mpic 31 1
 197
 198                                 /* IDSEL 0x15 (Slot 4) */
 199                                 0a800 0 0 1 &mpic 33 1
 200                                 0a800 0 0 2 &mpic 30 1
 201                                 0a800 0 0 3 &mpic 31 1
 202                                 0a800 0 0 4 &mpic 32 1
 203
 204                                 /* Bus 1 (Tundra Bridge) */
 205                                 /* IDSEL 0x12 (ISA bridge) */
 206                                 19000 0 0 1 &mpic 30 1
 207                                 19000 0 0 2 &mpic 31 1
 208                                 19000 0 0 3 &mpic 32 1
 209                                 19000 0 0 4 &mpic 33 1>;
 210                         interrupt-parent = <&mpic>;
 211                         interrupts = <08 2>;
 212                         bus-range = <0 0>;
 213                         ranges = <02000000 0 80000000 80000000 0 20000000
 214                                   01000000 0 00000000 e2000000 0 00100000>;
 215                         clock-frequency = <3f940aa>;
 216                         #interrupt-cells = <1>;
 217                         #size-cells = <2>;
 218                         #address-cells = <3>;
 219                         reg = <8000 1000>;
 220                         compatible = "85xx";
 221                         device_type = "pci";
 222
 223                         i8259@19000 {
 224                                 clock-frequency = <0>;
 225                                 interrupt-controller;
 226                                 device_type = "interrupt-controller";
 227                                 reg = <19000 0 0 0 1>;
 228                                 #address-cells = <0>;
 229                                 #interrupt-cells = <2>;
 230                                 built-in;
 231                                 compatible = "chrp,iic";
 232                                 big-endian;
 233                                 interrupts = <1>;
 234                                 interrupt-parent = <&pci1>;
 235                         };
 236                 };
 237
 238                 pci@9000 {
 239                         interrupt-map-mask = <f800 0 0 7>;
 240                         interrupt-map = <
 241
 242                                 /* IDSEL 0x15 */
 243                                 a800 0 0 1 &mpic 3b 1
 244                                 a800 0 0 2 &mpic 3b 1
 245                                 a800 0 0 3 &mpic 3b 1
 246                                 a800 0 0 4 &mpic 3b 1>;
 247                         interrupt-parent = <&mpic>;
 248                         interrupts = <09 2>;
 249                         bus-range = <0 0>;
 250                         ranges = <02000000 0 a0000000 a0000000 0 20000000
 251                                   01000000 0 00000000 e3000000 0 00100000>;
 252                         clock-frequency = <3f940aa>;
 253                         #interrupt-cells = <1>;
 254                         #size-cells = <2>;
 255                         #address-cells = <3>;
 256                         reg = <9000 1000>;
 257                         compatible = "85xx";
 258                         device_type = "pci";
 259                 };
 260
 261                 mpic: pic@40000 {
 262                         clock-frequency = <0>;
 263                         interrupt-controller;
 264                         #address-cells = <0>;
 265                         #interrupt-cells = <2>;
 266                         reg = <40000 40000>;
 267                         built-in;
 268                         compatible = "chrp,open-pic";
 269                         device_type = "open-pic";
 270                         big-endian;
 271                 };
 272         };
 273 };