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   1 /*
   2  * linux/arch/arm/mach-omap1/pm.c
   3  *
   4  * OMAP Power Management Routines
   5  *
   6  * Original code for the SA11x0:
   7  * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
   8  *
   9  * Modified for the PXA250 by Nicolas Pitre:
  10  * Copyright (c) 2002 Monta Vista Software, Inc.
  11  *
  12  * Modified for the OMAP1510 by David Singleton:
  13  * Copyright (c) 2002 Monta Vista Software, Inc.
  14  *
  15  * Cleanup 2004 for OMAP1510/1610 by Dirk Behme <dirk.behme@de.bosch.com>
  16  *
  17  * This program is free software; you can redistribute it and/or modify it
  18  * under the terms of the GNU General Public License as published by the
  19  * Free Software Foundation; either version 2 of the License, or (at your
  20  * option) any later version.
  21  *
  22  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  23  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  24  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  25  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  26  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  27  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  28  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  29  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  31  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  * You should have received a copy of the GNU General Public License along
  34  * with this program; if not, write to the Free Software Foundation, Inc.,
  35  * 675 Mass Ave, Cambridge, MA 02139, USA.
  36  */
  37
  38 #include <linux/pm.h>
  39 #include <linux/sched.h>
  40 #include <linux/proc_fs.h>
  41 #include <linux/pm.h>
  42 #include <linux/interrupt.h>
  43 #include <linux/sysfs.h>
  44 #include <linux/module.h>
  45
  46 #include <asm/io.h>
  47 #include <asm/irq.h>
  48 #include <asm/atomic.h>
  49 #include <asm/mach/time.h>
  50 #include <asm/mach/irq.h>
  51 #include <asm/mach-types.h>
  52
  53 #include <asm/arch/cpu.h>
  54 #include <asm/arch/irqs.h>
  55 #include <asm/arch/clock.h>
  56 #include <asm/arch/sram.h>
  57 #include <asm/arch/tc.h>
  58 #include <asm/arch/pm.h>
  59 #include <asm/arch/mux.h>
  60 #include <asm/arch/tps65010.h>
  61 #include <asm/arch/dma.h>
  62 #include <asm/arch/dsp_common.h>
  63 #include <asm/arch/dmtimer.h>
  64
  65 static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE];
  66 static unsigned short dsp_sleep_save[DSP_SLEEP_SAVE_SIZE];
  67 static unsigned short ulpd_sleep_save[ULPD_SLEEP_SAVE_SIZE];
  68 static unsigned int mpui730_sleep_save[MPUI730_SLEEP_SAVE_SIZE];
  69 static unsigned int mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_SIZE];
  70 static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE];
  71
  72 static unsigned short enable_dyn_sleep = 1;
  73
  74 static ssize_t omap_pm_sleep_while_idle_show(struct kset *kset, char *buf)
  75 {
  76         return sprintf(buf, "%hu\n", enable_dyn_sleep);
  77 }
  78
  79 static ssize_t omap_pm_sleep_while_idle_store(struct kset *kset,
  80                                               const char * buf,
  81                                               size_t n)
  82 {
  83         unsigned short value;
  84         if (sscanf(buf, "%hu", &value) != 1 ||
  85             (value != 0 && value != 1)) {
  86                 printk(KERN_ERR "idle_sleep_store: Invalid value\n");
  87                 return -EINVAL;
  88         }
  89         enable_dyn_sleep = value;
  90         return n;
  91 }
  92
  93 static struct subsys_attribute sleep_while_idle_attr = {
  94         .attr   = {
  95                 .name = __stringify(sleep_while_idle),
  96                 .mode = 0644,
  97         },
  98         .show   = omap_pm_sleep_while_idle_show,
  99         .store  = omap_pm_sleep_while_idle_store,
 100 };
 101
 102 extern struct kset power_subsys;
 103 static void (*omap_sram_idle)(void) = NULL;
 104 static void (*omap_sram_suspend)(unsigned long r0, unsigned long r1) = NULL;
 105
 106 /*
 107  * Let's power down on idle, but only if we are really
 108  * idle, because once we start down the path of
 109  * going idle we continue to do idle even if we get
 110  * a clock tick interrupt . .
 111  */
 112 void omap_pm_idle(void)
 113 {
 114         extern __u32 arm_idlect1_mask;
 115         __u32 use_idlect1 = arm_idlect1_mask;
 116 #ifndef CONFIG_OMAP_MPU_TIMER
 117         int do_sleep;
 118 #endif
 119
 120         local_irq_disable();
 121         local_fiq_disable();
 122         if (need_resched()) {
 123                 local_fiq_enable();
 124                 local_irq_enable();
 125                 return;
 126         }
 127
 128         /*
 129          * Since an interrupt may set up a timer, we don't want to
 130          * reprogram the hardware timer with interrupts enabled.
 131          * Re-enable interrupts only after returning from idle.
 132          */
 133         timer_dyn_reprogram();
 134
 135 #ifdef CONFIG_OMAP_MPU_TIMER
 136 #warning Enable 32kHz OS timer in order to allow sleep states in idle
 137         use_idlect1 = use_idlect1 & ~(1 << 9);
 138 #else
 139
 140         do_sleep = 0;
 141         while (enable_dyn_sleep) {
 142
 143 #ifdef CONFIG_CBUS_TAHVO_USB
 144                 extern int vbus_active;
 145                 /* Clock requirements? */
 146                 if (vbus_active)
 147                         break;
 148 #endif
 149                 do_sleep = 1;
 150                 break;
 151         }
 152
 153 #ifdef CONFIG_OMAP_DM_TIMER
 154         use_idlect1 = omap_dm_timer_modify_idlect_mask(use_idlect1);
 155 #endif
 156
 157         if (omap_dma_running()) {
 158                 use_idlect1 &= ~(1 << 6);
 159                 if (omap_lcd_dma_ext_running())
 160                         use_idlect1 &= ~(1 << 12);
 161         }
 162
 163         /* We should be able to remove the do_sleep variable and multiple
 164          * tests above as soon as drivers, timer and DMA code have been fixed.
 165          * Even the sleep block count should become obsolete. */
 166         if ((use_idlect1 != ~0) || !do_sleep) {
 167
 168                 __u32 saved_idlect1 = omap_readl(ARM_IDLECT1);
 169                 if (cpu_is_omap15xx())
 170                         use_idlect1 &= OMAP1510_BIG_SLEEP_REQUEST;
 171                 else
 172                         use_idlect1 &= OMAP1610_IDLECT1_SLEEP_VAL;
 173                 omap_writel(use_idlect1, ARM_IDLECT1);
 174                 __asm__ volatile ("mcr  p15, 0, r0, c7, c0, 4");
 175                 omap_writel(saved_idlect1, ARM_IDLECT1);
 176
 177                 local_fiq_enable();
 178                 local_irq_enable();
 179                 return;
 180         }
 181         omap_sram_suspend(omap_readl(ARM_IDLECT1),
 182                           omap_readl(ARM_IDLECT2));
 183 #endif
 184
 185         local_fiq_enable();
 186         local_irq_enable();
 187 }
 188
 189 /*
 190  * Configuration of the wakeup event is board specific. For the
 191  * moment we put it into this helper function. Later it may move
 192  * to board specific files.
 193  */
 194 static void omap_pm_wakeup_setup(void)
 195 {
 196         u32 level1_wake = 0;
 197         u32 level2_wake = OMAP_IRQ_BIT(INT_UART2);
 198
 199         /*
 200          * Turn off all interrupts except GPIO bank 1, L1-2nd level cascade,
 201          * and the L2 wakeup interrupts: keypad and UART2. Note that the
 202          * drivers must still separately call omap_set_gpio_wakeup() to
 203          * wake up to a GPIO interrupt.
 204          */
 205         if (cpu_is_omap730())
 206                 level1_wake = OMAP_IRQ_BIT(INT_730_GPIO_BANK1) |
 207                         OMAP_IRQ_BIT(INT_730_IH2_IRQ);
 208         else if (cpu_is_omap15xx())
 209                 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
 210                         OMAP_IRQ_BIT(INT_1510_IH2_IRQ);
 211         else if (cpu_is_omap16xx())
 212                 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
 213                         OMAP_IRQ_BIT(INT_1610_IH2_IRQ);
 214
 215         omap_writel(~level1_wake, OMAP_IH1_MIR);
 216
 217         if (cpu_is_omap730()) {
 218                 omap_writel(~level2_wake, OMAP_IH2_0_MIR);
 219                 omap_writel(~(OMAP_IRQ_BIT(INT_730_WAKE_UP_REQ) |
 220                                 OMAP_IRQ_BIT(INT_730_MPUIO_KEYPAD)),
 221                                 OMAP_IH2_1_MIR);
 222         } else if (cpu_is_omap15xx()) {
 223                 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
 224                 omap_writel(~level2_wake,  OMAP_IH2_MIR);
 225         } else if (cpu_is_omap16xx()) {
 226                 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
 227                 omap_writel(~level2_wake, OMAP_IH2_0_MIR);
 228
 229                 /* INT_1610_WAKE_UP_REQ is needed for GPIO wakeup... */
 230                 omap_writel(~OMAP_IRQ_BIT(INT_1610_WAKE_UP_REQ),
 231                             OMAP_IH2_1_MIR);
 232                 omap_writel(~0x0, OMAP_IH2_2_MIR);
 233                 omap_writel(~0x0, OMAP_IH2_3_MIR);
 234         }
 235
 236         /*  New IRQ agreement, recalculate in cascade order */
 237         omap_writel(1, OMAP_IH2_CONTROL);
 238         omap_writel(1, OMAP_IH1_CONTROL);
 239 }
 240
 241 #define EN_DSPCK        13      /* ARM_CKCTL */
 242 #define EN_APICK        6       /* ARM_IDLECT2 */
 243 #define DSP_EN          1       /* ARM_RSTCT1 */
 244
 245 void omap_pm_suspend(void)
 246 {
 247         unsigned long arg0 = 0, arg1 = 0;
 248
 249         printk("PM: OMAP%x is trying to enter deep sleep...\n", system_rev);
 250
 251         omap_serial_wake_trigger(1);
 252
 253         if (machine_is_omap_osk()) {
 254                 /* Stop LED1 (D9) blink */
 255                 tps65010_set_led(LED1, OFF);
 256         }
 257
 258         if (!cpu_is_omap15xx())
 259                 omap_writew(0xffff, ULPD_SOFT_DISABLE_REQ_REG);
 260
 261         /*
 262          * Step 1: turn off interrupts (FIXME: NOTE: already disabled)
 263          */
 264
 265         local_irq_disable();
 266         local_fiq_disable();
 267
 268         /*
 269          * Step 2: save registers
 270          *
 271          * The omap is a strange/beautiful device. The caches, memory
 272          * and register state are preserved across power saves.
 273          * We have to save and restore very little register state to
 274          * idle the omap.
 275          *
 276          * Save interrupt, MPUI, ARM and UPLD control registers.
 277          */
 278
 279         if (cpu_is_omap730()) {
 280                 MPUI730_SAVE(OMAP_IH1_MIR);
 281                 MPUI730_SAVE(OMAP_IH2_0_MIR);
 282                 MPUI730_SAVE(OMAP_IH2_1_MIR);
 283                 MPUI730_SAVE(MPUI_CTRL);
 284                 MPUI730_SAVE(MPUI_DSP_BOOT_CONFIG);
 285                 MPUI730_SAVE(MPUI_DSP_API_CONFIG);
 286                 MPUI730_SAVE(EMIFS_CONFIG);
 287                 MPUI730_SAVE(EMIFF_SDRAM_CONFIG);
 288
 289         } else if (cpu_is_omap15xx()) {
 290                 MPUI1510_SAVE(OMAP_IH1_MIR);
 291                 MPUI1510_SAVE(OMAP_IH2_MIR);
 292                 MPUI1510_SAVE(MPUI_CTRL);
 293                 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
 294                 MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
 295                 MPUI1510_SAVE(EMIFS_CONFIG);
 296                 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
 297         } else if (cpu_is_omap16xx()) {
 298                 MPUI1610_SAVE(OMAP_IH1_MIR);
 299                 MPUI1610_SAVE(OMAP_IH2_0_MIR);
 300                 MPUI1610_SAVE(OMAP_IH2_1_MIR);
 301                 MPUI1610_SAVE(OMAP_IH2_2_MIR);
 302                 MPUI1610_SAVE(OMAP_IH2_3_MIR);
 303                 MPUI1610_SAVE(MPUI_CTRL);
 304                 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
 305                 MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
 306                 MPUI1610_SAVE(EMIFS_CONFIG);
 307                 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
 308         }
 309
 310         ARM_SAVE(ARM_CKCTL);
 311         ARM_SAVE(ARM_IDLECT1);
 312         ARM_SAVE(ARM_IDLECT2);
 313         if (!(cpu_is_omap15xx()))
 314                 ARM_SAVE(ARM_IDLECT3);
 315         ARM_SAVE(ARM_EWUPCT);
 316         ARM_SAVE(ARM_RSTCT1);
 317         ARM_SAVE(ARM_RSTCT2);
 318         ARM_SAVE(ARM_SYSST);
 319         ULPD_SAVE(ULPD_CLOCK_CTRL);
 320         ULPD_SAVE(ULPD_STATUS_REQ);
 321
 322         /* (Step 3 removed - we now allow deep sleep by default) */
 323
 324         /*
 325          * Step 4: OMAP DSP Shutdown
 326          */
 327
 328         /* stop DSP */
 329         omap_writew(omap_readw(ARM_RSTCT1) & ~(1 << DSP_EN), ARM_RSTCT1);
 330
 331                 /* shut down dsp_ck */
 332         if (!cpu_is_omap730())
 333                 omap_writew(omap_readw(ARM_CKCTL) & ~(1 << EN_DSPCK), ARM_CKCTL);
 334
 335         /* temporarily enabling api_ck to access DSP registers */
 336         omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2);
 337
 338         /* save DSP registers */
 339         DSP_SAVE(DSP_IDLECT2);
 340
 341         /* Stop all DSP domain clocks */
 342         __raw_writew(0, DSP_IDLECT2);
 343
 344         /*
 345          * Step 5: Wakeup Event Setup
 346          */
 347
 348         omap_pm_wakeup_setup();
 349
 350         /*
 351          * Step 6: ARM and Traffic controller shutdown
 352          */
 353
 354         /* disable ARM watchdog */
 355         omap_writel(0x00F5, OMAP_WDT_TIMER_MODE);
 356         omap_writel(0x00A0, OMAP_WDT_TIMER_MODE);
 357
 358         /*
 359          * Step 6b: ARM and Traffic controller shutdown
 360          *
 361          * Step 6 continues here. Prepare jump to power management
 362          * assembly code in internal SRAM.
 363          *
 364          * Since the omap_cpu_suspend routine has been copied to
 365          * SRAM, we'll do an indirect procedure call to it and pass the
 366          * contents of arm_idlect1 and arm_idlect2 so it can restore
 367          * them when it wakes up and it will return.
 368          */
 369
 370         arg0 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT1];
 371         arg1 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT2];
 372
 373         /*
 374          * Step 6c: ARM and Traffic controller shutdown
 375          *
 376          * Jump to assembly code. The processor will stay there
 377          * until wake up.
 378          */
 379         omap_sram_suspend(arg0, arg1);
 380
 381         /*
 382          * If we are here, processor is woken up!
 383          */
 384
 385         /*
 386          * Restore DSP clocks
 387          */
 388
 389         /* again temporarily enabling api_ck to access DSP registers */
 390         omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2);
 391
 392         /* Restore DSP domain clocks */
 393         DSP_RESTORE(DSP_IDLECT2);
 394
 395         /*
 396          * Restore ARM state, except ARM_IDLECT1/2 which omap_cpu_suspend did
 397          */
 398
 399         if (!(cpu_is_omap15xx()))
 400                 ARM_RESTORE(ARM_IDLECT3);
 401         ARM_RESTORE(ARM_CKCTL);
 402         ARM_RESTORE(ARM_EWUPCT);
 403         ARM_RESTORE(ARM_RSTCT1);
 404         ARM_RESTORE(ARM_RSTCT2);
 405         ARM_RESTORE(ARM_SYSST);
 406         ULPD_RESTORE(ULPD_CLOCK_CTRL);
 407         ULPD_RESTORE(ULPD_STATUS_REQ);
 408
 409         if (cpu_is_omap730()) {
 410                 MPUI730_RESTORE(EMIFS_CONFIG);
 411                 MPUI730_RESTORE(EMIFF_SDRAM_CONFIG);
 412                 MPUI730_RESTORE(OMAP_IH1_MIR);
 413                 MPUI730_RESTORE(OMAP_IH2_0_MIR);
 414                 MPUI730_RESTORE(OMAP_IH2_1_MIR);
 415         } else if (cpu_is_omap15xx()) {
 416                 MPUI1510_RESTORE(MPUI_CTRL);
 417                 MPUI1510_RESTORE(MPUI_DSP_BOOT_CONFIG);
 418                 MPUI1510_RESTORE(MPUI_DSP_API_CONFIG);
 419                 MPUI1510_RESTORE(EMIFS_CONFIG);
 420                 MPUI1510_RESTORE(EMIFF_SDRAM_CONFIG);
 421                 MPUI1510_RESTORE(OMAP_IH1_MIR);
 422                 MPUI1510_RESTORE(OMAP_IH2_MIR);
 423         } else if (cpu_is_omap16xx()) {
 424                 MPUI1610_RESTORE(MPUI_CTRL);
 425                 MPUI1610_RESTORE(MPUI_DSP_BOOT_CONFIG);
 426                 MPUI1610_RESTORE(MPUI_DSP_API_CONFIG);
 427                 MPUI1610_RESTORE(EMIFS_CONFIG);
 428                 MPUI1610_RESTORE(EMIFF_SDRAM_CONFIG);
 429
 430                 MPUI1610_RESTORE(OMAP_IH1_MIR);
 431                 MPUI1610_RESTORE(OMAP_IH2_0_MIR);
 432                 MPUI1610_RESTORE(OMAP_IH2_1_MIR);
 433                 MPUI1610_RESTORE(OMAP_IH2_2_MIR);
 434                 MPUI1610_RESTORE(OMAP_IH2_3_MIR);
 435         }
 436
 437         if (!cpu_is_omap15xx())
 438                 omap_writew(0, ULPD_SOFT_DISABLE_REQ_REG);
 439
 440         /*
 441          * Re-enable interrupts
 442          */
 443
 444         local_irq_enable();
 445         local_fiq_enable();
 446
 447         omap_serial_wake_trigger(0);
 448
 449         printk("PM: OMAP%x is re-starting from deep sleep...\n", system_rev);
 450
 451         if (machine_is_omap_osk()) {
 452                 /* Let LED1 (D9) blink again */
 453                 tps65010_set_led(LED1, BLINK);
 454         }
 455 }
 456
 457 #if defined(DEBUG) && defined(CONFIG_PROC_FS)
 458 static int g_read_completed;
 459
 460 /*
 461  * Read system PM registers for debugging
 462  */
 463 static int omap_pm_read_proc(
 464         char *page_buffer,
 465         char **my_first_byte,
 466         off_t virtual_start,
 467         int length,
 468         int *eof,
 469         void *data)
 470 {
 471         int my_buffer_offset = 0;
 472         char * const my_base = page_buffer;
 473
 474         ARM_SAVE(ARM_CKCTL);
 475         ARM_SAVE(ARM_IDLECT1);
 476         ARM_SAVE(ARM_IDLECT2);
 477         if (!(cpu_is_omap15xx()))
 478                 ARM_SAVE(ARM_IDLECT3);
 479         ARM_SAVE(ARM_EWUPCT);
 480         ARM_SAVE(ARM_RSTCT1);
 481         ARM_SAVE(ARM_RSTCT2);
 482         ARM_SAVE(ARM_SYSST);
 483
 484         ULPD_SAVE(ULPD_IT_STATUS);
 485         ULPD_SAVE(ULPD_CLOCK_CTRL);
 486         ULPD_SAVE(ULPD_SOFT_REQ);
 487         ULPD_SAVE(ULPD_STATUS_REQ);
 488         ULPD_SAVE(ULPD_DPLL_CTRL);
 489         ULPD_SAVE(ULPD_POWER_CTRL);
 490
 491         if (cpu_is_omap730()) {
 492                 MPUI730_SAVE(MPUI_CTRL);
 493                 MPUI730_SAVE(MPUI_DSP_STATUS);
 494                 MPUI730_SAVE(MPUI_DSP_BOOT_CONFIG);
 495                 MPUI730_SAVE(MPUI_DSP_API_CONFIG);
 496                 MPUI730_SAVE(EMIFF_SDRAM_CONFIG);
 497                 MPUI730_SAVE(EMIFS_CONFIG);
 498         } else if (cpu_is_omap15xx()) {
 499                 MPUI1510_SAVE(MPUI_CTRL);
 500                 MPUI1510_SAVE(MPUI_DSP_STATUS);
 501                 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
 502                 MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
 503                 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
 504                 MPUI1510_SAVE(EMIFS_CONFIG);
 505         } else if (cpu_is_omap16xx()) {
 506                 MPUI1610_SAVE(MPUI_CTRL);
 507                 MPUI1610_SAVE(MPUI_DSP_STATUS);
 508                 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
 509                 MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
 510                 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
 511                 MPUI1610_SAVE(EMIFS_CONFIG);
 512         }
 513
 514         if (virtual_start == 0) {
 515                 g_read_completed = 0;
 516
 517                 my_buffer_offset += sprintf(my_base + my_buffer_offset,
 518                    "ARM_CKCTL_REG:            0x%-8x     \n"
 519                    "ARM_IDLECT1_REG:          0x%-8x     \n"
 520                    "ARM_IDLECT2_REG:          0x%-8x     \n"
 521                    "ARM_IDLECT3_REG:          0x%-8x     \n"
 522                    "ARM_EWUPCT_REG:           0x%-8x     \n"
 523                    "ARM_RSTCT1_REG:           0x%-8x     \n"
 524                    "ARM_RSTCT2_REG:           0x%-8x     \n"
 525                    "ARM_SYSST_REG:            0x%-8x     \n"
 526                    "ULPD_IT_STATUS_REG:       0x%-4x     \n"
 527                    "ULPD_CLOCK_CTRL_REG:      0x%-4x     \n"
 528                    "ULPD_SOFT_REQ_REG:        0x%-4x     \n"
 529                    "ULPD_DPLL_CTRL_REG:       0x%-4x     \n"
 530                    "ULPD_STATUS_REQ_REG:      0x%-4x     \n"
 531                    "ULPD_POWER_CTRL_REG:      0x%-4x     \n",
 532                    ARM_SHOW(ARM_CKCTL),
 533                    ARM_SHOW(ARM_IDLECT1),
 534                    ARM_SHOW(ARM_IDLECT2),
 535                    ARM_SHOW(ARM_IDLECT3),
 536                    ARM_SHOW(ARM_EWUPCT),
 537                    ARM_SHOW(ARM_RSTCT1),
 538                    ARM_SHOW(ARM_RSTCT2),
 539                    ARM_SHOW(ARM_SYSST),
 540                    ULPD_SHOW(ULPD_IT_STATUS),
 541                    ULPD_SHOW(ULPD_CLOCK_CTRL),
 542                    ULPD_SHOW(ULPD_SOFT_REQ),
 543                    ULPD_SHOW(ULPD_DPLL_CTRL),
 544                    ULPD_SHOW(ULPD_STATUS_REQ),
 545                    ULPD_SHOW(ULPD_POWER_CTRL));
 546
 547                 if (cpu_is_omap730()) {
 548                         my_buffer_offset += sprintf(my_base + my_buffer_offset,
 549                            "MPUI730_CTRL_REG         0x%-8x \n"
 550                            "MPUI730_DSP_STATUS_REG:      0x%-8x \n"
 551                            "MPUI730_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
 552                            "MPUI730_DSP_API_CONFIG_REG:  0x%-8x \n"
 553                            "MPUI730_SDRAM_CONFIG_REG:    0x%-8x \n"
 554                            "MPUI730_EMIFS_CONFIG_REG:    0x%-8x \n",
 555                            MPUI730_SHOW(MPUI_CTRL),
 556                            MPUI730_SHOW(MPUI_DSP_STATUS),
 557                            MPUI730_SHOW(MPUI_DSP_BOOT_CONFIG),
 558                            MPUI730_SHOW(MPUI_DSP_API_CONFIG),
 559                            MPUI730_SHOW(EMIFF_SDRAM_CONFIG),
 560                            MPUI730_SHOW(EMIFS_CONFIG));
 561                 } else if (cpu_is_omap15xx()) {
 562                         my_buffer_offset += sprintf(my_base + my_buffer_offset,
 563                            "MPUI1510_CTRL_REG             0x%-8x \n"
 564                            "MPUI1510_DSP_STATUS_REG:      0x%-8x \n"
 565                            "MPUI1510_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
 566                            "MPUI1510_DSP_API_CONFIG_REG:  0x%-8x \n"
 567                            "MPUI1510_SDRAM_CONFIG_REG:    0x%-8x \n"
 568                            "MPUI1510_EMIFS_CONFIG_REG:    0x%-8x \n",
 569                            MPUI1510_SHOW(MPUI_CTRL),
 570                            MPUI1510_SHOW(MPUI_DSP_STATUS),
 571                            MPUI1510_SHOW(MPUI_DSP_BOOT_CONFIG),
 572                            MPUI1510_SHOW(MPUI_DSP_API_CONFIG),
 573                            MPUI1510_SHOW(EMIFF_SDRAM_CONFIG),
 574                            MPUI1510_SHOW(EMIFS_CONFIG));
 575                 } else if (cpu_is_omap16xx()) {
 576                         my_buffer_offset += sprintf(my_base + my_buffer_offset,
 577                            "MPUI1610_CTRL_REG             0x%-8x \n"
 578                            "MPUI1610_DSP_STATUS_REG:      0x%-8x \n"
 579                            "MPUI1610_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
 580                            "MPUI1610_DSP_API_CONFIG_REG:  0x%-8x \n"
 581                            "MPUI1610_SDRAM_CONFIG_REG:    0x%-8x \n"
 582                            "MPUI1610_EMIFS_CONFIG_REG:    0x%-8x \n",
 583                            MPUI1610_SHOW(MPUI_CTRL),
 584                            MPUI1610_SHOW(MPUI_DSP_STATUS),
 585                            MPUI1610_SHOW(MPUI_DSP_BOOT_CONFIG),
 586                            MPUI1610_SHOW(MPUI_DSP_API_CONFIG),
 587                            MPUI1610_SHOW(EMIFF_SDRAM_CONFIG),
 588                            MPUI1610_SHOW(EMIFS_CONFIG));
 589                 }
 590
 591                 g_read_completed++;
 592         } else if (g_read_completed >= 1) {
 593                  *eof = 1;
 594                  return 0;
 595         }
 596         g_read_completed++;
 597
 598         *my_first_byte = page_buffer;
 599         return  my_buffer_offset;
 600 }
 601
 602 static void omap_pm_init_proc(void)
 603 {
 604         struct proc_dir_entry *entry;
 605
 606         entry = create_proc_read_entry("driver/omap_pm",
 607                                        S_IWUSR | S_IRUGO, NULL,
 608                                        omap_pm_read_proc, NULL);
 609 }
 610
 611 #endif /* DEBUG && CONFIG_PROC_FS */
 612
 613 static void (*saved_idle)(void) = NULL;
 614
 615 /*
 616  *      omap_pm_prepare - Do preliminary suspend work.
 617  *      @state:         suspend state we're entering.
 618  *
 619  */
 620 static int omap_pm_prepare(suspend_state_t state)
 621 {
 622         int error = 0;
 623
 624         /* We cannot sleep in idle until we have resumed */
 625         saved_idle = pm_idle;
 626         pm_idle = NULL;
 627
 628         switch (state)
 629         {
 630         case PM_SUSPEND_STANDBY:
 631         case PM_SUSPEND_MEM:
 632                 break;
 633         default:
 634                 return -EINVAL;
 635         }
 636
 637         return error;
 638 }
 639
 640
 641 /*
 642  *      omap_pm_enter - Actually enter a sleep state.
 643  *      @state:         State we're entering.
 644  *
 645  */
 646
 647 static int omap_pm_enter(suspend_state_t state)
 648 {
 649         switch (state)
 650         {
 651         case PM_SUSPEND_STANDBY:
 652         case PM_SUSPEND_MEM:
 653                 omap_pm_suspend();
 654                 break;
 655         default:
 656                 return -EINVAL;
 657         }
 658
 659         return 0;
 660 }
 661
 662
 663 /**
 664  *      omap_pm_finish - Finish up suspend sequence.
 665  *      @state:         State we're coming out of.
 666  *
 667  *      This is called after we wake back up (or if entering the sleep state
 668  *      failed).
 669  */
 670
 671 static int omap_pm_finish(suspend_state_t state)
 672 {
 673         pm_idle = saved_idle;
 674         return 0;
 675 }
 676
 677
 678 static irqreturn_t  omap_wakeup_interrupt(int irq, void *dev)
 679 {
 680         return IRQ_HANDLED;
 681 }
 682
 683 static struct irqaction omap_wakeup_irq = {
 684         .name           = "peripheral wakeup",
 685         .flags          = IRQF_DISABLED,
 686         .handler        = omap_wakeup_interrupt
 687 };
 688
 689
 690
 691 static struct pm_ops omap_pm_ops ={
 692         .prepare        = omap_pm_prepare,
 693         .enter          = omap_pm_enter,
 694         .finish         = omap_pm_finish,
 695         .valid          = pm_valid_only_mem,
 696 };
 697
 698 static int __init omap_pm_init(void)
 699 {
 700         int error;
 701
 702         printk("Power Management for TI OMAP.\n");
 703
 704         /*
 705          * We copy the assembler sleep/wakeup routines to SRAM.
 706          * These routines need to be in SRAM as that's the only
 707          * memory the MPU can see when it wakes up.
 708          */
 709         if (cpu_is_omap730()) {
 710                 omap_sram_idle = omap_sram_push(omap730_idle_loop_suspend,
 711                                                 omap730_idle_loop_suspend_sz);
 712                 omap_sram_suspend = omap_sram_push(omap730_cpu_suspend,
 713                                                    omap730_cpu_suspend_sz);
 714         } else if (cpu_is_omap15xx()) {
 715                 omap_sram_idle = omap_sram_push(omap1510_idle_loop_suspend,
 716                                                 omap1510_idle_loop_suspend_sz);
 717                 omap_sram_suspend = omap_sram_push(omap1510_cpu_suspend,
 718                                                    omap1510_cpu_suspend_sz);
 719         } else if (cpu_is_omap16xx()) {
 720                 omap_sram_idle = omap_sram_push(omap1610_idle_loop_suspend,
 721                                                 omap1610_idle_loop_suspend_sz);
 722                 omap_sram_suspend = omap_sram_push(omap1610_cpu_suspend,
 723                                                    omap1610_cpu_suspend_sz);
 724         }
 725
 726         if (omap_sram_idle == NULL || omap_sram_suspend == NULL) {
 727                 printk(KERN_ERR "PM not initialized: Missing SRAM support\n");
 728                 return -ENODEV;
 729         }
 730
 731         pm_idle = omap_pm_idle;
 732
 733         if (cpu_is_omap730())
 734                 setup_irq(INT_730_WAKE_UP_REQ, &omap_wakeup_irq);
 735         else if (cpu_is_omap16xx())
 736                 setup_irq(INT_1610_WAKE_UP_REQ, &omap_wakeup_irq);
 737
 738         /* Program new power ramp-up time
 739          * (0 for most boards since we don't lower voltage when in deep sleep)
 740          */
 741         omap_writew(ULPD_SETUP_ANALOG_CELL_3_VAL, ULPD_SETUP_ANALOG_CELL_3);
 742
 743         /* Setup ULPD POWER_CTRL_REG - enter deep sleep whenever possible */
 744         omap_writew(ULPD_POWER_CTRL_REG_VAL, ULPD_POWER_CTRL);
 745
 746         /* Configure IDLECT3 */
 747         if (cpu_is_omap730())
 748                 omap_writel(OMAP730_IDLECT3_VAL, OMAP730_IDLECT3);
 749         else if (cpu_is_omap16xx())
 750                 omap_writel(OMAP1610_IDLECT3_VAL, OMAP1610_IDLECT3);
 751
 752         pm_set_ops(&omap_pm_ops);
 753
 754 #if defined(DEBUG) && defined(CONFIG_PROC_FS)
 755         omap_pm_init_proc();
 756 #endif
 757
 758         error = subsys_create_file(&power_subsys, &sleep_while_idle_attr);
 759         if (error)
 760                 printk(KERN_ERR "subsys_create_file failed: %d\n", error);
 761
 762         if (cpu_is_omap16xx()) {
 763                 /* configure LOW_PWR pin */
 764                 omap_cfg_reg(T20_1610_LOW_PWR);
 765         }
 766
 767         return 0;
 768 }
 769 __initcall(omap_pm_init);