2 * linux/arch/arm/mm/cache-v6.S
4 * Copyright (C) 2001 Deep Blue Solutions Ltd.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This is the "shell" of the ARMv6 processor support.
12 #include <linux/linkage.h>
13 #include <linux/init.h>
14 #include <asm/assembler.h>
16 #include "proc-macros.S"
19 #define CACHE_LINE_SIZE 32
20 #define D_CACHE_LINE_SIZE 32
21 #define BTB_FLUSH_SIZE 8
24 * v6_flush_cache_all()
26 * Flush the entire cache.
30 ENTRY(v6_flush_kern_cache_all)
33 mcr p15, 0, r0, c7, c14, 0 @ D cache clean+invalidate
34 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
36 mcr p15, 0, r0, c7, c15, 0 @ Cache clean+invalidate
41 * v6_flush_cache_all()
43 * Flush all TLB entries in a particular address space
45 * - mm - mm_struct describing address space
47 ENTRY(v6_flush_user_cache_all)
51 * v6_flush_cache_range(start, end, flags)
53 * Flush a range of TLB entries in the specified address space.
55 * - start - start address (may not be aligned)
56 * - end - end address (exclusive, may not be aligned)
57 * - flags - vm_area_struct flags describing address space
60 * - we have a VIPT cache.
62 ENTRY(v6_flush_user_cache_range)
66 * v6_coherent_kern_range(start,end)
68 * Ensure that the I and D caches are coherent within specified
69 * region. This is typically used when code has been written to
70 * a memory region, and will be executed.
72 * - start - virtual start address of region
73 * - end - virtual end address of region
76 * - the Icache does not read data from the write buffer
78 ENTRY(v6_coherent_kern_range)
82 * v6_coherent_user_range(start,end)
84 * Ensure that the I and D caches are coherent within specified
85 * region. This is typically used when code has been written to
86 * a memory region, and will be executed.
88 * - start - virtual start address of region
89 * - end - virtual end address of region
92 * - the Icache does not read data from the write buffer
94 ENTRY(v6_coherent_user_range)
95 bic r0, r0, #CACHE_LINE_SIZE - 1
98 mcr p15, 0, r0, c7, c10, 1 @ clean D line
99 mcr p15, 0, r0, c7, c5, 1 @ invalidate I line
101 mcr p15, 0, r0, c7, c5, 7 @ invalidate BTB entry
102 add r0, r0, #BTB_FLUSH_SIZE
103 mcr p15, 0, r0, c7, c5, 7 @ invalidate BTB entry
104 add r0, r0, #BTB_FLUSH_SIZE
105 mcr p15, 0, r0, c7, c5, 7 @ invalidate BTB entry
106 add r0, r0, #BTB_FLUSH_SIZE
107 mcr p15, 0, r0, c7, c5, 7 @ invalidate BTB entry
108 add r0, r0, #BTB_FLUSH_SIZE
113 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
118 * v6_flush_kern_dcache_page(kaddr)
120 * Ensure that the data held in the page kaddr is written back
121 * to the page in question.
123 * - kaddr - kernel address (guaranteed to be page aligned)
125 ENTRY(v6_flush_kern_dcache_page)
129 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line
131 mcr p15, 0, r0, c7, c15, 1 @ clean & invalidate unified line
133 add r0, r0, #D_CACHE_LINE_SIZE
138 mcr p15, 0, r0, c7, c10, 4
144 * v6_dma_inv_range(start,end)
146 * Invalidate the data cache within the specified region; we will
147 * be performing a DMA operation in this region and we want to
148 * purge old data in the cache.
150 * - start - virtual start address of region
151 * - end - virtual end address of region
153 ENTRY(v6_dma_inv_range)
154 tst r0, #D_CACHE_LINE_SIZE - 1
155 bic r0, r0, #D_CACHE_LINE_SIZE - 1
157 mcrne p15, 0, r0, c7, c10, 1 @ clean D line
159 mcrne p15, 0, r0, c7, c11, 1 @ clean unified line
161 tst r1, #D_CACHE_LINE_SIZE - 1
162 bic r1, r1, #D_CACHE_LINE_SIZE - 1
164 mcrne p15, 0, r1, c7, c14, 1 @ clean & invalidate D line
166 mcrne p15, 0, r1, c7, c15, 1 @ clean & invalidate unified line
170 mcr p15, 0, r0, c7, c6, 1 @ invalidate D line
172 mcr p15, 0, r0, c7, c7, 1 @ invalidate unified line
174 add r0, r0, #D_CACHE_LINE_SIZE
178 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
182 * v6_dma_clean_range(start,end)
183 * - start - virtual start address of region
184 * - end - virtual end address of region
186 ENTRY(v6_dma_clean_range)
187 bic r0, r0, #D_CACHE_LINE_SIZE - 1
190 mcr p15, 0, r0, c7, c10, 1 @ clean D line
192 mcr p15, 0, r0, c7, c11, 1 @ clean unified line
194 add r0, r0, #D_CACHE_LINE_SIZE
198 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
202 * v6_dma_flush_range(start,end)
203 * - start - virtual start address of region
204 * - end - virtual end address of region
206 ENTRY(v6_dma_flush_range)
207 bic r0, r0, #D_CACHE_LINE_SIZE - 1
210 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line
212 mcr p15, 0, r0, c7, c15, 1 @ clean & invalidate line
214 add r0, r0, #D_CACHE_LINE_SIZE
218 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
223 .type v6_cache_fns, #object
225 .long v6_flush_kern_cache_all
226 .long v6_flush_user_cache_all
227 .long v6_flush_user_cache_range
228 .long v6_coherent_kern_range
229 .long v6_coherent_user_range
230 .long v6_flush_kern_dcache_page
231 .long v6_dma_inv_range
232 .long v6_dma_clean_range
233 .long v6_dma_flush_range
234 .size v6_cache_fns, . - v6_cache_fns