Pull style into test branch
[linux-2.6] / drivers / net / chelsio / mv88x201x.c
1 /*****************************************************************************
2  *                                                                           *
3  * File: mv88x201x.c                                                         *
4  * $Revision: 1.12 $                                                         *
5  * $Date: 2005/04/15 19:27:14 $                                              *
6  * Description:                                                              *
7  *  Marvell PHY (mv88x201x) functionality.                                   *
8  *  part of the Chelsio 10Gb Ethernet Driver.                                *
9  *                                                                           *
10  * This program is free software; you can redistribute it and/or modify      *
11  * it under the terms of the GNU General Public License, version 2, as       *
12  * published by the Free Software Foundation.                                *
13  *                                                                           *
14  * You should have received a copy of the GNU General Public License along   *
15  * with this program; if not, write to the Free Software Foundation, Inc.,   *
16  * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.                 *
17  *                                                                           *
18  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED    *
19  * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF      *
20  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.                     *
21  *                                                                           *
22  * http://www.chelsio.com                                                    *
23  *                                                                           *
24  * Copyright (c) 2003 - 2005 Chelsio Communications, Inc.                    *
25  * All rights reserved.                                                      *
26  *                                                                           *
27  * Maintainers: maintainers@chelsio.com                                      *
28  *                                                                           *
29  * Authors: Dimitrios Michailidis   <dm@chelsio.com>                         *
30  *          Tina Yang               <tainay@chelsio.com>                     *
31  *          Felix Marti             <felix@chelsio.com>                      *
32  *          Scott Bardone           <sbardone@chelsio.com>                   *
33  *          Kurt Ottaway            <kottaway@chelsio.com>                   *
34  *          Frank DiMambro          <frank@chelsio.com>                      *
35  *                                                                           *
36  * History:                                                                  *
37  *                                                                           *
38  ****************************************************************************/
39
40 #include "cphy.h"
41 #include "elmer0.h"
42
43 /*
44  * The 88x2010 Rev C. requires some link status registers * to be read
45  * twice in order to get the right values. Future * revisions will fix
46  * this problem and then this macro * can disappear.
47  */
48 #define MV88x2010_LINK_STATUS_BUGS    1
49
50 static int led_init(struct cphy *cphy)
51 {
52         /* Setup the LED registers so we can turn on/off.
53          * Writing these bits maps control to another
54          * register. mmd(0x1) addr(0x7)
55          */
56         mdio_write(cphy, 0x3, 0x8304, 0xdddd);
57         return 0;
58 }
59
60 static int led_link(struct cphy *cphy, u32 do_enable)
61 {
62         u32 led = 0;
63 #define LINK_ENABLE_BIT 0x1
64
65         mdio_read(cphy, 0x1, 0x7, &led);
66
67         if (do_enable & LINK_ENABLE_BIT) {
68                 led |= LINK_ENABLE_BIT;
69                 mdio_write(cphy, 0x1, 0x7, led);
70         } else {
71                 led &= ~LINK_ENABLE_BIT;
72                 mdio_write(cphy, 0x1, 0x7, led);
73         }
74         return 0;
75 }
76
77 /* Port Reset */
78 static int mv88x201x_reset(struct cphy *cphy, int wait)
79 {
80         /* This can be done through registers.  It is not required since
81          * a full chip reset is used.
82          */
83         return 0;
84 }
85
86 static int mv88x201x_interrupt_enable(struct cphy *cphy)
87 {
88         /* Enable PHY LASI interrupts. */
89         mdio_write(cphy, 0x1, 0x9002, 0x1);
90
91         /* Enable Marvell interrupts through Elmer0. */
92         if (t1_is_asic(cphy->adapter)) {
93                 u32 elmer;
94
95                 t1_tpi_read(cphy->adapter, A_ELMER0_INT_ENABLE, &elmer);
96                 elmer |= ELMER0_GP_BIT6;
97                 t1_tpi_write(cphy->adapter, A_ELMER0_INT_ENABLE, elmer);
98         }
99         return 0;
100 }
101
102 static int mv88x201x_interrupt_disable(struct cphy *cphy)
103 {
104         /* Disable PHY LASI interrupts. */
105         mdio_write(cphy, 0x1, 0x9002, 0x0);
106
107         /* Disable Marvell interrupts through Elmer0. */
108         if (t1_is_asic(cphy->adapter)) {
109                 u32 elmer;
110
111                 t1_tpi_read(cphy->adapter, A_ELMER0_INT_ENABLE, &elmer);
112                 elmer &= ~ELMER0_GP_BIT6;
113                 t1_tpi_write(cphy->adapter, A_ELMER0_INT_ENABLE, elmer);
114         }
115         return 0;
116 }
117
118 static int mv88x201x_interrupt_clear(struct cphy *cphy)
119 {
120         u32 elmer;
121         u32 val;
122
123 #ifdef MV88x2010_LINK_STATUS_BUGS
124         /* Required to read twice before clear takes affect. */
125         mdio_read(cphy, 0x1, 0x9003, &val);
126         mdio_read(cphy, 0x1, 0x9004, &val);
127         mdio_read(cphy, 0x1, 0x9005, &val);
128
129         /* Read this register after the others above it else
130          * the register doesn't clear correctly.
131          */
132         mdio_read(cphy, 0x1, 0x1, &val);
133 #endif
134
135         /* Clear link status. */
136         mdio_read(cphy, 0x1, 0x1, &val);
137         /* Clear PHY LASI interrupts. */
138         mdio_read(cphy, 0x1, 0x9005, &val);
139
140 #ifdef MV88x2010_LINK_STATUS_BUGS
141         /* Do it again. */
142         mdio_read(cphy, 0x1, 0x9003, &val);
143         mdio_read(cphy, 0x1, 0x9004, &val);
144 #endif
145
146         /* Clear Marvell interrupts through Elmer0. */
147         if (t1_is_asic(cphy->adapter)) {
148                 t1_tpi_read(cphy->adapter, A_ELMER0_INT_CAUSE, &elmer);
149                 elmer |= ELMER0_GP_BIT6;
150                 t1_tpi_write(cphy->adapter, A_ELMER0_INT_CAUSE, elmer);
151         }
152         return 0;
153 }
154
155 static int mv88x201x_interrupt_handler(struct cphy *cphy)
156 {
157         /* Clear interrupts */
158         mv88x201x_interrupt_clear(cphy);
159
160         /* We have only enabled link change interrupts and so
161          * cphy_cause must be a link change interrupt.
162          */
163         return cphy_cause_link_change;
164 }
165
166 static int mv88x201x_set_loopback(struct cphy *cphy, int on)
167 {
168         return 0;
169 }
170
171 static int mv88x201x_get_link_status(struct cphy *cphy, int *link_ok,
172                                      int *speed, int *duplex, int *fc)
173 {
174         u32 val = 0;
175 #define LINK_STATUS_BIT 0x4
176
177         if (link_ok) {
178                 /* Read link status. */
179                 mdio_read(cphy, 0x1, 0x1, &val);
180                 val &= LINK_STATUS_BIT;
181                 *link_ok = (val == LINK_STATUS_BIT);
182                 /* Turn on/off Link LED */
183                 led_link(cphy, *link_ok);
184         }
185         if (speed)
186                 *speed = SPEED_10000;
187         if (duplex)
188                 *duplex = DUPLEX_FULL;
189         if (fc)
190                 *fc = PAUSE_RX | PAUSE_TX;
191         return 0;
192 }
193
194 static void mv88x201x_destroy(struct cphy *cphy)
195 {
196         kfree(cphy);
197 }
198
199 static struct cphy_ops mv88x201x_ops = {
200         .destroy           = mv88x201x_destroy,
201         .reset             = mv88x201x_reset,
202         .interrupt_enable  = mv88x201x_interrupt_enable,
203         .interrupt_disable = mv88x201x_interrupt_disable,
204         .interrupt_clear   = mv88x201x_interrupt_clear,
205         .interrupt_handler = mv88x201x_interrupt_handler,
206         .get_link_status   = mv88x201x_get_link_status,
207         .set_loopback      = mv88x201x_set_loopback,
208 };
209
210 static struct cphy *mv88x201x_phy_create(adapter_t *adapter, int phy_addr,
211                                          struct mdio_ops *mdio_ops)
212 {
213         u32 val;
214         struct cphy *cphy = kzalloc(sizeof(*cphy), GFP_KERNEL);
215
216         if (!cphy)
217                 return NULL;
218
219         cphy_init(cphy, adapter, phy_addr, &mv88x201x_ops, mdio_ops);
220
221         /* Commands the PHY to enable XFP's clock. */
222         mdio_read(cphy, 0x3, 0x8300, &val);
223         mdio_write(cphy, 0x3, 0x8300, val | 1);
224
225         /* Clear link status. Required because of a bug in the PHY.  */
226         mdio_read(cphy, 0x1, 0x8, &val);
227         mdio_read(cphy, 0x3, 0x8, &val);
228
229         /* Allows for Link,Ack LED turn on/off */
230         led_init(cphy);
231         return cphy;
232 }
233
234 /* Chip Reset */
235 static int mv88x201x_phy_reset(adapter_t *adapter)
236 {
237         u32 val;
238
239         t1_tpi_read(adapter, A_ELMER0_GPO, &val);
240         val &= ~4;
241         t1_tpi_write(adapter, A_ELMER0_GPO, val);
242         msleep(100);
243
244         t1_tpi_write(adapter, A_ELMER0_GPO, val | 4);
245         msleep(1000);
246
247         /* Now lets enable the Laser. Delay 100us */
248         t1_tpi_read(adapter, A_ELMER0_GPO, &val);
249         val |= 0x8000;
250         t1_tpi_write(adapter, A_ELMER0_GPO, val);
251         udelay(100);
252         return 0;
253 }
254
255 struct gphy t1_mv88x201x_ops = {
256         mv88x201x_phy_create,
257         mv88x201x_phy_reset
258 };