powerpc/fsl: proliferate simple-bus compatibility to soc nodes
[linux-2.6] / arch / powerpc / boot / dts / mpc8548cds.dts
1 /*
2  * MPC8548 CDS Device Tree Source
3  *
4  * Copyright 2006, 2008 Freescale Semiconductor Inc.
5  *
6  * This program is free software; you can redistribute  it and/or modify it
7  * under  the terms of  the GNU General  Public License as published by the
8  * Free Software Foundation;  either version 2 of the  License, or (at your
9  * option) any later version.
10  */
11
12 /dts-v1/;
13
14 / {
15         model = "MPC8548CDS";
16         compatible = "MPC8548CDS", "MPC85xxCDS";
17         #address-cells = <1>;
18         #size-cells = <1>;
19
20         aliases {
21                 ethernet0 = &enet0;
22                 ethernet1 = &enet1;
23 /*
24                 ethernet2 = &enet2;
25                 ethernet3 = &enet3;
26 */
27                 serial0 = &serial0;
28                 serial1 = &serial1;
29                 pci0 = &pci0;
30                 pci1 = &pci1;
31                 pci2 = &pci2;
32         };
33
34         cpus {
35                 #address-cells = <1>;
36                 #size-cells = <0>;
37
38                 PowerPC,8548@0 {
39                         device_type = "cpu";
40                         reg = <0x0>;
41                         d-cache-line-size = <32>;       // 32 bytes
42                         i-cache-line-size = <32>;       // 32 bytes
43                         d-cache-size = <0x8000>;                // L1, 32K
44                         i-cache-size = <0x8000>;                // L1, 32K
45                         timebase-frequency = <0>;       //  33 MHz, from uboot
46                         bus-frequency = <0>;    // 166 MHz
47                         clock-frequency = <0>;  // 825 MHz, from uboot
48                         next-level-cache = <&L2>;
49                 };
50         };
51
52         memory {
53                 device_type = "memory";
54                 reg = <0x0 0x8000000>;  // 128M at 0x0
55         };
56
57         soc8548@e0000000 {
58                 #address-cells = <1>;
59                 #size-cells = <1>;
60                 device_type = "soc";
61                 compatible = "simple-bus";
62                 ranges = <0x0 0xe0000000 0x100000>;
63                 reg = <0xe0000000 0x1000>;      // CCSRBAR
64                 bus-frequency = <0>;
65
66                 memory-controller@2000 {
67                         compatible = "fsl,8548-memory-controller";
68                         reg = <0x2000 0x1000>;
69                         interrupt-parent = <&mpic>;
70                         interrupts = <18 2>;
71                 };
72
73                 L2: l2-cache-controller@20000 {
74                         compatible = "fsl,8548-l2-cache-controller";
75                         reg = <0x20000 0x1000>;
76                         cache-line-size = <32>; // 32 bytes
77                         cache-size = <0x80000>; // L2, 512K
78                         interrupt-parent = <&mpic>;
79                         interrupts = <16 2>;
80                 };
81
82                 i2c@3000 {
83                         #address-cells = <1>;
84                         #size-cells = <0>;
85                         cell-index = <0>;
86                         compatible = "fsl-i2c";
87                         reg = <0x3000 0x100>;
88                         interrupts = <43 2>;
89                         interrupt-parent = <&mpic>;
90                         dfsrr;
91                 };
92
93                 i2c@3100 {
94                         #address-cells = <1>;
95                         #size-cells = <0>;
96                         cell-index = <1>;
97                         compatible = "fsl-i2c";
98                         reg = <0x3100 0x100>;
99                         interrupts = <43 2>;
100                         interrupt-parent = <&mpic>;
101                         dfsrr;
102                 };
103
104                 dma@21300 {
105                         #address-cells = <1>;
106                         #size-cells = <1>;
107                         compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
108                         reg = <0x21300 0x4>;
109                         ranges = <0x0 0x21100 0x200>;
110                         cell-index = <0>;
111                         dma-channel@0 {
112                                 compatible = "fsl,mpc8548-dma-channel",
113                                                 "fsl,eloplus-dma-channel";
114                                 reg = <0x0 0x80>;
115                                 cell-index = <0>;
116                                 interrupt-parent = <&mpic>;
117                                 interrupts = <20 2>;
118                         };
119                         dma-channel@80 {
120                                 compatible = "fsl,mpc8548-dma-channel",
121                                                 "fsl,eloplus-dma-channel";
122                                 reg = <0x80 0x80>;
123                                 cell-index = <1>;
124                                 interrupt-parent = <&mpic>;
125                                 interrupts = <21 2>;
126                         };
127                         dma-channel@100 {
128                                 compatible = "fsl,mpc8548-dma-channel",
129                                                 "fsl,eloplus-dma-channel";
130                                 reg = <0x100 0x80>;
131                                 cell-index = <2>;
132                                 interrupt-parent = <&mpic>;
133                                 interrupts = <22 2>;
134                         };
135                         dma-channel@180 {
136                                 compatible = "fsl,mpc8548-dma-channel",
137                                                 "fsl,eloplus-dma-channel";
138                                 reg = <0x180 0x80>;
139                                 cell-index = <3>;
140                                 interrupt-parent = <&mpic>;
141                                 interrupts = <23 2>;
142                         };
143                 };
144
145                 mdio@24520 {
146                         #address-cells = <1>;
147                         #size-cells = <0>;
148                         compatible = "fsl,gianfar-mdio";
149                         reg = <0x24520 0x20>;
150
151                         phy0: ethernet-phy@0 {
152                                 interrupt-parent = <&mpic>;
153                                 interrupts = <5 1>;
154                                 reg = <0x0>;
155                                 device_type = "ethernet-phy";
156                         };
157                         phy1: ethernet-phy@1 {
158                                 interrupt-parent = <&mpic>;
159                                 interrupts = <5 1>;
160                                 reg = <0x1>;
161                                 device_type = "ethernet-phy";
162                         };
163                         phy2: ethernet-phy@2 {
164                                 interrupt-parent = <&mpic>;
165                                 interrupts = <5 1>;
166                                 reg = <0x2>;
167                                 device_type = "ethernet-phy";
168                         };
169                         phy3: ethernet-phy@3 {
170                                 interrupt-parent = <&mpic>;
171                                 interrupts = <5 1>;
172                                 reg = <0x3>;
173                                 device_type = "ethernet-phy";
174                         };
175                 };
176
177                 enet0: ethernet@24000 {
178                         cell-index = <0>;
179                         device_type = "network";
180                         model = "eTSEC";
181                         compatible = "gianfar";
182                         reg = <0x24000 0x1000>;
183                         local-mac-address = [ 00 00 00 00 00 00 ];
184                         interrupts = <29 2 30 2 34 2>;
185                         interrupt-parent = <&mpic>;
186                         phy-handle = <&phy0>;
187                 };
188
189                 enet1: ethernet@25000 {
190                         cell-index = <1>;
191                         device_type = "network";
192                         model = "eTSEC";
193                         compatible = "gianfar";
194                         reg = <0x25000 0x1000>;
195                         local-mac-address = [ 00 00 00 00 00 00 ];
196                         interrupts = <35 2 36 2 40 2>;
197                         interrupt-parent = <&mpic>;
198                         phy-handle = <&phy1>;
199                 };
200
201 /* eTSEC 3/4 are currently broken
202                 enet2: ethernet@26000 {
203                         cell-index = <2>;
204                         device_type = "network";
205                         model = "eTSEC";
206                         compatible = "gianfar";
207                         reg = <0x26000 0x1000>;
208                         local-mac-address = [ 00 00 00 00 00 00 ];
209                         interrupts = <31 2 32 2 33 2>;
210                         interrupt-parent = <&mpic>;
211                         phy-handle = <&phy2>;
212                 };
213
214                 enet3: ethernet@27000 {
215                         cell-index = <3>;
216                         device_type = "network";
217                         model = "eTSEC";
218                         compatible = "gianfar";
219                         reg = <0x27000 0x1000>;
220                         local-mac-address = [ 00 00 00 00 00 00 ];
221                         interrupts = <37 2 38 2 39 2>;
222                         interrupt-parent = <&mpic>;
223                         phy-handle = <&phy3>;
224                 };
225  */
226
227                 serial0: serial@4500 {
228                         cell-index = <0>;
229                         device_type = "serial";
230                         compatible = "ns16550";
231                         reg = <0x4500 0x100>;   // reg base, size
232                         clock-frequency = <0>;  // should we fill in in uboot?
233                         interrupts = <42 2>;
234                         interrupt-parent = <&mpic>;
235                 };
236
237                 serial1: serial@4600 {
238                         cell-index = <1>;
239                         device_type = "serial";
240                         compatible = "ns16550";
241                         reg = <0x4600 0x100>;   // reg base, size
242                         clock-frequency = <0>;  // should we fill in in uboot?
243                         interrupts = <42 2>;
244                         interrupt-parent = <&mpic>;
245                 };
246
247                 global-utilities@e0000 {        //global utilities reg
248                         compatible = "fsl,mpc8548-guts";
249                         reg = <0xe0000 0x1000>;
250                         fsl,has-rstcr;
251                 };
252
253                 crypto@30000 {
254                         compatible = "fsl,sec2.1", "fsl,sec2.0";
255                         reg = <0x30000 0x10000>;
256                         interrupts = <45 2>;
257                         interrupt-parent = <&mpic>;
258                         fsl,num-channels = <4>;
259                         fsl,channel-fifo-len = <24>;
260                         fsl,exec-units-mask = <0xfe>;
261                         fsl,descriptor-types-mask = <0x12b0ebf>;
262                 };
263
264                 mpic: pic@40000 {
265                         interrupt-controller;
266                         #address-cells = <0>;
267                         #interrupt-cells = <2>;
268                         reg = <0x40000 0x40000>;
269                         compatible = "chrp,open-pic";
270                         device_type = "open-pic";
271                 };
272         };
273
274         pci0: pci@e0008000 {
275                 cell-index = <0>;
276                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
277                 interrupt-map = <
278                         /* IDSEL 0x4 (PCIX Slot 2) */
279                         0x2000 0x0 0x0 0x1 &mpic 0x0 0x1
280                         0x2000 0x0 0x0 0x2 &mpic 0x1 0x1
281                         0x2000 0x0 0x0 0x3 &mpic 0x2 0x1
282                         0x2000 0x0 0x0 0x4 &mpic 0x3 0x1
283
284                         /* IDSEL 0x5 (PCIX Slot 3) */
285                         0x2800 0x0 0x0 0x1 &mpic 0x1 0x1
286                         0x2800 0x0 0x0 0x2 &mpic 0x2 0x1
287                         0x2800 0x0 0x0 0x3 &mpic 0x3 0x1
288                         0x2800 0x0 0x0 0x4 &mpic 0x0 0x1
289
290                         /* IDSEL 0x6 (PCIX Slot 4) */
291                         0x3000 0x0 0x0 0x1 &mpic 0x2 0x1
292                         0x3000 0x0 0x0 0x2 &mpic 0x3 0x1
293                         0x3000 0x0 0x0 0x3 &mpic 0x0 0x1
294                         0x3000 0x0 0x0 0x4 &mpic 0x1 0x1
295
296                         /* IDSEL 0x8 (PCIX Slot 5) */
297                         0x4000 0x0 0x0 0x1 &mpic 0x0 0x1
298                         0x4000 0x0 0x0 0x2 &mpic 0x1 0x1
299                         0x4000 0x0 0x0 0x3 &mpic 0x2 0x1
300                         0x4000 0x0 0x0 0x4 &mpic 0x3 0x1
301
302                         /* IDSEL 0xC (Tsi310 bridge) */
303                         0x6000 0x0 0x0 0x1 &mpic 0x0 0x1
304                         0x6000 0x0 0x0 0x2 &mpic 0x1 0x1
305                         0x6000 0x0 0x0 0x3 &mpic 0x2 0x1
306                         0x6000 0x0 0x0 0x4 &mpic 0x3 0x1
307
308                         /* IDSEL 0x14 (Slot 2) */
309                         0xa000 0x0 0x0 0x1 &mpic 0x0 0x1
310                         0xa000 0x0 0x0 0x2 &mpic 0x1 0x1
311                         0xa000 0x0 0x0 0x3 &mpic 0x2 0x1
312                         0xa000 0x0 0x0 0x4 &mpic 0x3 0x1
313
314                         /* IDSEL 0x15 (Slot 3) */
315                         0xa800 0x0 0x0 0x1 &mpic 0x1 0x1
316                         0xa800 0x0 0x0 0x2 &mpic 0x2 0x1
317                         0xa800 0x0 0x0 0x3 &mpic 0x3 0x1
318                         0xa800 0x0 0x0 0x4 &mpic 0x0 0x1
319
320                         /* IDSEL 0x16 (Slot 4) */
321                         0xb000 0x0 0x0 0x1 &mpic 0x2 0x1
322                         0xb000 0x0 0x0 0x2 &mpic 0x3 0x1
323                         0xb000 0x0 0x0 0x3 &mpic 0x0 0x1
324                         0xb000 0x0 0x0 0x4 &mpic 0x1 0x1
325
326                         /* IDSEL 0x18 (Slot 5) */
327                         0xc000 0x0 0x0 0x1 &mpic 0x0 0x1
328                         0xc000 0x0 0x0 0x2 &mpic 0x1 0x1
329                         0xc000 0x0 0x0 0x3 &mpic 0x2 0x1
330                         0xc000 0x0 0x0 0x4 &mpic 0x3 0x1
331
332                         /* IDSEL 0x1C (Tsi310 bridge PCI primary) */
333                         0xe000 0x0 0x0 0x1 &mpic 0x0 0x1
334                         0xe000 0x0 0x0 0x2 &mpic 0x1 0x1
335                         0xe000 0x0 0x0 0x3 &mpic 0x2 0x1
336                         0xe000 0x0 0x0 0x4 &mpic 0x3 0x1>;
337
338                 interrupt-parent = <&mpic>;
339                 interrupts = <24 2>;
340                 bus-range = <0 0>;
341                 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x10000000
342                           0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
343                 clock-frequency = <66666666>;
344                 #interrupt-cells = <1>;
345                 #size-cells = <2>;
346                 #address-cells = <3>;
347                 reg = <0xe0008000 0x1000>;
348                 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
349                 device_type = "pci";
350
351                 pci_bridge@1c {
352                         interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
353                         interrupt-map = <
354
355                                 /* IDSEL 0x00 (PrPMC Site) */
356                                 0000 0x0 0x0 0x1 &mpic 0x0 0x1
357                                 0000 0x0 0x0 0x2 &mpic 0x1 0x1
358                                 0000 0x0 0x0 0x3 &mpic 0x2 0x1
359                                 0000 0x0 0x0 0x4 &mpic 0x3 0x1
360
361                                 /* IDSEL 0x04 (VIA chip) */
362                                 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1
363                                 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1
364                                 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1
365                                 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1
366
367                                 /* IDSEL 0x05 (8139) */
368                                 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1
369
370                                 /* IDSEL 0x06 (Slot 6) */
371                                 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1
372                                 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1
373                                 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1
374                                 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1
375
376                                 /* IDESL 0x07 (Slot 7) */
377                                 0x3800 0x0 0x0 0x1 &mpic 0x3 0x1
378                                 0x3800 0x0 0x0 0x2 &mpic 0x0 0x1
379                                 0x3800 0x0 0x0 0x3 &mpic 0x1 0x1
380                                 0x3800 0x0 0x0 0x4 &mpic 0x2 0x1>;
381
382                         reg = <0xe000 0x0 0x0 0x0 0x0>;
383                         #interrupt-cells = <1>;
384                         #size-cells = <2>;
385                         #address-cells = <3>;
386                         ranges = <0x2000000 0x0 0x80000000
387                                   0x2000000 0x0 0x80000000
388                                   0x0 0x20000000
389                                   0x1000000 0x0 0x0
390                                   0x1000000 0x0 0x0
391                                   0x0 0x80000>;
392                         clock-frequency = <33333333>;
393
394                         isa@4 {
395                                 device_type = "isa";
396                                 #interrupt-cells = <2>;
397                                 #size-cells = <1>;
398                                 #address-cells = <2>;
399                                 reg = <0x2000 0x0 0x0 0x0 0x0>;
400                                 ranges = <0x1 0x0 0x1000000 0x0 0x0 0x1000>;
401                                 interrupt-parent = <&i8259>;
402
403                                 i8259: interrupt-controller@20 {
404                                         interrupt-controller;
405                                         device_type = "interrupt-controller";
406                                         reg = <0x1 0x20 0x2
407                                                0x1 0xa0 0x2
408                                                0x1 0x4d0 0x2>;
409                                         #address-cells = <0>;
410                                         #interrupt-cells = <2>;
411                                         compatible = "chrp,iic";
412                                         interrupts = <0 1>;
413                                         interrupt-parent = <&mpic>;
414                                 };
415
416                                 rtc@70 {
417                                         compatible = "pnpPNP,b00";
418                                         reg = <0x1 0x70 0x2>;
419                                 };
420                         };
421                 };
422         };
423
424         pci1: pci@e0009000 {
425                 cell-index = <1>;
426                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
427                 interrupt-map = <
428
429                         /* IDSEL 0x15 */
430                         0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
431                         0xa800 0x0 0x0 0x2 &mpic 0x1 0x1
432                         0xa800 0x0 0x0 0x3 &mpic 0x2 0x1
433                         0xa800 0x0 0x0 0x4 &mpic 0x3 0x1>;
434
435                 interrupt-parent = <&mpic>;
436                 interrupts = <25 2>;
437                 bus-range = <0 0>;
438                 ranges = <0x2000000 0x0 0x90000000 0x90000000 0x0 0x10000000
439                           0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
440                 clock-frequency = <66666666>;
441                 #interrupt-cells = <1>;
442                 #size-cells = <2>;
443                 #address-cells = <3>;
444                 reg = <0xe0009000 0x1000>;
445                 compatible = "fsl,mpc8540-pci";
446                 device_type = "pci";
447         };
448
449         pci2: pcie@e000a000 {
450                 cell-index = <2>;
451                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
452                 interrupt-map = <
453
454                         /* IDSEL 0x0 (PEX) */
455                         00000 0x0 0x0 0x1 &mpic 0x0 0x1
456                         00000 0x0 0x0 0x2 &mpic 0x1 0x1
457                         00000 0x0 0x0 0x3 &mpic 0x2 0x1
458                         00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
459
460                 interrupt-parent = <&mpic>;
461                 interrupts = <26 2>;
462                 bus-range = <0 255>;
463                 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
464                           0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
465                 clock-frequency = <33333333>;
466                 #interrupt-cells = <1>;
467                 #size-cells = <2>;
468                 #address-cells = <3>;
469                 reg = <0xe000a000 0x1000>;
470                 compatible = "fsl,mpc8548-pcie";
471                 device_type = "pci";
472                 pcie@0 {
473                         reg = <0x0 0x0 0x0 0x0 0x0>;
474                         #size-cells = <2>;
475                         #address-cells = <3>;
476                         device_type = "pci";
477                         ranges = <0x2000000 0x0 0xa0000000
478                                   0x2000000 0x0 0xa0000000
479                                   0x0 0x20000000
480
481                                   0x1000000 0x0 0x0
482                                   0x1000000 0x0 0x0
483                                   0x0 0x100000>;
484                 };
485         };
486 };