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   1 /* linux/arch/arm/mach-s3c2440/mach-osiris.c
   2  *
   3  * Copyright (c) 2005,2008 Simtec Electronics
   4  *      http://armlinux.simtec.co.uk/
   5  *      Ben Dooks <ben@simtec.co.uk>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10 */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/types.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/list.h>
  16 #include <linux/timer.h>
  17 #include <linux/init.h>
  18 #include <linux/gpio.h>
  19 #include <linux/device.h>
  20 #include <linux/sysdev.h>
  21 #include <linux/serial_core.h>
  22 #include <linux/clk.h>
  23 #include <linux/i2c.h>
  24 #include <linux/io.h>
  25
  26 #include <asm/mach/arch.h>
  27 #include <asm/mach/map.h>
  28 #include <asm/mach/irq.h>
  29
  30 #include <mach/osiris-map.h>
  31 #include <mach/osiris-cpld.h>
  32
  33 #include <mach/hardware.h>
  34 #include <asm/irq.h>
  35 #include <asm/mach-types.h>
  36
  37 #include <plat/regs-serial.h>
  38 #include <mach/regs-gpio.h>
  39 #include <mach/regs-mem.h>
  40 #include <mach/regs-lcd.h>
  41 #include <plat/nand.h>
  42 #include <plat/iic.h>
  43
  44 #include <linux/mtd/mtd.h>
  45 #include <linux/mtd/nand.h>
  46 #include <linux/mtd/nand_ecc.h>
  47 #include <linux/mtd/partitions.h>
  48
  49 #include <plat/clock.h>
  50 #include <plat/devs.h>
  51 #include <plat/cpu.h>
  52
  53 /* onboard perihperal map */
  54
  55 static struct map_desc osiris_iodesc[] __initdata = {
  56   /* ISA IO areas (may be over-written later) */
  57
  58   {
  59           .virtual      = (u32)S3C24XX_VA_ISA_BYTE,
  60           .pfn          = __phys_to_pfn(S3C2410_CS5),
  61           .length       = SZ_16M,
  62           .type         = MT_DEVICE,
  63   }, {
  64           .virtual      = (u32)S3C24XX_VA_ISA_WORD,
  65           .pfn          = __phys_to_pfn(S3C2410_CS5),
  66           .length       = SZ_16M,
  67           .type         = MT_DEVICE,
  68   },
  69
  70   /* CPLD control registers */
  71
  72   {
  73           .virtual      = (u32)OSIRIS_VA_CTRL0,
  74           .pfn          = __phys_to_pfn(OSIRIS_PA_CTRL0),
  75           .length       = SZ_16K,
  76           .type         = MT_DEVICE,
  77   }, {
  78           .virtual      = (u32)OSIRIS_VA_CTRL1,
  79           .pfn          = __phys_to_pfn(OSIRIS_PA_CTRL1),
  80           .length       = SZ_16K,
  81           .type         = MT_DEVICE,
  82   }, {
  83           .virtual      = (u32)OSIRIS_VA_CTRL2,
  84           .pfn          = __phys_to_pfn(OSIRIS_PA_CTRL2),
  85           .length       = SZ_16K,
  86           .type         = MT_DEVICE,
  87   }, {
  88           .virtual      = (u32)OSIRIS_VA_IDREG,
  89           .pfn          = __phys_to_pfn(OSIRIS_PA_IDREG),
  90           .length       = SZ_16K,
  91           .type         = MT_DEVICE,
  92   },
  93 };
  94
  95 #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
  96 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
  97 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
  98
  99 static struct s3c24xx_uart_clksrc osiris_serial_clocks[] = {
 100         [0] = {
 101                 .name           = "uclk",
 102                 .divisor        = 1,
 103                 .min_baud       = 0,
 104                 .max_baud       = 0,
 105         },
 106         [1] = {
 107                 .name           = "pclk",
 108                 .divisor        = 1,
 109                 .min_baud       = 0,
 110                 .max_baud       = 0,
 111         }
 112 };
 113
 114 static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = {
 115         [0] = {
 116                 .hwport      = 0,
 117                 .flags       = 0,
 118                 .ucon        = UCON,
 119                 .ulcon       = ULCON,
 120                 .ufcon       = UFCON,
 121                 .clocks      = osiris_serial_clocks,
 122                 .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
 123         },
 124         [1] = {
 125                 .hwport      = 1,
 126                 .flags       = 0,
 127                 .ucon        = UCON,
 128                 .ulcon       = ULCON,
 129                 .ufcon       = UFCON,
 130                 .clocks      = osiris_serial_clocks,
 131                 .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
 132         },
 133         [2] = {
 134                 .hwport      = 2,
 135                 .flags       = 0,
 136                 .ucon        = UCON,
 137                 .ulcon       = ULCON,
 138                 .ufcon       = UFCON,
 139                 .clocks      = osiris_serial_clocks,
 140                 .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
 141         }
 142 };
 143
 144 /* NAND Flash on Osiris board */
 145
 146 static int external_map[]   = { 2 };
 147 static int chip0_map[]      = { 0 };
 148 static int chip1_map[]      = { 1 };
 149
 150 static struct mtd_partition osiris_default_nand_part[] = {
 151         [0] = {
 152                 .name   = "Boot Agent",
 153                 .size   = SZ_16K,
 154                 .offset = 0,
 155         },
 156         [1] = {
 157                 .name   = "/boot",
 158                 .size   = SZ_4M - SZ_16K,
 159                 .offset = SZ_16K,
 160         },
 161         [2] = {
 162                 .name   = "user1",
 163                 .offset = SZ_4M,
 164                 .size   = SZ_32M - SZ_4M,
 165         },
 166         [3] = {
 167                 .name   = "user2",
 168                 .offset = SZ_32M,
 169                 .size   = MTDPART_SIZ_FULL,
 170         }
 171 };
 172
 173 static struct mtd_partition osiris_default_nand_part_large[] = {
 174         [0] = {
 175                 .name   = "Boot Agent",
 176                 .size   = SZ_128K,
 177                 .offset = 0,
 178         },
 179         [1] = {
 180                 .name   = "/boot",
 181                 .size   = SZ_4M - SZ_128K,
 182                 .offset = SZ_128K,
 183         },
 184         [2] = {
 185                 .name   = "user1",
 186                 .offset = SZ_4M,
 187                 .size   = SZ_32M - SZ_4M,
 188         },
 189         [3] = {
 190                 .name   = "user2",
 191                 .offset = SZ_32M,
 192                 .size   = MTDPART_SIZ_FULL,
 193         }
 194 };
 195
 196 /* the Osiris has 3 selectable slots for nand-flash, the two
 197  * on-board chip areas, as well as the external slot.
 198  *
 199  * Note, there is no current hot-plug support for the External
 200  * socket.
 201 */
 202
 203 static struct s3c2410_nand_set osiris_nand_sets[] = {
 204         [1] = {
 205                 .name           = "External",
 206                 .nr_chips       = 1,
 207                 .nr_map         = external_map,
 208                 .nr_partitions  = ARRAY_SIZE(osiris_default_nand_part),
 209                 .partitions     = osiris_default_nand_part,
 210         },
 211         [0] = {
 212                 .name           = "chip0",
 213                 .nr_chips       = 1,
 214                 .nr_map         = chip0_map,
 215                 .nr_partitions  = ARRAY_SIZE(osiris_default_nand_part),
 216                 .partitions     = osiris_default_nand_part,
 217         },
 218         [2] = {
 219                 .name           = "chip1",
 220                 .nr_chips       = 1,
 221                 .nr_map         = chip1_map,
 222                 .nr_partitions  = ARRAY_SIZE(osiris_default_nand_part),
 223                 .partitions     = osiris_default_nand_part,
 224         },
 225 };
 226
 227 static void osiris_nand_select(struct s3c2410_nand_set *set, int slot)
 228 {
 229         unsigned int tmp;
 230
 231         slot = set->nr_map[slot] & 3;
 232
 233         pr_debug("osiris_nand: selecting slot %d (set %p,%p)\n",
 234                  slot, set, set->nr_map);
 235
 236         tmp = __raw_readb(OSIRIS_VA_CTRL0);
 237         tmp &= ~OSIRIS_CTRL0_NANDSEL;
 238         tmp |= slot;
 239
 240         pr_debug("osiris_nand: ctrl0 now %02x\n", tmp);
 241
 242         __raw_writeb(tmp, OSIRIS_VA_CTRL0);
 243 }
 244
 245 static struct s3c2410_platform_nand osiris_nand_info = {
 246         .tacls          = 25,
 247         .twrph0         = 60,
 248         .twrph1         = 60,
 249         .nr_sets        = ARRAY_SIZE(osiris_nand_sets),
 250         .sets           = osiris_nand_sets,
 251         .select_chip    = osiris_nand_select,
 252 };
 253
 254 /* PCMCIA control and configuration */
 255
 256 static struct resource osiris_pcmcia_resource[] = {
 257         [0] = {
 258                 .start  = 0x0f000000,
 259                 .end    = 0x0f100000,
 260                 .flags  = IORESOURCE_MEM,
 261         },
 262         [1] = {
 263                 .start  = 0x0c000000,
 264                 .end    = 0x0c100000,
 265                 .flags  = IORESOURCE_MEM,
 266         }
 267 };
 268
 269 static struct platform_device osiris_pcmcia = {
 270         .name           = "osiris-pcmcia",
 271         .id             = -1,
 272         .num_resources  = ARRAY_SIZE(osiris_pcmcia_resource),
 273         .resource       = osiris_pcmcia_resource,
 274 };
 275
 276 /* Osiris power management device */
 277
 278 #ifdef CONFIG_PM
 279 static unsigned char pm_osiris_ctrl0;
 280
 281 static int osiris_pm_suspend(struct sys_device *sd, pm_message_t state)
 282 {
 283         unsigned int tmp;
 284
 285         pm_osiris_ctrl0 = __raw_readb(OSIRIS_VA_CTRL0);
 286         tmp = pm_osiris_ctrl0 & ~OSIRIS_CTRL0_NANDSEL;
 287
 288         /* ensure correct NAND slot is selected on resume */
 289         if ((pm_osiris_ctrl0 & OSIRIS_CTRL0_BOOT_INT) == 0)
 290                 tmp |= 2;
 291
 292         __raw_writeb(tmp, OSIRIS_VA_CTRL0);
 293
 294         /* ensure that an nRESET is not generated on resume. */
 295         s3c2410_gpio_setpin(S3C2410_GPA(21), 1);
 296         s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPIO_OUTPUT);
 297
 298         return 0;
 299 }
 300
 301 static int osiris_pm_resume(struct sys_device *sd)
 302 {
 303         if (pm_osiris_ctrl0 & OSIRIS_CTRL0_FIX8)
 304                 __raw_writeb(OSIRIS_CTRL1_FIX8, OSIRIS_VA_CTRL1);
 305
 306         __raw_writeb(pm_osiris_ctrl0, OSIRIS_VA_CTRL0);
 307
 308         s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);
 309
 310         return 0;
 311 }
 312
 313 #else
 314 #define osiris_pm_suspend NULL
 315 #define osiris_pm_resume NULL
 316 #endif
 317
 318 static struct sysdev_class osiris_pm_sysclass = {
 319         .name           = "mach-osiris",
 320         .suspend        = osiris_pm_suspend,
 321         .resume         = osiris_pm_resume,
 322 };
 323
 324 static struct sys_device osiris_pm_sysdev = {
 325         .cls            = &osiris_pm_sysclass,
 326 };
 327
 328 /* I2C devices fitted. */
 329
 330 static struct i2c_board_info osiris_i2c_devs[] __initdata = {
 331         {
 332                 I2C_BOARD_INFO("tps65011", 0x48),
 333                 .irq    = IRQ_EINT20,
 334         },
 335 };
 336
 337 /* Standard Osiris devices */
 338
 339 static struct platform_device *osiris_devices[] __initdata = {
 340         &s3c_device_i2c0,
 341         &s3c_device_wdt,
 342         &s3c_device_nand,
 343         &osiris_pcmcia,
 344 };
 345
 346 static struct clk *osiris_clocks[] __initdata = {
 347         &s3c24xx_dclk0,
 348         &s3c24xx_dclk1,
 349         &s3c24xx_clkout0,
 350         &s3c24xx_clkout1,
 351         &s3c24xx_uclk,
 352 };
 353
 354 static void __init osiris_map_io(void)
 355 {
 356         unsigned long flags;
 357
 358         /* initialise the clocks */
 359
 360         s3c24xx_dclk0.parent = &clk_upll;
 361         s3c24xx_dclk0.rate   = 12*1000*1000;
 362
 363         s3c24xx_dclk1.parent = &clk_upll;
 364         s3c24xx_dclk1.rate   = 24*1000*1000;
 365
 366         s3c24xx_clkout0.parent  = &s3c24xx_dclk0;
 367         s3c24xx_clkout1.parent  = &s3c24xx_dclk1;
 368
 369         s3c24xx_uclk.parent  = &s3c24xx_clkout1;
 370
 371         s3c24xx_register_clocks(osiris_clocks, ARRAY_SIZE(osiris_clocks));
 372
 373         s3c_device_nand.dev.platform_data = &osiris_nand_info;
 374
 375         s3c24xx_init_io(osiris_iodesc, ARRAY_SIZE(osiris_iodesc));
 376         s3c24xx_init_clocks(0);
 377         s3c24xx_init_uarts(osiris_uartcfgs, ARRAY_SIZE(osiris_uartcfgs));
 378
 379         /* check for the newer revision boards with large page nand */
 380
 381         if ((__raw_readb(OSIRIS_VA_IDREG) & OSIRIS_ID_REVMASK) >= 4) {
 382                 printk(KERN_INFO "OSIRIS-B detected (revision %d)\n",
 383                        __raw_readb(OSIRIS_VA_IDREG) & OSIRIS_ID_REVMASK);
 384                 osiris_nand_sets[0].partitions = osiris_default_nand_part_large;
 385                 osiris_nand_sets[0].nr_partitions = ARRAY_SIZE(osiris_default_nand_part_large);
 386         } else {
 387                 /* write-protect line to the NAND */
 388                 s3c2410_gpio_setpin(S3C2410_GPA(0), 1);
 389         }
 390
 391         /* fix bus configuration (nBE settings wrong on ABLE pre v2.20) */
 392
 393         local_irq_save(flags);
 394         __raw_writel(__raw_readl(S3C2410_BWSCON) | S3C2410_BWSCON_ST1 | S3C2410_BWSCON_ST2 | S3C2410_BWSCON_ST3 | S3C2410_BWSCON_ST4 | S3C2410_BWSCON_ST5, S3C2410_BWSCON);
 395         local_irq_restore(flags);
 396 }
 397
 398 static void __init osiris_init(void)
 399 {
 400         sysdev_class_register(&osiris_pm_sysclass);
 401         sysdev_register(&osiris_pm_sysdev);
 402
 403         s3c_i2c0_set_platdata(NULL);
 404
 405         i2c_register_board_info(0, osiris_i2c_devs,
 406                                 ARRAY_SIZE(osiris_i2c_devs));
 407
 408         platform_add_devices(osiris_devices, ARRAY_SIZE(osiris_devices));
 409 };
 410
 411 MACHINE_START(OSIRIS, "Simtec-OSIRIS")
 412         /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
 413         .phys_io        = S3C2410_PA_UART,
 414         .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
 415         .boot_params    = S3C2410_SDRAM_PA + 0x100,
 416         .map_io         = osiris_map_io,
 417         .init_irq       = s3c24xx_init_irq,
 418         .init_machine   = osiris_init,
 419         .timer          = &s3c24xx_timer,
 420 MACHINE_END