2 * Driver for DBRI sound chip found on Sparcs.
3 * Copyright (C) 2004, 2005 Martin Habets (mhabets@users.sourceforge.net)
5 * Converted to ring buffered version by Krzysztof Helt (krzysztof.h1@wp.pl)
7 * Based entirely upon drivers/sbus/audio/dbri.c which is:
8 * Copyright (C) 1997 Rudolf Koenig (rfkoenig@immd4.informatik.uni-erlangen.de)
9 * Copyright (C) 1998, 1999 Brent Baccala (baccala@freesoft.org)
11 * This is the low level driver for the DBRI & MMCODEC duo used for ISDN & AUDIO
12 * on Sun SPARCStation 10, 20, LX and Voyager models.
14 * - DBRI: AT&T T5900FX Dual Basic Rates ISDN Interface. It is a 32 channel
15 * data time multiplexer with ISDN support (aka T7259)
16 * Interfaces: SBus,ISDN NT & TE, CHI, 4 bits parallel.
17 * CHI: (spelled ki) Concentration Highway Interface (AT&T or Intel bus ?).
19 * - "STP 4000SBus Dual Basic Rate ISDN (DBRI) Transceiver" from
20 * Sparc Technology Business (courtesy of Sun Support)
21 * - Data sheet of the T7903, a newer but very similar ISA bus equivalent
22 * available from the Lucent (formerly AT&T microelectronics) home
24 * - http://www.freesoft.org/Linux/DBRI/
25 * - MMCODEC: Crystal Semiconductor CS4215 16 bit Multimedia Audio Codec
26 * Interfaces: CHI, Audio In & Out, 2 bits parallel
27 * Documentation: from the Crystal Semiconductor home page.
29 * The DBRI is a 32 pipe machine, each pipe can transfer some bits between
30 * memory and a serial device (long pipes, no. 0-15) or between two serial
31 * devices (short pipes, no. 16-31), or simply send a fixed data to a serial
32 * device (short pipes).
33 * A timeslot defines the bit-offset and no. of bits read from a serial device.
34 * The timeslots are linked to 6 circular lists, one for each direction for
35 * each serial device (NT,TE,CHI). A timeslot is associated to 1 or 2 pipes
36 * (the second one is a monitor/tee pipe, valid only for serial input).
38 * The mmcodec is connected via the CHI bus and needs the data & some
39 * parameters (volume, output selection) time multiplexed in 8 byte
40 * chunks. It also has a control mode, which serves for audio format setting.
42 * Looking at the CS4215 data sheet it is easy to set up 2 or 4 codecs on
43 * the same CHI bus, so I thought perhaps it is possible to use the on-board
44 * & the speakerbox codec simultaneously, giving 2 (not very independent :-)
45 * audio devices. But the SUN HW group decided against it, at least on my
46 * LX the speakerbox connector has at least 1 pin missing and 1 wrongly
49 * I've tried to stick to the following function naming conventions:
51 * cs4215_* CS4215 codec specific stuff
52 * dbri_* DBRI high-level stuff
53 * other DBRI low-level stuff
56 #include <sound/driver.h>
57 #include <linux/interrupt.h>
58 #include <linux/delay.h>
59 #include <linux/irq.h>
62 #include <sound/core.h>
63 #include <sound/pcm.h>
64 #include <sound/pcm_params.h>
65 #include <sound/info.h>
66 #include <sound/control.h>
67 #include <sound/initval.h>
70 #include <asm/atomic.h>
72 MODULE_AUTHOR("Rudolf Koenig, Brent Baccala and Martin Habets");
73 MODULE_DESCRIPTION("Sun DBRI");
74 MODULE_LICENSE("GPL");
75 MODULE_SUPPORTED_DEVICE("{{Sun,DBRI}}");
77 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
78 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
79 /* Enable this card */
80 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
82 module_param_array(index, int, NULL, 0444);
83 MODULE_PARM_DESC(index, "Index value for Sun DBRI soundcard.");
84 module_param_array(id, charp, NULL, 0444);
85 MODULE_PARM_DESC(id, "ID string for Sun DBRI soundcard.");
86 module_param_array(enable, bool, NULL, 0444);
87 MODULE_PARM_DESC(enable, "Enable Sun DBRI soundcard.");
98 static int dbri_debug;
99 module_param(dbri_debug, int, 0644);
100 MODULE_PARM_DESC(dbri_debug, "Debug value for Sun DBRI soundcard.");
103 static char *cmds[] = {
104 "WAIT", "PAUSE", "JUMP", "IIQ", "REX", "SDP", "CDP", "DTS",
105 "SSP", "CHI", "NT", "TE", "CDEC", "TEST", "CDM", "RESRV"
108 #define dprintk(a, x...) if (dbri_debug & a) printk(KERN_DEBUG x)
111 #define dprintk(a, x...) do { } while (0)
113 #endif /* DBRI_DEBUG */
115 #define DBRI_CMD(cmd, intr, value) ((cmd << 28) | \
119 /***************************************************************************
120 CS4215 specific definitions and structures
121 ****************************************************************************/
124 __u8 data[4]; /* Data mode: Time slots 5-8 */
125 __u8 ctrl[4]; /* Ctrl mode: Time slots 1-4 */
127 __u8 offset; /* Bit offset from frame sync to time slot 1 */
128 volatile __u32 status;
129 volatile __u32 version;
130 __u8 precision; /* In bits, either 8 or 16 */
131 __u8 channels; /* 1 or 2 */
138 /* Time Slot 1, Status register */
139 #define CS4215_CLB (1<<2) /* Control Latch Bit */
140 #define CS4215_OLB (1<<3) /* 1: line: 2.0V, speaker 4V */
141 /* 0: line: 2.8V, speaker 8V */
142 #define CS4215_MLB (1<<4) /* 1: Microphone: 20dB gain disabled */
143 #define CS4215_RSRVD_1 (1<<5)
145 /* Time Slot 2, Data Format Register */
146 #define CS4215_DFR_LINEAR16 0
147 #define CS4215_DFR_ULAW 1
148 #define CS4215_DFR_ALAW 2
149 #define CS4215_DFR_LINEAR8 3
150 #define CS4215_DFR_STEREO (1<<2)
156 { 8000, (1 << 4), (0 << 3) },
157 { 16000, (1 << 4), (1 << 3) },
158 { 27429, (1 << 4), (2 << 3) }, /* Actually 24428.57 */
159 { 32000, (1 << 4), (3 << 3) },
160 /* { NA, (1 << 4), (4 << 3) }, */
161 /* { NA, (1 << 4), (5 << 3) }, */
162 { 48000, (1 << 4), (6 << 3) },
163 { 9600, (1 << 4), (7 << 3) },
164 { 5512, (2 << 4), (0 << 3) }, /* Actually 5512.5 */
165 { 11025, (2 << 4), (1 << 3) },
166 { 18900, (2 << 4), (2 << 3) },
167 { 22050, (2 << 4), (3 << 3) },
168 { 37800, (2 << 4), (4 << 3) },
169 { 44100, (2 << 4), (5 << 3) },
170 { 33075, (2 << 4), (6 << 3) },
171 { 6615, (2 << 4), (7 << 3) },
175 #define CS4215_HPF (1<<7) /* High Pass Filter, 1: Enabled */
177 #define CS4215_12_MASK 0xfcbf /* Mask off reserved bits in slot 1 & 2 */
179 /* Time Slot 3, Serial Port Control register */
180 #define CS4215_XEN (1<<0) /* 0: Enable serial output */
181 #define CS4215_XCLK (1<<1) /* 1: Master mode: Generate SCLK */
182 #define CS4215_BSEL_64 (0<<2) /* Bitrate: 64 bits per frame */
183 #define CS4215_BSEL_128 (1<<2)
184 #define CS4215_BSEL_256 (2<<2)
185 #define CS4215_MCK_MAST (0<<4) /* Master clock */
186 #define CS4215_MCK_XTL1 (1<<4) /* 24.576 MHz clock source */
187 #define CS4215_MCK_XTL2 (2<<4) /* 16.9344 MHz clock source */
188 #define CS4215_MCK_CLK1 (3<<4) /* Clockin, 256 x Fs */
189 #define CS4215_MCK_CLK2 (4<<4) /* Clockin, see DFR */
191 /* Time Slot 4, Test Register */
192 #define CS4215_DAD (1<<0) /* 0:Digital-Dig loop, 1:Dig-Analog-Dig loop */
193 #define CS4215_ENL (1<<1) /* Enable Loopback Testing */
195 /* Time Slot 5, Parallel Port Register */
196 /* Read only here and the same as the in data mode */
198 /* Time Slot 6, Reserved */
200 /* Time Slot 7, Version Register */
201 #define CS4215_VERSION_MASK 0xf /* Known versions 0/C, 1/D, 2/E */
203 /* Time Slot 8, Reserved */
208 /* Time Slot 1-2: Left Channel Data, 2-3: Right Channel Data */
210 /* Time Slot 5, Output Setting */
211 #define CS4215_LO(v) v /* Left Output Attenuation 0x3f: -94.5 dB */
212 #define CS4215_LE (1<<6) /* Line Out Enable */
213 #define CS4215_HE (1<<7) /* Headphone Enable */
215 /* Time Slot 6, Output Setting */
216 #define CS4215_RO(v) v /* Right Output Attenuation 0x3f: -94.5 dB */
217 #define CS4215_SE (1<<6) /* Speaker Enable */
218 #define CS4215_ADI (1<<7) /* A/D Data Invalid: Busy in calibration */
220 /* Time Slot 7, Input Setting */
221 #define CS4215_LG(v) v /* Left Gain Setting 0xf: 22.5 dB */
222 #define CS4215_IS (1<<4) /* Input Select: 1=Microphone, 0=Line */
223 #define CS4215_OVR (1<<5) /* 1: Over range condition occurred */
224 #define CS4215_PIO0 (1<<6) /* Parallel I/O 0 */
225 #define CS4215_PIO1 (1<<7)
227 /* Time Slot 8, Input Setting */
228 #define CS4215_RG(v) v /* Right Gain Setting 0xf: 22.5 dB */
229 #define CS4215_MA(v) (v<<4) /* Monitor Path Attenuation 0xf: mute */
231 /***************************************************************************
232 DBRI specific definitions and structures
233 ****************************************************************************/
235 /* DBRI main registers */
236 #define REG0 0x00 /* Status and Control */
237 #define REG1 0x04 /* Mode and Interrupt */
238 #define REG2 0x08 /* Parallel IO */
239 #define REG3 0x0c /* Test */
240 #define REG8 0x20 /* Command Queue Pointer */
241 #define REG9 0x24 /* Interrupt Queue Pointer */
243 #define DBRI_NO_CMDS 64
244 #define DBRI_INT_BLK 64
245 #define DBRI_NO_DESCS 64
246 #define DBRI_NO_PIPES 32
247 #define DBRI_MAX_PIPE (DBRI_NO_PIPES - 1)
251 #define DBRI_NO_STREAMS 2
253 /* One transmit/receive descriptor */
254 /* When ba != 0 descriptor is used */
256 volatile __u32 word1;
257 __u32 ba; /* Transmit/Receive Buffer Address */
258 __u32 nda; /* Next Descriptor Address */
259 volatile __u32 word4;
262 /* This structure is in a DMA region where it can accessed by both
263 * the CPU and the DBRI
266 s32 cmd[DBRI_NO_CMDS]; /* Place for commands */
267 volatile s32 intr[DBRI_INT_BLK]; /* Interrupt field */
268 struct dbri_mem desc[DBRI_NO_DESCS]; /* Xmit/receive descriptors */
271 #define dbri_dma_off(member, elem) \
272 ((u32)(unsigned long) \
273 (&(((struct dbri_dma *)0)->member[elem])))
275 enum in_or_out { PIPEinput, PIPEoutput };
278 u32 sdp; /* SDP command word */
279 int nextpipe; /* Next pipe in linked list */
280 int length; /* Length of timeslot (bits) */
281 int first_desc; /* Index of first descriptor */
282 int desc; /* Index of active descriptor */
283 volatile __u32 *recv_fixed_ptr; /* Ptr to receive fixed data */
286 /* Per stream (playback or record) information */
287 struct dbri_streaminfo {
288 struct snd_pcm_substream *substream;
289 u32 dvma_buffer; /* Device view of ALSA DMA buffer */
290 int size; /* Size of DMA buffer */
291 size_t offset; /* offset in user buffer */
292 int pipe; /* Data pipe used */
293 int left_gain; /* mixer elements */
297 /* This structure holds the information for both chips (DBRI & CS4215) */
299 struct snd_card *card; /* ALSA card */
301 int regs_size, irq; /* Needed for unload */
302 struct sbus_dev *sdev; /* SBUS device info */
305 struct dbri_dma *dma; /* Pointer to our DMA block */
306 u32 dma_dvma; /* DBRI visible DMA address */
308 void __iomem *regs; /* dbri HW regs */
309 int dbri_irqp; /* intr queue pointer */
311 struct dbri_pipe pipes[DBRI_NO_PIPES]; /* DBRI's 32 data pipes */
312 int next_desc[DBRI_NO_DESCS]; /* Index of next desc, or -1 */
313 spinlock_t cmdlock; /* Protects cmd queue accesses */
314 s32 *cmdptr; /* Pointer to the last queued cmd */
318 struct cs4215 mm; /* mmcodec special info */
319 /* per stream (playback/record) info */
320 struct dbri_streaminfo stream_info[DBRI_NO_STREAMS];
322 struct snd_dbri *next;
325 #define DBRI_MAX_VOLUME 63 /* Output volume */
326 #define DBRI_MAX_GAIN 15 /* Input gain */
328 /* DBRI Reg0 - Status Control Register - defines. (Page 17) */
329 #define D_P (1<<15) /* Program command & queue pointer valid */
330 #define D_G (1<<14) /* Allow 4-Word SBus Burst */
331 #define D_S (1<<13) /* Allow 16-Word SBus Burst */
332 #define D_E (1<<12) /* Allow 8-Word SBus Burst */
333 #define D_X (1<<7) /* Sanity Timer Disable */
334 #define D_T (1<<6) /* Permit activation of the TE interface */
335 #define D_N (1<<5) /* Permit activation of the NT interface */
336 #define D_C (1<<4) /* Permit activation of the CHI interface */
337 #define D_F (1<<3) /* Force Sanity Timer Time-Out */
338 #define D_D (1<<2) /* Disable Master Mode */
339 #define D_H (1<<1) /* Halt for Analysis */
340 #define D_R (1<<0) /* Soft Reset */
342 /* DBRI Reg1 - Mode and Interrupt Register - defines. (Page 18) */
343 #define D_LITTLE_END (1<<8) /* Byte Order */
344 #define D_BIG_END (0<<8) /* Byte Order */
345 #define D_MRR (1<<4) /* Multiple Error Ack on SBus (read only) */
346 #define D_MLE (1<<3) /* Multiple Late Error on SBus (read only) */
347 #define D_LBG (1<<2) /* Lost Bus Grant on SBus (read only) */
348 #define D_MBE (1<<1) /* Burst Error on SBus (read only) */
349 #define D_IR (1<<0) /* Interrupt Indicator (read only) */
351 /* DBRI Reg2 - Parallel IO Register - defines. (Page 18) */
352 #define D_ENPIO3 (1<<7) /* Enable Pin 3 */
353 #define D_ENPIO2 (1<<6) /* Enable Pin 2 */
354 #define D_ENPIO1 (1<<5) /* Enable Pin 1 */
355 #define D_ENPIO0 (1<<4) /* Enable Pin 0 */
356 #define D_ENPIO (0xf0) /* Enable all the pins */
357 #define D_PIO3 (1<<3) /* Pin 3: 1: Data mode, 0: Ctrl mode */
358 #define D_PIO2 (1<<2) /* Pin 2: 1: Onboard PDN */
359 #define D_PIO1 (1<<1) /* Pin 1: 0: Reset */
360 #define D_PIO0 (1<<0) /* Pin 0: 1: Speakerbox PDN */
362 /* DBRI Commands (Page 20) */
363 #define D_WAIT 0x0 /* Stop execution */
364 #define D_PAUSE 0x1 /* Flush long pipes */
365 #define D_JUMP 0x2 /* New command queue */
366 #define D_IIQ 0x3 /* Initialize Interrupt Queue */
367 #define D_REX 0x4 /* Report command execution via interrupt */
368 #define D_SDP 0x5 /* Setup Data Pipe */
369 #define D_CDP 0x6 /* Continue Data Pipe (reread NULL Pointer) */
370 #define D_DTS 0x7 /* Define Time Slot */
371 #define D_SSP 0x8 /* Set short Data Pipe */
372 #define D_CHI 0x9 /* Set CHI Global Mode */
373 #define D_NT 0xa /* NT Command */
374 #define D_TE 0xb /* TE Command */
375 #define D_CDEC 0xc /* Codec setup */
376 #define D_TEST 0xd /* No comment */
377 #define D_CDM 0xe /* CHI Data mode command */
379 /* Special bits for some commands */
380 #define D_PIPE(v) ((v)<<0) /* Pipe No.: 0-15 long, 16-21 short */
382 /* Setup Data Pipe */
384 #define D_SDP_2SAME (1<<18) /* Report 2nd time in a row value received */
385 #define D_SDP_CHANGE (2<<18) /* Report any changes */
386 #define D_SDP_EVERY (3<<18) /* Report any changes */
387 #define D_SDP_EOL (1<<17) /* EOL interrupt enable */
388 #define D_SDP_IDLE (1<<16) /* HDLC idle interrupt enable */
391 #define D_SDP_MEM (0<<13) /* To/from memory */
392 #define D_SDP_HDLC (2<<13)
393 #define D_SDP_HDLC_D (3<<13) /* D Channel (prio control) */
394 #define D_SDP_SER (4<<13) /* Serial to serial */
395 #define D_SDP_FIXED (6<<13) /* Short only */
396 #define D_SDP_MODE(v) ((v)&(7<<13))
398 #define D_SDP_TO_SER (1<<12) /* Direction */
399 #define D_SDP_FROM_SER (0<<12) /* Direction */
400 #define D_SDP_MSB (1<<11) /* Bit order within Byte */
401 #define D_SDP_LSB (0<<11) /* Bit order within Byte */
402 #define D_SDP_P (1<<10) /* Pointer Valid */
403 #define D_SDP_A (1<<8) /* Abort */
404 #define D_SDP_C (1<<7) /* Clear */
406 /* Define Time Slot */
407 #define D_DTS_VI (1<<17) /* Valid Input Time-Slot Descriptor */
408 #define D_DTS_VO (1<<16) /* Valid Output Time-Slot Descriptor */
409 #define D_DTS_INS (1<<15) /* Insert Time Slot */
410 #define D_DTS_DEL (0<<15) /* Delete Time Slot */
411 #define D_DTS_PRVIN(v) ((v)<<10) /* Previous In Pipe */
412 #define D_DTS_PRVOUT(v) ((v)<<5) /* Previous Out Pipe */
414 /* Time Slot defines */
415 #define D_TS_LEN(v) ((v)<<24) /* Number of bits in this time slot */
416 #define D_TS_CYCLE(v) ((v)<<14) /* Bit Count at start of TS */
417 #define D_TS_DI (1<<13) /* Data Invert */
418 #define D_TS_1CHANNEL (0<<10) /* Single Channel / Normal mode */
419 #define D_TS_MONITOR (2<<10) /* Monitor pipe */
420 #define D_TS_NONCONTIG (3<<10) /* Non contiguous mode */
421 #define D_TS_ANCHOR (7<<10) /* Starting short pipes */
422 #define D_TS_MON(v) ((v)<<5) /* Monitor Pipe */
423 #define D_TS_NEXT(v) ((v)<<0) /* Pipe no.: 0-15 long, 16-21 short */
425 /* Concentration Highway Interface Modes */
426 #define D_CHI_CHICM(v) ((v)<<16) /* Clock mode */
427 #define D_CHI_IR (1<<15) /* Immediate Interrupt Report */
428 #define D_CHI_EN (1<<14) /* CHIL Interrupt enabled */
429 #define D_CHI_OD (1<<13) /* Open Drain Enable */
430 #define D_CHI_FE (1<<12) /* Sample CHIFS on Rising Frame Edge */
431 #define D_CHI_FD (1<<11) /* Frame Drive */
432 #define D_CHI_BPF(v) ((v)<<0) /* Bits per Frame */
434 /* NT: These are here for completeness */
435 #define D_NT_FBIT (1<<17) /* Frame Bit */
436 #define D_NT_NBF (1<<16) /* Number of bad frames to loose framing */
437 #define D_NT_IRM_IMM (1<<15) /* Interrupt Report & Mask: Immediate */
438 #define D_NT_IRM_EN (1<<14) /* Interrupt Report & Mask: Enable */
439 #define D_NT_ISNT (1<<13) /* Configure interface as NT */
440 #define D_NT_FT (1<<12) /* Fixed Timing */
441 #define D_NT_EZ (1<<11) /* Echo Channel is Zeros */
442 #define D_NT_IFA (1<<10) /* Inhibit Final Activation */
443 #define D_NT_ACT (1<<9) /* Activate Interface */
444 #define D_NT_MFE (1<<8) /* Multiframe Enable */
445 #define D_NT_RLB(v) ((v)<<5) /* Remote Loopback */
446 #define D_NT_LLB(v) ((v)<<2) /* Local Loopback */
447 #define D_NT_FACT (1<<1) /* Force Activation */
448 #define D_NT_ABV (1<<0) /* Activate Bipolar Violation */
451 #define D_CDEC_CK(v) ((v)<<24) /* Clock Select */
452 #define D_CDEC_FED(v) ((v)<<12) /* FSCOD Falling Edge Delay */
453 #define D_CDEC_RED(v) ((v)<<0) /* FSCOD Rising Edge Delay */
456 #define D_TEST_RAM(v) ((v)<<16) /* RAM Pointer */
457 #define D_TEST_SIZE(v) ((v)<<11) /* */
458 #define D_TEST_ROMONOFF 0x5 /* Toggle ROM opcode monitor on/off */
459 #define D_TEST_PROC 0x6 /* Microprocessor test */
460 #define D_TEST_SER 0x7 /* Serial-Controller test */
461 #define D_TEST_RAMREAD 0x8 /* Copy from Ram to system memory */
462 #define D_TEST_RAMWRITE 0x9 /* Copy into Ram from system memory */
463 #define D_TEST_RAMBIST 0xa /* RAM Built-In Self Test */
464 #define D_TEST_MCBIST 0xb /* Microcontroller Built-In Self Test */
465 #define D_TEST_DUMP 0xe /* ROM Dump */
468 #define D_CDM_THI (1 << 8) /* Transmit Data on CHIDR Pin */
469 #define D_CDM_RHI (1 << 7) /* Receive Data on CHIDX Pin */
470 #define D_CDM_RCE (1 << 6) /* Receive on Rising Edge of CHICK */
471 #define D_CDM_XCE (1 << 2) /* Transmit Data on Rising Edge of CHICK */
472 #define D_CDM_XEN (1 << 1) /* Transmit Highway Enable */
473 #define D_CDM_REN (1 << 0) /* Receive Highway Enable */
476 #define D_INTR_BRDY 1 /* Buffer Ready for processing */
477 #define D_INTR_MINT 2 /* Marked Interrupt in RD/TD */
478 #define D_INTR_IBEG 3 /* Flag to idle transition detected (HDLC) */
479 #define D_INTR_IEND 4 /* Idle to flag transition detected (HDLC) */
480 #define D_INTR_EOL 5 /* End of List */
481 #define D_INTR_CMDI 6 /* Command has bean read */
482 #define D_INTR_XCMP 8 /* Transmission of frame complete */
483 #define D_INTR_SBRI 9 /* BRI status change info */
484 #define D_INTR_FXDT 10 /* Fixed data change */
485 #define D_INTR_CHIL 11 /* CHI lost frame sync (channel 36 only) */
486 #define D_INTR_COLL 11 /* Unrecoverable D-Channel collision */
487 #define D_INTR_DBYT 12 /* Dropped by frame slip */
488 #define D_INTR_RBYT 13 /* Repeated by frame slip */
489 #define D_INTR_LINT 14 /* Lost Interrupt */
490 #define D_INTR_UNDR 15 /* DMA underrun */
494 #define D_INTR_CHI 36
495 #define D_INTR_CMD 38
497 #define D_INTR_GETCHAN(v) (((v) >> 24) & 0x3f)
498 #define D_INTR_GETCODE(v) (((v) >> 20) & 0xf)
499 #define D_INTR_GETCMD(v) (((v) >> 16) & 0xf)
500 #define D_INTR_GETVAL(v) ((v) & 0xffff)
501 #define D_INTR_GETRVAL(v) ((v) & 0xfffff)
503 #define D_P_0 0 /* TE receive anchor */
504 #define D_P_1 1 /* TE transmit anchor */
505 #define D_P_2 2 /* NT transmit anchor */
506 #define D_P_3 3 /* NT receive anchor */
507 #define D_P_4 4 /* CHI send data */
508 #define D_P_5 5 /* CHI receive data */
509 #define D_P_6 6 /* */
510 #define D_P_7 7 /* */
511 #define D_P_8 8 /* */
512 #define D_P_9 9 /* */
513 #define D_P_10 10 /* */
514 #define D_P_11 11 /* */
515 #define D_P_12 12 /* */
516 #define D_P_13 13 /* */
517 #define D_P_14 14 /* */
518 #define D_P_15 15 /* */
519 #define D_P_16 16 /* CHI anchor pipe */
520 #define D_P_17 17 /* CHI send */
521 #define D_P_18 18 /* CHI receive */
522 #define D_P_19 19 /* CHI receive */
523 #define D_P_20 20 /* CHI receive */
524 #define D_P_21 21 /* */
525 #define D_P_22 22 /* */
526 #define D_P_23 23 /* */
527 #define D_P_24 24 /* */
528 #define D_P_25 25 /* */
529 #define D_P_26 26 /* */
530 #define D_P_27 27 /* */
531 #define D_P_28 28 /* */
532 #define D_P_29 29 /* */
533 #define D_P_30 30 /* */
534 #define D_P_31 31 /* */
536 /* Transmit descriptor defines */
537 #define DBRI_TD_F (1 << 31) /* End of Frame */
538 #define DBRI_TD_D (1 << 30) /* Do not append CRC */
539 #define DBRI_TD_CNT(v) ((v) << 16) /* Number of valid bytes in the buffer */
540 #define DBRI_TD_B (1 << 15) /* Final interrupt */
541 #define DBRI_TD_M (1 << 14) /* Marker interrupt */
542 #define DBRI_TD_I (1 << 13) /* Transmit Idle Characters */
543 #define DBRI_TD_FCNT(v) (v) /* Flag Count */
544 #define DBRI_TD_UNR (1 << 3) /* Underrun: transmitter is out of data */
545 #define DBRI_TD_ABT (1 << 2) /* Abort: frame aborted */
546 #define DBRI_TD_TBC (1 << 0) /* Transmit buffer Complete */
547 #define DBRI_TD_STATUS(v) ((v) & 0xff) /* Transmit status */
548 /* Maximum buffer size per TD: almost 8KB */
549 #define DBRI_TD_MAXCNT ((1 << 13) - 4)
551 /* Receive descriptor defines */
552 #define DBRI_RD_F (1 << 31) /* End of Frame */
553 #define DBRI_RD_C (1 << 30) /* Completed buffer */
554 #define DBRI_RD_B (1 << 15) /* Final interrupt */
555 #define DBRI_RD_M (1 << 14) /* Marker interrupt */
556 #define DBRI_RD_BCNT(v) (v) /* Buffer size */
557 #define DBRI_RD_CRC (1 << 7) /* 0: CRC is correct */
558 #define DBRI_RD_BBC (1 << 6) /* 1: Bad Byte received */
559 #define DBRI_RD_ABT (1 << 5) /* Abort: frame aborted */
560 #define DBRI_RD_OVRN (1 << 3) /* Overrun: data lost */
561 #define DBRI_RD_STATUS(v) ((v) & 0xff) /* Receive status */
562 #define DBRI_RD_CNT(v) (((v) >> 16) & 0x1fff) /* Valid bytes in the buffer */
564 /* stream_info[] access */
565 /* Translate the ALSA direction into the array index */
566 #define DBRI_STREAMNO(substream) \
567 (substream->stream == \
568 SNDRV_PCM_STREAM_PLAYBACK ? DBRI_PLAY: DBRI_REC)
570 /* Return a pointer to dbri_streaminfo */
571 #define DBRI_STREAM(dbri, substream) \
572 &dbri->stream_info[DBRI_STREAMNO(substream)]
574 static struct snd_dbri *dbri_list; /* All DBRI devices */
577 * Short data pipes transmit LSB first. The CS4215 receives MSB first. Grrr.
578 * So we have to reverse the bits. Note: not all bit lengths are supported
580 static __u32 reverse_bytes(__u32 b, int len)
584 b = ((b & 0xffff0000) >> 16) | ((b & 0x0000ffff) << 16);
586 b = ((b & 0xff00ff00) >> 8) | ((b & 0x00ff00ff) << 8);
588 b = ((b & 0xf0f0f0f0) >> 4) | ((b & 0x0f0f0f0f) << 4);
590 b = ((b & 0xcccccccc) >> 2) | ((b & 0x33333333) << 2);
592 b = ((b & 0xaaaaaaaa) >> 1) | ((b & 0x55555555) << 1);
597 printk(KERN_ERR "DBRI reverse_bytes: unsupported length\n");
604 ****************************************************************************
605 ************** DBRI initialization and command synchronization *************
606 ****************************************************************************
608 Commands are sent to the DBRI by building a list of them in memory,
609 then writing the address of the first list item to DBRI register 8.
610 The list is terminated with a WAIT command, which generates a
611 CPU interrupt to signal completion.
613 Since the DBRI can run in parallel with the CPU, several means of
614 synchronization present themselves. The method implemented here uses
615 the dbri_cmdwait() to wait for execution of batch of sent commands.
617 A circular command buffer is used here. A new command is being added
618 while another can be executed. The scheme works by adding two WAIT commands
619 after each sent batch of commands. When the next batch is prepared it is
620 added after the WAIT commands then the WAITs are replaced with single JUMP
621 command to the new batch. The the DBRI is forced to reread the last WAIT
622 command (replaced by the JUMP by then). If the DBRI is still executing
623 previous commands the request to reread the WAIT command is ignored.
625 Every time a routine wants to write commands to the DBRI, it must
626 first call dbri_cmdlock() and get pointer to a free space in
627 dbri->dma->cmd buffer. After this, the commands can be written to
628 the buffer, and dbri_cmdsend() is called with the final pointer value
629 to send them to the DBRI.
635 * Wait for the current command string to execute
637 static void dbri_cmdwait(struct snd_dbri *dbri)
639 int maxloops = MAXLOOPS;
642 /* Delay if previous commands are still being processed */
643 spin_lock_irqsave(&dbri->lock, flags);
644 while ((--maxloops) > 0 && (sbus_readl(dbri->regs + REG0) & D_P)) {
645 spin_unlock_irqrestore(&dbri->lock, flags);
646 msleep_interruptible(1);
647 spin_lock_irqsave(&dbri->lock, flags);
649 spin_unlock_irqrestore(&dbri->lock, flags);
652 printk(KERN_ERR "DBRI: Chip never completed command buffer\n");
654 dprintk(D_CMD, "Chip completed command buffer (%d)\n",
655 MAXLOOPS - maxloops - 1);
658 * Lock the command queue and return pointer to space for len cmd words
659 * It locks the cmdlock spinlock.
661 static s32 *dbri_cmdlock(struct snd_dbri *dbri, int len)
663 /* Space for 2 WAIT cmds (replaced later by 1 JUMP cmd) */
665 spin_lock(&dbri->cmdlock);
666 if (dbri->cmdptr - dbri->dma->cmd + len < DBRI_NO_CMDS - 2)
667 return dbri->cmdptr + 2;
668 else if (len < sbus_readl(dbri->regs + REG8) - dbri->dma_dvma)
669 return dbri->dma->cmd;
671 printk(KERN_ERR "DBRI: no space for commands.");
677 * Send prepared cmd string. It works by writing a JUMP cmd into
678 * the last WAIT cmd and force DBRI to reread the cmd.
679 * The JUMP cmd points to the new cmd string.
680 * It also releases the cmdlock spinlock.
682 * Lock must be held before calling this.
684 static void dbri_cmdsend(struct snd_dbri *dbri, s32 *cmd, int len)
687 static int wait_id = 0;
690 wait_id &= 0xffff; /* restrict it to a 16 bit counter. */
691 *(cmd) = DBRI_CMD(D_WAIT, 1, wait_id);
692 *(cmd+1) = DBRI_CMD(D_WAIT, 1, wait_id);
694 /* Replace the last command with JUMP */
695 addr = dbri->dma_dvma + (cmd - len - dbri->dma->cmd) * sizeof(s32);
696 *(dbri->cmdptr+1) = addr;
697 *(dbri->cmdptr) = DBRI_CMD(D_JUMP, 0, 0);
700 if (cmd > dbri->cmdptr) {
703 for (ptr = dbri->cmdptr; ptr < cmd+2; ptr++)
704 dprintk(D_CMD, "cmd: %lx:%08x\n",
705 (unsigned long)ptr, *ptr);
707 s32 *ptr = dbri->cmdptr;
709 dprintk(D_CMD, "cmd: %lx:%08x\n", (unsigned long)ptr, *ptr);
711 dprintk(D_CMD, "cmd: %lx:%08x\n", (unsigned long)ptr, *ptr);
712 for (ptr = dbri->dma->cmd; ptr < cmd+2; ptr++)
713 dprintk(D_CMD, "cmd: %lx:%08x\n",
714 (unsigned long)ptr, *ptr);
718 /* Reread the last command */
719 tmp = sbus_readl(dbri->regs + REG0);
721 sbus_writel(tmp, dbri->regs + REG0);
724 spin_unlock(&dbri->cmdlock);
727 /* Lock must be held when calling this */
728 static void dbri_reset(struct snd_dbri *dbri)
733 dprintk(D_GEN, "reset 0:%x 2:%x 8:%x 9:%x\n",
734 sbus_readl(dbri->regs + REG0),
735 sbus_readl(dbri->regs + REG2),
736 sbus_readl(dbri->regs + REG8), sbus_readl(dbri->regs + REG9));
738 sbus_writel(D_R, dbri->regs + REG0); /* Soft Reset */
739 for (i = 0; (sbus_readl(dbri->regs + REG0) & D_R) && i < 64; i++)
742 /* A brute approach - DBRI falls back to working burst size by itself
743 * On SS20 D_S does not work, so do not try so high. */
744 tmp = sbus_readl(dbri->regs + REG0);
747 sbus_writel(tmp, dbri->regs + REG0);
750 /* Lock must not be held before calling this */
751 static void __init dbri_initialize(struct snd_dbri *dbri)
758 spin_lock_irqsave(&dbri->lock, flags);
762 /* Initialize pipes */
763 for (n = 0; n < DBRI_NO_PIPES; n++)
764 dbri->pipes[n].desc = dbri->pipes[n].first_desc = -1;
766 spin_lock_init(&dbri->cmdlock);
768 * Initialize the interrupt ring buffer.
770 dma_addr = dbri->dma_dvma + dbri_dma_off(intr, 0);
771 dbri->dma->intr[0] = dma_addr;
774 * Set up the interrupt queue
776 spin_lock(&dbri->cmdlock);
777 cmd = dbri->cmdptr = dbri->dma->cmd;
778 *(cmd++) = DBRI_CMD(D_IIQ, 0, 0);
780 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
782 *(cmd++) = DBRI_CMD(D_WAIT, 1, 0);
783 *(cmd++) = DBRI_CMD(D_WAIT, 1, 0);
784 dma_addr = dbri->dma_dvma + dbri_dma_off(cmd, 0);
785 sbus_writel(dma_addr, dbri->regs + REG8);
786 spin_unlock(&dbri->cmdlock);
788 spin_unlock_irqrestore(&dbri->lock, flags);
793 ****************************************************************************
794 ************************** DBRI data pipe management ***********************
795 ****************************************************************************
797 While DBRI control functions use the command and interrupt buffers, the
798 main data path takes the form of data pipes, which can be short (command
799 and interrupt driven), or long (attached to DMA buffers). These functions
800 provide a rudimentary means of setting up and managing the DBRI's pipes,
801 but the calling functions have to make sure they respect the pipes' linked
802 list ordering, among other things. The transmit and receive functions
803 here interface closely with the transmit and receive interrupt code.
806 static inline int pipe_active(struct snd_dbri *dbri, int pipe)
808 return ((pipe >= 0) && (dbri->pipes[pipe].desc != -1));
811 /* reset_pipe(dbri, pipe)
813 * Called on an in-use pipe to clear anything being transmitted or received
814 * Lock must be held before calling this.
816 static void reset_pipe(struct snd_dbri *dbri, int pipe)
822 if (pipe < 0 || pipe > DBRI_MAX_PIPE) {
823 printk(KERN_ERR "DBRI: reset_pipe called with "
824 "illegal pipe number\n");
828 sdp = dbri->pipes[pipe].sdp;
830 printk(KERN_ERR "DBRI: reset_pipe called "
831 "on uninitialized pipe\n");
835 cmd = dbri_cmdlock(dbri, 3);
836 *(cmd++) = DBRI_CMD(D_SDP, 0, sdp | D_SDP_C | D_SDP_P);
838 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
839 dbri_cmdsend(dbri, cmd, 3);
841 desc = dbri->pipes[pipe].first_desc;
844 dbri->dma->desc[desc].ba = 0;
845 dbri->dma->desc[desc].nda = 0;
846 desc = dbri->next_desc[desc];
847 } while (desc != -1 && desc != dbri->pipes[pipe].first_desc);
849 dbri->pipes[pipe].desc = -1;
850 dbri->pipes[pipe].first_desc = -1;
854 * Lock must be held before calling this.
856 static void setup_pipe(struct snd_dbri *dbri, int pipe, int sdp)
858 if (pipe < 0 || pipe > DBRI_MAX_PIPE) {
859 printk(KERN_ERR "DBRI: setup_pipe called "
860 "with illegal pipe number\n");
864 if ((sdp & 0xf800) != sdp) {
865 printk(KERN_ERR "DBRI: setup_pipe called "
866 "with strange SDP value\n");
870 /* If this is a fixed receive pipe, arrange for an interrupt
871 * every time its data changes
873 if (D_SDP_MODE(sdp) == D_SDP_FIXED && !(sdp & D_SDP_TO_SER))
877 dbri->pipes[pipe].sdp = sdp;
878 dbri->pipes[pipe].desc = -1;
879 dbri->pipes[pipe].first_desc = -1;
881 reset_pipe(dbri, pipe);
885 * Lock must be held before calling this.
887 static void link_time_slot(struct snd_dbri *dbri, int pipe,
888 int prevpipe, int nextpipe,
889 int length, int cycle)
894 if (pipe < 0 || pipe > DBRI_MAX_PIPE
895 || prevpipe < 0 || prevpipe > DBRI_MAX_PIPE
896 || nextpipe < 0 || nextpipe > DBRI_MAX_PIPE) {
898 "DBRI: link_time_slot called with illegal pipe number\n");
902 if (dbri->pipes[pipe].sdp == 0
903 || dbri->pipes[prevpipe].sdp == 0
904 || dbri->pipes[nextpipe].sdp == 0) {
905 printk(KERN_ERR "DBRI: link_time_slot called "
906 "on uninitialized pipe\n");
910 dbri->pipes[prevpipe].nextpipe = pipe;
911 dbri->pipes[pipe].nextpipe = nextpipe;
912 dbri->pipes[pipe].length = length;
914 cmd = dbri_cmdlock(dbri, 4);
916 if (dbri->pipes[pipe].sdp & D_SDP_TO_SER) {
917 /* Deal with CHI special case:
918 * "If transmission on edges 0 or 1 is desired, then cycle n
919 * (where n = # of bit times per frame...) must be used."
920 * - DBRI data sheet, page 11
922 if (prevpipe == 16 && cycle == 0)
923 cycle = dbri->chi_bpf;
925 val = D_DTS_VO | D_DTS_INS | D_DTS_PRVOUT(prevpipe) | pipe;
926 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
929 D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe);
931 val = D_DTS_VI | D_DTS_INS | D_DTS_PRVIN(prevpipe) | pipe;
932 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
934 D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe);
937 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
939 dbri_cmdsend(dbri, cmd, 4);
944 * Lock must be held before calling this.
946 static void unlink_time_slot(struct snd_dbri *dbri, int pipe,
947 enum in_or_out direction, int prevpipe,
953 if (pipe < 0 || pipe > DBRI_MAX_PIPE
954 || prevpipe < 0 || prevpipe > DBRI_MAX_PIPE
955 || nextpipe < 0 || nextpipe > DBRI_MAX_PIPE) {
957 "DBRI: unlink_time_slot called with illegal pipe number\n");
961 cmd = dbri_cmdlock(dbri, 4);
963 if (direction == PIPEinput) {
964 val = D_DTS_VI | D_DTS_DEL | D_DTS_PRVIN(prevpipe) | pipe;
965 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
966 *(cmd++) = D_TS_NEXT(nextpipe);
969 val = D_DTS_VO | D_DTS_DEL | D_DTS_PRVOUT(prevpipe) | pipe;
970 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
972 *(cmd++) = D_TS_NEXT(nextpipe);
974 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
976 dbri_cmdsend(dbri, cmd, 4);
980 /* xmit_fixed() / recv_fixed()
982 * Transmit/receive data on a "fixed" pipe - i.e, one whose contents are not
983 * expected to change much, and which we don't need to buffer.
984 * The DBRI only interrupts us when the data changes (receive pipes),
985 * or only changes the data when this function is called (transmit pipes).
986 * Only short pipes (numbers 16-31) can be used in fixed data mode.
988 * These function operate on a 32-bit field, no matter how large
989 * the actual time slot is. The interrupt handler takes care of bit
990 * ordering and alignment. An 8-bit time slot will always end up
991 * in the low-order 8 bits, filled either MSB-first or LSB-first,
992 * depending on the settings passed to setup_pipe().
994 * Lock must not be held before calling it.
996 static void xmit_fixed(struct snd_dbri *dbri, int pipe, unsigned int data)
1001 if (pipe < 16 || pipe > DBRI_MAX_PIPE) {
1002 printk(KERN_ERR "DBRI: xmit_fixed: Illegal pipe number\n");
1006 if (D_SDP_MODE(dbri->pipes[pipe].sdp) == 0) {
1007 printk(KERN_ERR "DBRI: xmit_fixed: "
1008 "Uninitialized pipe %d\n", pipe);
1012 if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) {
1013 printk(KERN_ERR "DBRI: xmit_fixed: Non-fixed pipe %d\n", pipe);
1017 if (!(dbri->pipes[pipe].sdp & D_SDP_TO_SER)) {
1018 printk(KERN_ERR "DBRI: xmit_fixed: Called on receive pipe %d\n",
1023 /* DBRI short pipes always transmit LSB first */
1025 if (dbri->pipes[pipe].sdp & D_SDP_MSB)
1026 data = reverse_bytes(data, dbri->pipes[pipe].length);
1028 cmd = dbri_cmdlock(dbri, 3);
1030 *(cmd++) = DBRI_CMD(D_SSP, 0, pipe);
1032 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
1034 spin_lock_irqsave(&dbri->lock, flags);
1035 dbri_cmdsend(dbri, cmd, 3);
1036 spin_unlock_irqrestore(&dbri->lock, flags);
1041 static void recv_fixed(struct snd_dbri *dbri, int pipe, volatile __u32 *ptr)
1043 if (pipe < 16 || pipe > DBRI_MAX_PIPE) {
1044 printk(KERN_ERR "DBRI: recv_fixed called with "
1045 "illegal pipe number\n");
1049 if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) {
1050 printk(KERN_ERR "DBRI: recv_fixed called on "
1051 "non-fixed pipe %d\n", pipe);
1055 if (dbri->pipes[pipe].sdp & D_SDP_TO_SER) {
1056 printk(KERN_ERR "DBRI: recv_fixed called on "
1057 "transmit pipe %d\n", pipe);
1061 dbri->pipes[pipe].recv_fixed_ptr = ptr;
1066 * Setup transmit/receive data on a "long" pipe - i.e, one associated
1067 * with a DMA buffer.
1069 * Only pipe numbers 0-15 can be used in this mode.
1071 * This function takes a stream number pointing to a data buffer,
1072 * and work by building chains of descriptors which identify the
1073 * data buffers. Buffers too large for a single descriptor will
1074 * be spread across multiple descriptors.
1076 * All descriptors create a ring buffer.
1078 * Lock must be held before calling this.
1080 static int setup_descs(struct snd_dbri *dbri, int streamno, unsigned int period)
1082 struct dbri_streaminfo *info = &dbri->stream_info[streamno];
1086 int first_desc = -1;
1089 if (info->pipe < 0 || info->pipe > 15) {
1090 printk(KERN_ERR "DBRI: setup_descs: Illegal pipe number\n");
1094 if (dbri->pipes[info->pipe].sdp == 0) {
1095 printk(KERN_ERR "DBRI: setup_descs: Uninitialized pipe %d\n",
1100 dvma_buffer = info->dvma_buffer;
1103 if (streamno == DBRI_PLAY) {
1104 if (!(dbri->pipes[info->pipe].sdp & D_SDP_TO_SER)) {
1105 printk(KERN_ERR "DBRI: setup_descs: "
1106 "Called on receive pipe %d\n", info->pipe);
1110 if (dbri->pipes[info->pipe].sdp & D_SDP_TO_SER) {
1112 "DBRI: setup_descs: Called on transmit pipe %d\n",
1116 /* Should be able to queue multiple buffers
1117 * to receive on a pipe
1119 if (pipe_active(dbri, info->pipe)) {
1120 printk(KERN_ERR "DBRI: recv_on_pipe: "
1121 "Called on active pipe %d\n", info->pipe);
1125 /* Make sure buffer size is multiple of four */
1129 /* Free descriptors if pipe has any */
1130 desc = dbri->pipes[info->pipe].first_desc;
1133 dbri->dma->desc[desc].ba = 0;
1134 dbri->dma->desc[desc].nda = 0;
1135 desc = dbri->next_desc[desc];
1136 } while (desc != -1 &&
1137 desc != dbri->pipes[info->pipe].first_desc);
1139 dbri->pipes[info->pipe].desc = -1;
1140 dbri->pipes[info->pipe].first_desc = -1;
1146 for (; desc < DBRI_NO_DESCS; desc++) {
1147 if (!dbri->dma->desc[desc].ba)
1151 if (desc == DBRI_NO_DESCS) {
1152 printk(KERN_ERR "DBRI: setup_descs: No descriptors\n");
1156 if (len > DBRI_TD_MAXCNT)
1157 mylen = DBRI_TD_MAXCNT; /* 8KB - 4 */
1164 dbri->next_desc[desc] = -1;
1165 dbri->dma->desc[desc].ba = dvma_buffer;
1166 dbri->dma->desc[desc].nda = 0;
1168 if (streamno == DBRI_PLAY) {
1169 dbri->dma->desc[desc].word1 = DBRI_TD_CNT(mylen);
1170 dbri->dma->desc[desc].word4 = 0;
1171 dbri->dma->desc[desc].word1 |= DBRI_TD_F | DBRI_TD_B;
1173 dbri->dma->desc[desc].word1 = 0;
1174 dbri->dma->desc[desc].word4 =
1175 DBRI_RD_B | DBRI_RD_BCNT(mylen);
1178 if (first_desc == -1)
1181 dbri->next_desc[last_desc] = desc;
1182 dbri->dma->desc[last_desc].nda =
1183 dbri->dma_dvma + dbri_dma_off(desc, desc);
1187 dvma_buffer += mylen;
1191 if (first_desc == -1 || last_desc == -1) {
1192 printk(KERN_ERR "DBRI: setup_descs: "
1193 " Not enough descriptors available\n");
1197 dbri->dma->desc[last_desc].nda =
1198 dbri->dma_dvma + dbri_dma_off(desc, first_desc);
1199 dbri->next_desc[last_desc] = first_desc;
1200 dbri->pipes[info->pipe].first_desc = first_desc;
1201 dbri->pipes[info->pipe].desc = first_desc;
1204 for (desc = first_desc; desc != -1;) {
1205 dprintk(D_DESC, "DESC %d: %08x %08x %08x %08x\n",
1207 dbri->dma->desc[desc].word1,
1208 dbri->dma->desc[desc].ba,
1209 dbri->dma->desc[desc].nda, dbri->dma->desc[desc].word4);
1210 desc = dbri->next_desc[desc];
1211 if (desc == first_desc)
1219 ****************************************************************************
1220 ************************** DBRI - CHI interface ****************************
1221 ****************************************************************************
1223 The CHI is a four-wire (clock, frame sync, data in, data out) time-division
1224 multiplexed serial interface which the DBRI can operate in either master
1225 (give clock/frame sync) or slave (take clock/frame sync) mode.
1229 enum master_or_slave { CHImaster, CHIslave };
1232 * Lock must not be held before calling it.
1234 static void reset_chi(struct snd_dbri *dbri,
1235 enum master_or_slave master_or_slave,
1241 /* Set CHI Anchor: Pipe 16 */
1243 cmd = dbri_cmdlock(dbri, 4);
1244 val = D_DTS_VO | D_DTS_VI | D_DTS_INS
1245 | D_DTS_PRVIN(16) | D_PIPE(16) | D_DTS_PRVOUT(16);
1246 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
1247 *(cmd++) = D_TS_ANCHOR | D_TS_NEXT(16);
1248 *(cmd++) = D_TS_ANCHOR | D_TS_NEXT(16);
1249 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
1250 dbri_cmdsend(dbri, cmd, 4);
1252 dbri->pipes[16].sdp = 1;
1253 dbri->pipes[16].nextpipe = 16;
1255 cmd = dbri_cmdlock(dbri, 4);
1257 if (master_or_slave == CHIslave) {
1258 /* Setup DBRI for CHI Slave - receive clock, frame sync (FS)
1260 * CHICM = 0 (slave mode, 8 kHz frame rate)
1261 * IR = give immediate CHI status interrupt
1262 * EN = give CHI status interrupt upon change
1264 *(cmd++) = DBRI_CMD(D_CHI, 0, D_CHI_CHICM(0));
1266 /* Setup DBRI for CHI Master - generate clock, FS
1268 * BPF = bits per 8 kHz frame
1269 * 12.288 MHz / CHICM_divisor = clock rate
1270 * FD = 1 - drive CHIFS on rising edge of CHICK
1272 int clockrate = bits_per_frame * 8;
1273 int divisor = 12288 / clockrate;
1275 if (divisor > 255 || divisor * clockrate != 12288)
1276 printk(KERN_ERR "DBRI: illegal bits_per_frame "
1279 *(cmd++) = DBRI_CMD(D_CHI, 0, D_CHI_CHICM(divisor) | D_CHI_FD
1280 | D_CHI_BPF(bits_per_frame));
1283 dbri->chi_bpf = bits_per_frame;
1287 * RCE = 0 - receive on falling edge of CHICK
1288 * XCE = 1 - transmit on rising edge of CHICK
1289 * XEN = 1 - enable transmitter
1290 * REN = 1 - enable receiver
1293 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
1294 *(cmd++) = DBRI_CMD(D_CDM, 0, D_CDM_XCE | D_CDM_XEN | D_CDM_REN);
1295 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
1297 dbri_cmdsend(dbri, cmd, 4);
1301 ****************************************************************************
1302 *********************** CS4215 audio codec management **********************
1303 ****************************************************************************
1305 In the standard SPARC audio configuration, the CS4215 codec is attached
1306 to the DBRI via the CHI interface and few of the DBRI's PIO pins.
1308 * Lock must not be held before calling it.
1311 static __init void cs4215_setup_pipes(struct snd_dbri *dbri)
1313 unsigned long flags;
1315 spin_lock_irqsave(&dbri->lock, flags);
1318 * Pipe 4: Send timeslots 1-4 (audio data)
1319 * Pipe 20: Send timeslots 5-8 (part of ctrl data)
1320 * Pipe 6: Receive timeslots 1-4 (audio data)
1321 * Pipe 21: Receive timeslots 6-7. We can only receive 20 bits via
1322 * interrupt, and the rest of the data (slot 5 and 8) is
1323 * not relevant for us (only for doublechecking).
1326 * Pipe 17: Send timeslots 1-4 (slots 5-8 are read only)
1327 * Pipe 18: Receive timeslot 1 (clb).
1328 * Pipe 19: Receive timeslot 7 (version).
1331 setup_pipe(dbri, 4, D_SDP_MEM | D_SDP_TO_SER | D_SDP_MSB);
1332 setup_pipe(dbri, 20, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB);
1333 setup_pipe(dbri, 6, D_SDP_MEM | D_SDP_FROM_SER | D_SDP_MSB);
1334 setup_pipe(dbri, 21, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1336 setup_pipe(dbri, 17, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB);
1337 setup_pipe(dbri, 18, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1338 setup_pipe(dbri, 19, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1339 spin_unlock_irqrestore(&dbri->lock, flags);
1344 static __init int cs4215_init_data(struct cs4215 *mm)
1347 * No action, memory resetting only.
1349 * Data Time Slot 5-8
1350 * Speaker,Line and Headphone enable. Gain set to the half.
1353 mm->data[0] = CS4215_LO(0x20) | CS4215_HE | CS4215_LE;
1354 mm->data[1] = CS4215_RO(0x20) | CS4215_SE;
1355 mm->data[2] = CS4215_LG(0x8) | CS4215_IS | CS4215_PIO0 | CS4215_PIO1;
1356 mm->data[3] = CS4215_RG(0x8) | CS4215_MA(0xf);
1359 * Control Time Slot 1-4
1360 * 0: Default I/O voltage scale
1361 * 1: 8 bit ulaw, 8kHz, mono, high pass filter disabled
1362 * 2: Serial enable, CHI master, 128 bits per frame, clock 1
1365 mm->ctrl[0] = CS4215_RSRVD_1 | CS4215_MLB;
1366 mm->ctrl[1] = CS4215_DFR_ULAW | CS4215_FREQ[0].csval;
1367 mm->ctrl[2] = CS4215_XCLK | CS4215_BSEL_128 | CS4215_FREQ[0].xtal;
1372 mm->precision = 8; /* For ULAW */
1378 static void cs4215_setdata(struct snd_dbri *dbri, int muted)
1381 dbri->mm.data[0] |= 63;
1382 dbri->mm.data[1] |= 63;
1383 dbri->mm.data[2] &= ~15;
1384 dbri->mm.data[3] &= ~15;
1386 /* Start by setting the playback attenuation. */
1387 struct dbri_streaminfo *info = &dbri->stream_info[DBRI_PLAY];
1388 int left_gain = info->left_gain & 0x3f;
1389 int right_gain = info->right_gain & 0x3f;
1391 dbri->mm.data[0] &= ~0x3f; /* Reset the volume bits */
1392 dbri->mm.data[1] &= ~0x3f;
1393 dbri->mm.data[0] |= (DBRI_MAX_VOLUME - left_gain);
1394 dbri->mm.data[1] |= (DBRI_MAX_VOLUME - right_gain);
1396 /* Now set the recording gain. */
1397 info = &dbri->stream_info[DBRI_REC];
1398 left_gain = info->left_gain & 0xf;
1399 right_gain = info->right_gain & 0xf;
1400 dbri->mm.data[2] |= CS4215_LG(left_gain);
1401 dbri->mm.data[3] |= CS4215_RG(right_gain);
1404 xmit_fixed(dbri, 20, *(int *)dbri->mm.data);
1408 * Set the CS4215 to data mode.
1410 static void cs4215_open(struct snd_dbri *dbri)
1414 unsigned long flags;
1416 dprintk(D_MM, "cs4215_open: %d channels, %d bits\n",
1417 dbri->mm.channels, dbri->mm.precision);
1419 /* Temporarily mute outputs, and wait 1/8000 sec (125 us)
1420 * to make sure this takes. This avoids clicking noises.
1423 cs4215_setdata(dbri, 1);
1428 * Pipe 4: Send timeslots 1-4 (audio data)
1429 * Pipe 20: Send timeslots 5-8 (part of ctrl data)
1430 * Pipe 6: Receive timeslots 1-4 (audio data)
1431 * Pipe 21: Receive timeslots 6-7. We can only receive 20 bits via
1432 * interrupt, and the rest of the data (slot 5 and 8) is
1433 * not relevant for us (only for doublechecking).
1435 * Just like in control mode, the time slots are all offset by eight
1436 * bits. The CS4215, it seems, observes TSIN (the delayed signal)
1437 * even if it's the CHI master. Don't ask me...
1439 spin_lock_irqsave(&dbri->lock, flags);
1440 tmp = sbus_readl(dbri->regs + REG0);
1441 tmp &= ~(D_C); /* Disable CHI */
1442 sbus_writel(tmp, dbri->regs + REG0);
1444 /* Switch CS4215 to data mode - set PIO3 to 1 */
1445 sbus_writel(D_ENPIO | D_PIO1 | D_PIO3 |
1446 (dbri->mm.onboard ? D_PIO0 : D_PIO2), dbri->regs + REG2);
1448 reset_chi(dbri, CHIslave, 128);
1450 /* Note: this next doesn't work for 8-bit stereo, because the two
1451 * channels would be on timeslots 1 and 3, with 2 and 4 idle.
1452 * (See CS4215 datasheet Fig 15)
1454 * DBRI non-contiguous mode would be required to make this work.
1456 data_width = dbri->mm.channels * dbri->mm.precision;
1458 link_time_slot(dbri, 4, 16, 16, data_width, dbri->mm.offset);
1459 link_time_slot(dbri, 20, 4, 16, 32, dbri->mm.offset + 32);
1460 link_time_slot(dbri, 6, 16, 16, data_width, dbri->mm.offset);
1461 link_time_slot(dbri, 21, 6, 16, 16, dbri->mm.offset + 40);
1463 /* FIXME: enable CHI after _setdata? */
1464 tmp = sbus_readl(dbri->regs + REG0);
1465 tmp |= D_C; /* Enable CHI */
1466 sbus_writel(tmp, dbri->regs + REG0);
1467 spin_unlock_irqrestore(&dbri->lock, flags);
1469 cs4215_setdata(dbri, 0);
1473 * Send the control information (i.e. audio format)
1475 static int cs4215_setctrl(struct snd_dbri *dbri)
1479 unsigned long flags;
1481 /* FIXME - let the CPU do something useful during these delays */
1483 /* Temporarily mute outputs, and wait 1/8000 sec (125 us)
1484 * to make sure this takes. This avoids clicking noises.
1486 cs4215_setdata(dbri, 1);
1490 * Enable Control mode: Set DBRI's PIO3 (4215's D/~C) to 0, then wait
1491 * 12 cycles <= 12/(5512.5*64) sec = 34.01 usec
1493 val = D_ENPIO | D_PIO1 | (dbri->mm.onboard ? D_PIO0 : D_PIO2);
1494 sbus_writel(val, dbri->regs + REG2);
1495 dprintk(D_MM, "cs4215_setctrl: reg2=0x%x\n", val);
1498 /* In Control mode, the CS4215 is a slave device, so the DBRI must
1499 * operate as CHI master, supplying clocking and frame synchronization.
1501 * In Data mode, however, the CS4215 must be CHI master to insure
1502 * that its data stream is synchronous with its codec.
1504 * The upshot of all this? We start by putting the DBRI into master
1505 * mode, program the CS4215 in Control mode, then switch the CS4215
1506 * into Data mode and put the DBRI into slave mode. Various timing
1507 * requirements must be observed along the way.
1509 * Oh, and one more thing, on a SPARCStation 20 (and maybe
1510 * others?), the addressing of the CS4215's time slots is
1511 * offset by eight bits, so we add eight to all the "cycle"
1512 * values in the Define Time Slot (DTS) commands. This is
1513 * done in hardware by a TI 248 that delays the DBRI->4215
1514 * frame sync signal by eight clock cycles. Anybody know why?
1516 spin_lock_irqsave(&dbri->lock, flags);
1517 tmp = sbus_readl(dbri->regs + REG0);
1518 tmp &= ~D_C; /* Disable CHI */
1519 sbus_writel(tmp, dbri->regs + REG0);
1521 reset_chi(dbri, CHImaster, 128);
1525 * Pipe 17: Send timeslots 1-4 (slots 5-8 are read only)
1526 * Pipe 18: Receive timeslot 1 (clb).
1527 * Pipe 19: Receive timeslot 7 (version).
1530 link_time_slot(dbri, 17, 16, 16, 32, dbri->mm.offset);
1531 link_time_slot(dbri, 18, 16, 16, 8, dbri->mm.offset);
1532 link_time_slot(dbri, 19, 18, 16, 8, dbri->mm.offset + 48);
1533 spin_unlock_irqrestore(&dbri->lock, flags);
1535 /* Wait for the chip to echo back CLB (Control Latch Bit) as zero */
1536 dbri->mm.ctrl[0] &= ~CS4215_CLB;
1537 xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl);
1539 spin_lock_irqsave(&dbri->lock, flags);
1540 tmp = sbus_readl(dbri->regs + REG0);
1541 tmp |= D_C; /* Enable CHI */
1542 sbus_writel(tmp, dbri->regs + REG0);
1543 spin_unlock_irqrestore(&dbri->lock, flags);
1545 for (i = 10; ((dbri->mm.status & 0xe4) != 0x20); --i)
1546 msleep_interruptible(1);
1549 dprintk(D_MM, "CS4215 didn't respond to CLB (0x%02x)\n",
1554 /* Disable changes to our copy of the version number, as we are about
1555 * to leave control mode.
1557 recv_fixed(dbri, 19, NULL);
1559 /* Terminate CS4215 control mode - data sheet says
1560 * "Set CLB=1 and send two more frames of valid control info"
1562 dbri->mm.ctrl[0] |= CS4215_CLB;
1563 xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl);
1565 /* Two frames of control info @ 8kHz frame rate = 250 us delay */
1568 cs4215_setdata(dbri, 0);
1574 * Setup the codec with the sampling rate, audio format and number of
1576 * As part of the process we resend the settings for the data
1577 * timeslots as well.
1579 static int cs4215_prepare(struct snd_dbri *dbri, unsigned int rate,
1580 snd_pcm_format_t format, unsigned int channels)
1585 /* Lookup index for this rate */
1586 for (freq_idx = 0; CS4215_FREQ[freq_idx].freq != 0; freq_idx++) {
1587 if (CS4215_FREQ[freq_idx].freq == rate)
1590 if (CS4215_FREQ[freq_idx].freq != rate) {
1591 printk(KERN_WARNING "DBRI: Unsupported rate %d Hz\n", rate);
1596 case SNDRV_PCM_FORMAT_MU_LAW:
1597 dbri->mm.ctrl[1] = CS4215_DFR_ULAW;
1598 dbri->mm.precision = 8;
1600 case SNDRV_PCM_FORMAT_A_LAW:
1601 dbri->mm.ctrl[1] = CS4215_DFR_ALAW;
1602 dbri->mm.precision = 8;
1604 case SNDRV_PCM_FORMAT_U8:
1605 dbri->mm.ctrl[1] = CS4215_DFR_LINEAR8;
1606 dbri->mm.precision = 8;
1608 case SNDRV_PCM_FORMAT_S16_BE:
1609 dbri->mm.ctrl[1] = CS4215_DFR_LINEAR16;
1610 dbri->mm.precision = 16;
1613 printk(KERN_WARNING "DBRI: Unsupported format %d\n", format);
1617 /* Add rate parameters */
1618 dbri->mm.ctrl[1] |= CS4215_FREQ[freq_idx].csval;
1619 dbri->mm.ctrl[2] = CS4215_XCLK |
1620 CS4215_BSEL_128 | CS4215_FREQ[freq_idx].xtal;
1622 dbri->mm.channels = channels;
1624 dbri->mm.ctrl[1] |= CS4215_DFR_STEREO;
1626 ret = cs4215_setctrl(dbri);
1628 cs4215_open(dbri); /* set codec to data mode */
1636 static __init int cs4215_init(struct snd_dbri *dbri)
1638 u32 reg2 = sbus_readl(dbri->regs + REG2);
1639 dprintk(D_MM, "cs4215_init: reg2=0x%x\n", reg2);
1641 /* Look for the cs4215 chips */
1642 if (reg2 & D_PIO2) {
1643 dprintk(D_MM, "Onboard CS4215 detected\n");
1644 dbri->mm.onboard = 1;
1646 if (reg2 & D_PIO0) {
1647 dprintk(D_MM, "Speakerbox detected\n");
1648 dbri->mm.onboard = 0;
1650 if (reg2 & D_PIO2) {
1651 printk(KERN_INFO "DBRI: Using speakerbox / "
1652 "ignoring onboard mmcodec.\n");
1653 sbus_writel(D_ENPIO2, dbri->regs + REG2);
1657 if (!(reg2 & (D_PIO0 | D_PIO2))) {
1658 printk(KERN_ERR "DBRI: no mmcodec found.\n");
1662 cs4215_setup_pipes(dbri);
1663 cs4215_init_data(&dbri->mm);
1665 /* Enable capture of the status & version timeslots. */
1666 recv_fixed(dbri, 18, &dbri->mm.status);
1667 recv_fixed(dbri, 19, &dbri->mm.version);
1669 dbri->mm.offset = dbri->mm.onboard ? 0 : 8;
1670 if (cs4215_setctrl(dbri) == -1 || dbri->mm.version == 0xff) {
1671 dprintk(D_MM, "CS4215 failed probe at offset %d\n",
1675 dprintk(D_MM, "Found CS4215 at offset %d\n", dbri->mm.offset);
1681 ****************************************************************************
1682 *************************** DBRI interrupt handler *************************
1683 ****************************************************************************
1685 The DBRI communicates with the CPU mainly via a circular interrupt
1686 buffer. When an interrupt is signaled, the CPU walks through the
1687 buffer and calls dbri_process_one_interrupt() for each interrupt word.
1688 Complicated interrupts are handled by dedicated functions (which
1689 appear first in this file). Any pending interrupts can be serviced by
1690 calling dbri_process_interrupt_buffer(), which works even if the CPU's
1691 interrupts are disabled.
1697 * Starts transmitting the current TD's for recording/playing.
1698 * For playback, ALSA has filled the DMA memory with new data (we hope).
1700 static void xmit_descs(struct snd_dbri *dbri)
1702 struct dbri_streaminfo *info;
1704 unsigned long flags;
1708 return; /* Disabled */
1710 info = &dbri->stream_info[DBRI_REC];
1711 spin_lock_irqsave(&dbri->lock, flags);
1713 if (info->pipe >= 0) {
1714 first_td = dbri->pipes[info->pipe].first_desc;
1716 dprintk(D_DESC, "xmit_descs rec @ TD %d\n", first_td);
1718 /* Stream could be closed by the time we run. */
1719 if (first_td >= 0) {
1720 cmd = dbri_cmdlock(dbri, 2);
1721 *(cmd++) = DBRI_CMD(D_SDP, 0,
1722 dbri->pipes[info->pipe].sdp
1723 | D_SDP_P | D_SDP_EVERY | D_SDP_C);
1724 *(cmd++) = dbri->dma_dvma +
1725 dbri_dma_off(desc, first_td);
1726 dbri_cmdsend(dbri, cmd, 2);
1728 /* Reset our admin of the pipe. */
1729 dbri->pipes[info->pipe].desc = first_td;
1733 info = &dbri->stream_info[DBRI_PLAY];
1735 if (info->pipe >= 0) {
1736 first_td = dbri->pipes[info->pipe].first_desc;
1738 dprintk(D_DESC, "xmit_descs play @ TD %d\n", first_td);
1740 /* Stream could be closed by the time we run. */
1741 if (first_td >= 0) {
1742 cmd = dbri_cmdlock(dbri, 2);
1743 *(cmd++) = DBRI_CMD(D_SDP, 0,
1744 dbri->pipes[info->pipe].sdp
1745 | D_SDP_P | D_SDP_EVERY | D_SDP_C);
1746 *(cmd++) = dbri->dma_dvma +
1747 dbri_dma_off(desc, first_td);
1748 dbri_cmdsend(dbri, cmd, 2);
1750 /* Reset our admin of the pipe. */
1751 dbri->pipes[info->pipe].desc = first_td;
1755 spin_unlock_irqrestore(&dbri->lock, flags);
1758 /* transmission_complete_intr()
1760 * Called by main interrupt handler when DBRI signals transmission complete
1761 * on a pipe (interrupt triggered by the B bit in a transmit descriptor).
1763 * Walks through the pipe's list of transmit buffer descriptors and marks
1764 * them as available. Stops when the first descriptor is found without
1765 * TBC (Transmit Buffer Complete) set, or we've run through them all.
1767 * The DMA buffers are not released. They form a ring buffer and
1768 * they are filled by ALSA while others are transmitted by DMA.
1772 static void transmission_complete_intr(struct snd_dbri *dbri, int pipe)
1774 struct dbri_streaminfo *info = &dbri->stream_info[DBRI_PLAY];
1775 int td = dbri->pipes[pipe].desc;
1779 if (td >= DBRI_NO_DESCS) {
1780 printk(KERN_ERR "DBRI: invalid td on pipe %d\n", pipe);
1784 status = DBRI_TD_STATUS(dbri->dma->desc[td].word4);
1785 if (!(status & DBRI_TD_TBC))
1788 dprintk(D_INT, "TD %d, status 0x%02x\n", td, status);
1790 dbri->dma->desc[td].word4 = 0; /* Reset it for next time. */
1791 info->offset += DBRI_RD_CNT(dbri->dma->desc[td].word1);
1793 td = dbri->next_desc[td];
1794 dbri->pipes[pipe].desc = td;
1798 spin_unlock(&dbri->lock);
1799 snd_pcm_period_elapsed(info->substream);
1800 spin_lock(&dbri->lock);
1803 static void reception_complete_intr(struct snd_dbri *dbri, int pipe)
1805 struct dbri_streaminfo *info;
1806 int rd = dbri->pipes[pipe].desc;
1809 if (rd < 0 || rd >= DBRI_NO_DESCS) {
1810 printk(KERN_ERR "DBRI: invalid rd on pipe %d\n", pipe);
1814 dbri->pipes[pipe].desc = dbri->next_desc[rd];
1815 status = dbri->dma->desc[rd].word1;
1816 dbri->dma->desc[rd].word1 = 0; /* Reset it for next time. */
1818 info = &dbri->stream_info[DBRI_REC];
1819 info->offset += DBRI_RD_CNT(status);
1821 /* FIXME: Check status */
1823 dprintk(D_INT, "Recv RD %d, status 0x%02x, len %d\n",
1824 rd, DBRI_RD_STATUS(status), DBRI_RD_CNT(status));
1827 spin_unlock(&dbri->lock);
1828 snd_pcm_period_elapsed(info->substream);
1829 spin_lock(&dbri->lock);
1832 static void dbri_process_one_interrupt(struct snd_dbri *dbri, int x)
1834 int val = D_INTR_GETVAL(x);
1835 int channel = D_INTR_GETCHAN(x);
1836 int command = D_INTR_GETCMD(x);
1837 int code = D_INTR_GETCODE(x);
1839 int rval = D_INTR_GETRVAL(x);
1842 if (channel == D_INTR_CMD) {
1843 dprintk(D_CMD, "INTR: Command: %-5s Value:%d\n",
1844 cmds[command], val);
1846 dprintk(D_INT, "INTR: Chan:%d Code:%d Val:%#x\n",
1847 channel, code, rval);
1852 if (command != D_WAIT)
1853 printk(KERN_ERR "DBRI: Command read interrupt\n");
1856 reception_complete_intr(dbri, channel);
1860 transmission_complete_intr(dbri, channel);
1863 /* UNDR - Transmission underrun
1864 * resend SDP command with clear pipe bit (C) set
1867 /* FIXME: do something useful in case of underrun */
1868 printk(KERN_ERR "DBRI: Underrun error\n");
1872 int td = dbri->pipes[pipe].desc;
1874 dbri->dma->desc[td].word4 = 0;
1875 cmd = dbri_cmdlock(dbri, NoGetLock);
1876 *(cmd++) = DBRI_CMD(D_SDP, 0,
1877 dbri->pipes[pipe].sdp
1878 | D_SDP_P | D_SDP_C | D_SDP_2SAME);
1879 *(cmd++) = dbri->dma_dvma + dbri_dma_off(desc, td);
1880 dbri_cmdsend(dbri, cmd);
1885 /* FXDT - Fixed data change */
1886 if (dbri->pipes[channel].sdp & D_SDP_MSB)
1887 val = reverse_bytes(val, dbri->pipes[channel].length);
1889 if (dbri->pipes[channel].recv_fixed_ptr)
1890 *(dbri->pipes[channel].recv_fixed_ptr) = val;
1893 if (channel != D_INTR_CMD)
1895 "DBRI: Ignored Interrupt: %d (0x%x)\n", code, x);
1899 /* dbri_process_interrupt_buffer advances through the DBRI's interrupt
1900 * buffer until it finds a zero word (indicating nothing more to do
1901 * right now). Non-zero words require processing and are handed off
1902 * to dbri_process_one_interrupt AFTER advancing the pointer.
1904 static void dbri_process_interrupt_buffer(struct snd_dbri *dbri)
1908 while ((x = dbri->dma->intr[dbri->dbri_irqp]) != 0) {
1909 dbri->dma->intr[dbri->dbri_irqp] = 0;
1911 if (dbri->dbri_irqp == DBRI_INT_BLK)
1912 dbri->dbri_irqp = 1;
1914 dbri_process_one_interrupt(dbri, x);
1918 static irqreturn_t snd_dbri_interrupt(int irq, void *dev_id)
1920 struct snd_dbri *dbri = dev_id;
1921 static int errcnt = 0;
1926 spin_lock(&dbri->lock);
1929 * Read it, so the interrupt goes away.
1931 x = sbus_readl(dbri->regs + REG1);
1933 if (x & (D_MRR | D_MLE | D_LBG | D_MBE)) {
1938 "DBRI: Multiple Error Ack on SBus reg1=0x%x\n",
1942 "DBRI: Multiple Late Error on SBus reg1=0x%x\n",
1946 "DBRI: Lost Bus Grant on SBus reg1=0x%x\n", x);
1949 "DBRI: Burst Error on SBus reg1=0x%x\n", x);
1951 /* Some of these SBus errors cause the chip's SBus circuitry
1952 * to be disabled, so just re-enable and try to keep going.
1954 * The only one I've seen is MRR, which will be triggered
1955 * if you let a transmit pipe underrun, then try to CDP it.
1957 * If these things persist, we reset the chip.
1959 if ((++errcnt) % 10 == 0) {
1960 dprintk(D_INT, "Interrupt errors exceeded.\n");
1963 tmp = sbus_readl(dbri->regs + REG0);
1965 sbus_writel(tmp, dbri->regs + REG0);
1969 dbri_process_interrupt_buffer(dbri);
1971 spin_unlock(&dbri->lock);
1976 /****************************************************************************
1978 ****************************************************************************/
1979 static struct snd_pcm_hardware snd_dbri_pcm_hw = {
1980 .info = SNDRV_PCM_INFO_MMAP |
1981 SNDRV_PCM_INFO_INTERLEAVED |
1982 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1983 SNDRV_PCM_INFO_MMAP_VALID,
1984 .formats = SNDRV_PCM_FMTBIT_MU_LAW |
1985 SNDRV_PCM_FMTBIT_A_LAW |
1986 SNDRV_PCM_FMTBIT_U8 |
1987 SNDRV_PCM_FMTBIT_S16_BE,
1988 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_5512,
1993 .buffer_bytes_max = 64 * 1024,
1994 .period_bytes_min = 1,
1995 .period_bytes_max = DBRI_TD_MAXCNT,
1997 .periods_max = 1024,
2000 static int snd_hw_rule_format(struct snd_pcm_hw_params *params,
2001 struct snd_pcm_hw_rule *rule)
2003 struct snd_interval *c = hw_param_interval(params,
2004 SNDRV_PCM_HW_PARAM_CHANNELS);
2005 struct snd_mask *f = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
2006 struct snd_mask fmt;
2010 fmt.bits[0] &= SNDRV_PCM_FMTBIT_S16_BE;
2011 return snd_mask_refine(f, &fmt);
2016 static int snd_hw_rule_channels(struct snd_pcm_hw_params *params,
2017 struct snd_pcm_hw_rule *rule)
2019 struct snd_interval *c = hw_param_interval(params,
2020 SNDRV_PCM_HW_PARAM_CHANNELS);
2021 struct snd_mask *f = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
2022 struct snd_interval ch;
2024 snd_interval_any(&ch);
2025 if (!(f->bits[0] & SNDRV_PCM_FMTBIT_S16_BE)) {
2029 return snd_interval_refine(c, &ch);
2034 static int snd_dbri_open(struct snd_pcm_substream *substream)
2036 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2037 struct snd_pcm_runtime *runtime = substream->runtime;
2038 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2039 unsigned long flags;
2041 dprintk(D_USR, "open audio output.\n");
2042 runtime->hw = snd_dbri_pcm_hw;
2044 spin_lock_irqsave(&dbri->lock, flags);
2045 info->substream = substream;
2047 info->dvma_buffer = 0;
2049 spin_unlock_irqrestore(&dbri->lock, flags);
2051 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
2052 snd_hw_rule_format, NULL, SNDRV_PCM_HW_PARAM_FORMAT,
2054 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_FORMAT,
2055 snd_hw_rule_channels, NULL,
2056 SNDRV_PCM_HW_PARAM_CHANNELS,
2064 static int snd_dbri_close(struct snd_pcm_substream *substream)
2066 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2067 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2069 dprintk(D_USR, "close audio output.\n");
2070 info->substream = NULL;
2076 static int snd_dbri_hw_params(struct snd_pcm_substream *substream,
2077 struct snd_pcm_hw_params *hw_params)
2079 struct snd_pcm_runtime *runtime = substream->runtime;
2080 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2081 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2085 /* set sampling rate, audio format and number of channels */
2086 ret = cs4215_prepare(dbri, params_rate(hw_params),
2087 params_format(hw_params),
2088 params_channels(hw_params));
2092 if ((ret = snd_pcm_lib_malloc_pages(substream,
2093 params_buffer_bytes(hw_params))) < 0) {
2094 printk(KERN_ERR "malloc_pages failed with %d\n", ret);
2098 /* hw_params can get called multiple times. Only map the DMA once.
2100 if (info->dvma_buffer == 0) {
2101 if (DBRI_STREAMNO(substream) == DBRI_PLAY)
2102 direction = SBUS_DMA_TODEVICE;
2104 direction = SBUS_DMA_FROMDEVICE;
2106 info->dvma_buffer = sbus_map_single(dbri->sdev,
2108 params_buffer_bytes(hw_params),
2112 direction = params_buffer_bytes(hw_params);
2113 dprintk(D_USR, "hw_params: %d bytes, dvma=%x\n",
2114 direction, info->dvma_buffer);
2118 static int snd_dbri_hw_free(struct snd_pcm_substream *substream)
2120 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2121 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2124 dprintk(D_USR, "hw_free.\n");
2126 /* hw_free can get called multiple times. Only unmap the DMA once.
2128 if (info->dvma_buffer) {
2129 if (DBRI_STREAMNO(substream) == DBRI_PLAY)
2130 direction = SBUS_DMA_TODEVICE;
2132 direction = SBUS_DMA_FROMDEVICE;
2134 sbus_unmap_single(dbri->sdev, info->dvma_buffer,
2135 substream->runtime->buffer_size, direction);
2136 info->dvma_buffer = 0;
2138 if (info->pipe != -1) {
2139 reset_pipe(dbri, info->pipe);
2143 return snd_pcm_lib_free_pages(substream);
2146 static int snd_dbri_prepare(struct snd_pcm_substream *substream)
2148 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2149 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2152 info->size = snd_pcm_lib_buffer_bytes(substream);
2153 if (DBRI_STREAMNO(substream) == DBRI_PLAY)
2154 info->pipe = 4; /* Send pipe */
2156 info->pipe = 6; /* Receive pipe */
2158 spin_lock_irq(&dbri->lock);
2161 /* Setup the all the transmit/receive descriptors to cover the
2164 ret = setup_descs(dbri, DBRI_STREAMNO(substream),
2165 snd_pcm_lib_period_bytes(substream));
2167 spin_unlock_irq(&dbri->lock);
2169 dprintk(D_USR, "prepare audio output. %d bytes\n", info->size);
2173 static int snd_dbri_trigger(struct snd_pcm_substream *substream, int cmd)
2175 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2176 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2180 case SNDRV_PCM_TRIGGER_START:
2181 dprintk(D_USR, "start audio, period is %d bytes\n",
2182 (int)snd_pcm_lib_period_bytes(substream));
2183 /* Re-submit the TDs. */
2186 case SNDRV_PCM_TRIGGER_STOP:
2187 dprintk(D_USR, "stop audio.\n");
2188 reset_pipe(dbri, info->pipe);
2197 static snd_pcm_uframes_t snd_dbri_pointer(struct snd_pcm_substream *substream)
2199 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2200 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2201 snd_pcm_uframes_t ret;
2203 ret = bytes_to_frames(substream->runtime, info->offset)
2204 % substream->runtime->buffer_size;
2205 dprintk(D_USR, "I/O pointer: %ld frames of %ld.\n",
2206 ret, substream->runtime->buffer_size);
2210 static struct snd_pcm_ops snd_dbri_ops = {
2211 .open = snd_dbri_open,
2212 .close = snd_dbri_close,
2213 .ioctl = snd_pcm_lib_ioctl,
2214 .hw_params = snd_dbri_hw_params,
2215 .hw_free = snd_dbri_hw_free,
2216 .prepare = snd_dbri_prepare,
2217 .trigger = snd_dbri_trigger,
2218 .pointer = snd_dbri_pointer,
2221 static int __devinit snd_dbri_pcm(struct snd_dbri *dbri)
2223 struct snd_pcm *pcm;
2226 if ((err = snd_pcm_new(dbri->card,
2227 /* ID */ "sun_dbri",
2229 /* playback count */ 1,
2230 /* capture count */ 1, &pcm)) < 0)
2232 snd_assert(pcm != NULL, return -EINVAL);
2234 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_dbri_ops);
2235 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_dbri_ops);
2237 pcm->private_data = dbri;
2238 pcm->info_flags = 0;
2239 strcpy(pcm->name, dbri->card->shortname);
2241 if ((err = snd_pcm_lib_preallocate_pages_for_all(pcm,
2242 SNDRV_DMA_TYPE_CONTINUOUS,
2243 snd_dma_continuous_data(GFP_KERNEL),
2244 64 * 1024, 64 * 1024)) < 0)
2250 /*****************************************************************************
2252 *****************************************************************************/
2254 static int snd_cs4215_info_volume(struct snd_kcontrol *kcontrol,
2255 struct snd_ctl_elem_info *uinfo)
2257 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2259 uinfo->value.integer.min = 0;
2260 if (kcontrol->private_value == DBRI_PLAY)
2261 uinfo->value.integer.max = DBRI_MAX_VOLUME;
2263 uinfo->value.integer.max = DBRI_MAX_GAIN;
2267 static int snd_cs4215_get_volume(struct snd_kcontrol *kcontrol,
2268 struct snd_ctl_elem_value *ucontrol)
2270 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2271 struct dbri_streaminfo *info;
2272 snd_assert(dbri != NULL, return -EINVAL);
2273 info = &dbri->stream_info[kcontrol->private_value];
2274 snd_assert(info != NULL, return -EINVAL);
2276 ucontrol->value.integer.value[0] = info->left_gain;
2277 ucontrol->value.integer.value[1] = info->right_gain;
2281 static int snd_cs4215_put_volume(struct snd_kcontrol *kcontrol,
2282 struct snd_ctl_elem_value *ucontrol)
2284 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2285 struct dbri_streaminfo *info =
2286 &dbri->stream_info[kcontrol->private_value];
2289 if (info->left_gain != ucontrol->value.integer.value[0]) {
2290 info->left_gain = ucontrol->value.integer.value[0];
2293 if (info->right_gain != ucontrol->value.integer.value[1]) {
2294 info->right_gain = ucontrol->value.integer.value[1];
2298 /* First mute outputs, and wait 1/8000 sec (125 us)
2299 * to make sure this takes. This avoids clicking noises.
2301 cs4215_setdata(dbri, 1);
2303 cs4215_setdata(dbri, 0);
2308 static int snd_cs4215_info_single(struct snd_kcontrol *kcontrol,
2309 struct snd_ctl_elem_info *uinfo)
2311 int mask = (kcontrol->private_value >> 16) & 0xff;
2313 uinfo->type = (mask == 1) ?
2314 SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2316 uinfo->value.integer.min = 0;
2317 uinfo->value.integer.max = mask;
2321 static int snd_cs4215_get_single(struct snd_kcontrol *kcontrol,
2322 struct snd_ctl_elem_value *ucontrol)
2324 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2325 int elem = kcontrol->private_value & 0xff;
2326 int shift = (kcontrol->private_value >> 8) & 0xff;
2327 int mask = (kcontrol->private_value >> 16) & 0xff;
2328 int invert = (kcontrol->private_value >> 24) & 1;
2329 snd_assert(dbri != NULL, return -EINVAL);
2332 ucontrol->value.integer.value[0] =
2333 (dbri->mm.data[elem] >> shift) & mask;
2335 ucontrol->value.integer.value[0] =
2336 (dbri->mm.ctrl[elem - 4] >> shift) & mask;
2339 ucontrol->value.integer.value[0] =
2340 mask - ucontrol->value.integer.value[0];
2344 static int snd_cs4215_put_single(struct snd_kcontrol *kcontrol,
2345 struct snd_ctl_elem_value *ucontrol)
2347 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2348 int elem = kcontrol->private_value & 0xff;
2349 int shift = (kcontrol->private_value >> 8) & 0xff;
2350 int mask = (kcontrol->private_value >> 16) & 0xff;
2351 int invert = (kcontrol->private_value >> 24) & 1;
2354 snd_assert(dbri != NULL, return -EINVAL);
2356 val = (ucontrol->value.integer.value[0] & mask);
2362 dbri->mm.data[elem] = (dbri->mm.data[elem] &
2363 ~(mask << shift)) | val;
2364 changed = (val != dbri->mm.data[elem]);
2366 dbri->mm.ctrl[elem - 4] = (dbri->mm.ctrl[elem - 4] &
2367 ~(mask << shift)) | val;
2368 changed = (val != dbri->mm.ctrl[elem - 4]);
2371 dprintk(D_GEN, "put_single: mask=0x%x, changed=%d, "
2372 "mixer-value=%ld, mm-value=0x%x\n",
2373 mask, changed, ucontrol->value.integer.value[0],
2374 dbri->mm.data[elem & 3]);
2377 /* First mute outputs, and wait 1/8000 sec (125 us)
2378 * to make sure this takes. This avoids clicking noises.
2380 cs4215_setdata(dbri, 1);
2382 cs4215_setdata(dbri, 0);
2387 /* Entries 0-3 map to the 4 data timeslots, entries 4-7 map to the 4 control
2388 timeslots. Shift is the bit offset in the timeslot, mask defines the
2389 number of bits. invert is a boolean for use with attenuation.
2391 #define CS4215_SINGLE(xname, entry, shift, mask, invert) \
2392 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
2393 .info = snd_cs4215_info_single, \
2394 .get = snd_cs4215_get_single, .put = snd_cs4215_put_single, \
2395 .private_value = (entry) | ((shift) << 8) | ((mask) << 16) | \
2398 static struct snd_kcontrol_new dbri_controls[] __devinitdata = {
2400 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2401 .name = "Playback Volume",
2402 .info = snd_cs4215_info_volume,
2403 .get = snd_cs4215_get_volume,
2404 .put = snd_cs4215_put_volume,
2405 .private_value = DBRI_PLAY,
2407 CS4215_SINGLE("Headphone switch", 0, 7, 1, 0)
2408 CS4215_SINGLE("Line out switch", 0, 6, 1, 0)
2409 CS4215_SINGLE("Speaker switch", 1, 6, 1, 0)
2411 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2412 .name = "Capture Volume",
2413 .info = snd_cs4215_info_volume,
2414 .get = snd_cs4215_get_volume,
2415 .put = snd_cs4215_put_volume,
2416 .private_value = DBRI_REC,
2418 /* FIXME: mic/line switch */
2419 CS4215_SINGLE("Line in switch", 2, 4, 1, 0)
2420 CS4215_SINGLE("High Pass Filter switch", 5, 7, 1, 0)
2421 CS4215_SINGLE("Monitor Volume", 3, 4, 0xf, 1)
2422 CS4215_SINGLE("Mic boost", 4, 4, 1, 1)
2425 static int __init snd_dbri_mixer(struct snd_dbri *dbri)
2427 struct snd_card *card;
2430 snd_assert(dbri != NULL && dbri->card != NULL, return -EINVAL);
2433 strcpy(card->mixername, card->shortname);
2435 for (idx = 0; idx < ARRAY_SIZE(dbri_controls); idx++) {
2436 err = snd_ctl_add(card,
2437 snd_ctl_new1(&dbri_controls[idx], dbri));
2442 for (idx = DBRI_REC; idx < DBRI_NO_STREAMS; idx++) {
2443 dbri->stream_info[idx].left_gain = 0;
2444 dbri->stream_info[idx].right_gain = 0;
2450 /****************************************************************************
2452 ****************************************************************************/
2453 static void dbri_regs_read(struct snd_info_entry *entry,
2454 struct snd_info_buffer *buffer)
2456 struct snd_dbri *dbri = entry->private_data;
2458 snd_iprintf(buffer, "REG0: 0x%x\n", sbus_readl(dbri->regs + REG0));
2459 snd_iprintf(buffer, "REG2: 0x%x\n", sbus_readl(dbri->regs + REG2));
2460 snd_iprintf(buffer, "REG8: 0x%x\n", sbus_readl(dbri->regs + REG8));
2461 snd_iprintf(buffer, "REG9: 0x%x\n", sbus_readl(dbri->regs + REG9));
2465 static void dbri_debug_read(struct snd_info_entry *entry,
2466 struct snd_info_buffer *buffer)
2468 struct snd_dbri *dbri = entry->private_data;
2470 snd_iprintf(buffer, "debug=%d\n", dbri_debug);
2472 for (pipe = 0; pipe < 32; pipe++) {
2473 if (pipe_active(dbri, pipe)) {
2474 struct dbri_pipe *pptr = &dbri->pipes[pipe];
2476 "Pipe %d: %s SDP=0x%x desc=%d, "
2479 (pptr->sdp & D_SDP_TO_SER) ? "output" :
2481 pptr->sdp, pptr->desc,
2482 pptr->length, pptr->nextpipe);
2488 void snd_dbri_proc(struct snd_dbri *dbri)
2490 struct snd_info_entry *entry;
2492 if (!snd_card_proc_new(dbri->card, "regs", &entry))
2493 snd_info_set_text_ops(entry, dbri, dbri_regs_read);
2496 if (!snd_card_proc_new(dbri->card, "debug", &entry)) {
2497 snd_info_set_text_ops(entry, dbri, dbri_debug_read);
2498 entry->mode = S_IFREG | S_IRUGO; /* Readable only. */
2504 ****************************************************************************
2505 **************************** Initialization ********************************
2506 ****************************************************************************
2508 static void snd_dbri_free(struct snd_dbri *dbri);
2510 static int __init snd_dbri_create(struct snd_card *card,
2511 struct sbus_dev *sdev,
2512 struct linux_prom_irqs *irq, int dev)
2514 struct snd_dbri *dbri = card->private_data;
2517 spin_lock_init(&dbri->lock);
2520 dbri->irq = irq->pri;
2522 dbri->dma = sbus_alloc_consistent(sdev, sizeof(struct dbri_dma),
2524 memset((void *)dbri->dma, 0, sizeof(struct dbri_dma));
2526 dprintk(D_GEN, "DMA Cmd Block 0x%p (0x%08x)\n",
2527 dbri->dma, dbri->dma_dvma);
2529 /* Map the registers into memory. */
2530 dbri->regs_size = sdev->reg_addrs[0].reg_size;
2531 dbri->regs = sbus_ioremap(&sdev->resource[0], 0,
2532 dbri->regs_size, "DBRI Registers");
2534 printk(KERN_ERR "DBRI: could not allocate registers\n");
2535 sbus_free_consistent(sdev, sizeof(struct dbri_dma),
2536 (void *)dbri->dma, dbri->dma_dvma);
2540 err = request_irq(dbri->irq, snd_dbri_interrupt, IRQF_SHARED,
2541 "DBRI audio", dbri);
2543 printk(KERN_ERR "DBRI: Can't get irq %d\n", dbri->irq);
2544 sbus_iounmap(dbri->regs, dbri->regs_size);
2545 sbus_free_consistent(sdev, sizeof(struct dbri_dma),
2546 (void *)dbri->dma, dbri->dma_dvma);
2550 /* Do low level initialization of the DBRI and CS4215 chips */
2551 dbri_initialize(dbri);
2552 err = cs4215_init(dbri);
2554 snd_dbri_free(dbri);
2558 dbri->next = dbri_list;
2564 static void snd_dbri_free(struct snd_dbri *dbri)
2566 dprintk(D_GEN, "snd_dbri_free\n");
2570 free_irq(dbri->irq, dbri);
2573 sbus_iounmap(dbri->regs, dbri->regs_size);
2576 sbus_free_consistent(dbri->sdev, sizeof(struct dbri_dma),
2577 (void *)dbri->dma, dbri->dma_dvma);
2580 static int __init dbri_attach(int prom_node, struct sbus_dev *sdev)
2582 struct snd_dbri *dbri;
2583 struct linux_prom_irqs irq;
2584 struct resource *rp;
2585 struct snd_card *card;
2589 if (sdev->prom_name[9] < 'e') {
2590 printk(KERN_ERR "DBRI: unsupported chip version %c found.\n",
2591 sdev->prom_name[9]);
2595 if (dev >= SNDRV_CARDS)
2602 err = prom_getproperty(prom_node, "intr", (char *)&irq, sizeof(irq));
2604 printk(KERN_ERR "DBRI-%d: Firmware node lacks IRQ property.\n",
2609 card = snd_card_new(index[dev], id[dev], THIS_MODULE,
2610 sizeof(struct snd_dbri));
2614 strcpy(card->driver, "DBRI");
2615 strcpy(card->shortname, "Sun DBRI");
2616 rp = &sdev->resource[0];
2617 sprintf(card->longname, "%s at 0x%02lx:0x%016Lx, irq %d",
2619 rp->flags & 0xffL, (unsigned long long)rp->start, irq.pri);
2621 if ((err = snd_dbri_create(card, sdev, &irq, dev)) < 0) {
2622 snd_card_free(card);
2626 dbri = card->private_data;
2627 err = snd_dbri_pcm(dbri);
2631 err = snd_dbri_mixer(dbri);
2635 /* /proc file handling */
2636 snd_dbri_proc(dbri);
2638 err = snd_card_register(card);
2642 printk(KERN_INFO "audio%d at %p (irq %d) is DBRI(%c)+CS4215(%d)\n",
2644 dbri->irq, sdev->prom_name[9], dbri->mm.version);
2650 snd_dbri_free(dbri);
2651 snd_card_free(card);
2655 /* Probe for the dbri chip and then attach the driver. */
2656 static int __init dbri_init(void)
2658 struct sbus_bus *sbus;
2659 struct sbus_dev *sdev;
2662 /* Probe each SBUS for the DBRI chip(s). */
2663 for_all_sbusdev(sdev, sbus) {
2665 * The version is coded in the last character
2667 if (!strncmp(sdev->prom_name, "SUNW,DBRI", 9)) {
2668 dprintk(D_GEN, "DBRI: Found %s in SBUS slot %d\n",
2669 sdev->prom_name, sdev->slot);
2671 if (dbri_attach(sdev->prom_node, sdev) == 0)
2676 return (found > 0) ? 0 : -EIO;
2679 static void __exit dbri_exit(void)
2681 struct snd_dbri *this = dbri_list;
2683 while (this != NULL) {
2684 struct snd_dbri *next = this->next;
2685 struct snd_card *card = this->card;
2687 snd_dbri_free(this);
2688 snd_card_free(card);
2694 module_init(dbri_init);
2695 module_exit(dbri_exit);