Merge git://git.kernel.org/pub/scm/linux/kernel/git/wim/linux-2.6-watchdog
[linux-2.6] / drivers / pci / intr_remapping.c
1 #include <linux/interrupt.h>
2 #include <linux/dmar.h>
3 #include <linux/spinlock.h>
4 #include <linux/jiffies.h>
5 #include <linux/pci.h>
6 #include <linux/irq.h>
7 #include <asm/io_apic.h>
8 #include <asm/smp.h>
9 #include <asm/cpu.h>
10 #include <linux/intel-iommu.h>
11 #include "intr_remapping.h"
12 #include <acpi/acpi.h>
13
14 static struct ioapic_scope ir_ioapic[MAX_IO_APICS];
15 static int ir_ioapic_num;
16 int intr_remapping_enabled;
17
18 static int disable_intremap;
19 static __init int setup_nointremap(char *str)
20 {
21         disable_intremap = 1;
22         return 0;
23 }
24 early_param("nointremap", setup_nointremap);
25
26 struct irq_2_iommu {
27         struct intel_iommu *iommu;
28         u16 irte_index;
29         u16 sub_handle;
30         u8  irte_mask;
31 };
32
33 #ifdef CONFIG_GENERIC_HARDIRQS
34 static struct irq_2_iommu *get_one_free_irq_2_iommu(int node)
35 {
36         struct irq_2_iommu *iommu;
37
38         iommu = kzalloc_node(sizeof(*iommu), GFP_ATOMIC, node);
39         printk(KERN_DEBUG "alloc irq_2_iommu on node %d\n", node);
40
41         return iommu;
42 }
43
44 static struct irq_2_iommu *irq_2_iommu(unsigned int irq)
45 {
46         struct irq_desc *desc;
47
48         desc = irq_to_desc(irq);
49
50         if (WARN_ON_ONCE(!desc))
51                 return NULL;
52
53         return desc->irq_2_iommu;
54 }
55
56 static struct irq_2_iommu *irq_2_iommu_alloc_node(unsigned int irq, int node)
57 {
58         struct irq_desc *desc;
59         struct irq_2_iommu *irq_iommu;
60
61         /*
62          * alloc irq desc if not allocated already.
63          */
64         desc = irq_to_desc_alloc_node(irq, node);
65         if (!desc) {
66                 printk(KERN_INFO "can not get irq_desc for %d\n", irq);
67                 return NULL;
68         }
69
70         irq_iommu = desc->irq_2_iommu;
71
72         if (!irq_iommu)
73                 desc->irq_2_iommu = get_one_free_irq_2_iommu(node);
74
75         return desc->irq_2_iommu;
76 }
77
78 static struct irq_2_iommu *irq_2_iommu_alloc(unsigned int irq)
79 {
80         return irq_2_iommu_alloc_node(irq, cpu_to_node(boot_cpu_id));
81 }
82
83 #else /* !CONFIG_SPARSE_IRQ */
84
85 static struct irq_2_iommu irq_2_iommuX[NR_IRQS];
86
87 static struct irq_2_iommu *irq_2_iommu(unsigned int irq)
88 {
89         if (irq < nr_irqs)
90                 return &irq_2_iommuX[irq];
91
92         return NULL;
93 }
94 static struct irq_2_iommu *irq_2_iommu_alloc(unsigned int irq)
95 {
96         return irq_2_iommu(irq);
97 }
98 #endif
99
100 static DEFINE_SPINLOCK(irq_2_ir_lock);
101
102 static struct irq_2_iommu *valid_irq_2_iommu(unsigned int irq)
103 {
104         struct irq_2_iommu *irq_iommu;
105
106         irq_iommu = irq_2_iommu(irq);
107
108         if (!irq_iommu)
109                 return NULL;
110
111         if (!irq_iommu->iommu)
112                 return NULL;
113
114         return irq_iommu;
115 }
116
117 int irq_remapped(int irq)
118 {
119         return valid_irq_2_iommu(irq) != NULL;
120 }
121
122 int get_irte(int irq, struct irte *entry)
123 {
124         int index;
125         struct irq_2_iommu *irq_iommu;
126         unsigned long flags;
127
128         if (!entry)
129                 return -1;
130
131         spin_lock_irqsave(&irq_2_ir_lock, flags);
132         irq_iommu = valid_irq_2_iommu(irq);
133         if (!irq_iommu) {
134                 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
135                 return -1;
136         }
137
138         index = irq_iommu->irte_index + irq_iommu->sub_handle;
139         *entry = *(irq_iommu->iommu->ir_table->base + index);
140
141         spin_unlock_irqrestore(&irq_2_ir_lock, flags);
142         return 0;
143 }
144
145 int alloc_irte(struct intel_iommu *iommu, int irq, u16 count)
146 {
147         struct ir_table *table = iommu->ir_table;
148         struct irq_2_iommu *irq_iommu;
149         u16 index, start_index;
150         unsigned int mask = 0;
151         unsigned long flags;
152         int i;
153
154         if (!count)
155                 return -1;
156
157 #ifndef CONFIG_SPARSE_IRQ
158         /* protect irq_2_iommu_alloc later */
159         if (irq >= nr_irqs)
160                 return -1;
161 #endif
162
163         /*
164          * start the IRTE search from index 0.
165          */
166         index = start_index = 0;
167
168         if (count > 1) {
169                 count = __roundup_pow_of_two(count);
170                 mask = ilog2(count);
171         }
172
173         if (mask > ecap_max_handle_mask(iommu->ecap)) {
174                 printk(KERN_ERR
175                        "Requested mask %x exceeds the max invalidation handle"
176                        " mask value %Lx\n", mask,
177                        ecap_max_handle_mask(iommu->ecap));
178                 return -1;
179         }
180
181         spin_lock_irqsave(&irq_2_ir_lock, flags);
182         do {
183                 for (i = index; i < index + count; i++)
184                         if  (table->base[i].present)
185                                 break;
186                 /* empty index found */
187                 if (i == index + count)
188                         break;
189
190                 index = (index + count) % INTR_REMAP_TABLE_ENTRIES;
191
192                 if (index == start_index) {
193                         spin_unlock_irqrestore(&irq_2_ir_lock, flags);
194                         printk(KERN_ERR "can't allocate an IRTE\n");
195                         return -1;
196                 }
197         } while (1);
198
199         for (i = index; i < index + count; i++)
200                 table->base[i].present = 1;
201
202         irq_iommu = irq_2_iommu_alloc(irq);
203         if (!irq_iommu) {
204                 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
205                 printk(KERN_ERR "can't allocate irq_2_iommu\n");
206                 return -1;
207         }
208
209         irq_iommu->iommu = iommu;
210         irq_iommu->irte_index =  index;
211         irq_iommu->sub_handle = 0;
212         irq_iommu->irte_mask = mask;
213
214         spin_unlock_irqrestore(&irq_2_ir_lock, flags);
215
216         return index;
217 }
218
219 static int qi_flush_iec(struct intel_iommu *iommu, int index, int mask)
220 {
221         struct qi_desc desc;
222
223         desc.low = QI_IEC_IIDEX(index) | QI_IEC_TYPE | QI_IEC_IM(mask)
224                    | QI_IEC_SELECTIVE;
225         desc.high = 0;
226
227         return qi_submit_sync(&desc, iommu);
228 }
229
230 int map_irq_to_irte_handle(int irq, u16 *sub_handle)
231 {
232         int index;
233         struct irq_2_iommu *irq_iommu;
234         unsigned long flags;
235
236         spin_lock_irqsave(&irq_2_ir_lock, flags);
237         irq_iommu = valid_irq_2_iommu(irq);
238         if (!irq_iommu) {
239                 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
240                 return -1;
241         }
242
243         *sub_handle = irq_iommu->sub_handle;
244         index = irq_iommu->irte_index;
245         spin_unlock_irqrestore(&irq_2_ir_lock, flags);
246         return index;
247 }
248
249 int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index, u16 subhandle)
250 {
251         struct irq_2_iommu *irq_iommu;
252         unsigned long flags;
253
254         spin_lock_irqsave(&irq_2_ir_lock, flags);
255
256         irq_iommu = irq_2_iommu_alloc(irq);
257
258         if (!irq_iommu) {
259                 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
260                 printk(KERN_ERR "can't allocate irq_2_iommu\n");
261                 return -1;
262         }
263
264         irq_iommu->iommu = iommu;
265         irq_iommu->irte_index = index;
266         irq_iommu->sub_handle = subhandle;
267         irq_iommu->irte_mask = 0;
268
269         spin_unlock_irqrestore(&irq_2_ir_lock, flags);
270
271         return 0;
272 }
273
274 int clear_irte_irq(int irq, struct intel_iommu *iommu, u16 index)
275 {
276         struct irq_2_iommu *irq_iommu;
277         unsigned long flags;
278
279         spin_lock_irqsave(&irq_2_ir_lock, flags);
280         irq_iommu = valid_irq_2_iommu(irq);
281         if (!irq_iommu) {
282                 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
283                 return -1;
284         }
285
286         irq_iommu->iommu = NULL;
287         irq_iommu->irte_index = 0;
288         irq_iommu->sub_handle = 0;
289         irq_2_iommu(irq)->irte_mask = 0;
290
291         spin_unlock_irqrestore(&irq_2_ir_lock, flags);
292
293         return 0;
294 }
295
296 int modify_irte(int irq, struct irte *irte_modified)
297 {
298         int rc;
299         int index;
300         struct irte *irte;
301         struct intel_iommu *iommu;
302         struct irq_2_iommu *irq_iommu;
303         unsigned long flags;
304
305         spin_lock_irqsave(&irq_2_ir_lock, flags);
306         irq_iommu = valid_irq_2_iommu(irq);
307         if (!irq_iommu) {
308                 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
309                 return -1;
310         }
311
312         iommu = irq_iommu->iommu;
313
314         index = irq_iommu->irte_index + irq_iommu->sub_handle;
315         irte = &iommu->ir_table->base[index];
316
317         set_64bit((unsigned long *)irte, irte_modified->low);
318         __iommu_flush_cache(iommu, irte, sizeof(*irte));
319
320         rc = qi_flush_iec(iommu, index, 0);
321         spin_unlock_irqrestore(&irq_2_ir_lock, flags);
322
323         return rc;
324 }
325
326 int flush_irte(int irq)
327 {
328         int rc;
329         int index;
330         struct intel_iommu *iommu;
331         struct irq_2_iommu *irq_iommu;
332         unsigned long flags;
333
334         spin_lock_irqsave(&irq_2_ir_lock, flags);
335         irq_iommu = valid_irq_2_iommu(irq);
336         if (!irq_iommu) {
337                 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
338                 return -1;
339         }
340
341         iommu = irq_iommu->iommu;
342
343         index = irq_iommu->irte_index + irq_iommu->sub_handle;
344
345         rc = qi_flush_iec(iommu, index, irq_iommu->irte_mask);
346         spin_unlock_irqrestore(&irq_2_ir_lock, flags);
347
348         return rc;
349 }
350
351 struct intel_iommu *map_ioapic_to_ir(int apic)
352 {
353         int i;
354
355         for (i = 0; i < MAX_IO_APICS; i++)
356                 if (ir_ioapic[i].id == apic)
357                         return ir_ioapic[i].iommu;
358         return NULL;
359 }
360
361 struct intel_iommu *map_dev_to_ir(struct pci_dev *dev)
362 {
363         struct dmar_drhd_unit *drhd;
364
365         drhd = dmar_find_matched_drhd_unit(dev);
366         if (!drhd)
367                 return NULL;
368
369         return drhd->iommu;
370 }
371
372 int free_irte(int irq)
373 {
374         int rc = 0;
375         int index, i;
376         struct irte *irte;
377         struct intel_iommu *iommu;
378         struct irq_2_iommu *irq_iommu;
379         unsigned long flags;
380
381         spin_lock_irqsave(&irq_2_ir_lock, flags);
382         irq_iommu = valid_irq_2_iommu(irq);
383         if (!irq_iommu) {
384                 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
385                 return -1;
386         }
387
388         iommu = irq_iommu->iommu;
389
390         index = irq_iommu->irte_index + irq_iommu->sub_handle;
391         irte = &iommu->ir_table->base[index];
392
393         if (!irq_iommu->sub_handle) {
394                 for (i = 0; i < (1 << irq_iommu->irte_mask); i++)
395                         set_64bit((unsigned long *)(irte + i), 0);
396                 rc = qi_flush_iec(iommu, index, irq_iommu->irte_mask);
397         }
398
399         irq_iommu->iommu = NULL;
400         irq_iommu->irte_index = 0;
401         irq_iommu->sub_handle = 0;
402         irq_iommu->irte_mask = 0;
403
404         spin_unlock_irqrestore(&irq_2_ir_lock, flags);
405
406         return rc;
407 }
408
409 static void iommu_set_intr_remapping(struct intel_iommu *iommu, int mode)
410 {
411         u64 addr;
412         u32 sts;
413         unsigned long flags;
414
415         addr = virt_to_phys((void *)iommu->ir_table->base);
416
417         spin_lock_irqsave(&iommu->register_lock, flags);
418
419         dmar_writeq(iommu->reg + DMAR_IRTA_REG,
420                     (addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE);
421
422         /* Set interrupt-remapping table pointer */
423         iommu->gcmd |= DMA_GCMD_SIRTP;
424         writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
425
426         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
427                       readl, (sts & DMA_GSTS_IRTPS), sts);
428         spin_unlock_irqrestore(&iommu->register_lock, flags);
429
430         /*
431          * global invalidation of interrupt entry cache before enabling
432          * interrupt-remapping.
433          */
434         qi_global_iec(iommu);
435
436         spin_lock_irqsave(&iommu->register_lock, flags);
437
438         /* Enable interrupt-remapping */
439         iommu->gcmd |= DMA_GCMD_IRE;
440         writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
441
442         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
443                       readl, (sts & DMA_GSTS_IRES), sts);
444
445         spin_unlock_irqrestore(&iommu->register_lock, flags);
446 }
447
448
449 static int setup_intr_remapping(struct intel_iommu *iommu, int mode)
450 {
451         struct ir_table *ir_table;
452         struct page *pages;
453
454         ir_table = iommu->ir_table = kzalloc(sizeof(struct ir_table),
455                                              GFP_ATOMIC);
456
457         if (!iommu->ir_table)
458                 return -ENOMEM;
459
460         pages = alloc_pages(GFP_ATOMIC | __GFP_ZERO, INTR_REMAP_PAGE_ORDER);
461
462         if (!pages) {
463                 printk(KERN_ERR "failed to allocate pages of order %d\n",
464                        INTR_REMAP_PAGE_ORDER);
465                 kfree(iommu->ir_table);
466                 return -ENOMEM;
467         }
468
469         ir_table->base = page_address(pages);
470
471         iommu_set_intr_remapping(iommu, mode);
472         return 0;
473 }
474
475 /*
476  * Disable Interrupt Remapping.
477  */
478 static void iommu_disable_intr_remapping(struct intel_iommu *iommu)
479 {
480         unsigned long flags;
481         u32 sts;
482
483         if (!ecap_ir_support(iommu->ecap))
484                 return;
485
486         /*
487          * global invalidation of interrupt entry cache before disabling
488          * interrupt-remapping.
489          */
490         qi_global_iec(iommu);
491
492         spin_lock_irqsave(&iommu->register_lock, flags);
493
494         sts = dmar_readq(iommu->reg + DMAR_GSTS_REG);
495         if (!(sts & DMA_GSTS_IRES))
496                 goto end;
497
498         iommu->gcmd &= ~DMA_GCMD_IRE;
499         writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
500
501         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
502                       readl, !(sts & DMA_GSTS_IRES), sts);
503
504 end:
505         spin_unlock_irqrestore(&iommu->register_lock, flags);
506 }
507
508 int __init intr_remapping_supported(void)
509 {
510         struct dmar_drhd_unit *drhd;
511
512         if (disable_intremap)
513                 return 0;
514
515         for_each_drhd_unit(drhd) {
516                 struct intel_iommu *iommu = drhd->iommu;
517
518                 if (!ecap_ir_support(iommu->ecap))
519                         return 0;
520         }
521
522         return 1;
523 }
524
525 int __init enable_intr_remapping(int eim)
526 {
527         struct dmar_drhd_unit *drhd;
528         int setup = 0;
529
530         for_each_drhd_unit(drhd) {
531                 struct intel_iommu *iommu = drhd->iommu;
532
533                 /*
534                  * If the queued invalidation is already initialized,
535                  * shouldn't disable it.
536                  */
537                 if (iommu->qi)
538                         continue;
539
540                 /*
541                  * Clear previous faults.
542                  */
543                 dmar_fault(-1, iommu);
544
545                 /*
546                  * Disable intr remapping and queued invalidation, if already
547                  * enabled prior to OS handover.
548                  */
549                 iommu_disable_intr_remapping(iommu);
550
551                 dmar_disable_qi(iommu);
552         }
553
554         /*
555          * check for the Interrupt-remapping support
556          */
557         for_each_drhd_unit(drhd) {
558                 struct intel_iommu *iommu = drhd->iommu;
559
560                 if (!ecap_ir_support(iommu->ecap))
561                         continue;
562
563                 if (eim && !ecap_eim_support(iommu->ecap)) {
564                         printk(KERN_INFO "DRHD %Lx: EIM not supported by DRHD, "
565                                " ecap %Lx\n", drhd->reg_base_addr, iommu->ecap);
566                         return -1;
567                 }
568         }
569
570         /*
571          * Enable queued invalidation for all the DRHD's.
572          */
573         for_each_drhd_unit(drhd) {
574                 int ret;
575                 struct intel_iommu *iommu = drhd->iommu;
576                 ret = dmar_enable_qi(iommu);
577
578                 if (ret) {
579                         printk(KERN_ERR "DRHD %Lx: failed to enable queued, "
580                                " invalidation, ecap %Lx, ret %d\n",
581                                drhd->reg_base_addr, iommu->ecap, ret);
582                         return -1;
583                 }
584         }
585
586         /*
587          * Setup Interrupt-remapping for all the DRHD's now.
588          */
589         for_each_drhd_unit(drhd) {
590                 struct intel_iommu *iommu = drhd->iommu;
591
592                 if (!ecap_ir_support(iommu->ecap))
593                         continue;
594
595                 if (setup_intr_remapping(iommu, eim))
596                         goto error;
597
598                 setup = 1;
599         }
600
601         if (!setup)
602                 goto error;
603
604         intr_remapping_enabled = 1;
605
606         return 0;
607
608 error:
609         /*
610          * handle error condition gracefully here!
611          */
612         return -1;
613 }
614
615 static int ir_parse_ioapic_scope(struct acpi_dmar_header *header,
616                                  struct intel_iommu *iommu)
617 {
618         struct acpi_dmar_hardware_unit *drhd;
619         struct acpi_dmar_device_scope *scope;
620         void *start, *end;
621
622         drhd = (struct acpi_dmar_hardware_unit *)header;
623
624         start = (void *)(drhd + 1);
625         end = ((void *)drhd) + header->length;
626
627         while (start < end) {
628                 scope = start;
629                 if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC) {
630                         if (ir_ioapic_num == MAX_IO_APICS) {
631                                 printk(KERN_WARNING "Exceeded Max IO APICS\n");
632                                 return -1;
633                         }
634
635                         printk(KERN_INFO "IOAPIC id %d under DRHD base"
636                                " 0x%Lx\n", scope->enumeration_id,
637                                drhd->address);
638
639                         ir_ioapic[ir_ioapic_num].iommu = iommu;
640                         ir_ioapic[ir_ioapic_num].id = scope->enumeration_id;
641                         ir_ioapic_num++;
642                 }
643                 start += scope->length;
644         }
645
646         return 0;
647 }
648
649 /*
650  * Finds the assocaition between IOAPIC's and its Interrupt-remapping
651  * hardware unit.
652  */
653 int __init parse_ioapics_under_ir(void)
654 {
655         struct dmar_drhd_unit *drhd;
656         int ir_supported = 0;
657
658         for_each_drhd_unit(drhd) {
659                 struct intel_iommu *iommu = drhd->iommu;
660
661                 if (ecap_ir_support(iommu->ecap)) {
662                         if (ir_parse_ioapic_scope(drhd->hdr, iommu))
663                                 return -1;
664
665                         ir_supported = 1;
666                 }
667         }
668
669         if (ir_supported && ir_ioapic_num != nr_ioapics) {
670                 printk(KERN_WARNING
671                        "Not all IO-APIC's listed under remapping hardware\n");
672                 return -1;
673         }
674
675         return ir_supported;
676 }
677
678 void disable_intr_remapping(void)
679 {
680         struct dmar_drhd_unit *drhd;
681         struct intel_iommu *iommu = NULL;
682
683         /*
684          * Disable Interrupt-remapping for all the DRHD's now.
685          */
686         for_each_iommu(iommu, drhd) {
687                 if (!ecap_ir_support(iommu->ecap))
688                         continue;
689
690                 iommu_disable_intr_remapping(iommu);
691         }
692 }
693
694 int reenable_intr_remapping(int eim)
695 {
696         struct dmar_drhd_unit *drhd;
697         int setup = 0;
698         struct intel_iommu *iommu = NULL;
699
700         for_each_iommu(iommu, drhd)
701                 if (iommu->qi)
702                         dmar_reenable_qi(iommu);
703
704         /*
705          * Setup Interrupt-remapping for all the DRHD's now.
706          */
707         for_each_iommu(iommu, drhd) {
708                 if (!ecap_ir_support(iommu->ecap))
709                         continue;
710
711                 /* Set up interrupt remapping for iommu.*/
712                 iommu_set_intr_remapping(iommu, eim);
713                 setup = 1;
714         }
715
716         if (!setup)
717                 goto error;
718
719         return 0;
720
721 error:
722         /*
723          * handle error condition gracefully here!
724          */
725         return -1;
726 }
727