Merge master.kernel.org:/pub/scm/linux/kernel/git/sridhar/lksctp-2.6
[linux-2.6] / arch / arm / mach-ixp4xx / common.c
1 /*
2  * arch/arm/mach-ixp4xx/common.c
3  *
4  * Generic code shared across all IXP4XX platforms
5  *
6  * Maintainer: Deepak Saxena <dsaxena@plexity.net>
7  *
8  * Copyright 2002 (c) Intel Corporation
9  * Copyright 2003-2004 (c) MontaVista, Software, Inc. 
10  * 
11  * This file is licensed under  the terms of the GNU General Public 
12  * License version 2. This program is licensed "as is" without any 
13  * warranty of any kind, whether express or implied.
14  */
15
16 #include <linux/config.h>
17 #include <linux/kernel.h>
18 #include <linux/mm.h>
19 #include <linux/init.h>
20 #include <linux/serial.h>
21 #include <linux/sched.h>
22 #include <linux/tty.h>
23 #include <linux/platform_device.h>
24 #include <linux/serial_core.h>
25 #include <linux/bootmem.h>
26 #include <linux/interrupt.h>
27 #include <linux/bitops.h>
28 #include <linux/time.h>
29 #include <linux/timex.h>
30
31 #include <asm/hardware.h>
32 #include <asm/uaccess.h>
33 #include <asm/io.h>
34 #include <asm/pgtable.h>
35 #include <asm/page.h>
36 #include <asm/irq.h>
37
38 #include <asm/mach/map.h>
39 #include <asm/mach/irq.h>
40 #include <asm/mach/time.h>
41
42 /*************************************************************************
43  * IXP4xx chipset I/O mapping
44  *************************************************************************/
45 static struct map_desc ixp4xx_io_desc[] __initdata = {
46         {       /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACs, USB .... */
47                 .virtual        = IXP4XX_PERIPHERAL_BASE_VIRT,
48                 .pfn            = __phys_to_pfn(IXP4XX_PERIPHERAL_BASE_PHYS),
49                 .length         = IXP4XX_PERIPHERAL_REGION_SIZE,
50                 .type           = MT_DEVICE
51         }, {    /* Expansion Bus Config Registers */
52                 .virtual        = IXP4XX_EXP_CFG_BASE_VIRT,
53                 .pfn            = __phys_to_pfn(IXP4XX_EXP_CFG_BASE_PHYS),
54                 .length         = IXP4XX_EXP_CFG_REGION_SIZE,
55                 .type           = MT_DEVICE
56         }, {    /* PCI Registers */
57                 .virtual        = IXP4XX_PCI_CFG_BASE_VIRT,
58                 .pfn            = __phys_to_pfn(IXP4XX_PCI_CFG_BASE_PHYS),
59                 .length         = IXP4XX_PCI_CFG_REGION_SIZE,
60                 .type           = MT_DEVICE
61         },
62 #ifdef CONFIG_DEBUG_LL
63         {       /* Debug UART mapping */
64                 .virtual        = IXP4XX_DEBUG_UART_BASE_VIRT,
65                 .pfn            = __phys_to_pfn(IXP4XX_DEBUG_UART_BASE_PHYS),
66                 .length         = IXP4XX_DEBUG_UART_REGION_SIZE,
67                 .type           = MT_DEVICE
68         }
69 #endif
70 };
71
72 void __init ixp4xx_map_io(void)
73 {
74         iotable_init(ixp4xx_io_desc, ARRAY_SIZE(ixp4xx_io_desc));
75 }
76
77
78 /*************************************************************************
79  * IXP4xx chipset IRQ handling
80  *
81  * TODO: GPIO IRQs should be marked invalid until the user of the IRQ
82  *       (be it PCI or something else) configures that GPIO line
83  *       as an IRQ.
84  **************************************************************************/
85 enum ixp4xx_irq_type {
86         IXP4XX_IRQ_LEVEL, IXP4XX_IRQ_EDGE
87 };
88
89 static void ixp4xx_config_irq(unsigned irq, enum ixp4xx_irq_type type);
90
91 /*
92  * IRQ -> GPIO mapping table
93  */
94 static int irq2gpio[32] = {
95         -1, -1, -1, -1, -1, -1,  0,  1,
96         -1, -1, -1, -1, -1, -1, -1, -1,
97         -1, -1, -1,  2,  3,  4,  5,  6,
98          7,  8,  9, 10, 11, 12, -1, -1,
99 };
100
101 static int ixp4xx_set_irq_type(unsigned int irq, unsigned int type)
102 {
103         int line = irq2gpio[irq];
104         u32 int_style;
105         enum ixp4xx_irq_type irq_type;
106         volatile u32 *int_reg;
107
108         /*
109          * Only for GPIO IRQs
110          */
111         if (line < 0)
112                 return -EINVAL;
113
114         if (type & IRQT_BOTHEDGE) {
115                 int_style = IXP4XX_GPIO_STYLE_TRANSITIONAL;
116                 irq_type = IXP4XX_IRQ_EDGE;
117         } else  if (type & IRQT_RISING) {
118                 int_style = IXP4XX_GPIO_STYLE_RISING_EDGE;
119                 irq_type = IXP4XX_IRQ_EDGE;
120         } else if (type & IRQT_FALLING) {
121                 int_style = IXP4XX_GPIO_STYLE_FALLING_EDGE;
122                 irq_type = IXP4XX_IRQ_EDGE;
123         } else if (type & IRQT_HIGH) {
124                 int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH;
125                 irq_type = IXP4XX_IRQ_LEVEL;
126         } else if (type & IRQT_LOW) {
127                 int_style = IXP4XX_GPIO_STYLE_ACTIVE_LOW;
128                 irq_type = IXP4XX_IRQ_LEVEL;
129         } else
130                 return -EINVAL;
131
132         ixp4xx_config_irq(irq, irq_type);
133
134         if (line >= 8) {        /* pins 8-15 */
135                 line -= 8;
136                 int_reg = IXP4XX_GPIO_GPIT2R;
137         } else {                /* pins 0-7 */
138                 int_reg = IXP4XX_GPIO_GPIT1R;
139         }
140
141         /* Clear the style for the appropriate pin */
142         *int_reg &= ~(IXP4XX_GPIO_STYLE_CLEAR <<
143                         (line * IXP4XX_GPIO_STYLE_SIZE));
144
145         *IXP4XX_GPIO_GPISR = (1 << line);
146
147         /* Set the new style */
148         *int_reg |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE));
149
150         return 0;
151 }
152
153 static void ixp4xx_irq_mask(unsigned int irq)
154 {
155         if (cpu_is_ixp46x() && irq >= 32)
156                 *IXP4XX_ICMR2 &= ~(1 << (irq - 32));
157         else
158                 *IXP4XX_ICMR &= ~(1 << irq);
159 }
160
161 static void ixp4xx_irq_unmask(unsigned int irq)
162 {
163         if (cpu_is_ixp46x() && irq >= 32)
164                 *IXP4XX_ICMR2 |= (1 << (irq - 32));
165         else
166                 *IXP4XX_ICMR |= (1 << irq);
167 }
168
169 static void ixp4xx_irq_ack(unsigned int irq)
170 {
171         int line = (irq < 32) ? irq2gpio[irq] : -1;
172
173         if (line >= 0)
174                 *IXP4XX_GPIO_GPISR = (1 << line);
175 }
176
177 /*
178  * Level triggered interrupts on GPIO lines can only be cleared when the
179  * interrupt condition disappears.
180  */
181 static void ixp4xx_irq_level_unmask(unsigned int irq)
182 {
183         ixp4xx_irq_ack(irq);
184         ixp4xx_irq_unmask(irq);
185 }
186
187 static struct irqchip ixp4xx_irq_level_chip = {
188         .ack            = ixp4xx_irq_mask,
189         .mask           = ixp4xx_irq_mask,
190         .unmask         = ixp4xx_irq_level_unmask,
191         .set_type       = ixp4xx_set_irq_type,
192 };
193
194 static struct irqchip ixp4xx_irq_edge_chip = {
195         .ack            = ixp4xx_irq_ack,
196         .mask           = ixp4xx_irq_mask,
197         .unmask         = ixp4xx_irq_unmask,
198         .set_type       = ixp4xx_set_irq_type,
199 };
200
201 static void ixp4xx_config_irq(unsigned irq, enum ixp4xx_irq_type type)
202 {
203         switch (type) {
204         case IXP4XX_IRQ_LEVEL:
205                 set_irq_chip(irq, &ixp4xx_irq_level_chip);
206                 set_irq_handler(irq, do_level_IRQ);
207                 break;
208         case IXP4XX_IRQ_EDGE:
209                 set_irq_chip(irq, &ixp4xx_irq_edge_chip);
210                 set_irq_handler(irq, do_edge_IRQ);
211                 break;
212         }
213         set_irq_flags(irq, IRQF_VALID);
214 }
215
216 void __init ixp4xx_init_irq(void)
217 {
218         int i = 0;
219
220         /* Route all sources to IRQ instead of FIQ */
221         *IXP4XX_ICLR = 0x0;
222
223         /* Disable all interrupt */
224         *IXP4XX_ICMR = 0x0; 
225
226         if (cpu_is_ixp46x()) {
227                 /* Route upper 32 sources to IRQ instead of FIQ */
228                 *IXP4XX_ICLR2 = 0x00;
229
230                 /* Disable upper 32 interrupts */
231                 *IXP4XX_ICMR2 = 0x00;
232         }
233
234         /* Default to all level triggered */
235         for(i = 0; i < NR_IRQS; i++)
236                 ixp4xx_config_irq(i, IXP4XX_IRQ_LEVEL);
237 }
238
239
240 /*************************************************************************
241  * IXP4xx timer tick
242  * We use OS timer1 on the CPU for the timer tick and the timestamp 
243  * counter as a source of real clock ticks to account for missed jiffies.
244  *************************************************************************/
245
246 static unsigned volatile last_jiffy_time;
247
248 #define CLOCK_TICKS_PER_USEC    ((CLOCK_TICK_RATE + USEC_PER_SEC/2) / USEC_PER_SEC)
249
250 /* IRQs are disabled before entering here from do_gettimeofday() */
251 static unsigned long ixp4xx_gettimeoffset(void)
252 {
253         u32 elapsed;
254
255         elapsed = *IXP4XX_OSTS - last_jiffy_time;
256
257         return elapsed / CLOCK_TICKS_PER_USEC;
258 }
259
260 static irqreturn_t ixp4xx_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
261 {
262         write_seqlock(&xtime_lock);
263
264         /* Clear Pending Interrupt by writing '1' to it */
265         *IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
266
267         /*
268          * Catch up with the real idea of time
269          */
270         while ((*IXP4XX_OSTS - last_jiffy_time) > LATCH) {
271                 timer_tick(regs);
272                 last_jiffy_time += LATCH;
273         }
274
275         write_sequnlock(&xtime_lock);
276
277         return IRQ_HANDLED;
278 }
279
280 static struct irqaction ixp4xx_timer_irq = {
281         .name           = "IXP4xx Timer Tick",
282         .flags          = SA_INTERRUPT | SA_TIMER,
283         .handler        = ixp4xx_timer_interrupt,
284 };
285
286 static void __init ixp4xx_timer_init(void)
287 {
288         /* Clear Pending Interrupt by writing '1' to it */
289         *IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
290
291         /* Setup the Timer counter value */
292         *IXP4XX_OSRT1 = (LATCH & ~IXP4XX_OST_RELOAD_MASK) | IXP4XX_OST_ENABLE;
293
294         /* Reset time-stamp counter */
295         *IXP4XX_OSTS = 0;
296         last_jiffy_time = 0;
297
298         /* Connect the interrupt handler and enable the interrupt */
299         setup_irq(IRQ_IXP4XX_TIMER1, &ixp4xx_timer_irq);
300 }
301
302 struct sys_timer ixp4xx_timer = {
303         .init           = ixp4xx_timer_init,
304         .offset         = ixp4xx_gettimeoffset,
305 };
306
307 static struct resource ixp46x_i2c_resources[] = {
308         [0] = {
309                 .start  = 0xc8011000,
310                 .end    = 0xc801101c,
311                 .flags  = IORESOURCE_MEM,
312         },
313         [1] = {
314                 .start  = IRQ_IXP4XX_I2C,
315                 .end    = IRQ_IXP4XX_I2C,
316                 .flags  = IORESOURCE_IRQ
317         }
318 };
319
320 /*
321  * I2C controller. The IXP46x uses the same block as the IOP3xx, so
322  * we just use the same device name.
323  */
324 static struct platform_device ixp46x_i2c_controller = {
325         .name           = "IOP3xx-I2C",
326         .id             = 0,
327         .num_resources  = 2,
328         .resource       = ixp46x_i2c_resources
329 };
330
331 static struct platform_device *ixp46x_devices[] __initdata = {
332         &ixp46x_i2c_controller
333 };
334
335 unsigned long ixp4xx_exp_bus_size;
336 EXPORT_SYMBOL(ixp4xx_exp_bus_size);
337
338 void __init ixp4xx_sys_init(void)
339 {
340         ixp4xx_exp_bus_size = SZ_16M;
341
342         if (cpu_is_ixp46x()) {
343                 int region;
344
345                 platform_add_devices(ixp46x_devices,
346                                 ARRAY_SIZE(ixp46x_devices));
347
348                 for (region = 0; region < 7; region++) {
349                         if((*(IXP4XX_EXP_REG(0x4 * region)) & 0x200)) {
350                                 ixp4xx_exp_bus_size = SZ_32M;
351                                 break;
352                         }
353                 }
354         }
355
356         printk("IXP4xx: Using %luMiB expansion bus window size\n",
357                         ixp4xx_exp_bus_size >> 20);
358 }
359