git.oblomov.eu Git - linux-2.6/blob - arch/powerpc/platforms/cell/spufs/switch.c

   1 /*
   2  * spu_switch.c
   3  *
   4  * (C) Copyright IBM Corp. 2005
   5  *
   6  * Author: Mark Nutter <mnutter@us.ibm.com>
   7  *
   8  * Host-side part of SPU context switch sequence outlined in
   9  * Synergistic Processor Element, Book IV.
  10  *
  11  * A fully premptive switch of an SPE is very expensive in terms
  12  * of time and system resources.  SPE Book IV indicates that SPE
  13  * allocation should follow a "serially reusable device" model,
  14  * in which the SPE is assigned a task until it completes.  When
  15  * this is not possible, this sequence may be used to premptively
  16  * save, and then later (optionally) restore the context of a
  17  * program executing on an SPE.
  18  *
  19  *
  20  * This program is free software; you can redistribute it and/or modify
  21  * it under the terms of the GNU General Public License as published by
  22  * the Free Software Foundation; either version 2, or (at your option)
  23  * any later version.
  24  *
  25  * This program is distributed in the hope that it will be useful,
  26  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  27  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  28  * GNU General Public License for more details.
  29  *
  30  * You should have received a copy of the GNU General Public License
  31  * along with this program; if not, write to the Free Software
  32  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  33  */
  34
  35 #include <linux/module.h>
  36 #include <linux/errno.h>
  37 #include <linux/sched.h>
  38 #include <linux/kernel.h>
  39 #include <linux/mm.h>
  40 #include <linux/vmalloc.h>
  41 #include <linux/smp.h>
  42 #include <linux/stddef.h>
  43 #include <linux/unistd.h>
  44
  45 #include <asm/io.h>
  46 #include <asm/spu.h>
  47 #include <asm/spu_priv1.h>
  48 #include <asm/spu_csa.h>
  49 #include <asm/mmu_context.h>
  50
  51 #include "spu_save_dump.h"
  52 #include "spu_restore_dump.h"
  53
  54 #if 0
  55 #define POLL_WHILE_TRUE(_c) {                           \
  56     do {                                                \
  57     } while (_c);                                       \
  58   }
  59 #else
  60 #define RELAX_SPIN_COUNT                                1000
  61 #define POLL_WHILE_TRUE(_c) {                           \
  62     do {                                                \
  63         int _i;                                         \
  64         for (_i=0; _i<RELAX_SPIN_COUNT && (_c); _i++) { \
  65             cpu_relax();                                \
  66         }                                               \
  67         if (unlikely(_c)) yield();                      \
  68         else break;                                     \
  69     } while (_c);                                       \
  70   }
  71 #endif                          /* debug */
  72
  73 #define POLL_WHILE_FALSE(_c)    POLL_WHILE_TRUE(!(_c))
  74
  75 static inline void acquire_spu_lock(struct spu *spu)
  76 {
  77         /* Save, Step 1:
  78          * Restore, Step 1:
  79          *    Acquire SPU-specific mutual exclusion lock.
  80          *    TBD.
  81          */
  82 }
  83
  84 static inline void release_spu_lock(struct spu *spu)
  85 {
  86         /* Restore, Step 76:
  87          *    Release SPU-specific mutual exclusion lock.
  88          *    TBD.
  89          */
  90 }
  91
  92 static inline int check_spu_isolate(struct spu_state *csa, struct spu *spu)
  93 {
  94         struct spu_problem __iomem *prob = spu->problem;
  95         u32 isolate_state;
  96
  97         /* Save, Step 2:
  98          * Save, Step 6:
  99          *     If SPU_Status[E,L,IS] any field is '1', this
 100          *     SPU is in isolate state and cannot be context
 101          *     saved at this time.
 102          */
 103         isolate_state = SPU_STATUS_ISOLATED_STATE |
 104             SPU_STATUS_ISOLATED_LOAD_STATUS | SPU_STATUS_ISOLATED_EXIT_STATUS;
 105         return (in_be32(&prob->spu_status_R) & isolate_state) ? 1 : 0;
 106 }
 107
 108 static inline void disable_interrupts(struct spu_state *csa, struct spu *spu)
 109 {
 110         /* Save, Step 3:
 111          * Restore, Step 2:
 112          *     Save INT_Mask_class0 in CSA.
 113          *     Write INT_MASK_class0 with value of 0.
 114          *     Save INT_Mask_class1 in CSA.
 115          *     Write INT_MASK_class1 with value of 0.
 116          *     Save INT_Mask_class2 in CSA.
 117          *     Write INT_MASK_class2 with value of 0.
 118          */
 119         spin_lock_irq(&spu->register_lock);
 120         if (csa) {
 121                 csa->priv1.int_mask_class0_RW = spu_int_mask_get(spu, 0);
 122                 csa->priv1.int_mask_class1_RW = spu_int_mask_get(spu, 1);
 123                 csa->priv1.int_mask_class2_RW = spu_int_mask_get(spu, 2);
 124         }
 125         spu_int_mask_set(spu, 0, 0ul);
 126         spu_int_mask_set(spu, 1, 0ul);
 127         spu_int_mask_set(spu, 2, 0ul);
 128         eieio();
 129         spin_unlock_irq(&spu->register_lock);
 130 }
 131
 132 static inline void set_watchdog_timer(struct spu_state *csa, struct spu *spu)
 133 {
 134         /* Save, Step 4:
 135          * Restore, Step 25.
 136          *    Set a software watchdog timer, which specifies the
 137          *    maximum allowable time for a context save sequence.
 138          *
 139          *    For present, this implementation will not set a global
 140          *    watchdog timer, as virtualization & variable system load
 141          *    may cause unpredictable execution times.
 142          */
 143 }
 144
 145 static inline void inhibit_user_access(struct spu_state *csa, struct spu *spu)
 146 {
 147         /* Save, Step 5:
 148          * Restore, Step 3:
 149          *     Inhibit user-space access (if provided) to this
 150          *     SPU by unmapping the virtual pages assigned to
 151          *     the SPU memory-mapped I/O (MMIO) for problem
 152          *     state. TBD.
 153          */
 154 }
 155
 156 static inline void set_switch_pending(struct spu_state *csa, struct spu *spu)
 157 {
 158         /* Save, Step 7:
 159          * Restore, Step 5:
 160          *     Set a software context switch pending flag.
 161          */
 162         set_bit(SPU_CONTEXT_SWITCH_PENDING, &spu->flags);
 163         mb();
 164 }
 165
 166 static inline void save_mfc_cntl(struct spu_state *csa, struct spu *spu)
 167 {
 168         struct spu_priv2 __iomem *priv2 = spu->priv2;
 169
 170         /* Save, Step 8:
 171          *     Suspend DMA and save MFC_CNTL.
 172          */
 173         switch (in_be64(&priv2->mfc_control_RW) &
 174                MFC_CNTL_SUSPEND_DMA_STATUS_MASK) {
 175         case MFC_CNTL_SUSPEND_IN_PROGRESS:
 176                 POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &
 177                                   MFC_CNTL_SUSPEND_DMA_STATUS_MASK) ==
 178                                  MFC_CNTL_SUSPEND_COMPLETE);
 179                 /* fall through */
 180         case MFC_CNTL_SUSPEND_COMPLETE:
 181                 if (csa) {
 182                         csa->priv2.mfc_control_RW =
 183                                 in_be64(&priv2->mfc_control_RW) |
 184                                 MFC_CNTL_SUSPEND_DMA_QUEUE;
 185                 }
 186                 break;
 187         case MFC_CNTL_NORMAL_DMA_QUEUE_OPERATION:
 188                 out_be64(&priv2->mfc_control_RW, MFC_CNTL_SUSPEND_DMA_QUEUE);
 189                 POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &
 190                                   MFC_CNTL_SUSPEND_DMA_STATUS_MASK) ==
 191                                  MFC_CNTL_SUSPEND_COMPLETE);
 192                 if (csa) {
 193                         csa->priv2.mfc_control_RW =
 194                                 in_be64(&priv2->mfc_control_RW) &
 195                                 ~MFC_CNTL_SUSPEND_DMA_QUEUE;
 196                 }
 197                 break;
 198         }
 199 }
 200
 201 static inline void save_spu_runcntl(struct spu_state *csa, struct spu *spu)
 202 {
 203         struct spu_problem __iomem *prob = spu->problem;
 204
 205         /* Save, Step 9:
 206          *     Save SPU_Runcntl in the CSA.  This value contains
 207          *     the "Application Desired State".
 208          */
 209         csa->prob.spu_runcntl_RW = in_be32(&prob->spu_runcntl_RW);
 210 }
 211
 212 static inline void save_mfc_sr1(struct spu_state *csa, struct spu *spu)
 213 {
 214         /* Save, Step 10:
 215          *     Save MFC_SR1 in the CSA.
 216          */
 217         csa->priv1.mfc_sr1_RW = spu_mfc_sr1_get(spu);
 218 }
 219
 220 static inline void save_spu_status(struct spu_state *csa, struct spu *spu)
 221 {
 222         struct spu_problem __iomem *prob = spu->problem;
 223
 224         /* Save, Step 11:
 225          *     Read SPU_Status[R], and save to CSA.
 226          */
 227         if ((in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING) == 0) {
 228                 csa->prob.spu_status_R = in_be32(&prob->spu_status_R);
 229         } else {
 230                 u32 stopped;
 231
 232                 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_STOP);
 233                 eieio();
 234                 POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
 235                                 SPU_STATUS_RUNNING);
 236                 stopped =
 237                     SPU_STATUS_INVALID_INSTR | SPU_STATUS_SINGLE_STEP |
 238                     SPU_STATUS_STOPPED_BY_HALT | SPU_STATUS_STOPPED_BY_STOP;
 239                 if ((in_be32(&prob->spu_status_R) & stopped) == 0)
 240                         csa->prob.spu_status_R = SPU_STATUS_RUNNING;
 241                 else
 242                         csa->prob.spu_status_R = in_be32(&prob->spu_status_R);
 243         }
 244 }
 245
 246 static inline void save_mfc_decr(struct spu_state *csa, struct spu *spu)
 247 {
 248         struct spu_priv2 __iomem *priv2 = spu->priv2;
 249
 250         /* Save, Step 12:
 251          *     Read MFC_CNTL[Ds].  Update saved copy of
 252          *     CSA.MFC_CNTL[Ds].
 253          */
 254         if (in_be64(&priv2->mfc_control_RW) & MFC_CNTL_DECREMENTER_RUNNING) {
 255                 csa->priv2.mfc_control_RW |= MFC_CNTL_DECREMENTER_RUNNING;
 256         } else {
 257                 csa->priv2.mfc_control_RW &= ~MFC_CNTL_DECREMENTER_RUNNING;
 258         }
 259 }
 260
 261 static inline void halt_mfc_decr(struct spu_state *csa, struct spu *spu)
 262 {
 263         struct spu_priv2 __iomem *priv2 = spu->priv2;
 264
 265         /* Save, Step 13:
 266          *     Write MFC_CNTL[Dh] set to a '1' to halt
 267          *     the decrementer.
 268          */
 269         out_be64(&priv2->mfc_control_RW,
 270                  MFC_CNTL_DECREMENTER_HALTED | MFC_CNTL_SUSPEND_MASK);
 271         eieio();
 272 }
 273
 274 static inline void save_timebase(struct spu_state *csa, struct spu *spu)
 275 {
 276         /* Save, Step 14:
 277          *    Read PPE Timebase High and Timebase low registers
 278          *    and save in CSA.  TBD.
 279          */
 280         csa->suspend_time = get_cycles();
 281 }
 282
 283 static inline void remove_other_spu_access(struct spu_state *csa,
 284                                            struct spu *spu)
 285 {
 286         /* Save, Step 15:
 287          *     Remove other SPU access to this SPU by unmapping
 288          *     this SPU's pages from their address space.  TBD.
 289          */
 290 }
 291
 292 static inline void do_mfc_mssync(struct spu_state *csa, struct spu *spu)
 293 {
 294         struct spu_problem __iomem *prob = spu->problem;
 295
 296         /* Save, Step 16:
 297          * Restore, Step 11.
 298          *     Write SPU_MSSync register. Poll SPU_MSSync[P]
 299          *     for a value of 0.
 300          */
 301         out_be64(&prob->spc_mssync_RW, 1UL);
 302         POLL_WHILE_TRUE(in_be64(&prob->spc_mssync_RW) & MS_SYNC_PENDING);
 303 }
 304
 305 static inline void issue_mfc_tlbie(struct spu_state *csa, struct spu *spu)
 306 {
 307         /* Save, Step 17:
 308          * Restore, Step 12.
 309          * Restore, Step 48.
 310          *     Write TLB_Invalidate_Entry[IS,VPN,L,Lp]=0 register.
 311          *     Then issue a PPE sync instruction.
 312          */
 313         spu_tlb_invalidate(spu);
 314         mb();
 315 }
 316
 317 static inline void handle_pending_interrupts(struct spu_state *csa,
 318                                              struct spu *spu)
 319 {
 320         /* Save, Step 18:
 321          *     Handle any pending interrupts from this SPU
 322          *     here.  This is OS or hypervisor specific.  One
 323          *     option is to re-enable interrupts to handle any
 324          *     pending interrupts, with the interrupt handlers
 325          *     recognizing the software Context Switch Pending
 326          *     flag, to ensure the SPU execution or MFC command
 327          *     queue is not restarted.  TBD.
 328          */
 329 }
 330
 331 static inline void save_mfc_queues(struct spu_state *csa, struct spu *spu)
 332 {
 333         struct spu_priv2 __iomem *priv2 = spu->priv2;
 334         int i;
 335
 336         /* Save, Step 19:
 337          *     If MFC_Cntl[Se]=0 then save
 338          *     MFC command queues.
 339          */
 340         if ((in_be64(&priv2->mfc_control_RW) & MFC_CNTL_DMA_QUEUES_EMPTY) == 0) {
 341                 for (i = 0; i < 8; i++) {
 342                         csa->priv2.puq[i].mfc_cq_data0_RW =
 343                             in_be64(&priv2->puq[i].mfc_cq_data0_RW);
 344                         csa->priv2.puq[i].mfc_cq_data1_RW =
 345                             in_be64(&priv2->puq[i].mfc_cq_data1_RW);
 346                         csa->priv2.puq[i].mfc_cq_data2_RW =
 347                             in_be64(&priv2->puq[i].mfc_cq_data2_RW);
 348                         csa->priv2.puq[i].mfc_cq_data3_RW =
 349                             in_be64(&priv2->puq[i].mfc_cq_data3_RW);
 350                 }
 351                 for (i = 0; i < 16; i++) {
 352                         csa->priv2.spuq[i].mfc_cq_data0_RW =
 353                             in_be64(&priv2->spuq[i].mfc_cq_data0_RW);
 354                         csa->priv2.spuq[i].mfc_cq_data1_RW =
 355                             in_be64(&priv2->spuq[i].mfc_cq_data1_RW);
 356                         csa->priv2.spuq[i].mfc_cq_data2_RW =
 357                             in_be64(&priv2->spuq[i].mfc_cq_data2_RW);
 358                         csa->priv2.spuq[i].mfc_cq_data3_RW =
 359                             in_be64(&priv2->spuq[i].mfc_cq_data3_RW);
 360                 }
 361         }
 362 }
 363
 364 static inline void save_ppu_querymask(struct spu_state *csa, struct spu *spu)
 365 {
 366         struct spu_problem __iomem *prob = spu->problem;
 367
 368         /* Save, Step 20:
 369          *     Save the PPU_QueryMask register
 370          *     in the CSA.
 371          */
 372         csa->prob.dma_querymask_RW = in_be32(&prob->dma_querymask_RW);
 373 }
 374
 375 static inline void save_ppu_querytype(struct spu_state *csa, struct spu *spu)
 376 {
 377         struct spu_problem __iomem *prob = spu->problem;
 378
 379         /* Save, Step 21:
 380          *     Save the PPU_QueryType register
 381          *     in the CSA.
 382          */
 383         csa->prob.dma_querytype_RW = in_be32(&prob->dma_querytype_RW);
 384 }
 385
 386 static inline void save_ppu_tagstatus(struct spu_state *csa, struct spu *spu)
 387 {
 388         struct spu_problem __iomem *prob = spu->problem;
 389
 390         /* Save the Prxy_TagStatus register in the CSA.
 391          *
 392          * It is unnecessary to restore dma_tagstatus_R, however,
 393          * dma_tagstatus_R in the CSA is accessed via backing_ops, so
 394          * we must save it.
 395          */
 396         csa->prob.dma_tagstatus_R = in_be32(&prob->dma_tagstatus_R);
 397 }
 398
 399 static inline void save_mfc_csr_tsq(struct spu_state *csa, struct spu *spu)
 400 {
 401         struct spu_priv2 __iomem *priv2 = spu->priv2;
 402
 403         /* Save, Step 22:
 404          *     Save the MFC_CSR_TSQ register
 405          *     in the LSCSA.
 406          */
 407         csa->priv2.spu_tag_status_query_RW =
 408             in_be64(&priv2->spu_tag_status_query_RW);
 409 }
 410
 411 static inline void save_mfc_csr_cmd(struct spu_state *csa, struct spu *spu)
 412 {
 413         struct spu_priv2 __iomem *priv2 = spu->priv2;
 414
 415         /* Save, Step 23:
 416          *     Save the MFC_CSR_CMD1 and MFC_CSR_CMD2
 417          *     registers in the CSA.
 418          */
 419         csa->priv2.spu_cmd_buf1_RW = in_be64(&priv2->spu_cmd_buf1_RW);
 420         csa->priv2.spu_cmd_buf2_RW = in_be64(&priv2->spu_cmd_buf2_RW);
 421 }
 422
 423 static inline void save_mfc_csr_ato(struct spu_state *csa, struct spu *spu)
 424 {
 425         struct spu_priv2 __iomem *priv2 = spu->priv2;
 426
 427         /* Save, Step 24:
 428          *     Save the MFC_CSR_ATO register in
 429          *     the CSA.
 430          */
 431         csa->priv2.spu_atomic_status_RW = in_be64(&priv2->spu_atomic_status_RW);
 432 }
 433
 434 static inline void save_mfc_tclass_id(struct spu_state *csa, struct spu *spu)
 435 {
 436         /* Save, Step 25:
 437          *     Save the MFC_TCLASS_ID register in
 438          *     the CSA.
 439          */
 440         csa->priv1.mfc_tclass_id_RW = spu_mfc_tclass_id_get(spu);
 441 }
 442
 443 static inline void set_mfc_tclass_id(struct spu_state *csa, struct spu *spu)
 444 {
 445         /* Save, Step 26:
 446          * Restore, Step 23.
 447          *     Write the MFC_TCLASS_ID register with
 448          *     the value 0x10000000.
 449          */
 450         spu_mfc_tclass_id_set(spu, 0x10000000);
 451         eieio();
 452 }
 453
 454 static inline void purge_mfc_queue(struct spu_state *csa, struct spu *spu)
 455 {
 456         struct spu_priv2 __iomem *priv2 = spu->priv2;
 457
 458         /* Save, Step 27:
 459          * Restore, Step 14.
 460          *     Write MFC_CNTL[Pc]=1 (purge queue).
 461          */
 462         out_be64(&priv2->mfc_control_RW, MFC_CNTL_PURGE_DMA_REQUEST);
 463         eieio();
 464 }
 465
 466 static inline void wait_purge_complete(struct spu_state *csa, struct spu *spu)
 467 {
 468         struct spu_priv2 __iomem *priv2 = spu->priv2;
 469
 470         /* Save, Step 28:
 471          *     Poll MFC_CNTL[Ps] until value '11' is read
 472          *     (purge complete).
 473          */
 474         POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &
 475                          MFC_CNTL_PURGE_DMA_STATUS_MASK) ==
 476                          MFC_CNTL_PURGE_DMA_COMPLETE);
 477 }
 478
 479 static inline void setup_mfc_sr1(struct spu_state *csa, struct spu *spu)
 480 {
 481         /* Save, Step 30:
 482          * Restore, Step 18:
 483          *     Write MFC_SR1 with MFC_SR1[D=0,S=1] and
 484          *     MFC_SR1[TL,R,Pr,T] set correctly for the
 485          *     OS specific environment.
 486          *
 487          *     Implementation note: The SPU-side code
 488          *     for save/restore is privileged, so the
 489          *     MFC_SR1[Pr] bit is not set.
 490          *
 491          */
 492         spu_mfc_sr1_set(spu, (MFC_STATE1_MASTER_RUN_CONTROL_MASK |
 493                               MFC_STATE1_RELOCATE_MASK |
 494                               MFC_STATE1_BUS_TLBIE_MASK));
 495 }
 496
 497 static inline void save_spu_npc(struct spu_state *csa, struct spu *spu)
 498 {
 499         struct spu_problem __iomem *prob = spu->problem;
 500
 501         /* Save, Step 31:
 502          *     Save SPU_NPC in the CSA.
 503          */
 504         csa->prob.spu_npc_RW = in_be32(&prob->spu_npc_RW);
 505 }
 506
 507 static inline void save_spu_privcntl(struct spu_state *csa, struct spu *spu)
 508 {
 509         struct spu_priv2 __iomem *priv2 = spu->priv2;
 510
 511         /* Save, Step 32:
 512          *     Save SPU_PrivCntl in the CSA.
 513          */
 514         csa->priv2.spu_privcntl_RW = in_be64(&priv2->spu_privcntl_RW);
 515 }
 516
 517 static inline void reset_spu_privcntl(struct spu_state *csa, struct spu *spu)
 518 {
 519         struct spu_priv2 __iomem *priv2 = spu->priv2;
 520
 521         /* Save, Step 33:
 522          * Restore, Step 16:
 523          *     Write SPU_PrivCntl[S,Le,A] fields reset to 0.
 524          */
 525         out_be64(&priv2->spu_privcntl_RW, 0UL);
 526         eieio();
 527 }
 528
 529 static inline void save_spu_lslr(struct spu_state *csa, struct spu *spu)
 530 {
 531         struct spu_priv2 __iomem *priv2 = spu->priv2;
 532
 533         /* Save, Step 34:
 534          *     Save SPU_LSLR in the CSA.
 535          */
 536         csa->priv2.spu_lslr_RW = in_be64(&priv2->spu_lslr_RW);
 537 }
 538
 539 static inline void reset_spu_lslr(struct spu_state *csa, struct spu *spu)
 540 {
 541         struct spu_priv2 __iomem *priv2 = spu->priv2;
 542
 543         /* Save, Step 35:
 544          * Restore, Step 17.
 545          *     Reset SPU_LSLR.
 546          */
 547         out_be64(&priv2->spu_lslr_RW, LS_ADDR_MASK);
 548         eieio();
 549 }
 550
 551 static inline void save_spu_cfg(struct spu_state *csa, struct spu *spu)
 552 {
 553         struct spu_priv2 __iomem *priv2 = spu->priv2;
 554
 555         /* Save, Step 36:
 556          *     Save SPU_Cfg in the CSA.
 557          */
 558         csa->priv2.spu_cfg_RW = in_be64(&priv2->spu_cfg_RW);
 559 }
 560
 561 static inline void save_pm_trace(struct spu_state *csa, struct spu *spu)
 562 {
 563         /* Save, Step 37:
 564          *     Save PM_Trace_Tag_Wait_Mask in the CSA.
 565          *     Not performed by this implementation.
 566          */
 567 }
 568
 569 static inline void save_mfc_rag(struct spu_state *csa, struct spu *spu)
 570 {
 571         /* Save, Step 38:
 572          *     Save RA_GROUP_ID register and the
 573          *     RA_ENABLE reigster in the CSA.
 574          */
 575         csa->priv1.resource_allocation_groupID_RW =
 576                 spu_resource_allocation_groupID_get(spu);
 577         csa->priv1.resource_allocation_enable_RW =
 578                 spu_resource_allocation_enable_get(spu);
 579 }
 580
 581 static inline void save_ppu_mb_stat(struct spu_state *csa, struct spu *spu)
 582 {
 583         struct spu_problem __iomem *prob = spu->problem;
 584
 585         /* Save, Step 39:
 586          *     Save MB_Stat register in the CSA.
 587          */
 588         csa->prob.mb_stat_R = in_be32(&prob->mb_stat_R);
 589 }
 590
 591 static inline void save_ppu_mb(struct spu_state *csa, struct spu *spu)
 592 {
 593         struct spu_problem __iomem *prob = spu->problem;
 594
 595         /* Save, Step 40:
 596          *     Save the PPU_MB register in the CSA.
 597          */
 598         csa->prob.pu_mb_R = in_be32(&prob->pu_mb_R);
 599 }
 600
 601 static inline void save_ppuint_mb(struct spu_state *csa, struct spu *spu)
 602 {
 603         struct spu_priv2 __iomem *priv2 = spu->priv2;
 604
 605         /* Save, Step 41:
 606          *     Save the PPUINT_MB register in the CSA.
 607          */
 608         csa->priv2.puint_mb_R = in_be64(&priv2->puint_mb_R);
 609 }
 610
 611 static inline void save_ch_part1(struct spu_state *csa, struct spu *spu)
 612 {
 613         struct spu_priv2 __iomem *priv2 = spu->priv2;
 614         u64 idx, ch_indices[] = { 0UL, 3UL, 4UL, 24UL, 25UL, 27UL };
 615         int i;
 616
 617         /* Save, Step 42:
 618          */
 619
 620         /* Save CH 1, without channel count */
 621         out_be64(&priv2->spu_chnlcntptr_RW, 1);
 622         csa->spu_chnldata_RW[1] = in_be64(&priv2->spu_chnldata_RW);
 623
 624         /* Save the following CH: [0,3,4,24,25,27] */
 625         for (i = 0; i < ARRAY_SIZE(ch_indices); i++) {
 626                 idx = ch_indices[i];
 627                 out_be64(&priv2->spu_chnlcntptr_RW, idx);
 628                 eieio();
 629                 csa->spu_chnldata_RW[idx] = in_be64(&priv2->spu_chnldata_RW);
 630                 csa->spu_chnlcnt_RW[idx] = in_be64(&priv2->spu_chnlcnt_RW);
 631                 out_be64(&priv2->spu_chnldata_RW, 0UL);
 632                 out_be64(&priv2->spu_chnlcnt_RW, 0UL);
 633                 eieio();
 634         }
 635 }
 636
 637 static inline void save_spu_mb(struct spu_state *csa, struct spu *spu)
 638 {
 639         struct spu_priv2 __iomem *priv2 = spu->priv2;
 640         int i;
 641
 642         /* Save, Step 43:
 643          *     Save SPU Read Mailbox Channel.
 644          */
 645         out_be64(&priv2->spu_chnlcntptr_RW, 29UL);
 646         eieio();
 647         csa->spu_chnlcnt_RW[29] = in_be64(&priv2->spu_chnlcnt_RW);
 648         for (i = 0; i < 4; i++) {
 649                 csa->spu_mailbox_data[i] = in_be64(&priv2->spu_chnldata_RW);
 650         }
 651         out_be64(&priv2->spu_chnlcnt_RW, 0UL);
 652         eieio();
 653 }
 654
 655 static inline void save_mfc_cmd(struct spu_state *csa, struct spu *spu)
 656 {
 657         struct spu_priv2 __iomem *priv2 = spu->priv2;
 658
 659         /* Save, Step 44:
 660          *     Save MFC_CMD Channel.
 661          */
 662         out_be64(&priv2->spu_chnlcntptr_RW, 21UL);
 663         eieio();
 664         csa->spu_chnlcnt_RW[21] = in_be64(&priv2->spu_chnlcnt_RW);
 665         eieio();
 666 }
 667
 668 static inline void reset_ch(struct spu_state *csa, struct spu *spu)
 669 {
 670         struct spu_priv2 __iomem *priv2 = spu->priv2;
 671         u64 ch_indices[4] = { 21UL, 23UL, 28UL, 30UL };
 672         u64 ch_counts[4] = { 16UL, 1UL, 1UL, 1UL };
 673         u64 idx;
 674         int i;
 675
 676         /* Save, Step 45:
 677          *     Reset the following CH: [21, 23, 28, 30]
 678          */
 679         for (i = 0; i < 4; i++) {
 680                 idx = ch_indices[i];
 681                 out_be64(&priv2->spu_chnlcntptr_RW, idx);
 682                 eieio();
 683                 out_be64(&priv2->spu_chnlcnt_RW, ch_counts[i]);
 684                 eieio();
 685         }
 686 }
 687
 688 static inline void resume_mfc_queue(struct spu_state *csa, struct spu *spu)
 689 {
 690         struct spu_priv2 __iomem *priv2 = spu->priv2;
 691
 692         /* Save, Step 46:
 693          * Restore, Step 25.
 694          *     Write MFC_CNTL[Sc]=0 (resume queue processing).
 695          */
 696         out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESUME_DMA_QUEUE);
 697 }
 698
 699 static inline void get_kernel_slb(u64 ea, u64 slb[2])
 700 {
 701         u64 llp;
 702
 703         if (REGION_ID(ea) == KERNEL_REGION_ID)
 704                 llp = mmu_psize_defs[mmu_linear_psize].sllp;
 705         else
 706                 llp = mmu_psize_defs[mmu_virtual_psize].sllp;
 707         slb[0] = (get_kernel_vsid(ea) << SLB_VSID_SHIFT) |
 708                 SLB_VSID_KERNEL | llp;
 709         slb[1] = (ea & ESID_MASK) | SLB_ESID_V;
 710 }
 711
 712 static inline void load_mfc_slb(struct spu *spu, u64 slb[2], int slbe)
 713 {
 714         struct spu_priv2 __iomem *priv2 = spu->priv2;
 715
 716         out_be64(&priv2->slb_index_W, slbe);
 717         eieio();
 718         out_be64(&priv2->slb_vsid_RW, slb[0]);
 719         out_be64(&priv2->slb_esid_RW, slb[1]);
 720         eieio();
 721 }
 722
 723 static inline void setup_mfc_slbs(struct spu_state *csa, struct spu *spu)
 724 {
 725         u64 code_slb[2];
 726         u64 lscsa_slb[2];
 727
 728         /* Save, Step 47:
 729          * Restore, Step 30.
 730          *     If MFC_SR1[R]=1, write 0 to SLB_Invalidate_All
 731          *     register, then initialize SLB_VSID and SLB_ESID
 732          *     to provide access to SPU context save code and
 733          *     LSCSA.
 734          *
 735          *     This implementation places both the context
 736          *     switch code and LSCSA in kernel address space.
 737          *
 738          *     Further this implementation assumes that the
 739          *     MFC_SR1[R]=1 (in other words, assume that
 740          *     translation is desired by OS environment).
 741          */
 742         spu_invalidate_slbs(spu);
 743         get_kernel_slb((unsigned long)&spu_save_code[0], code_slb);
 744         get_kernel_slb((unsigned long)csa->lscsa, lscsa_slb);
 745         load_mfc_slb(spu, code_slb, 0);
 746         if ((lscsa_slb[0] != code_slb[0]) || (lscsa_slb[1] != code_slb[1]))
 747                 load_mfc_slb(spu, lscsa_slb, 1);
 748 }
 749
 750 static inline void set_switch_active(struct spu_state *csa, struct spu *spu)
 751 {
 752         /* Save, Step 48:
 753          * Restore, Step 23.
 754          *     Change the software context switch pending flag
 755          *     to context switch active.
 756          */
 757         set_bit(SPU_CONTEXT_SWITCH_ACTIVE, &spu->flags);
 758         clear_bit(SPU_CONTEXT_SWITCH_PENDING, &spu->flags);
 759         mb();
 760 }
 761
 762 static inline void enable_interrupts(struct spu_state *csa, struct spu *spu)
 763 {
 764         unsigned long class1_mask = CLASS1_ENABLE_SEGMENT_FAULT_INTR |
 765             CLASS1_ENABLE_STORAGE_FAULT_INTR;
 766
 767         /* Save, Step 49:
 768          * Restore, Step 22:
 769          *     Reset and then enable interrupts, as
 770          *     needed by OS.
 771          *
 772          *     This implementation enables only class1
 773          *     (translation) interrupts.
 774          */
 775         spin_lock_irq(&spu->register_lock);
 776         spu_int_stat_clear(spu, 0, ~0ul);
 777         spu_int_stat_clear(spu, 1, ~0ul);
 778         spu_int_stat_clear(spu, 2, ~0ul);
 779         spu_int_mask_set(spu, 0, 0ul);
 780         spu_int_mask_set(spu, 1, class1_mask);
 781         spu_int_mask_set(spu, 2, 0ul);
 782         spin_unlock_irq(&spu->register_lock);
 783 }
 784
 785 static inline int send_mfc_dma(struct spu *spu, unsigned long ea,
 786                                unsigned int ls_offset, unsigned int size,
 787                                unsigned int tag, unsigned int rclass,
 788                                unsigned int cmd)
 789 {
 790         struct spu_problem __iomem *prob = spu->problem;
 791         union mfc_tag_size_class_cmd command;
 792         unsigned int transfer_size;
 793         volatile unsigned int status = 0x0;
 794
 795         while (size > 0) {
 796                 transfer_size =
 797                     (size > MFC_MAX_DMA_SIZE) ? MFC_MAX_DMA_SIZE : size;
 798                 command.u.mfc_size = transfer_size;
 799                 command.u.mfc_tag = tag;
 800                 command.u.mfc_rclassid = rclass;
 801                 command.u.mfc_cmd = cmd;
 802                 do {
 803                         out_be32(&prob->mfc_lsa_W, ls_offset);
 804                         out_be64(&prob->mfc_ea_W, ea);
 805                         out_be64(&prob->mfc_union_W.all64, command.all64);
 806                         status =
 807                             in_be32(&prob->mfc_union_W.by32.mfc_class_cmd32);
 808                         if (unlikely(status & 0x2)) {
 809                                 cpu_relax();
 810                         }
 811                 } while (status & 0x3);
 812                 size -= transfer_size;
 813                 ea += transfer_size;
 814                 ls_offset += transfer_size;
 815         }
 816         return 0;
 817 }
 818
 819 static inline void save_ls_16kb(struct spu_state *csa, struct spu *spu)
 820 {
 821         unsigned long addr = (unsigned long)&csa->lscsa->ls[0];
 822         unsigned int ls_offset = 0x0;
 823         unsigned int size = 16384;
 824         unsigned int tag = 0;
 825         unsigned int rclass = 0;
 826         unsigned int cmd = MFC_PUT_CMD;
 827
 828         /* Save, Step 50:
 829          *     Issue a DMA command to copy the first 16K bytes
 830          *     of local storage to the CSA.
 831          */
 832         send_mfc_dma(spu, addr, ls_offset, size, tag, rclass, cmd);
 833 }
 834
 835 static inline void set_spu_npc(struct spu_state *csa, struct spu *spu)
 836 {
 837         struct spu_problem __iomem *prob = spu->problem;
 838
 839         /* Save, Step 51:
 840          * Restore, Step 31.
 841          *     Write SPU_NPC[IE]=0 and SPU_NPC[LSA] to entry
 842          *     point address of context save code in local
 843          *     storage.
 844          *
 845          *     This implementation uses SPU-side save/restore
 846          *     programs with entry points at LSA of 0.
 847          */
 848         out_be32(&prob->spu_npc_RW, 0);
 849         eieio();
 850 }
 851
 852 static inline void set_signot1(struct spu_state *csa, struct spu *spu)
 853 {
 854         struct spu_problem __iomem *prob = spu->problem;
 855         union {
 856                 u64 ull;
 857                 u32 ui[2];
 858         } addr64;
 859
 860         /* Save, Step 52:
 861          * Restore, Step 32:
 862          *    Write SPU_Sig_Notify_1 register with upper 32-bits
 863          *    of the CSA.LSCSA effective address.
 864          */
 865         addr64.ull = (u64) csa->lscsa;
 866         out_be32(&prob->signal_notify1, addr64.ui[0]);
 867         eieio();
 868 }
 869
 870 static inline void set_signot2(struct spu_state *csa, struct spu *spu)
 871 {
 872         struct spu_problem __iomem *prob = spu->problem;
 873         union {
 874                 u64 ull;
 875                 u32 ui[2];
 876         } addr64;
 877
 878         /* Save, Step 53:
 879          * Restore, Step 33:
 880          *    Write SPU_Sig_Notify_2 register with lower 32-bits
 881          *    of the CSA.LSCSA effective address.
 882          */
 883         addr64.ull = (u64) csa->lscsa;
 884         out_be32(&prob->signal_notify2, addr64.ui[1]);
 885         eieio();
 886 }
 887
 888 static inline void send_save_code(struct spu_state *csa, struct spu *spu)
 889 {
 890         unsigned long addr = (unsigned long)&spu_save_code[0];
 891         unsigned int ls_offset = 0x0;
 892         unsigned int size = sizeof(spu_save_code);
 893         unsigned int tag = 0;
 894         unsigned int rclass = 0;
 895         unsigned int cmd = MFC_GETFS_CMD;
 896
 897         /* Save, Step 54:
 898          *     Issue a DMA command to copy context save code
 899          *     to local storage and start SPU.
 900          */
 901         send_mfc_dma(spu, addr, ls_offset, size, tag, rclass, cmd);
 902 }
 903
 904 static inline void set_ppu_querymask(struct spu_state *csa, struct spu *spu)
 905 {
 906         struct spu_problem __iomem *prob = spu->problem;
 907
 908         /* Save, Step 55:
 909          * Restore, Step 38.
 910          *     Write PPU_QueryMask=1 (enable Tag Group 0)
 911          *     and issue eieio instruction.
 912          */
 913         out_be32(&prob->dma_querymask_RW, MFC_TAGID_TO_TAGMASK(0));
 914         eieio();
 915 }
 916
 917 static inline void wait_tag_complete(struct spu_state *csa, struct spu *spu)
 918 {
 919         struct spu_problem __iomem *prob = spu->problem;
 920         u32 mask = MFC_TAGID_TO_TAGMASK(0);
 921         unsigned long flags;
 922
 923         /* Save, Step 56:
 924          * Restore, Step 39.
 925          * Restore, Step 39.
 926          * Restore, Step 46.
 927          *     Poll PPU_TagStatus[gn] until 01 (Tag group 0 complete)
 928          *     or write PPU_QueryType[TS]=01 and wait for Tag Group
 929          *     Complete Interrupt.  Write INT_Stat_Class0 or
 930          *     INT_Stat_Class2 with value of 'handled'.
 931          */
 932         POLL_WHILE_FALSE(in_be32(&prob->dma_tagstatus_R) & mask);
 933
 934         local_irq_save(flags);
 935         spu_int_stat_clear(spu, 0, ~(0ul));
 936         spu_int_stat_clear(spu, 2, ~(0ul));
 937         local_irq_restore(flags);
 938 }
 939
 940 static inline void wait_spu_stopped(struct spu_state *csa, struct spu *spu)
 941 {
 942         struct spu_problem __iomem *prob = spu->problem;
 943         unsigned long flags;
 944
 945         /* Save, Step 57:
 946          * Restore, Step 40.
 947          *     Poll until SPU_Status[R]=0 or wait for SPU Class 0
 948          *     or SPU Class 2 interrupt.  Write INT_Stat_class0
 949          *     or INT_Stat_class2 with value of handled.
 950          */
 951         POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING);
 952
 953         local_irq_save(flags);
 954         spu_int_stat_clear(spu, 0, ~(0ul));
 955         spu_int_stat_clear(spu, 2, ~(0ul));
 956         local_irq_restore(flags);
 957 }
 958
 959 static inline int check_save_status(struct spu_state *csa, struct spu *spu)
 960 {
 961         struct spu_problem __iomem *prob = spu->problem;
 962         u32 complete;
 963
 964         /* Save, Step 54:
 965          *     If SPU_Status[P]=1 and SPU_Status[SC] = "success",
 966          *     context save succeeded, otherwise context save
 967          *     failed.
 968          */
 969         complete = ((SPU_SAVE_COMPLETE << SPU_STOP_STATUS_SHIFT) |
 970                     SPU_STATUS_STOPPED_BY_STOP);
 971         return (in_be32(&prob->spu_status_R) != complete) ? 1 : 0;
 972 }
 973
 974 static inline void terminate_spu_app(struct spu_state *csa, struct spu *spu)
 975 {
 976         /* Restore, Step 4:
 977          *    If required, notify the "using application" that
 978          *    the SPU task has been terminated.  TBD.
 979          */
 980 }
 981
 982 static inline void suspend_mfc(struct spu_state *csa, struct spu *spu)
 983 {
 984         struct spu_priv2 __iomem *priv2 = spu->priv2;
 985
 986         /* Restore, Step 7:
 987          * Restore, Step 47.
 988          *     Write MFC_Cntl[Dh,Sc]='1','1' to suspend
 989          *     the queue and halt the decrementer.
 990          */
 991         out_be64(&priv2->mfc_control_RW, MFC_CNTL_SUSPEND_DMA_QUEUE |
 992                  MFC_CNTL_DECREMENTER_HALTED);
 993         eieio();
 994 }
 995
 996 static inline void wait_suspend_mfc_complete(struct spu_state *csa,
 997                                              struct spu *spu)
 998 {
 999         struct spu_priv2 __iomem *priv2 = spu->priv2;
1000
1001         /* Restore, Step 8:
1002          * Restore, Step 47.
1003          *     Poll MFC_CNTL[Ss] until 11 is returned.
1004          */
1005         POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &
1006                          MFC_CNTL_SUSPEND_DMA_STATUS_MASK) ==
1007                          MFC_CNTL_SUSPEND_COMPLETE);
1008 }
1009
1010 static inline int suspend_spe(struct spu_state *csa, struct spu *spu)
1011 {
1012         struct spu_problem __iomem *prob = spu->problem;
1013
1014         /* Restore, Step 9:
1015          *    If SPU_Status[R]=1, stop SPU execution
1016          *    and wait for stop to complete.
1017          *
1018          *    Returns       1 if SPU_Status[R]=1 on entry.
1019          *                  0 otherwise
1020          */
1021         if (in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING) {
1022                 if (in_be32(&prob->spu_status_R) &
1023                     SPU_STATUS_ISOLATED_EXIT_STATUS) {
1024                         POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1025                                         SPU_STATUS_RUNNING);
1026                 }
1027                 if ((in_be32(&prob->spu_status_R) &
1028                      SPU_STATUS_ISOLATED_LOAD_STATUS)
1029                     || (in_be32(&prob->spu_status_R) &
1030                         SPU_STATUS_ISOLATED_STATE)) {
1031                         out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_STOP);
1032                         eieio();
1033                         POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1034                                         SPU_STATUS_RUNNING);
1035                         out_be32(&prob->spu_runcntl_RW, 0x2);
1036                         eieio();
1037                         POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1038                                         SPU_STATUS_RUNNING);
1039                 }
1040                 if (in_be32(&prob->spu_status_R) &
1041                     SPU_STATUS_WAITING_FOR_CHANNEL) {
1042                         out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_STOP);
1043                         eieio();
1044                         POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1045                                         SPU_STATUS_RUNNING);
1046                 }
1047                 return 1;
1048         }
1049         return 0;
1050 }
1051
1052 static inline void clear_spu_status(struct spu_state *csa, struct spu *spu)
1053 {
1054         struct spu_problem __iomem *prob = spu->problem;
1055
1056         /* Restore, Step 10:
1057          *    If SPU_Status[R]=0 and SPU_Status[E,L,IS]=1,
1058          *    release SPU from isolate state.
1059          */
1060         if (!(in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING)) {
1061                 if (in_be32(&prob->spu_status_R) &
1062                     SPU_STATUS_ISOLATED_EXIT_STATUS) {
1063                         spu_mfc_sr1_set(spu,
1064                                         MFC_STATE1_MASTER_RUN_CONTROL_MASK);
1065                         eieio();
1066                         out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_RUNNABLE);
1067                         eieio();
1068                         POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1069                                         SPU_STATUS_RUNNING);
1070                 }
1071                 if ((in_be32(&prob->spu_status_R) &
1072                      SPU_STATUS_ISOLATED_LOAD_STATUS)
1073                     || (in_be32(&prob->spu_status_R) &
1074                         SPU_STATUS_ISOLATED_STATE)) {
1075                         spu_mfc_sr1_set(spu,
1076                                         MFC_STATE1_MASTER_RUN_CONTROL_MASK);
1077                         eieio();
1078                         out_be32(&prob->spu_runcntl_RW, 0x2);
1079                         eieio();
1080                         POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1081                                         SPU_STATUS_RUNNING);
1082                 }
1083         }
1084 }
1085
1086 static inline void reset_ch_part1(struct spu_state *csa, struct spu *spu)
1087 {
1088         struct spu_priv2 __iomem *priv2 = spu->priv2;
1089         u64 ch_indices[] = { 0UL, 3UL, 4UL, 24UL, 25UL, 27UL };
1090         u64 idx;
1091         int i;
1092
1093         /* Restore, Step 20:
1094          */
1095
1096         /* Reset CH 1 */
1097         out_be64(&priv2->spu_chnlcntptr_RW, 1);
1098         out_be64(&priv2->spu_chnldata_RW, 0UL);
1099
1100         /* Reset the following CH: [0,3,4,24,25,27] */
1101         for (i = 0; i < ARRAY_SIZE(ch_indices); i++) {
1102                 idx = ch_indices[i];
1103                 out_be64(&priv2->spu_chnlcntptr_RW, idx);
1104                 eieio();
1105                 out_be64(&priv2->spu_chnldata_RW, 0UL);
1106                 out_be64(&priv2->spu_chnlcnt_RW, 0UL);
1107                 eieio();
1108         }
1109 }
1110
1111 static inline void reset_ch_part2(struct spu_state *csa, struct spu *spu)
1112 {
1113         struct spu_priv2 __iomem *priv2 = spu->priv2;
1114         u64 ch_indices[5] = { 21UL, 23UL, 28UL, 29UL, 30UL };
1115         u64 ch_counts[5] = { 16UL, 1UL, 1UL, 0UL, 1UL };
1116         u64 idx;
1117         int i;
1118
1119         /* Restore, Step 21:
1120          *     Reset the following CH: [21, 23, 28, 29, 30]
1121          */
1122         for (i = 0; i < 5; i++) {
1123                 idx = ch_indices[i];
1124                 out_be64(&priv2->spu_chnlcntptr_RW, idx);
1125                 eieio();
1126                 out_be64(&priv2->spu_chnlcnt_RW, ch_counts[i]);
1127                 eieio();
1128         }
1129 }
1130
1131 static inline void setup_spu_status_part1(struct spu_state *csa,
1132                                           struct spu *spu)
1133 {
1134         u32 status_P = SPU_STATUS_STOPPED_BY_STOP;
1135         u32 status_I = SPU_STATUS_INVALID_INSTR;
1136         u32 status_H = SPU_STATUS_STOPPED_BY_HALT;
1137         u32 status_S = SPU_STATUS_SINGLE_STEP;
1138         u32 status_S_I = SPU_STATUS_SINGLE_STEP | SPU_STATUS_INVALID_INSTR;
1139         u32 status_S_P = SPU_STATUS_SINGLE_STEP | SPU_STATUS_STOPPED_BY_STOP;
1140         u32 status_P_H = SPU_STATUS_STOPPED_BY_HALT |SPU_STATUS_STOPPED_BY_STOP;
1141         u32 status_P_I = SPU_STATUS_STOPPED_BY_STOP |SPU_STATUS_INVALID_INSTR;
1142         u32 status_code;
1143
1144         /* Restore, Step 27:
1145          *     If the CSA.SPU_Status[I,S,H,P]=1 then add the correct
1146          *     instruction sequence to the end of the SPU based restore
1147          *     code (after the "context restored" stop and signal) to
1148          *     restore the correct SPU status.
1149          *
1150          *     NOTE: Rather than modifying the SPU executable, we
1151          *     instead add a new 'stopped_status' field to the
1152          *     LSCSA.  The SPU-side restore reads this field and
1153          *     takes the appropriate action when exiting.
1154          */
1155
1156         status_code =
1157             (csa->prob.spu_status_R >> SPU_STOP_STATUS_SHIFT) & 0xFFFF;
1158         if ((csa->prob.spu_status_R & status_P_I) == status_P_I) {
1159
1160                 /* SPU_Status[P,I]=1 - Illegal Instruction followed
1161                  * by Stop and Signal instruction, followed by 'br -4'.
1162                  *
1163                  */
1164                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_P_I;
1165                 csa->lscsa->stopped_status.slot[1] = status_code;
1166
1167         } else if ((csa->prob.spu_status_R & status_P_H) == status_P_H) {
1168
1169                 /* SPU_Status[P,H]=1 - Halt Conditional, followed
1170                  * by Stop and Signal instruction, followed by
1171                  * 'br -4'.
1172                  */
1173                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_P_H;
1174                 csa->lscsa->stopped_status.slot[1] = status_code;
1175
1176         } else if ((csa->prob.spu_status_R & status_S_P) == status_S_P) {
1177
1178                 /* SPU_Status[S,P]=1 - Stop and Signal instruction
1179                  * followed by 'br -4'.
1180                  */
1181                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_S_P;
1182                 csa->lscsa->stopped_status.slot[1] = status_code;
1183
1184         } else if ((csa->prob.spu_status_R & status_S_I) == status_S_I) {
1185
1186                 /* SPU_Status[S,I]=1 - Illegal instruction followed
1187                  * by 'br -4'.
1188                  */
1189                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_S_I;
1190                 csa->lscsa->stopped_status.slot[1] = status_code;
1191
1192         } else if ((csa->prob.spu_status_R & status_P) == status_P) {
1193
1194                 /* SPU_Status[P]=1 - Stop and Signal instruction
1195                  * followed by 'br -4'.
1196                  */
1197                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_P;
1198                 csa->lscsa->stopped_status.slot[1] = status_code;
1199
1200         } else if ((csa->prob.spu_status_R & status_H) == status_H) {
1201
1202                 /* SPU_Status[H]=1 - Halt Conditional, followed
1203                  * by 'br -4'.
1204                  */
1205                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_H;
1206
1207         } else if ((csa->prob.spu_status_R & status_S) == status_S) {
1208
1209                 /* SPU_Status[S]=1 - Two nop instructions.
1210                  */
1211                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_S;
1212
1213         } else if ((csa->prob.spu_status_R & status_I) == status_I) {
1214
1215                 /* SPU_Status[I]=1 - Illegal instruction followed
1216                  * by 'br -4'.
1217                  */
1218                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_I;
1219
1220         }
1221 }
1222
1223 static inline void setup_spu_status_part2(struct spu_state *csa,
1224                                           struct spu *spu)
1225 {
1226         u32 mask;
1227
1228         /* Restore, Step 28:
1229          *     If the CSA.SPU_Status[I,S,H,P,R]=0 then
1230          *     add a 'br *' instruction to the end of
1231          *     the SPU based restore code.
1232          *
1233          *     NOTE: Rather than modifying the SPU executable, we
1234          *     instead add a new 'stopped_status' field to the
1235          *     LSCSA.  The SPU-side restore reads this field and
1236          *     takes the appropriate action when exiting.
1237          */
1238         mask = SPU_STATUS_INVALID_INSTR |
1239             SPU_STATUS_SINGLE_STEP |
1240             SPU_STATUS_STOPPED_BY_HALT |
1241             SPU_STATUS_STOPPED_BY_STOP | SPU_STATUS_RUNNING;
1242         if (!(csa->prob.spu_status_R & mask)) {
1243                 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_R;
1244         }
1245 }
1246
1247 static inline void restore_mfc_rag(struct spu_state *csa, struct spu *spu)
1248 {
1249         /* Restore, Step 29:
1250          *     Restore RA_GROUP_ID register and the
1251          *     RA_ENABLE reigster from the CSA.
1252          */
1253         spu_resource_allocation_groupID_set(spu,
1254                         csa->priv1.resource_allocation_groupID_RW);
1255         spu_resource_allocation_enable_set(spu,
1256                         csa->priv1.resource_allocation_enable_RW);
1257 }
1258
1259 static inline void send_restore_code(struct spu_state *csa, struct spu *spu)
1260 {
1261         unsigned long addr = (unsigned long)&spu_restore_code[0];
1262         unsigned int ls_offset = 0x0;
1263         unsigned int size = sizeof(spu_restore_code);
1264         unsigned int tag = 0;
1265         unsigned int rclass = 0;
1266         unsigned int cmd = MFC_GETFS_CMD;
1267
1268         /* Restore, Step 37:
1269          *     Issue MFC DMA command to copy context
1270          *     restore code to local storage.
1271          */
1272         send_mfc_dma(spu, addr, ls_offset, size, tag, rclass, cmd);
1273 }
1274
1275 static inline void setup_decr(struct spu_state *csa, struct spu *spu)
1276 {
1277         /* Restore, Step 34:
1278          *     If CSA.MFC_CNTL[Ds]=1 (decrementer was
1279          *     running) then adjust decrementer, set
1280          *     decrementer running status in LSCSA,
1281          *     and set decrementer "wrapped" status
1282          *     in LSCSA.
1283          */
1284         if (csa->priv2.mfc_control_RW & MFC_CNTL_DECREMENTER_RUNNING) {
1285                 cycles_t resume_time = get_cycles();
1286                 cycles_t delta_time = resume_time - csa->suspend_time;
1287
1288                 csa->lscsa->decr.slot[0] -= delta_time;
1289         }
1290 }
1291
1292 static inline void setup_ppu_mb(struct spu_state *csa, struct spu *spu)
1293 {
1294         /* Restore, Step 35:
1295          *     Copy the CSA.PU_MB data into the LSCSA.
1296          */
1297         csa->lscsa->ppu_mb.slot[0] = csa->prob.pu_mb_R;
1298 }
1299
1300 static inline void setup_ppuint_mb(struct spu_state *csa, struct spu *spu)
1301 {
1302         /* Restore, Step 36:
1303          *     Copy the CSA.PUINT_MB data into the LSCSA.
1304          */
1305         csa->lscsa->ppuint_mb.slot[0] = csa->priv2.puint_mb_R;
1306 }
1307
1308 static inline int check_restore_status(struct spu_state *csa, struct spu *spu)
1309 {
1310         struct spu_problem __iomem *prob = spu->problem;
1311         u32 complete;
1312
1313         /* Restore, Step 40:
1314          *     If SPU_Status[P]=1 and SPU_Status[SC] = "success",
1315          *     context restore succeeded, otherwise context restore
1316          *     failed.
1317          */
1318         complete = ((SPU_RESTORE_COMPLETE << SPU_STOP_STATUS_SHIFT) |
1319                     SPU_STATUS_STOPPED_BY_STOP);
1320         return (in_be32(&prob->spu_status_R) != complete) ? 1 : 0;
1321 }
1322
1323 static inline void restore_spu_privcntl(struct spu_state *csa, struct spu *spu)
1324 {
1325         struct spu_priv2 __iomem *priv2 = spu->priv2;
1326
1327         /* Restore, Step 41:
1328          *     Restore SPU_PrivCntl from the CSA.
1329          */
1330         out_be64(&priv2->spu_privcntl_RW, csa->priv2.spu_privcntl_RW);
1331         eieio();
1332 }
1333
1334 static inline void restore_status_part1(struct spu_state *csa, struct spu *spu)
1335 {
1336         struct spu_problem __iomem *prob = spu->problem;
1337         u32 mask;
1338
1339         /* Restore, Step 42:
1340          *     If any CSA.SPU_Status[I,S,H,P]=1, then
1341          *     restore the error or single step state.
1342          */
1343         mask = SPU_STATUS_INVALID_INSTR |
1344             SPU_STATUS_SINGLE_STEP |
1345             SPU_STATUS_STOPPED_BY_HALT | SPU_STATUS_STOPPED_BY_STOP;
1346         if (csa->prob.spu_status_R & mask) {
1347                 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_RUNNABLE);
1348                 eieio();
1349                 POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1350                                 SPU_STATUS_RUNNING);
1351         }
1352 }
1353
1354 static inline void restore_status_part2(struct spu_state *csa, struct spu *spu)
1355 {
1356         struct spu_problem __iomem *prob = spu->problem;
1357         u32 mask;
1358
1359         /* Restore, Step 43:
1360          *     If all CSA.SPU_Status[I,S,H,P,R]=0 then write
1361          *     SPU_RunCntl[R0R1]='01', wait for SPU_Status[R]=1,
1362          *     then write '00' to SPU_RunCntl[R0R1] and wait
1363          *     for SPU_Status[R]=0.
1364          */
1365         mask = SPU_STATUS_INVALID_INSTR |
1366             SPU_STATUS_SINGLE_STEP |
1367             SPU_STATUS_STOPPED_BY_HALT |
1368             SPU_STATUS_STOPPED_BY_STOP | SPU_STATUS_RUNNING;
1369         if (!(csa->prob.spu_status_R & mask)) {
1370                 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_RUNNABLE);
1371                 eieio();
1372                 POLL_WHILE_FALSE(in_be32(&prob->spu_status_R) &
1373                                  SPU_STATUS_RUNNING);
1374                 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_STOP);
1375                 eieio();
1376                 POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1377                                 SPU_STATUS_RUNNING);
1378         }
1379 }
1380
1381 static inline void restore_ls_16kb(struct spu_state *csa, struct spu *spu)
1382 {
1383         unsigned long addr = (unsigned long)&csa->lscsa->ls[0];
1384         unsigned int ls_offset = 0x0;
1385         unsigned int size = 16384;
1386         unsigned int tag = 0;
1387         unsigned int rclass = 0;
1388         unsigned int cmd = MFC_GET_CMD;
1389
1390         /* Restore, Step 44:
1391          *     Issue a DMA command to restore the first
1392          *     16kb of local storage from CSA.
1393          */
1394         send_mfc_dma(spu, addr, ls_offset, size, tag, rclass, cmd);
1395 }
1396
1397 static inline void clear_interrupts(struct spu_state *csa, struct spu *spu)
1398 {
1399         /* Restore, Step 49:
1400          *     Write INT_MASK_class0 with value of 0.
1401          *     Write INT_MASK_class1 with value of 0.
1402          *     Write INT_MASK_class2 with value of 0.
1403          *     Write INT_STAT_class0 with value of -1.
1404          *     Write INT_STAT_class1 with value of -1.
1405          *     Write INT_STAT_class2 with value of -1.
1406          */
1407         spin_lock_irq(&spu->register_lock);
1408         spu_int_mask_set(spu, 0, 0ul);
1409         spu_int_mask_set(spu, 1, 0ul);
1410         spu_int_mask_set(spu, 2, 0ul);
1411         spu_int_stat_clear(spu, 0, ~0ul);
1412         spu_int_stat_clear(spu, 1, ~0ul);
1413         spu_int_stat_clear(spu, 2, ~0ul);
1414         spin_unlock_irq(&spu->register_lock);
1415 }
1416
1417 static inline void restore_mfc_queues(struct spu_state *csa, struct spu *spu)
1418 {
1419         struct spu_priv2 __iomem *priv2 = spu->priv2;
1420         int i;
1421
1422         /* Restore, Step 50:
1423          *     If MFC_Cntl[Se]!=0 then restore
1424          *     MFC command queues.
1425          */
1426         if ((csa->priv2.mfc_control_RW & MFC_CNTL_DMA_QUEUES_EMPTY_MASK) == 0) {
1427                 for (i = 0; i < 8; i++) {
1428                         out_be64(&priv2->puq[i].mfc_cq_data0_RW,
1429                                  csa->priv2.puq[i].mfc_cq_data0_RW);
1430                         out_be64(&priv2->puq[i].mfc_cq_data1_RW,
1431                                  csa->priv2.puq[i].mfc_cq_data1_RW);
1432                         out_be64(&priv2->puq[i].mfc_cq_data2_RW,
1433                                  csa->priv2.puq[i].mfc_cq_data2_RW);
1434                         out_be64(&priv2->puq[i].mfc_cq_data3_RW,
1435                                  csa->priv2.puq[i].mfc_cq_data3_RW);
1436                 }
1437                 for (i = 0; i < 16; i++) {
1438                         out_be64(&priv2->spuq[i].mfc_cq_data0_RW,
1439                                  csa->priv2.spuq[i].mfc_cq_data0_RW);
1440                         out_be64(&priv2->spuq[i].mfc_cq_data1_RW,
1441                                  csa->priv2.spuq[i].mfc_cq_data1_RW);
1442                         out_be64(&priv2->spuq[i].mfc_cq_data2_RW,
1443                                  csa->priv2.spuq[i].mfc_cq_data2_RW);
1444                         out_be64(&priv2->spuq[i].mfc_cq_data3_RW,
1445                                  csa->priv2.spuq[i].mfc_cq_data3_RW);
1446                 }
1447         }
1448         eieio();
1449 }
1450
1451 static inline void restore_ppu_querymask(struct spu_state *csa, struct spu *spu)
1452 {
1453         struct spu_problem __iomem *prob = spu->problem;
1454
1455         /* Restore, Step 51:
1456          *     Restore the PPU_QueryMask register from CSA.
1457          */
1458         out_be32(&prob->dma_querymask_RW, csa->prob.dma_querymask_RW);
1459         eieio();
1460 }
1461
1462 static inline void restore_ppu_querytype(struct spu_state *csa, struct spu *spu)
1463 {
1464         struct spu_problem __iomem *prob = spu->problem;
1465
1466         /* Restore, Step 52:
1467          *     Restore the PPU_QueryType register from CSA.
1468          */
1469         out_be32(&prob->dma_querytype_RW, csa->prob.dma_querytype_RW);
1470         eieio();
1471 }
1472
1473 static inline void restore_mfc_csr_tsq(struct spu_state *csa, struct spu *spu)
1474 {
1475         struct spu_priv2 __iomem *priv2 = spu->priv2;
1476
1477         /* Restore, Step 53:
1478          *     Restore the MFC_CSR_TSQ register from CSA.
1479          */
1480         out_be64(&priv2->spu_tag_status_query_RW,
1481                  csa->priv2.spu_tag_status_query_RW);
1482         eieio();
1483 }
1484
1485 static inline void restore_mfc_csr_cmd(struct spu_state *csa, struct spu *spu)
1486 {
1487         struct spu_priv2 __iomem *priv2 = spu->priv2;
1488
1489         /* Restore, Step 54:
1490          *     Restore the MFC_CSR_CMD1 and MFC_CSR_CMD2
1491          *     registers from CSA.
1492          */
1493         out_be64(&priv2->spu_cmd_buf1_RW, csa->priv2.spu_cmd_buf1_RW);
1494         out_be64(&priv2->spu_cmd_buf2_RW, csa->priv2.spu_cmd_buf2_RW);
1495         eieio();
1496 }
1497
1498 static inline void restore_mfc_csr_ato(struct spu_state *csa, struct spu *spu)
1499 {
1500         struct spu_priv2 __iomem *priv2 = spu->priv2;
1501
1502         /* Restore, Step 55:
1503          *     Restore the MFC_CSR_ATO register from CSA.
1504          */
1505         out_be64(&priv2->spu_atomic_status_RW, csa->priv2.spu_atomic_status_RW);
1506 }
1507
1508 static inline void restore_mfc_tclass_id(struct spu_state *csa, struct spu *spu)
1509 {
1510         /* Restore, Step 56:
1511          *     Restore the MFC_TCLASS_ID register from CSA.
1512          */
1513         spu_mfc_tclass_id_set(spu, csa->priv1.mfc_tclass_id_RW);
1514         eieio();
1515 }
1516
1517 static inline void set_llr_event(struct spu_state *csa, struct spu *spu)
1518 {
1519         u64 ch0_cnt, ch0_data;
1520         u64 ch1_data;
1521
1522         /* Restore, Step 57:
1523          *    Set the Lock Line Reservation Lost Event by:
1524          *      1. OR CSA.SPU_Event_Status with bit 21 (Lr) set to 1.
1525          *      2. If CSA.SPU_Channel_0_Count=0 and
1526          *         CSA.SPU_Wr_Event_Mask[Lr]=1 and
1527          *         CSA.SPU_Event_Status[Lr]=0 then set
1528          *         CSA.SPU_Event_Status_Count=1.
1529          */
1530         ch0_cnt = csa->spu_chnlcnt_RW[0];
1531         ch0_data = csa->spu_chnldata_RW[0];
1532         ch1_data = csa->spu_chnldata_RW[1];
1533         csa->spu_chnldata_RW[0] |= MFC_LLR_LOST_EVENT;
1534         if ((ch0_cnt == 0) && !(ch0_data & MFC_LLR_LOST_EVENT) &&
1535             (ch1_data & MFC_LLR_LOST_EVENT)) {
1536                 csa->spu_chnlcnt_RW[0] = 1;
1537         }
1538 }
1539
1540 static inline void restore_decr_wrapped(struct spu_state *csa, struct spu *spu)
1541 {
1542         /* Restore, Step 58:
1543          *     If the status of the CSA software decrementer
1544          *     "wrapped" flag is set, OR in a '1' to
1545          *     CSA.SPU_Event_Status[Tm].
1546          */
1547         if (csa->lscsa->decr_status.slot[0] == 1) {
1548                 csa->spu_chnldata_RW[0] |= 0x20;
1549         }
1550         if ((csa->lscsa->decr_status.slot[0] == 1) &&
1551             (csa->spu_chnlcnt_RW[0] == 0 &&
1552              ((csa->spu_chnldata_RW[2] & 0x20) == 0x0) &&
1553              ((csa->spu_chnldata_RW[0] & 0x20) != 0x1))) {
1554                 csa->spu_chnlcnt_RW[0] = 1;
1555         }
1556 }
1557
1558 static inline void restore_ch_part1(struct spu_state *csa, struct spu *spu)
1559 {
1560         struct spu_priv2 __iomem *priv2 = spu->priv2;
1561         u64 idx, ch_indices[] = { 0UL, 3UL, 4UL, 24UL, 25UL, 27UL };
1562         int i;
1563
1564         /* Restore, Step 59:
1565          *      Restore the following CH: [0,3,4,24,25,27]
1566          */
1567         for (i = 0; i < ARRAY_SIZE(ch_indices); i++) {
1568                 idx = ch_indices[i];
1569                 out_be64(&priv2->spu_chnlcntptr_RW, idx);
1570                 eieio();
1571                 out_be64(&priv2->spu_chnldata_RW, csa->spu_chnldata_RW[idx]);
1572                 out_be64(&priv2->spu_chnlcnt_RW, csa->spu_chnlcnt_RW[idx]);
1573                 eieio();
1574         }
1575 }
1576
1577 static inline void restore_ch_part2(struct spu_state *csa, struct spu *spu)
1578 {
1579         struct spu_priv2 __iomem *priv2 = spu->priv2;
1580         u64 ch_indices[3] = { 9UL, 21UL, 23UL };
1581         u64 ch_counts[3] = { 1UL, 16UL, 1UL };
1582         u64 idx;
1583         int i;
1584
1585         /* Restore, Step 60:
1586          *     Restore the following CH: [9,21,23].
1587          */
1588         ch_counts[0] = 1UL;
1589         ch_counts[1] = csa->spu_chnlcnt_RW[21];
1590         ch_counts[2] = 1UL;
1591         for (i = 0; i < 3; i++) {
1592                 idx = ch_indices[i];
1593                 out_be64(&priv2->spu_chnlcntptr_RW, idx);
1594                 eieio();
1595                 out_be64(&priv2->spu_chnlcnt_RW, ch_counts[i]);
1596                 eieio();
1597         }
1598 }
1599
1600 static inline void restore_spu_lslr(struct spu_state *csa, struct spu *spu)
1601 {
1602         struct spu_priv2 __iomem *priv2 = spu->priv2;
1603
1604         /* Restore, Step 61:
1605          *     Restore the SPU_LSLR register from CSA.
1606          */
1607         out_be64(&priv2->spu_lslr_RW, csa->priv2.spu_lslr_RW);
1608         eieio();
1609 }
1610
1611 static inline void restore_spu_cfg(struct spu_state *csa, struct spu *spu)
1612 {
1613         struct spu_priv2 __iomem *priv2 = spu->priv2;
1614
1615         /* Restore, Step 62:
1616          *     Restore the SPU_Cfg register from CSA.
1617          */
1618         out_be64(&priv2->spu_cfg_RW, csa->priv2.spu_cfg_RW);
1619         eieio();
1620 }
1621
1622 static inline void restore_pm_trace(struct spu_state *csa, struct spu *spu)
1623 {
1624         /* Restore, Step 63:
1625          *     Restore PM_Trace_Tag_Wait_Mask from CSA.
1626          *     Not performed by this implementation.
1627          */
1628 }
1629
1630 static inline void restore_spu_npc(struct spu_state *csa, struct spu *spu)
1631 {
1632         struct spu_problem __iomem *prob = spu->problem;
1633
1634         /* Restore, Step 64:
1635          *     Restore SPU_NPC from CSA.
1636          */
1637         out_be32(&prob->spu_npc_RW, csa->prob.spu_npc_RW);
1638         eieio();
1639 }
1640
1641 static inline void restore_spu_mb(struct spu_state *csa, struct spu *spu)
1642 {
1643         struct spu_priv2 __iomem *priv2 = spu->priv2;
1644         int i;
1645
1646         /* Restore, Step 65:
1647          *     Restore MFC_RdSPU_MB from CSA.
1648          */
1649         out_be64(&priv2->spu_chnlcntptr_RW, 29UL);
1650         eieio();
1651         out_be64(&priv2->spu_chnlcnt_RW, csa->spu_chnlcnt_RW[29]);
1652         for (i = 0; i < 4; i++) {
1653                 out_be64(&priv2->spu_chnldata_RW, csa->spu_mailbox_data[i]);
1654         }
1655         eieio();
1656 }
1657
1658 static inline void check_ppu_mb_stat(struct spu_state *csa, struct spu *spu)
1659 {
1660         struct spu_problem __iomem *prob = spu->problem;
1661         u32 dummy = 0;
1662
1663         /* Restore, Step 66:
1664          *     If CSA.MB_Stat[P]=0 (mailbox empty) then
1665          *     read from the PPU_MB register.
1666          */
1667         if ((csa->prob.mb_stat_R & 0xFF) == 0) {
1668                 dummy = in_be32(&prob->pu_mb_R);
1669                 eieio();
1670         }
1671 }
1672
1673 static inline void check_ppuint_mb_stat(struct spu_state *csa, struct spu *spu)
1674 {
1675         struct spu_priv2 __iomem *priv2 = spu->priv2;
1676         u64 dummy = 0UL;
1677
1678         /* Restore, Step 66:
1679          *     If CSA.MB_Stat[I]=0 (mailbox empty) then
1680          *     read from the PPUINT_MB register.
1681          */
1682         if ((csa->prob.mb_stat_R & 0xFF0000) == 0) {
1683                 dummy = in_be64(&priv2->puint_mb_R);
1684                 eieio();
1685                 spu_int_stat_clear(spu, 2, CLASS2_ENABLE_MAILBOX_INTR);
1686                 eieio();
1687         }
1688 }
1689
1690 static inline void restore_mfc_sr1(struct spu_state *csa, struct spu *spu)
1691 {
1692         /* Restore, Step 69:
1693          *     Restore the MFC_SR1 register from CSA.
1694          */
1695         spu_mfc_sr1_set(spu, csa->priv1.mfc_sr1_RW);
1696         eieio();
1697 }
1698
1699 static inline void restore_other_spu_access(struct spu_state *csa,
1700                                             struct spu *spu)
1701 {
1702         /* Restore, Step 70:
1703          *     Restore other SPU mappings to this SPU. TBD.
1704          */
1705 }
1706
1707 static inline void restore_spu_runcntl(struct spu_state *csa, struct spu *spu)
1708 {
1709         struct spu_problem __iomem *prob = spu->problem;
1710
1711         /* Restore, Step 71:
1712          *     If CSA.SPU_Status[R]=1 then write
1713          *     SPU_RunCntl[R0R1]='01'.
1714          */
1715         if (csa->prob.spu_status_R & SPU_STATUS_RUNNING) {
1716                 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_RUNNABLE);
1717                 eieio();
1718         }
1719 }
1720
1721 static inline void restore_mfc_cntl(struct spu_state *csa, struct spu *spu)
1722 {
1723         struct spu_priv2 __iomem *priv2 = spu->priv2;
1724
1725         /* Restore, Step 72:
1726          *    Restore the MFC_CNTL register for the CSA.
1727          */
1728         out_be64(&priv2->mfc_control_RW, csa->priv2.mfc_control_RW);
1729         eieio();
1730         /*
1731          * FIXME: this is to restart a DMA that we were processing
1732          *        before the save. better remember the fault information
1733          *        in the csa instead.
1734          */
1735         if ((csa->priv2.mfc_control_RW & MFC_CNTL_SUSPEND_DMA_QUEUE_MASK)) {
1736                 out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESTART_DMA_COMMAND);
1737                 eieio();
1738         }
1739 }
1740
1741 static inline void enable_user_access(struct spu_state *csa, struct spu *spu)
1742 {
1743         /* Restore, Step 73:
1744          *     Enable user-space access (if provided) to this
1745          *     SPU by mapping the virtual pages assigned to
1746          *     the SPU memory-mapped I/O (MMIO) for problem
1747          *     state. TBD.
1748          */
1749 }
1750
1751 static inline void reset_switch_active(struct spu_state *csa, struct spu *spu)
1752 {
1753         /* Restore, Step 74:
1754          *     Reset the "context switch active" flag.
1755          */
1756         clear_bit(SPU_CONTEXT_SWITCH_ACTIVE, &spu->flags);
1757         mb();
1758 }
1759
1760 static inline void reenable_interrupts(struct spu_state *csa, struct spu *spu)
1761 {
1762         /* Restore, Step 75:
1763          *     Re-enable SPU interrupts.
1764          */
1765         spin_lock_irq(&spu->register_lock);
1766         spu_int_mask_set(spu, 0, csa->priv1.int_mask_class0_RW);
1767         spu_int_mask_set(spu, 1, csa->priv1.int_mask_class1_RW);
1768         spu_int_mask_set(spu, 2, csa->priv1.int_mask_class2_RW);
1769         spin_unlock_irq(&spu->register_lock);
1770 }
1771
1772 static int quiece_spu(struct spu_state *prev, struct spu *spu)
1773 {
1774         /*
1775          * Combined steps 2-18 of SPU context save sequence, which
1776          * quiesce the SPU state (disable SPU execution, MFC command
1777          * queues, decrementer, SPU interrupts, etc.).
1778          *
1779          * Returns      0 on success.
1780          *              2 if failed step 2.
1781          *              6 if failed step 6.
1782          */
1783
1784         if (check_spu_isolate(prev, spu)) {     /* Step 2. */
1785                 return 2;
1786         }
1787         disable_interrupts(prev, spu);          /* Step 3. */
1788         set_watchdog_timer(prev, spu);          /* Step 4. */
1789         inhibit_user_access(prev, spu);         /* Step 5. */
1790         if (check_spu_isolate(prev, spu)) {     /* Step 6. */
1791                 return 6;
1792         }
1793         set_switch_pending(prev, spu);          /* Step 7. */
1794         save_mfc_cntl(prev, spu);               /* Step 8. */
1795         save_spu_runcntl(prev, spu);            /* Step 9. */
1796         save_mfc_sr1(prev, spu);                /* Step 10. */
1797         save_spu_status(prev, spu);             /* Step 11. */
1798         save_mfc_decr(prev, spu);               /* Step 12. */
1799         halt_mfc_decr(prev, spu);               /* Step 13. */
1800         save_timebase(prev, spu);               /* Step 14. */
1801         remove_other_spu_access(prev, spu);     /* Step 15. */
1802         do_mfc_mssync(prev, spu);               /* Step 16. */
1803         issue_mfc_tlbie(prev, spu);             /* Step 17. */
1804         handle_pending_interrupts(prev, spu);   /* Step 18. */
1805
1806         return 0;
1807 }
1808
1809 static void save_csa(struct spu_state *prev, struct spu *spu)
1810 {
1811         /*
1812          * Combine steps 19-44 of SPU context save sequence, which
1813          * save regions of the privileged & problem state areas.
1814          */
1815
1816         save_mfc_queues(prev, spu);     /* Step 19. */
1817         save_ppu_querymask(prev, spu);  /* Step 20. */
1818         save_ppu_querytype(prev, spu);  /* Step 21. */
1819         save_ppu_tagstatus(prev, spu);  /* NEW.     */
1820         save_mfc_csr_tsq(prev, spu);    /* Step 22. */
1821         save_mfc_csr_cmd(prev, spu);    /* Step 23. */
1822         save_mfc_csr_ato(prev, spu);    /* Step 24. */
1823         save_mfc_tclass_id(prev, spu);  /* Step 25. */
1824         set_mfc_tclass_id(prev, spu);   /* Step 26. */
1825         purge_mfc_queue(prev, spu);     /* Step 27. */
1826         wait_purge_complete(prev, spu); /* Step 28. */
1827         setup_mfc_sr1(prev, spu);       /* Step 30. */
1828         save_spu_npc(prev, spu);        /* Step 31. */
1829         save_spu_privcntl(prev, spu);   /* Step 32. */
1830         reset_spu_privcntl(prev, spu);  /* Step 33. */
1831         save_spu_lslr(prev, spu);       /* Step 34. */
1832         reset_spu_lslr(prev, spu);      /* Step 35. */
1833         save_spu_cfg(prev, spu);        /* Step 36. */
1834         save_pm_trace(prev, spu);       /* Step 37. */
1835         save_mfc_rag(prev, spu);        /* Step 38. */
1836         save_ppu_mb_stat(prev, spu);    /* Step 39. */
1837         save_ppu_mb(prev, spu);         /* Step 40. */
1838         save_ppuint_mb(prev, spu);      /* Step 41. */
1839         save_ch_part1(prev, spu);       /* Step 42. */
1840         save_spu_mb(prev, spu);         /* Step 43. */
1841         save_mfc_cmd(prev, spu);        /* Step 44. */
1842         reset_ch(prev, spu);            /* Step 45. */
1843 }
1844
1845 static void save_lscsa(struct spu_state *prev, struct spu *spu)
1846 {
1847         /*
1848          * Perform steps 46-57 of SPU context save sequence,
1849          * which save regions of the local store and register
1850          * file.
1851          */
1852
1853         resume_mfc_queue(prev, spu);    /* Step 46. */
1854         setup_mfc_slbs(prev, spu);      /* Step 47. */
1855         set_switch_active(prev, spu);   /* Step 48. */
1856         enable_interrupts(prev, spu);   /* Step 49. */
1857         save_ls_16kb(prev, spu);        /* Step 50. */
1858         set_spu_npc(prev, spu);         /* Step 51. */
1859         set_signot1(prev, spu);         /* Step 52. */
1860         set_signot2(prev, spu);         /* Step 53. */
1861         send_save_code(prev, spu);      /* Step 54. */
1862         set_ppu_querymask(prev, spu);   /* Step 55. */
1863         wait_tag_complete(prev, spu);   /* Step 56. */
1864         wait_spu_stopped(prev, spu);    /* Step 57. */
1865 }
1866
1867 static void force_spu_isolate_exit(struct spu *spu)
1868 {
1869         struct spu_problem __iomem *prob = spu->problem;
1870         struct spu_priv2 __iomem *priv2 = spu->priv2;
1871
1872         /* Stop SPE execution and wait for completion. */
1873         out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_STOP);
1874         iobarrier_rw();
1875         POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING);
1876
1877         /* Restart SPE master runcntl. */
1878         spu_mfc_sr1_set(spu, MFC_STATE1_MASTER_RUN_CONTROL_MASK);
1879         iobarrier_w();
1880
1881         /* Initiate isolate exit request and wait for completion. */
1882         out_be64(&priv2->spu_privcntl_RW, 4LL);
1883         iobarrier_w();
1884         out_be32(&prob->spu_runcntl_RW, 2);
1885         iobarrier_rw();
1886         POLL_WHILE_FALSE((in_be32(&prob->spu_status_R)
1887                                 & SPU_STATUS_STOPPED_BY_STOP));
1888
1889         /* Reset load request to normal. */
1890         out_be64(&priv2->spu_privcntl_RW, SPU_PRIVCNT_LOAD_REQUEST_NORMAL);
1891         iobarrier_w();
1892 }
1893
1894 /**
1895  * stop_spu_isolate
1896  *      Check SPU run-control state and force isolated
1897  *      exit function as necessary.
1898  */
1899 static void stop_spu_isolate(struct spu *spu)
1900 {
1901         struct spu_problem __iomem *prob = spu->problem;
1902
1903         if (in_be32(&prob->spu_status_R) & SPU_STATUS_ISOLATED_STATE) {
1904                 /* The SPU is in isolated state; the only way
1905                  * to get it out is to perform an isolated
1906                  * exit (clean) operation.
1907                  */
1908                 force_spu_isolate_exit(spu);
1909         }
1910 }
1911
1912 static void harvest(struct spu_state *prev, struct spu *spu)
1913 {
1914         /*
1915          * Perform steps 2-25 of SPU context restore sequence,
1916          * which resets an SPU either after a failed save, or
1917          * when using SPU for first time.
1918          */
1919
1920         disable_interrupts(prev, spu);          /* Step 2.  */
1921         inhibit_user_access(prev, spu);         /* Step 3.  */
1922         terminate_spu_app(prev, spu);           /* Step 4.  */
1923         set_switch_pending(prev, spu);          /* Step 5.  */
1924         stop_spu_isolate(spu);                  /* NEW.     */
1925         remove_other_spu_access(prev, spu);     /* Step 6.  */
1926         suspend_mfc(prev, spu);                 /* Step 7.  */
1927         wait_suspend_mfc_complete(prev, spu);   /* Step 8.  */
1928         if (!suspend_spe(prev, spu))            /* Step 9.  */
1929                 clear_spu_status(prev, spu);    /* Step 10. */
1930         do_mfc_mssync(prev, spu);               /* Step 11. */
1931         issue_mfc_tlbie(prev, spu);             /* Step 12. */
1932         handle_pending_interrupts(prev, spu);   /* Step 13. */
1933         purge_mfc_queue(prev, spu);             /* Step 14. */
1934         wait_purge_complete(prev, spu);         /* Step 15. */
1935         reset_spu_privcntl(prev, spu);          /* Step 16. */
1936         reset_spu_lslr(prev, spu);              /* Step 17. */
1937         setup_mfc_sr1(prev, spu);               /* Step 18. */
1938         spu_invalidate_slbs(spu);               /* Step 19. */
1939         reset_ch_part1(prev, spu);              /* Step 20. */
1940         reset_ch_part2(prev, spu);              /* Step 21. */
1941         enable_interrupts(prev, spu);           /* Step 22. */
1942         set_switch_active(prev, spu);           /* Step 23. */
1943         set_mfc_tclass_id(prev, spu);           /* Step 24. */
1944         resume_mfc_queue(prev, spu);            /* Step 25. */
1945 }
1946
1947 static void restore_lscsa(struct spu_state *next, struct spu *spu)
1948 {
1949         /*
1950          * Perform steps 26-40 of SPU context restore sequence,
1951          * which restores regions of the local store and register
1952          * file.
1953          */
1954
1955         set_watchdog_timer(next, spu);          /* Step 26. */
1956         setup_spu_status_part1(next, spu);      /* Step 27. */
1957         setup_spu_status_part2(next, spu);      /* Step 28. */
1958         restore_mfc_rag(next, spu);             /* Step 29. */
1959         setup_mfc_slbs(next, spu);              /* Step 30. */
1960         set_spu_npc(next, spu);                 /* Step 31. */
1961         set_signot1(next, spu);                 /* Step 32. */
1962         set_signot2(next, spu);                 /* Step 33. */
1963         setup_decr(next, spu);                  /* Step 34. */
1964         setup_ppu_mb(next, spu);                /* Step 35. */
1965         setup_ppuint_mb(next, spu);             /* Step 36. */
1966         send_restore_code(next, spu);           /* Step 37. */
1967         set_ppu_querymask(next, spu);           /* Step 38. */
1968         wait_tag_complete(next, spu);           /* Step 39. */
1969         wait_spu_stopped(next, spu);            /* Step 40. */
1970 }
1971
1972 static void restore_csa(struct spu_state *next, struct spu *spu)
1973 {
1974         /*
1975          * Combine steps 41-76 of SPU context restore sequence, which
1976          * restore regions of the privileged & problem state areas.
1977          */
1978
1979         restore_spu_privcntl(next, spu);        /* Step 41. */
1980         restore_status_part1(next, spu);        /* Step 42. */
1981         restore_status_part2(next, spu);        /* Step 43. */
1982         restore_ls_16kb(next, spu);             /* Step 44. */
1983         wait_tag_complete(next, spu);           /* Step 45. */
1984         suspend_mfc(next, spu);                 /* Step 46. */
1985         wait_suspend_mfc_complete(next, spu);   /* Step 47. */
1986         issue_mfc_tlbie(next, spu);             /* Step 48. */
1987         clear_interrupts(next, spu);            /* Step 49. */
1988         restore_mfc_queues(next, spu);          /* Step 50. */
1989         restore_ppu_querymask(next, spu);       /* Step 51. */
1990         restore_ppu_querytype(next, spu);       /* Step 52. */
1991         restore_mfc_csr_tsq(next, spu);         /* Step 53. */
1992         restore_mfc_csr_cmd(next, spu);         /* Step 54. */
1993         restore_mfc_csr_ato(next, spu);         /* Step 55. */
1994         restore_mfc_tclass_id(next, spu);       /* Step 56. */
1995         set_llr_event(next, spu);               /* Step 57. */
1996         restore_decr_wrapped(next, spu);        /* Step 58. */
1997         restore_ch_part1(next, spu);            /* Step 59. */
1998         restore_ch_part2(next, spu);            /* Step 60. */
1999         restore_spu_lslr(next, spu);            /* Step 61. */
2000         restore_spu_cfg(next, spu);             /* Step 62. */
2001         restore_pm_trace(next, spu);            /* Step 63. */
2002         restore_spu_npc(next, spu);             /* Step 64. */
2003         restore_spu_mb(next, spu);              /* Step 65. */
2004         check_ppu_mb_stat(next, spu);           /* Step 66. */
2005         check_ppuint_mb_stat(next, spu);        /* Step 67. */
2006         spu_invalidate_slbs(spu);               /* Modified Step 68. */
2007         restore_mfc_sr1(next, spu);             /* Step 69. */
2008         restore_other_spu_access(next, spu);    /* Step 70. */
2009         restore_spu_runcntl(next, spu);         /* Step 71. */
2010         restore_mfc_cntl(next, spu);            /* Step 72. */
2011         enable_user_access(next, spu);          /* Step 73. */
2012         reset_switch_active(next, spu);         /* Step 74. */
2013         reenable_interrupts(next, spu);         /* Step 75. */
2014 }
2015
2016 static int __do_spu_save(struct spu_state *prev, struct spu *spu)
2017 {
2018         int rc;
2019
2020         /*
2021          * SPU context save can be broken into three phases:
2022          *
2023          *     (a) quiesce [steps 2-16].
2024          *     (b) save of CSA, performed by PPE [steps 17-42]
2025          *     (c) save of LSCSA, mostly performed by SPU [steps 43-52].
2026          *
2027          * Returns      0 on success.
2028          *              2,6 if failed to quiece SPU
2029          *              53 if SPU-side of save failed.
2030          */
2031
2032         rc = quiece_spu(prev, spu);             /* Steps 2-16. */
2033         switch (rc) {
2034         default:
2035         case 2:
2036         case 6:
2037                 harvest(prev, spu);
2038                 return rc;
2039                 break;
2040         case 0:
2041                 break;
2042         }
2043         save_csa(prev, spu);                    /* Steps 17-43. */
2044         save_lscsa(prev, spu);                  /* Steps 44-53. */
2045         return check_save_status(prev, spu);    /* Step 54.     */
2046 }
2047
2048 static int __do_spu_restore(struct spu_state *next, struct spu *spu)
2049 {
2050         int rc;
2051
2052         /*
2053          * SPU context restore can be broken into three phases:
2054          *
2055          *    (a) harvest (or reset) SPU [steps 2-24].
2056          *    (b) restore LSCSA [steps 25-40], mostly performed by SPU.
2057          *    (c) restore CSA [steps 41-76], performed by PPE.
2058          *
2059          * The 'harvest' step is not performed here, but rather
2060          * as needed below.
2061          */
2062
2063         restore_lscsa(next, spu);               /* Steps 24-39. */
2064         rc = check_restore_status(next, spu);   /* Step 40.     */
2065         switch (rc) {
2066         default:
2067                 /* Failed. Return now. */
2068                 return rc;
2069                 break;
2070         case 0:
2071                 /* Fall through to next step. */
2072                 break;
2073         }
2074         restore_csa(next, spu);
2075
2076         return 0;
2077 }
2078
2079 /**
2080  * spu_save - SPU context save, with locking.
2081  * @prev: pointer to SPU context save area, to be saved.
2082  * @spu: pointer to SPU iomem structure.
2083  *
2084  * Acquire locks, perform the save operation then return.
2085  */
2086 int spu_save(struct spu_state *prev, struct spu *spu)
2087 {
2088         int rc;
2089
2090         acquire_spu_lock(spu);          /* Step 1.     */
2091         prev->dar = spu->dar;
2092         prev->dsisr = spu->dsisr;
2093         spu->dar = 0;
2094         spu->dsisr = 0;
2095         rc = __do_spu_save(prev, spu);  /* Steps 2-53. */
2096         release_spu_lock(spu);
2097         if (rc != 0 && rc != 2 && rc != 6) {
2098                 panic("%s failed on SPU[%d], rc=%d.\n",
2099                       __func__, spu->number, rc);
2100         }
2101         return 0;
2102 }
2103 EXPORT_SYMBOL_GPL(spu_save);
2104
2105 /**
2106  * spu_restore - SPU context restore, with harvest and locking.
2107  * @new: pointer to SPU context save area, to be restored.
2108  * @spu: pointer to SPU iomem structure.
2109  *
2110  * Perform harvest + restore, as we may not be coming
2111  * from a previous successful save operation, and the
2112  * hardware state is unknown.
2113  */
2114 int spu_restore(struct spu_state *new, struct spu *spu)
2115 {
2116         int rc;
2117
2118         acquire_spu_lock(spu);
2119         harvest(NULL, spu);
2120         spu->slb_replace = 0;
2121         new->dar = 0;
2122         new->dsisr = 0;
2123         spu->class_0_pending = 0;
2124         rc = __do_spu_restore(new, spu);
2125         release_spu_lock(spu);
2126         if (rc) {
2127                 panic("%s failed on SPU[%d] rc=%d.\n",
2128                        __func__, spu->number, rc);
2129         }
2130         return rc;
2131 }
2132 EXPORT_SYMBOL_GPL(spu_restore);
2133
2134 /**
2135  * spu_harvest - SPU harvest (reset) operation
2136  * @spu: pointer to SPU iomem structure.
2137  *
2138  * Perform SPU harvest (reset) operation.
2139  */
2140 void spu_harvest(struct spu *spu)
2141 {
2142         acquire_spu_lock(spu);
2143         harvest(NULL, spu);
2144         release_spu_lock(spu);
2145 }
2146
2147 static void init_prob(struct spu_state *csa)
2148 {
2149         csa->spu_chnlcnt_RW[9] = 1;
2150         csa->spu_chnlcnt_RW[21] = 16;
2151         csa->spu_chnlcnt_RW[23] = 1;
2152         csa->spu_chnlcnt_RW[28] = 1;
2153         csa->spu_chnlcnt_RW[30] = 1;
2154         csa->prob.spu_runcntl_RW = SPU_RUNCNTL_STOP;
2155         csa->prob.mb_stat_R = 0x000400;
2156 }
2157
2158 static void init_priv1(struct spu_state *csa)
2159 {
2160         /* Enable decode, relocate, tlbie response, master runcntl. */
2161         csa->priv1.mfc_sr1_RW = MFC_STATE1_LOCAL_STORAGE_DECODE_MASK |
2162             MFC_STATE1_MASTER_RUN_CONTROL_MASK |
2163             MFC_STATE1_PROBLEM_STATE_MASK |
2164             MFC_STATE1_RELOCATE_MASK | MFC_STATE1_BUS_TLBIE_MASK;
2165
2166         /* Enable OS-specific set of interrupts. */
2167         csa->priv1.int_mask_class0_RW = CLASS0_ENABLE_DMA_ALIGNMENT_INTR |
2168             CLASS0_ENABLE_INVALID_DMA_COMMAND_INTR |
2169             CLASS0_ENABLE_SPU_ERROR_INTR;
2170         csa->priv1.int_mask_class1_RW = CLASS1_ENABLE_SEGMENT_FAULT_INTR |
2171             CLASS1_ENABLE_STORAGE_FAULT_INTR;
2172         csa->priv1.int_mask_class2_RW = CLASS2_ENABLE_SPU_STOP_INTR |
2173             CLASS2_ENABLE_SPU_HALT_INTR |
2174             CLASS2_ENABLE_SPU_DMA_TAG_GROUP_COMPLETE_INTR;
2175 }
2176
2177 static void init_priv2(struct spu_state *csa)
2178 {
2179         csa->priv2.spu_lslr_RW = LS_ADDR_MASK;
2180         csa->priv2.mfc_control_RW = MFC_CNTL_RESUME_DMA_QUEUE |
2181             MFC_CNTL_NORMAL_DMA_QUEUE_OPERATION |
2182             MFC_CNTL_DMA_QUEUES_EMPTY_MASK;
2183 }
2184
2185 /**
2186  * spu_alloc_csa - allocate and initialize an SPU context save area.
2187  *
2188  * Allocate and initialize the contents of an SPU context save area.
2189  * This includes enabling address translation, interrupt masks, etc.,
2190  * as appropriate for the given OS environment.
2191  *
2192  * Note that storage for the 'lscsa' is allocated separately,
2193  * as it is by far the largest of the context save regions,
2194  * and may need to be pinned or otherwise specially aligned.
2195  */
2196 int spu_init_csa(struct spu_state *csa)
2197 {
2198         int rc;
2199
2200         if (!csa)
2201                 return -EINVAL;
2202         memset(csa, 0, sizeof(struct spu_state));
2203
2204         rc = spu_alloc_lscsa(csa);
2205         if (rc)
2206                 return rc;
2207
2208         spin_lock_init(&csa->register_lock);
2209
2210         init_prob(csa);
2211         init_priv1(csa);
2212         init_priv2(csa);
2213
2214         return 0;
2215 }
2216 EXPORT_SYMBOL_GPL(spu_init_csa);
2217
2218 void spu_fini_csa(struct spu_state *csa)
2219 {
2220         spu_free_lscsa(csa);
2221 }
2222 EXPORT_SYMBOL_GPL(spu_fini_csa);