git.oblomov.eu Git - linux-2.6/blob - drivers/net/qlge/qlge_main.c

   1 /*
   2  * QLogic qlge NIC HBA Driver
   3  * Copyright (c)  2003-2008 QLogic Corporation
   4  * See LICENSE.qlge for copyright and licensing details.
   5  * Author:     Linux qlge network device driver by
   6  *                      Ron Mercer <ron.mercer@qlogic.com>
   7  */
   8 #include <linux/kernel.h>
   9 #include <linux/init.h>
  10 #include <linux/types.h>
  11 #include <linux/module.h>
  12 #include <linux/list.h>
  13 #include <linux/pci.h>
  14 #include <linux/dma-mapping.h>
  15 #include <linux/pagemap.h>
  16 #include <linux/sched.h>
  17 #include <linux/slab.h>
  18 #include <linux/dmapool.h>
  19 #include <linux/mempool.h>
  20 #include <linux/spinlock.h>
  21 #include <linux/kthread.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/errno.h>
  24 #include <linux/ioport.h>
  25 #include <linux/in.h>
  26 #include <linux/ip.h>
  27 #include <linux/ipv6.h>
  28 #include <net/ipv6.h>
  29 #include <linux/tcp.h>
  30 #include <linux/udp.h>
  31 #include <linux/if_arp.h>
  32 #include <linux/if_ether.h>
  33 #include <linux/netdevice.h>
  34 #include <linux/etherdevice.h>
  35 #include <linux/ethtool.h>
  36 #include <linux/skbuff.h>
  37 #include <linux/rtnetlink.h>
  38 #include <linux/if_vlan.h>
  39 #include <linux/delay.h>
  40 #include <linux/mm.h>
  41 #include <linux/vmalloc.h>
  42 #include <net/ip6_checksum.h>
  43
  44 #include "qlge.h"
  45
  46 char qlge_driver_name[] = DRV_NAME;
  47 const char qlge_driver_version[] = DRV_VERSION;
  48
  49 MODULE_AUTHOR("Ron Mercer <ron.mercer@qlogic.com>");
  50 MODULE_DESCRIPTION(DRV_STRING " ");
  51 MODULE_LICENSE("GPL");
  52 MODULE_VERSION(DRV_VERSION);
  53
  54 static const u32 default_msg =
  55     NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK |
  56 /* NETIF_MSG_TIMER |    */
  57     NETIF_MSG_IFDOWN |
  58     NETIF_MSG_IFUP |
  59     NETIF_MSG_RX_ERR |
  60     NETIF_MSG_TX_ERR |
  61 /*  NETIF_MSG_TX_QUEUED | */
  62 /*  NETIF_MSG_INTR | NETIF_MSG_TX_DONE | NETIF_MSG_RX_STATUS | */
  63 /* NETIF_MSG_PKTDATA | */
  64     NETIF_MSG_HW | NETIF_MSG_WOL | 0;
  65
  66 static int debug = 0x00007fff;  /* defaults above */
  67 module_param(debug, int, 0);
  68 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
  69
  70 #define MSIX_IRQ 0
  71 #define MSI_IRQ 1
  72 #define LEG_IRQ 2
  73 static int irq_type = MSIX_IRQ;
  74 module_param(irq_type, int, MSIX_IRQ);
  75 MODULE_PARM_DESC(irq_type, "0 = MSI-X, 1 = MSI, 2 = Legacy.");
  76
  77 static struct pci_device_id qlge_pci_tbl[] __devinitdata = {
  78         {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QLGE_DEVICE_ID_8012)},
  79         {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QLGE_DEVICE_ID_8000)},
  80         /* required last entry */
  81         {0,}
  82 };
  83
  84 MODULE_DEVICE_TABLE(pci, qlge_pci_tbl);
  85
  86 /* This hardware semaphore causes exclusive access to
  87  * resources shared between the NIC driver, MPI firmware,
  88  * FCOE firmware and the FC driver.
  89  */
  90 static int ql_sem_trylock(struct ql_adapter *qdev, u32 sem_mask)
  91 {
  92         u32 sem_bits = 0;
  93
  94         switch (sem_mask) {
  95         case SEM_XGMAC0_MASK:
  96                 sem_bits = SEM_SET << SEM_XGMAC0_SHIFT;
  97                 break;
  98         case SEM_XGMAC1_MASK:
  99                 sem_bits = SEM_SET << SEM_XGMAC1_SHIFT;
 100                 break;
 101         case SEM_ICB_MASK:
 102                 sem_bits = SEM_SET << SEM_ICB_SHIFT;
 103                 break;
 104         case SEM_MAC_ADDR_MASK:
 105                 sem_bits = SEM_SET << SEM_MAC_ADDR_SHIFT;
 106                 break;
 107         case SEM_FLASH_MASK:
 108                 sem_bits = SEM_SET << SEM_FLASH_SHIFT;
 109                 break;
 110         case SEM_PROBE_MASK:
 111                 sem_bits = SEM_SET << SEM_PROBE_SHIFT;
 112                 break;
 113         case SEM_RT_IDX_MASK:
 114                 sem_bits = SEM_SET << SEM_RT_IDX_SHIFT;
 115                 break;
 116         case SEM_PROC_REG_MASK:
 117                 sem_bits = SEM_SET << SEM_PROC_REG_SHIFT;
 118                 break;
 119         default:
 120                 QPRINTK(qdev, PROBE, ALERT, "Bad Semaphore mask!.\n");
 121                 return -EINVAL;
 122         }
 123
 124         ql_write32(qdev, SEM, sem_bits | sem_mask);
 125         return !(ql_read32(qdev, SEM) & sem_bits);
 126 }
 127
 128 int ql_sem_spinlock(struct ql_adapter *qdev, u32 sem_mask)
 129 {
 130         unsigned int wait_count = 30;
 131         do {
 132                 if (!ql_sem_trylock(qdev, sem_mask))
 133                         return 0;
 134                 udelay(100);
 135         } while (--wait_count);
 136         return -ETIMEDOUT;
 137 }
 138
 139 void ql_sem_unlock(struct ql_adapter *qdev, u32 sem_mask)
 140 {
 141         ql_write32(qdev, SEM, sem_mask);
 142         ql_read32(qdev, SEM);   /* flush */
 143 }
 144
 145 /* This function waits for a specific bit to come ready
 146  * in a given register.  It is used mostly by the initialize
 147  * process, but is also used in kernel thread API such as
 148  * netdev->set_multi, netdev->set_mac_address, netdev->vlan_rx_add_vid.
 149  */
 150 int ql_wait_reg_rdy(struct ql_adapter *qdev, u32 reg, u32 bit, u32 err_bit)
 151 {
 152         u32 temp;
 153         int count = UDELAY_COUNT;
 154
 155         while (count) {
 156                 temp = ql_read32(qdev, reg);
 157
 158                 /* check for errors */
 159                 if (temp & err_bit) {
 160                         QPRINTK(qdev, PROBE, ALERT,
 161                                 "register 0x%.08x access error, value = 0x%.08x!.\n",
 162                                 reg, temp);
 163                         return -EIO;
 164                 } else if (temp & bit)
 165                         return 0;
 166                 udelay(UDELAY_DELAY);
 167                 count--;
 168         }
 169         QPRINTK(qdev, PROBE, ALERT,
 170                 "Timed out waiting for reg %x to come ready.\n", reg);
 171         return -ETIMEDOUT;
 172 }
 173
 174 /* The CFG register is used to download TX and RX control blocks
 175  * to the chip. This function waits for an operation to complete.
 176  */
 177 static int ql_wait_cfg(struct ql_adapter *qdev, u32 bit)
 178 {
 179         int count = UDELAY_COUNT;
 180         u32 temp;
 181
 182         while (count) {
 183                 temp = ql_read32(qdev, CFG);
 184                 if (temp & CFG_LE)
 185                         return -EIO;
 186                 if (!(temp & bit))
 187                         return 0;
 188                 udelay(UDELAY_DELAY);
 189                 count--;
 190         }
 191         return -ETIMEDOUT;
 192 }
 193
 194
 195 /* Used to issue init control blocks to hw. Maps control block,
 196  * sets address, triggers download, waits for completion.
 197  */
 198 int ql_write_cfg(struct ql_adapter *qdev, void *ptr, int size, u32 bit,
 199                  u16 q_id)
 200 {
 201         u64 map;
 202         int status = 0;
 203         int direction;
 204         u32 mask;
 205         u32 value;
 206
 207         direction =
 208             (bit & (CFG_LRQ | CFG_LR | CFG_LCQ)) ? PCI_DMA_TODEVICE :
 209             PCI_DMA_FROMDEVICE;
 210
 211         map = pci_map_single(qdev->pdev, ptr, size, direction);
 212         if (pci_dma_mapping_error(qdev->pdev, map)) {
 213                 QPRINTK(qdev, IFUP, ERR, "Couldn't map DMA area.\n");
 214                 return -ENOMEM;
 215         }
 216
 217         status = ql_wait_cfg(qdev, bit);
 218         if (status) {
 219                 QPRINTK(qdev, IFUP, ERR,
 220                         "Timed out waiting for CFG to come ready.\n");
 221                 goto exit;
 222         }
 223
 224         status = ql_sem_spinlock(qdev, SEM_ICB_MASK);
 225         if (status)
 226                 goto exit;
 227         ql_write32(qdev, ICB_L, (u32) map);
 228         ql_write32(qdev, ICB_H, (u32) (map >> 32));
 229         ql_sem_unlock(qdev, SEM_ICB_MASK);      /* does flush too */
 230
 231         mask = CFG_Q_MASK | (bit << 16);
 232         value = bit | (q_id << CFG_Q_SHIFT);
 233         ql_write32(qdev, CFG, (mask | value));
 234
 235         /*
 236          * Wait for the bit to clear after signaling hw.
 237          */
 238         status = ql_wait_cfg(qdev, bit);
 239 exit:
 240         pci_unmap_single(qdev->pdev, map, size, direction);
 241         return status;
 242 }
 243
 244 /* Get a specific MAC address from the CAM.  Used for debug and reg dump. */
 245 int ql_get_mac_addr_reg(struct ql_adapter *qdev, u32 type, u16 index,
 246                         u32 *value)
 247 {
 248         u32 offset = 0;
 249         int status;
 250
 251         switch (type) {
 252         case MAC_ADDR_TYPE_MULTI_MAC:
 253         case MAC_ADDR_TYPE_CAM_MAC:
 254                 {
 255                         status =
 256                             ql_wait_reg_rdy(qdev,
 257                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 258                         if (status)
 259                                 goto exit;
 260                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
 261                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
 262                                    MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
 263                         status =
 264                             ql_wait_reg_rdy(qdev,
 265                                 MAC_ADDR_IDX, MAC_ADDR_MR, 0);
 266                         if (status)
 267                                 goto exit;
 268                         *value++ = ql_read32(qdev, MAC_ADDR_DATA);
 269                         status =
 270                             ql_wait_reg_rdy(qdev,
 271                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 272                         if (status)
 273                                 goto exit;
 274                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
 275                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
 276                                    MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
 277                         status =
 278                             ql_wait_reg_rdy(qdev,
 279                                 MAC_ADDR_IDX, MAC_ADDR_MR, 0);
 280                         if (status)
 281                                 goto exit;
 282                         *value++ = ql_read32(qdev, MAC_ADDR_DATA);
 283                         if (type == MAC_ADDR_TYPE_CAM_MAC) {
 284                                 status =
 285                                     ql_wait_reg_rdy(qdev,
 286                                         MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 287                                 if (status)
 288                                         goto exit;
 289                                 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
 290                                            (index << MAC_ADDR_IDX_SHIFT) | /* index */
 291                                            MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
 292                                 status =
 293                                     ql_wait_reg_rdy(qdev, MAC_ADDR_IDX,
 294                                                     MAC_ADDR_MR, 0);
 295                                 if (status)
 296                                         goto exit;
 297                                 *value++ = ql_read32(qdev, MAC_ADDR_DATA);
 298                         }
 299                         break;
 300                 }
 301         case MAC_ADDR_TYPE_VLAN:
 302         case MAC_ADDR_TYPE_MULTI_FLTR:
 303         default:
 304                 QPRINTK(qdev, IFUP, CRIT,
 305                         "Address type %d not yet supported.\n", type);
 306                 status = -EPERM;
 307         }
 308 exit:
 309         return status;
 310 }
 311
 312 /* Set up a MAC, multicast or VLAN address for the
 313  * inbound frame matching.
 314  */
 315 static int ql_set_mac_addr_reg(struct ql_adapter *qdev, u8 *addr, u32 type,
 316                                u16 index)
 317 {
 318         u32 offset = 0;
 319         int status = 0;
 320
 321         switch (type) {
 322         case MAC_ADDR_TYPE_MULTI_MAC:
 323         case MAC_ADDR_TYPE_CAM_MAC:
 324                 {
 325                         u32 cam_output;
 326                         u32 upper = (addr[0] << 8) | addr[1];
 327                         u32 lower =
 328                             (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) |
 329                             (addr[5]);
 330
 331                         QPRINTK(qdev, IFUP, DEBUG,
 332                                 "Adding %s address %pM"
 333                                 " at index %d in the CAM.\n",
 334                                 ((type ==
 335                                   MAC_ADDR_TYPE_MULTI_MAC) ? "MULTICAST" :
 336                                  "UNICAST"), addr, index);
 337
 338                         status =
 339                             ql_wait_reg_rdy(qdev,
 340                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 341                         if (status)
 342                                 goto exit;
 343                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
 344                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
 345                                    type);       /* type */
 346                         ql_write32(qdev, MAC_ADDR_DATA, lower);
 347                         status =
 348                             ql_wait_reg_rdy(qdev,
 349                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 350                         if (status)
 351                                 goto exit;
 352                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
 353                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
 354                                    type);       /* type */
 355                         ql_write32(qdev, MAC_ADDR_DATA, upper);
 356                         status =
 357                             ql_wait_reg_rdy(qdev,
 358                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 359                         if (status)
 360                                 goto exit;
 361                         ql_write32(qdev, MAC_ADDR_IDX, (offset) |       /* offset */
 362                                    (index << MAC_ADDR_IDX_SHIFT) |      /* index */
 363                                    type);       /* type */
 364                         /* This field should also include the queue id
 365                            and possibly the function id.  Right now we hardcode
 366                            the route field to NIC core.
 367                          */
 368                         if (type == MAC_ADDR_TYPE_CAM_MAC) {
 369                                 cam_output = (CAM_OUT_ROUTE_NIC |
 370                                               (qdev->
 371                                                func << CAM_OUT_FUNC_SHIFT) |
 372                                               (qdev->
 373                                                rss_ring_first_cq_id <<
 374                                                CAM_OUT_CQ_ID_SHIFT));
 375                                 if (qdev->vlgrp)
 376                                         cam_output |= CAM_OUT_RV;
 377                                 /* route to NIC core */
 378                                 ql_write32(qdev, MAC_ADDR_DATA, cam_output);
 379                         }
 380                         break;
 381                 }
 382         case MAC_ADDR_TYPE_VLAN:
 383                 {
 384                         u32 enable_bit = *((u32 *) &addr[0]);
 385                         /* For VLAN, the addr actually holds a bit that
 386                          * either enables or disables the vlan id we are
 387                          * addressing. It's either MAC_ADDR_E on or off.
 388                          * That's bit-27 we're talking about.
 389                          */
 390                         QPRINTK(qdev, IFUP, INFO, "%s VLAN ID %d %s the CAM.\n",
 391                                 (enable_bit ? "Adding" : "Removing"),
 392                                 index, (enable_bit ? "to" : "from"));
 393
 394                         status =
 395                             ql_wait_reg_rdy(qdev,
 396                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 397                         if (status)
 398                                 goto exit;
 399                         ql_write32(qdev, MAC_ADDR_IDX, offset | /* offset */
 400                                    (index << MAC_ADDR_IDX_SHIFT) |      /* index */
 401                                    type |       /* type */
 402                                    enable_bit); /* enable/disable */
 403                         break;
 404                 }
 405         case MAC_ADDR_TYPE_MULTI_FLTR:
 406         default:
 407                 QPRINTK(qdev, IFUP, CRIT,
 408                         "Address type %d not yet supported.\n", type);
 409                 status = -EPERM;
 410         }
 411 exit:
 412         return status;
 413 }
 414
 415 /* Get a specific frame routing value from the CAM.
 416  * Used for debug and reg dump.
 417  */
 418 int ql_get_routing_reg(struct ql_adapter *qdev, u32 index, u32 *value)
 419 {
 420         int status = 0;
 421
 422         status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, 0);
 423         if (status)
 424                 goto exit;
 425
 426         ql_write32(qdev, RT_IDX,
 427                    RT_IDX_TYPE_NICQ | RT_IDX_RS | (index << RT_IDX_IDX_SHIFT));
 428         status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MR, 0);
 429         if (status)
 430                 goto exit;
 431         *value = ql_read32(qdev, RT_DATA);
 432 exit:
 433         return status;
 434 }
 435
 436 /* The NIC function for this chip has 16 routing indexes.  Each one can be used
 437  * to route different frame types to various inbound queues.  We send broadcast/
 438  * multicast/error frames to the default queue for slow handling,
 439  * and CAM hit/RSS frames to the fast handling queues.
 440  */
 441 static int ql_set_routing_reg(struct ql_adapter *qdev, u32 index, u32 mask,
 442                               int enable)
 443 {
 444         int status = -EINVAL; /* Return error if no mask match. */
 445         u32 value = 0;
 446
 447         QPRINTK(qdev, IFUP, DEBUG,
 448                 "%s %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s mask %s the routing reg.\n",
 449                 (enable ? "Adding" : "Removing"),
 450                 ((index == RT_IDX_ALL_ERR_SLOT) ? "MAC ERROR/ALL ERROR" : ""),
 451                 ((index == RT_IDX_IP_CSUM_ERR_SLOT) ? "IP CSUM ERROR" : ""),
 452                 ((index ==
 453                   RT_IDX_TCP_UDP_CSUM_ERR_SLOT) ? "TCP/UDP CSUM ERROR" : ""),
 454                 ((index == RT_IDX_BCAST_SLOT) ? "BROADCAST" : ""),
 455                 ((index == RT_IDX_MCAST_MATCH_SLOT) ? "MULTICAST MATCH" : ""),
 456                 ((index == RT_IDX_ALLMULTI_SLOT) ? "ALL MULTICAST MATCH" : ""),
 457                 ((index == RT_IDX_UNUSED6_SLOT) ? "UNUSED6" : ""),
 458                 ((index == RT_IDX_UNUSED7_SLOT) ? "UNUSED7" : ""),
 459                 ((index == RT_IDX_RSS_MATCH_SLOT) ? "RSS ALL/IPV4 MATCH" : ""),
 460                 ((index == RT_IDX_RSS_IPV6_SLOT) ? "RSS IPV6" : ""),
 461                 ((index == RT_IDX_RSS_TCP4_SLOT) ? "RSS TCP4" : ""),
 462                 ((index == RT_IDX_RSS_TCP6_SLOT) ? "RSS TCP6" : ""),
 463                 ((index == RT_IDX_CAM_HIT_SLOT) ? "CAM HIT" : ""),
 464                 ((index == RT_IDX_UNUSED013) ? "UNUSED13" : ""),
 465                 ((index == RT_IDX_UNUSED014) ? "UNUSED14" : ""),
 466                 ((index == RT_IDX_PROMISCUOUS_SLOT) ? "PROMISCUOUS" : ""),
 467                 (enable ? "to" : "from"));
 468
 469         switch (mask) {
 470         case RT_IDX_CAM_HIT:
 471                 {
 472                         value = RT_IDX_DST_CAM_Q |      /* dest */
 473                             RT_IDX_TYPE_NICQ |  /* type */
 474                             (RT_IDX_CAM_HIT_SLOT << RT_IDX_IDX_SHIFT);/* index */
 475                         break;
 476                 }
 477         case RT_IDX_VALID:      /* Promiscuous Mode frames. */
 478                 {
 479                         value = RT_IDX_DST_DFLT_Q |     /* dest */
 480                             RT_IDX_TYPE_NICQ |  /* type */
 481                             (RT_IDX_PROMISCUOUS_SLOT << RT_IDX_IDX_SHIFT);/* index */
 482                         break;
 483                 }
 484         case RT_IDX_ERR:        /* Pass up MAC,IP,TCP/UDP error frames. */
 485                 {
 486                         value = RT_IDX_DST_DFLT_Q |     /* dest */
 487                             RT_IDX_TYPE_NICQ |  /* type */
 488                             (RT_IDX_ALL_ERR_SLOT << RT_IDX_IDX_SHIFT);/* index */
 489                         break;
 490                 }
 491         case RT_IDX_BCAST:      /* Pass up Broadcast frames to default Q. */
 492                 {
 493                         value = RT_IDX_DST_DFLT_Q |     /* dest */
 494                             RT_IDX_TYPE_NICQ |  /* type */
 495                             (RT_IDX_BCAST_SLOT << RT_IDX_IDX_SHIFT);/* index */
 496                         break;
 497                 }
 498         case RT_IDX_MCAST:      /* Pass up All Multicast frames. */
 499                 {
 500                         value = RT_IDX_DST_CAM_Q |      /* dest */
 501                             RT_IDX_TYPE_NICQ |  /* type */
 502                             (RT_IDX_ALLMULTI_SLOT << RT_IDX_IDX_SHIFT);/* index */
 503                         break;
 504                 }
 505         case RT_IDX_MCAST_MATCH:        /* Pass up matched Multicast frames. */
 506                 {
 507                         value = RT_IDX_DST_CAM_Q |      /* dest */
 508                             RT_IDX_TYPE_NICQ |  /* type */
 509                             (RT_IDX_MCAST_MATCH_SLOT << RT_IDX_IDX_SHIFT);/* index */
 510                         break;
 511                 }
 512         case RT_IDX_RSS_MATCH:  /* Pass up matched RSS frames. */
 513                 {
 514                         value = RT_IDX_DST_RSS |        /* dest */
 515                             RT_IDX_TYPE_NICQ |  /* type */
 516                             (RT_IDX_RSS_MATCH_SLOT << RT_IDX_IDX_SHIFT);/* index */
 517                         break;
 518                 }
 519         case 0:         /* Clear the E-bit on an entry. */
 520                 {
 521                         value = RT_IDX_DST_DFLT_Q |     /* dest */
 522                             RT_IDX_TYPE_NICQ |  /* type */
 523                             (index << RT_IDX_IDX_SHIFT);/* index */
 524                         break;
 525                 }
 526         default:
 527                 QPRINTK(qdev, IFUP, ERR, "Mask type %d not yet supported.\n",
 528                         mask);
 529                 status = -EPERM;
 530                 goto exit;
 531         }
 532
 533         if (value) {
 534                 status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, 0);
 535                 if (status)
 536                         goto exit;
 537                 value |= (enable ? RT_IDX_E : 0);
 538                 ql_write32(qdev, RT_IDX, value);
 539                 ql_write32(qdev, RT_DATA, enable ? mask : 0);
 540         }
 541 exit:
 542         return status;
 543 }
 544
 545 static void ql_enable_interrupts(struct ql_adapter *qdev)
 546 {
 547         ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16) | INTR_EN_EI);
 548 }
 549
 550 static void ql_disable_interrupts(struct ql_adapter *qdev)
 551 {
 552         ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16));
 553 }
 554
 555 /* If we're running with multiple MSI-X vectors then we enable on the fly.
 556  * Otherwise, we may have multiple outstanding workers and don't want to
 557  * enable until the last one finishes. In this case, the irq_cnt gets
 558  * incremented everytime we queue a worker and decremented everytime
 559  * a worker finishes.  Once it hits zero we enable the interrupt.
 560  */
 561 u32 ql_enable_completion_interrupt(struct ql_adapter *qdev, u32 intr)
 562 {
 563         u32 var = 0;
 564         unsigned long hw_flags = 0;
 565         struct intr_context *ctx = qdev->intr_context + intr;
 566
 567         if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags) && intr)) {
 568                 /* Always enable if we're MSIX multi interrupts and
 569                  * it's not the default (zeroeth) interrupt.
 570                  */
 571                 ql_write32(qdev, INTR_EN,
 572                            ctx->intr_en_mask);
 573                 var = ql_read32(qdev, STS);
 574                 return var;
 575         }
 576
 577         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
 578         if (atomic_dec_and_test(&ctx->irq_cnt)) {
 579                 ql_write32(qdev, INTR_EN,
 580                            ctx->intr_en_mask);
 581                 var = ql_read32(qdev, STS);
 582         }
 583         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
 584         return var;
 585 }
 586
 587 static u32 ql_disable_completion_interrupt(struct ql_adapter *qdev, u32 intr)
 588 {
 589         u32 var = 0;
 590         struct intr_context *ctx;
 591
 592         /* HW disables for us if we're MSIX multi interrupts and
 593          * it's not the default (zeroeth) interrupt.
 594          */
 595         if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags) && intr))
 596                 return 0;
 597
 598         ctx = qdev->intr_context + intr;
 599         spin_lock(&qdev->hw_lock);
 600         if (!atomic_read(&ctx->irq_cnt)) {
 601                 ql_write32(qdev, INTR_EN,
 602                 ctx->intr_dis_mask);
 603                 var = ql_read32(qdev, STS);
 604         }
 605         atomic_inc(&ctx->irq_cnt);
 606         spin_unlock(&qdev->hw_lock);
 607         return var;
 608 }
 609
 610 static void ql_enable_all_completion_interrupts(struct ql_adapter *qdev)
 611 {
 612         int i;
 613         for (i = 0; i < qdev->intr_count; i++) {
 614                 /* The enable call does a atomic_dec_and_test
 615                  * and enables only if the result is zero.
 616                  * So we precharge it here.
 617                  */
 618                 if (unlikely(!test_bit(QL_MSIX_ENABLED, &qdev->flags) ||
 619                         i == 0))
 620                         atomic_set(&qdev->intr_context[i].irq_cnt, 1);
 621                 ql_enable_completion_interrupt(qdev, i);
 622         }
 623
 624 }
 625
 626 static int ql_validate_flash(struct ql_adapter *qdev, u32 size, const char *str)
 627 {
 628         int status, i;
 629         u16 csum = 0;
 630         __le16 *flash = (__le16 *)&qdev->flash;
 631
 632         status = strncmp((char *)&qdev->flash, str, 4);
 633         if (status) {
 634                 QPRINTK(qdev, IFUP, ERR, "Invalid flash signature.\n");
 635                 return  status;
 636         }
 637
 638         for (i = 0; i < size; i++)
 639                 csum += le16_to_cpu(*flash++);
 640
 641         if (csum)
 642                 QPRINTK(qdev, IFUP, ERR,
 643                         "Invalid flash checksum, csum = 0x%.04x.\n", csum);
 644
 645         return csum;
 646 }
 647
 648 static int ql_read_flash_word(struct ql_adapter *qdev, int offset, __le32 *data)
 649 {
 650         int status = 0;
 651         /* wait for reg to come ready */
 652         status = ql_wait_reg_rdy(qdev,
 653                         FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR);
 654         if (status)
 655                 goto exit;
 656         /* set up for reg read */
 657         ql_write32(qdev, FLASH_ADDR, FLASH_ADDR_R | offset);
 658         /* wait for reg to come ready */
 659         status = ql_wait_reg_rdy(qdev,
 660                         FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR);
 661         if (status)
 662                 goto exit;
 663          /* This data is stored on flash as an array of
 664          * __le32.  Since ql_read32() returns cpu endian
 665          * we need to swap it back.
 666          */
 667         *data = cpu_to_le32(ql_read32(qdev, FLASH_DATA));
 668 exit:
 669         return status;
 670 }
 671
 672 static int ql_get_8000_flash_params(struct ql_adapter *qdev)
 673 {
 674         u32 i, size;
 675         int status;
 676         __le32 *p = (__le32 *)&qdev->flash;
 677         u32 offset;
 678
 679         /* Get flash offset for function and adjust
 680          * for dword access.
 681          */
 682         if (!qdev->func)
 683                 offset = FUNC0_FLASH_OFFSET / sizeof(u32);
 684         else
 685                 offset = FUNC1_FLASH_OFFSET / sizeof(u32);
 686
 687         if (ql_sem_spinlock(qdev, SEM_FLASH_MASK))
 688                 return -ETIMEDOUT;
 689
 690         size = sizeof(struct flash_params_8000) / sizeof(u32);
 691         for (i = 0; i < size; i++, p++) {
 692                 status = ql_read_flash_word(qdev, i+offset, p);
 693                 if (status) {
 694                         QPRINTK(qdev, IFUP, ERR, "Error reading flash.\n");
 695                         goto exit;
 696                 }
 697         }
 698
 699         status = ql_validate_flash(qdev,
 700                         sizeof(struct flash_params_8000) / sizeof(u16),
 701                         "8000");
 702         if (status) {
 703                 QPRINTK(qdev, IFUP, ERR, "Invalid flash.\n");
 704                 status = -EINVAL;
 705                 goto exit;
 706         }
 707
 708         if (!is_valid_ether_addr(qdev->flash.flash_params_8000.mac_addr)) {
 709                 QPRINTK(qdev, IFUP, ERR, "Invalid MAC address.\n");
 710                 status = -EINVAL;
 711                 goto exit;
 712         }
 713
 714         memcpy(qdev->ndev->dev_addr,
 715                 qdev->flash.flash_params_8000.mac_addr,
 716                 qdev->ndev->addr_len);
 717
 718 exit:
 719         ql_sem_unlock(qdev, SEM_FLASH_MASK);
 720         return status;
 721 }
 722
 723 static int ql_get_8012_flash_params(struct ql_adapter *qdev)
 724 {
 725         int i;
 726         int status;
 727         __le32 *p = (__le32 *)&qdev->flash;
 728         u32 offset = 0;
 729         u32 size = sizeof(struct flash_params_8012) / sizeof(u32);
 730
 731         /* Second function's parameters follow the first
 732          * function's.
 733          */
 734         if (qdev->func)
 735                 offset = size;
 736
 737         if (ql_sem_spinlock(qdev, SEM_FLASH_MASK))
 738                 return -ETIMEDOUT;
 739
 740         for (i = 0; i < size; i++, p++) {
 741                 status = ql_read_flash_word(qdev, i+offset, p);
 742                 if (status) {
 743                         QPRINTK(qdev, IFUP, ERR, "Error reading flash.\n");
 744                         goto exit;
 745                 }
 746
 747         }
 748
 749         status = ql_validate_flash(qdev,
 750                         sizeof(struct flash_params_8012) / sizeof(u16),
 751                         "8012");
 752         if (status) {
 753                 QPRINTK(qdev, IFUP, ERR, "Invalid flash.\n");
 754                 status = -EINVAL;
 755                 goto exit;
 756         }
 757
 758         if (!is_valid_ether_addr(qdev->flash.flash_params_8012.mac_addr)) {
 759                 status = -EINVAL;
 760                 goto exit;
 761         }
 762
 763         memcpy(qdev->ndev->dev_addr,
 764                 qdev->flash.flash_params_8012.mac_addr,
 765                 qdev->ndev->addr_len);
 766
 767 exit:
 768         ql_sem_unlock(qdev, SEM_FLASH_MASK);
 769         return status;
 770 }
 771
 772 /* xgmac register are located behind the xgmac_addr and xgmac_data
 773  * register pair.  Each read/write requires us to wait for the ready
 774  * bit before reading/writing the data.
 775  */
 776 static int ql_write_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 data)
 777 {
 778         int status;
 779         /* wait for reg to come ready */
 780         status = ql_wait_reg_rdy(qdev,
 781                         XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
 782         if (status)
 783                 return status;
 784         /* write the data to the data reg */
 785         ql_write32(qdev, XGMAC_DATA, data);
 786         /* trigger the write */
 787         ql_write32(qdev, XGMAC_ADDR, reg);
 788         return status;
 789 }
 790
 791 /* xgmac register are located behind the xgmac_addr and xgmac_data
 792  * register pair.  Each read/write requires us to wait for the ready
 793  * bit before reading/writing the data.
 794  */
 795 int ql_read_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 *data)
 796 {
 797         int status = 0;
 798         /* wait for reg to come ready */
 799         status = ql_wait_reg_rdy(qdev,
 800                         XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
 801         if (status)
 802                 goto exit;
 803         /* set up for reg read */
 804         ql_write32(qdev, XGMAC_ADDR, reg | XGMAC_ADDR_R);
 805         /* wait for reg to come ready */
 806         status = ql_wait_reg_rdy(qdev,
 807                         XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
 808         if (status)
 809                 goto exit;
 810         /* get the data */
 811         *data = ql_read32(qdev, XGMAC_DATA);
 812 exit:
 813         return status;
 814 }
 815
 816 /* This is used for reading the 64-bit statistics regs. */
 817 int ql_read_xgmac_reg64(struct ql_adapter *qdev, u32 reg, u64 *data)
 818 {
 819         int status = 0;
 820         u32 hi = 0;
 821         u32 lo = 0;
 822
 823         status = ql_read_xgmac_reg(qdev, reg, &lo);
 824         if (status)
 825                 goto exit;
 826
 827         status = ql_read_xgmac_reg(qdev, reg + 4, &hi);
 828         if (status)
 829                 goto exit;
 830
 831         *data = (u64) lo | ((u64) hi << 32);
 832
 833 exit:
 834         return status;
 835 }
 836
 837 static int ql_8000_port_initialize(struct ql_adapter *qdev)
 838 {
 839         int status;
 840         /*
 841          * Get MPI firmware version for driver banner
 842          * and ethool info.
 843          */
 844         status = ql_mb_about_fw(qdev);
 845         if (status)
 846                 goto exit;
 847         status = ql_mb_get_fw_state(qdev);
 848         if (status)
 849                 goto exit;
 850         /* Wake up a worker to get/set the TX/RX frame sizes. */
 851         queue_delayed_work(qdev->workqueue, &qdev->mpi_port_cfg_work, 0);
 852 exit:
 853         return status;
 854 }
 855
 856 /* Take the MAC Core out of reset.
 857  * Enable statistics counting.
 858  * Take the transmitter/receiver out of reset.
 859  * This functionality may be done in the MPI firmware at a
 860  * later date.
 861  */
 862 static int ql_8012_port_initialize(struct ql_adapter *qdev)
 863 {
 864         int status = 0;
 865         u32 data;
 866
 867         if (ql_sem_trylock(qdev, qdev->xg_sem_mask)) {
 868                 /* Another function has the semaphore, so
 869                  * wait for the port init bit to come ready.
 870                  */
 871                 QPRINTK(qdev, LINK, INFO,
 872                         "Another function has the semaphore, so wait for the port init bit to come ready.\n");
 873                 status = ql_wait_reg_rdy(qdev, STS, qdev->port_init, 0);
 874                 if (status) {
 875                         QPRINTK(qdev, LINK, CRIT,
 876                                 "Port initialize timed out.\n");
 877                 }
 878                 return status;
 879         }
 880
 881         QPRINTK(qdev, LINK, INFO, "Got xgmac semaphore!.\n");
 882         /* Set the core reset. */
 883         status = ql_read_xgmac_reg(qdev, GLOBAL_CFG, &data);
 884         if (status)
 885                 goto end;
 886         data |= GLOBAL_CFG_RESET;
 887         status = ql_write_xgmac_reg(qdev, GLOBAL_CFG, data);
 888         if (status)
 889                 goto end;
 890
 891         /* Clear the core reset and turn on jumbo for receiver. */
 892         data &= ~GLOBAL_CFG_RESET;      /* Clear core reset. */
 893         data |= GLOBAL_CFG_JUMBO;       /* Turn on jumbo. */
 894         data |= GLOBAL_CFG_TX_STAT_EN;
 895         data |= GLOBAL_CFG_RX_STAT_EN;
 896         status = ql_write_xgmac_reg(qdev, GLOBAL_CFG, data);
 897         if (status)
 898                 goto end;
 899
 900         /* Enable transmitter, and clear it's reset. */
 901         status = ql_read_xgmac_reg(qdev, TX_CFG, &data);
 902         if (status)
 903                 goto end;
 904         data &= ~TX_CFG_RESET;  /* Clear the TX MAC reset. */
 905         data |= TX_CFG_EN;      /* Enable the transmitter. */
 906         status = ql_write_xgmac_reg(qdev, TX_CFG, data);
 907         if (status)
 908                 goto end;
 909
 910         /* Enable receiver and clear it's reset. */
 911         status = ql_read_xgmac_reg(qdev, RX_CFG, &data);
 912         if (status)
 913                 goto end;
 914         data &= ~RX_CFG_RESET;  /* Clear the RX MAC reset. */
 915         data |= RX_CFG_EN;      /* Enable the receiver. */
 916         status = ql_write_xgmac_reg(qdev, RX_CFG, data);
 917         if (status)
 918                 goto end;
 919
 920         /* Turn on jumbo. */
 921         status =
 922             ql_write_xgmac_reg(qdev, MAC_TX_PARAMS, MAC_TX_PARAMS_JUMBO | (0x2580 << 16));
 923         if (status)
 924                 goto end;
 925         status =
 926             ql_write_xgmac_reg(qdev, MAC_RX_PARAMS, 0x2580);
 927         if (status)
 928                 goto end;
 929
 930         /* Signal to the world that the port is enabled.        */
 931         ql_write32(qdev, STS, ((qdev->port_init << 16) | qdev->port_init));
 932 end:
 933         ql_sem_unlock(qdev, qdev->xg_sem_mask);
 934         return status;
 935 }
 936
 937 /* Get the next large buffer. */
 938 static struct bq_desc *ql_get_curr_lbuf(struct rx_ring *rx_ring)
 939 {
 940         struct bq_desc *lbq_desc = &rx_ring->lbq[rx_ring->lbq_curr_idx];
 941         rx_ring->lbq_curr_idx++;
 942         if (rx_ring->lbq_curr_idx == rx_ring->lbq_len)
 943                 rx_ring->lbq_curr_idx = 0;
 944         rx_ring->lbq_free_cnt++;
 945         return lbq_desc;
 946 }
 947
 948 /* Get the next small buffer. */
 949 static struct bq_desc *ql_get_curr_sbuf(struct rx_ring *rx_ring)
 950 {
 951         struct bq_desc *sbq_desc = &rx_ring->sbq[rx_ring->sbq_curr_idx];
 952         rx_ring->sbq_curr_idx++;
 953         if (rx_ring->sbq_curr_idx == rx_ring->sbq_len)
 954                 rx_ring->sbq_curr_idx = 0;
 955         rx_ring->sbq_free_cnt++;
 956         return sbq_desc;
 957 }
 958
 959 /* Update an rx ring index. */
 960 static void ql_update_cq(struct rx_ring *rx_ring)
 961 {
 962         rx_ring->cnsmr_idx++;
 963         rx_ring->curr_entry++;
 964         if (unlikely(rx_ring->cnsmr_idx == rx_ring->cq_len)) {
 965                 rx_ring->cnsmr_idx = 0;
 966                 rx_ring->curr_entry = rx_ring->cq_base;
 967         }
 968 }
 969
 970 static void ql_write_cq_idx(struct rx_ring *rx_ring)
 971 {
 972         ql_write_db_reg(rx_ring->cnsmr_idx, rx_ring->cnsmr_idx_db_reg);
 973 }
 974
 975 /* Process (refill) a large buffer queue. */
 976 static void ql_update_lbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
 977 {
 978         u32 clean_idx = rx_ring->lbq_clean_idx;
 979         u32 start_idx = clean_idx;
 980         struct bq_desc *lbq_desc;
 981         u64 map;
 982         int i;
 983
 984         while (rx_ring->lbq_free_cnt > 16) {
 985                 for (i = 0; i < 16; i++) {
 986                         QPRINTK(qdev, RX_STATUS, DEBUG,
 987                                 "lbq: try cleaning clean_idx = %d.\n",
 988                                 clean_idx);
 989                         lbq_desc = &rx_ring->lbq[clean_idx];
 990                         if (lbq_desc->p.lbq_page == NULL) {
 991                                 QPRINTK(qdev, RX_STATUS, DEBUG,
 992                                         "lbq: getting new page for index %d.\n",
 993                                         lbq_desc->index);
 994                                 lbq_desc->p.lbq_page = alloc_page(GFP_ATOMIC);
 995                                 if (lbq_desc->p.lbq_page == NULL) {
 996                                         rx_ring->lbq_clean_idx = clean_idx;
 997                                         QPRINTK(qdev, RX_STATUS, ERR,
 998                                                 "Couldn't get a page.\n");
 999                                         return;
1000                                 }
1001                                 map = pci_map_page(qdev->pdev,
1002                                                    lbq_desc->p.lbq_page,
1003                                                    0, PAGE_SIZE,
1004                                                    PCI_DMA_FROMDEVICE);
1005                                 if (pci_dma_mapping_error(qdev->pdev, map)) {
1006                                         rx_ring->lbq_clean_idx = clean_idx;
1007                                         put_page(lbq_desc->p.lbq_page);
1008                                         lbq_desc->p.lbq_page = NULL;
1009                                         QPRINTK(qdev, RX_STATUS, ERR,
1010                                                 "PCI mapping failed.\n");
1011                                         return;
1012                                 }
1013                                 pci_unmap_addr_set(lbq_desc, mapaddr, map);
1014                                 pci_unmap_len_set(lbq_desc, maplen, PAGE_SIZE);
1015                                 *lbq_desc->addr = cpu_to_le64(map);
1016                         }
1017                         clean_idx++;
1018                         if (clean_idx == rx_ring->lbq_len)
1019                                 clean_idx = 0;
1020                 }
1021
1022                 rx_ring->lbq_clean_idx = clean_idx;
1023                 rx_ring->lbq_prod_idx += 16;
1024                 if (rx_ring->lbq_prod_idx == rx_ring->lbq_len)
1025                         rx_ring->lbq_prod_idx = 0;
1026                 rx_ring->lbq_free_cnt -= 16;
1027         }
1028
1029         if (start_idx != clean_idx) {
1030                 QPRINTK(qdev, RX_STATUS, DEBUG,
1031                         "lbq: updating prod idx = %d.\n",
1032                         rx_ring->lbq_prod_idx);
1033                 ql_write_db_reg(rx_ring->lbq_prod_idx,
1034                                 rx_ring->lbq_prod_idx_db_reg);
1035         }
1036 }
1037
1038 /* Process (refill) a small buffer queue. */
1039 static void ql_update_sbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
1040 {
1041         u32 clean_idx = rx_ring->sbq_clean_idx;
1042         u32 start_idx = clean_idx;
1043         struct bq_desc *sbq_desc;
1044         u64 map;
1045         int i;
1046
1047         while (rx_ring->sbq_free_cnt > 16) {
1048                 for (i = 0; i < 16; i++) {
1049                         sbq_desc = &rx_ring->sbq[clean_idx];
1050                         QPRINTK(qdev, RX_STATUS, DEBUG,
1051                                 "sbq: try cleaning clean_idx = %d.\n",
1052                                 clean_idx);
1053                         if (sbq_desc->p.skb == NULL) {
1054                                 QPRINTK(qdev, RX_STATUS, DEBUG,
1055                                         "sbq: getting new skb for index %d.\n",
1056                                         sbq_desc->index);
1057                                 sbq_desc->p.skb =
1058                                     netdev_alloc_skb(qdev->ndev,
1059                                                      rx_ring->sbq_buf_size);
1060                                 if (sbq_desc->p.skb == NULL) {
1061                                         QPRINTK(qdev, PROBE, ERR,
1062                                                 "Couldn't get an skb.\n");
1063                                         rx_ring->sbq_clean_idx = clean_idx;
1064                                         return;
1065                                 }
1066                                 skb_reserve(sbq_desc->p.skb, QLGE_SB_PAD);
1067                                 map = pci_map_single(qdev->pdev,
1068                                                      sbq_desc->p.skb->data,
1069                                                      rx_ring->sbq_buf_size /
1070                                                      2, PCI_DMA_FROMDEVICE);
1071                                 if (pci_dma_mapping_error(qdev->pdev, map)) {
1072                                         QPRINTK(qdev, IFUP, ERR, "PCI mapping failed.\n");
1073                                         rx_ring->sbq_clean_idx = clean_idx;
1074                                         dev_kfree_skb_any(sbq_desc->p.skb);
1075                                         sbq_desc->p.skb = NULL;
1076                                         return;
1077                                 }
1078                                 pci_unmap_addr_set(sbq_desc, mapaddr, map);
1079                                 pci_unmap_len_set(sbq_desc, maplen,
1080                                                   rx_ring->sbq_buf_size / 2);
1081                                 *sbq_desc->addr = cpu_to_le64(map);
1082                         }
1083
1084                         clean_idx++;
1085                         if (clean_idx == rx_ring->sbq_len)
1086                                 clean_idx = 0;
1087                 }
1088                 rx_ring->sbq_clean_idx = clean_idx;
1089                 rx_ring->sbq_prod_idx += 16;
1090                 if (rx_ring->sbq_prod_idx == rx_ring->sbq_len)
1091                         rx_ring->sbq_prod_idx = 0;
1092                 rx_ring->sbq_free_cnt -= 16;
1093         }
1094
1095         if (start_idx != clean_idx) {
1096                 QPRINTK(qdev, RX_STATUS, DEBUG,
1097                         "sbq: updating prod idx = %d.\n",
1098                         rx_ring->sbq_prod_idx);
1099                 ql_write_db_reg(rx_ring->sbq_prod_idx,
1100                                 rx_ring->sbq_prod_idx_db_reg);
1101         }
1102 }
1103
1104 static void ql_update_buffer_queues(struct ql_adapter *qdev,
1105                                     struct rx_ring *rx_ring)
1106 {
1107         ql_update_sbq(qdev, rx_ring);
1108         ql_update_lbq(qdev, rx_ring);
1109 }
1110
1111 /* Unmaps tx buffers.  Can be called from send() if a pci mapping
1112  * fails at some stage, or from the interrupt when a tx completes.
1113  */
1114 static void ql_unmap_send(struct ql_adapter *qdev,
1115                           struct tx_ring_desc *tx_ring_desc, int mapped)
1116 {
1117         int i;
1118         for (i = 0; i < mapped; i++) {
1119                 if (i == 0 || (i == 7 && mapped > 7)) {
1120                         /*
1121                          * Unmap the skb->data area, or the
1122                          * external sglist (AKA the Outbound
1123                          * Address List (OAL)).
1124                          * If its the zeroeth element, then it's
1125                          * the skb->data area.  If it's the 7th
1126                          * element and there is more than 6 frags,
1127                          * then its an OAL.
1128                          */
1129                         if (i == 7) {
1130                                 QPRINTK(qdev, TX_DONE, DEBUG,
1131                                         "unmapping OAL area.\n");
1132                         }
1133                         pci_unmap_single(qdev->pdev,
1134                                          pci_unmap_addr(&tx_ring_desc->map[i],
1135                                                         mapaddr),
1136                                          pci_unmap_len(&tx_ring_desc->map[i],
1137                                                        maplen),
1138                                          PCI_DMA_TODEVICE);
1139                 } else {
1140                         QPRINTK(qdev, TX_DONE, DEBUG, "unmapping frag %d.\n",
1141                                 i);
1142                         pci_unmap_page(qdev->pdev,
1143                                        pci_unmap_addr(&tx_ring_desc->map[i],
1144                                                       mapaddr),
1145                                        pci_unmap_len(&tx_ring_desc->map[i],
1146                                                      maplen), PCI_DMA_TODEVICE);
1147                 }
1148         }
1149
1150 }
1151
1152 /* Map the buffers for this transmit.  This will return
1153  * NETDEV_TX_BUSY or NETDEV_TX_OK based on success.
1154  */
1155 static int ql_map_send(struct ql_adapter *qdev,
1156                        struct ob_mac_iocb_req *mac_iocb_ptr,
1157                        struct sk_buff *skb, struct tx_ring_desc *tx_ring_desc)
1158 {
1159         int len = skb_headlen(skb);
1160         dma_addr_t map;
1161         int frag_idx, err, map_idx = 0;
1162         struct tx_buf_desc *tbd = mac_iocb_ptr->tbd;
1163         int frag_cnt = skb_shinfo(skb)->nr_frags;
1164
1165         if (frag_cnt) {
1166                 QPRINTK(qdev, TX_QUEUED, DEBUG, "frag_cnt = %d.\n", frag_cnt);
1167         }
1168         /*
1169          * Map the skb buffer first.
1170          */
1171         map = pci_map_single(qdev->pdev, skb->data, len, PCI_DMA_TODEVICE);
1172
1173         err = pci_dma_mapping_error(qdev->pdev, map);
1174         if (err) {
1175                 QPRINTK(qdev, TX_QUEUED, ERR,
1176                         "PCI mapping failed with error: %d\n", err);
1177
1178                 return NETDEV_TX_BUSY;
1179         }
1180
1181         tbd->len = cpu_to_le32(len);
1182         tbd->addr = cpu_to_le64(map);
1183         pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr, map);
1184         pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen, len);
1185         map_idx++;
1186
1187         /*
1188          * This loop fills the remainder of the 8 address descriptors
1189          * in the IOCB.  If there are more than 7 fragments, then the
1190          * eighth address desc will point to an external list (OAL).
1191          * When this happens, the remainder of the frags will be stored
1192          * in this list.
1193          */
1194         for (frag_idx = 0; frag_idx < frag_cnt; frag_idx++, map_idx++) {
1195                 skb_frag_t *frag = &skb_shinfo(skb)->frags[frag_idx];
1196                 tbd++;
1197                 if (frag_idx == 6 && frag_cnt > 7) {
1198                         /* Let's tack on an sglist.
1199                          * Our control block will now
1200                          * look like this:
1201                          * iocb->seg[0] = skb->data
1202                          * iocb->seg[1] = frag[0]
1203                          * iocb->seg[2] = frag[1]
1204                          * iocb->seg[3] = frag[2]
1205                          * iocb->seg[4] = frag[3]
1206                          * iocb->seg[5] = frag[4]
1207                          * iocb->seg[6] = frag[5]
1208                          * iocb->seg[7] = ptr to OAL (external sglist)
1209                          * oal->seg[0] = frag[6]
1210                          * oal->seg[1] = frag[7]
1211                          * oal->seg[2] = frag[8]
1212                          * oal->seg[3] = frag[9]
1213                          * oal->seg[4] = frag[10]
1214                          *      etc...
1215                          */
1216                         /* Tack on the OAL in the eighth segment of IOCB. */
1217                         map = pci_map_single(qdev->pdev, &tx_ring_desc->oal,
1218                                              sizeof(struct oal),
1219                                              PCI_DMA_TODEVICE);
1220                         err = pci_dma_mapping_error(qdev->pdev, map);
1221                         if (err) {
1222                                 QPRINTK(qdev, TX_QUEUED, ERR,
1223                                         "PCI mapping outbound address list with error: %d\n",
1224                                         err);
1225                                 goto map_error;
1226                         }
1227
1228                         tbd->addr = cpu_to_le64(map);
1229                         /*
1230                          * The length is the number of fragments
1231                          * that remain to be mapped times the length
1232                          * of our sglist (OAL).
1233                          */
1234                         tbd->len =
1235                             cpu_to_le32((sizeof(struct tx_buf_desc) *
1236                                          (frag_cnt - frag_idx)) | TX_DESC_C);
1237                         pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr,
1238                                            map);
1239                         pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen,
1240                                           sizeof(struct oal));
1241                         tbd = (struct tx_buf_desc *)&tx_ring_desc->oal;
1242                         map_idx++;
1243                 }
1244
1245                 map =
1246                     pci_map_page(qdev->pdev, frag->page,
1247                                  frag->page_offset, frag->size,
1248                                  PCI_DMA_TODEVICE);
1249
1250                 err = pci_dma_mapping_error(qdev->pdev, map);
1251                 if (err) {
1252                         QPRINTK(qdev, TX_QUEUED, ERR,
1253                                 "PCI mapping frags failed with error: %d.\n",
1254                                 err);
1255                         goto map_error;
1256                 }
1257
1258                 tbd->addr = cpu_to_le64(map);
1259                 tbd->len = cpu_to_le32(frag->size);
1260                 pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr, map);
1261                 pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen,
1262                                   frag->size);
1263
1264         }
1265         /* Save the number of segments we've mapped. */
1266         tx_ring_desc->map_cnt = map_idx;
1267         /* Terminate the last segment. */
1268         tbd->len = cpu_to_le32(le32_to_cpu(tbd->len) | TX_DESC_E);
1269         return NETDEV_TX_OK;
1270
1271 map_error:
1272         /*
1273          * If the first frag mapping failed, then i will be zero.
1274          * This causes the unmap of the skb->data area.  Otherwise
1275          * we pass in the number of frags that mapped successfully
1276          * so they can be umapped.
1277          */
1278         ql_unmap_send(qdev, tx_ring_desc, map_idx);
1279         return NETDEV_TX_BUSY;
1280 }
1281
1282 static void ql_realign_skb(struct sk_buff *skb, int len)
1283 {
1284         void *temp_addr = skb->data;
1285
1286         /* Undo the skb_reserve(skb,32) we did before
1287          * giving to hardware, and realign data on
1288          * a 2-byte boundary.
1289          */
1290         skb->data -= QLGE_SB_PAD - NET_IP_ALIGN;
1291         skb->tail -= QLGE_SB_PAD - NET_IP_ALIGN;
1292         skb_copy_to_linear_data(skb, temp_addr,
1293                 (unsigned int)len);
1294 }
1295
1296 /*
1297  * This function builds an skb for the given inbound
1298  * completion.  It will be rewritten for readability in the near
1299  * future, but for not it works well.
1300  */
1301 static struct sk_buff *ql_build_rx_skb(struct ql_adapter *qdev,
1302                                        struct rx_ring *rx_ring,
1303                                        struct ib_mac_iocb_rsp *ib_mac_rsp)
1304 {
1305         struct bq_desc *lbq_desc;
1306         struct bq_desc *sbq_desc;
1307         struct sk_buff *skb = NULL;
1308         u32 length = le32_to_cpu(ib_mac_rsp->data_len);
1309        u32 hdr_len = le32_to_cpu(ib_mac_rsp->hdr_len);
1310
1311         /*
1312          * Handle the header buffer if present.
1313          */
1314         if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HV &&
1315             ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1316                 QPRINTK(qdev, RX_STATUS, DEBUG, "Header of %d bytes in small buffer.\n", hdr_len);
1317                 /*
1318                  * Headers fit nicely into a small buffer.
1319                  */
1320                 sbq_desc = ql_get_curr_sbuf(rx_ring);
1321                 pci_unmap_single(qdev->pdev,
1322                                 pci_unmap_addr(sbq_desc, mapaddr),
1323                                 pci_unmap_len(sbq_desc, maplen),
1324                                 PCI_DMA_FROMDEVICE);
1325                 skb = sbq_desc->p.skb;
1326                 ql_realign_skb(skb, hdr_len);
1327                 skb_put(skb, hdr_len);
1328                 sbq_desc->p.skb = NULL;
1329         }
1330
1331         /*
1332          * Handle the data buffer(s).
1333          */
1334         if (unlikely(!length)) {        /* Is there data too? */
1335                 QPRINTK(qdev, RX_STATUS, DEBUG,
1336                         "No Data buffer in this packet.\n");
1337                 return skb;
1338         }
1339
1340         if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DS) {
1341                 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1342                         QPRINTK(qdev, RX_STATUS, DEBUG,
1343                                 "Headers in small, data of %d bytes in small, combine them.\n", length);
1344                         /*
1345                          * Data is less than small buffer size so it's
1346                          * stuffed in a small buffer.
1347                          * For this case we append the data
1348                          * from the "data" small buffer to the "header" small
1349                          * buffer.
1350                          */
1351                         sbq_desc = ql_get_curr_sbuf(rx_ring);
1352                         pci_dma_sync_single_for_cpu(qdev->pdev,
1353                                                     pci_unmap_addr
1354                                                     (sbq_desc, mapaddr),
1355                                                     pci_unmap_len
1356                                                     (sbq_desc, maplen),
1357                                                     PCI_DMA_FROMDEVICE);
1358                         memcpy(skb_put(skb, length),
1359                                sbq_desc->p.skb->data, length);
1360                         pci_dma_sync_single_for_device(qdev->pdev,
1361                                                        pci_unmap_addr
1362                                                        (sbq_desc,
1363                                                         mapaddr),
1364                                                        pci_unmap_len
1365                                                        (sbq_desc,
1366                                                         maplen),
1367                                                        PCI_DMA_FROMDEVICE);
1368                 } else {
1369                         QPRINTK(qdev, RX_STATUS, DEBUG,
1370                                 "%d bytes in a single small buffer.\n", length);
1371                         sbq_desc = ql_get_curr_sbuf(rx_ring);
1372                         skb = sbq_desc->p.skb;
1373                         ql_realign_skb(skb, length);
1374                         skb_put(skb, length);
1375                         pci_unmap_single(qdev->pdev,
1376                                          pci_unmap_addr(sbq_desc,
1377                                                         mapaddr),
1378                                          pci_unmap_len(sbq_desc,
1379                                                        maplen),
1380                                          PCI_DMA_FROMDEVICE);
1381                         sbq_desc->p.skb = NULL;
1382                 }
1383         } else if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DL) {
1384                 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1385                         QPRINTK(qdev, RX_STATUS, DEBUG,
1386                                 "Header in small, %d bytes in large. Chain large to small!\n", length);
1387                         /*
1388                          * The data is in a single large buffer.  We
1389                          * chain it to the header buffer's skb and let
1390                          * it rip.
1391                          */
1392                         lbq_desc = ql_get_curr_lbuf(rx_ring);
1393                         pci_unmap_page(qdev->pdev,
1394                                        pci_unmap_addr(lbq_desc,
1395                                                       mapaddr),
1396                                        pci_unmap_len(lbq_desc, maplen),
1397                                        PCI_DMA_FROMDEVICE);
1398                         QPRINTK(qdev, RX_STATUS, DEBUG,
1399                                 "Chaining page to skb.\n");
1400                         skb_fill_page_desc(skb, 0, lbq_desc->p.lbq_page,
1401                                            0, length);
1402                         skb->len += length;
1403                         skb->data_len += length;
1404                         skb->truesize += length;
1405                         lbq_desc->p.lbq_page = NULL;
1406                 } else {
1407                         /*
1408                          * The headers and data are in a single large buffer. We
1409                          * copy it to a new skb and let it go. This can happen with
1410                          * jumbo mtu on a non-TCP/UDP frame.
1411                          */
1412                         lbq_desc = ql_get_curr_lbuf(rx_ring);
1413                         skb = netdev_alloc_skb(qdev->ndev, length);
1414                         if (skb == NULL) {
1415                                 QPRINTK(qdev, PROBE, DEBUG,
1416                                         "No skb available, drop the packet.\n");
1417                                 return NULL;
1418                         }
1419                         pci_unmap_page(qdev->pdev,
1420                                        pci_unmap_addr(lbq_desc,
1421                                                       mapaddr),
1422                                        pci_unmap_len(lbq_desc, maplen),
1423                                        PCI_DMA_FROMDEVICE);
1424                         skb_reserve(skb, NET_IP_ALIGN);
1425                         QPRINTK(qdev, RX_STATUS, DEBUG,
1426                                 "%d bytes of headers and data in large. Chain page to new skb and pull tail.\n", length);
1427                         skb_fill_page_desc(skb, 0, lbq_desc->p.lbq_page,
1428                                            0, length);
1429                         skb->len += length;
1430                         skb->data_len += length;
1431                         skb->truesize += length;
1432                         length -= length;
1433                         lbq_desc->p.lbq_page = NULL;
1434                         __pskb_pull_tail(skb,
1435                                 (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) ?
1436                                 VLAN_ETH_HLEN : ETH_HLEN);
1437                 }
1438         } else {
1439                 /*
1440                  * The data is in a chain of large buffers
1441                  * pointed to by a small buffer.  We loop
1442                  * thru and chain them to the our small header
1443                  * buffer's skb.
1444                  * frags:  There are 18 max frags and our small
1445                  *         buffer will hold 32 of them. The thing is,
1446                  *         we'll use 3 max for our 9000 byte jumbo
1447                  *         frames.  If the MTU goes up we could
1448                  *          eventually be in trouble.
1449                  */
1450                 int size, offset, i = 0;
1451                 __le64 *bq, bq_array[8];
1452                 sbq_desc = ql_get_curr_sbuf(rx_ring);
1453                 pci_unmap_single(qdev->pdev,
1454                                  pci_unmap_addr(sbq_desc, mapaddr),
1455                                  pci_unmap_len(sbq_desc, maplen),
1456                                  PCI_DMA_FROMDEVICE);
1457                 if (!(ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS)) {
1458                         /*
1459                          * This is an non TCP/UDP IP frame, so
1460                          * the headers aren't split into a small
1461                          * buffer.  We have to use the small buffer
1462                          * that contains our sg list as our skb to
1463                          * send upstairs. Copy the sg list here to
1464                          * a local buffer and use it to find the
1465                          * pages to chain.
1466                          */
1467                         QPRINTK(qdev, RX_STATUS, DEBUG,
1468                                 "%d bytes of headers & data in chain of large.\n", length);
1469                         skb = sbq_desc->p.skb;
1470                         bq = &bq_array[0];
1471                         memcpy(bq, skb->data, sizeof(bq_array));
1472                         sbq_desc->p.skb = NULL;
1473                         skb_reserve(skb, NET_IP_ALIGN);
1474                 } else {
1475                         QPRINTK(qdev, RX_STATUS, DEBUG,
1476                                 "Headers in small, %d bytes of data in chain of large.\n", length);
1477                         bq = (__le64 *)sbq_desc->p.skb->data;
1478                 }
1479                 while (length > 0) {
1480                         lbq_desc = ql_get_curr_lbuf(rx_ring);
1481                         pci_unmap_page(qdev->pdev,
1482                                        pci_unmap_addr(lbq_desc,
1483                                                       mapaddr),
1484                                        pci_unmap_len(lbq_desc,
1485                                                      maplen),
1486                                        PCI_DMA_FROMDEVICE);
1487                         size = (length < PAGE_SIZE) ? length : PAGE_SIZE;
1488                         offset = 0;
1489
1490                         QPRINTK(qdev, RX_STATUS, DEBUG,
1491                                 "Adding page %d to skb for %d bytes.\n",
1492                                 i, size);
1493                         skb_fill_page_desc(skb, i, lbq_desc->p.lbq_page,
1494                                            offset, size);
1495                         skb->len += size;
1496                         skb->data_len += size;
1497                         skb->truesize += size;
1498                         length -= size;
1499                         lbq_desc->p.lbq_page = NULL;
1500                         bq++;
1501                         i++;
1502                 }
1503                 __pskb_pull_tail(skb, (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) ?
1504                                 VLAN_ETH_HLEN : ETH_HLEN);
1505         }
1506         return skb;
1507 }
1508
1509 /* Process an inbound completion from an rx ring. */
1510 static void ql_process_mac_rx_intr(struct ql_adapter *qdev,
1511                                    struct rx_ring *rx_ring,
1512                                    struct ib_mac_iocb_rsp *ib_mac_rsp)
1513 {
1514         struct net_device *ndev = qdev->ndev;
1515         struct sk_buff *skb = NULL;
1516         u16 vlan_id = (le16_to_cpu(ib_mac_rsp->vlan_id) &
1517                         IB_MAC_IOCB_RSP_VLAN_MASK)
1518
1519         QL_DUMP_IB_MAC_RSP(ib_mac_rsp);
1520
1521         skb = ql_build_rx_skb(qdev, rx_ring, ib_mac_rsp);
1522         if (unlikely(!skb)) {
1523                 QPRINTK(qdev, RX_STATUS, DEBUG,
1524                         "No skb available, drop packet.\n");
1525                 return;
1526         }
1527
1528         prefetch(skb->data);
1529         skb->dev = ndev;
1530         if (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) {
1531                 QPRINTK(qdev, RX_STATUS, DEBUG, "%s%s%s Multicast.\n",
1532                         (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1533                         IB_MAC_IOCB_RSP_M_HASH ? "Hash" : "",
1534                         (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1535                         IB_MAC_IOCB_RSP_M_REG ? "Registered" : "",
1536                         (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1537                         IB_MAC_IOCB_RSP_M_PROM ? "Promiscuous" : "");
1538         }
1539         if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_P) {
1540                 QPRINTK(qdev, RX_STATUS, DEBUG, "Promiscuous Packet.\n");
1541         }
1542
1543         skb->protocol = eth_type_trans(skb, ndev);
1544         skb->ip_summed = CHECKSUM_NONE;
1545
1546         /* If rx checksum is on, and there are no
1547          * csum or frame errors.
1548          */
1549         if (qdev->rx_csum &&
1550                 !(ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_ERR_MASK) &&
1551                 !(ib_mac_rsp->flags1 & IB_MAC_CSUM_ERR_MASK)) {
1552                 /* TCP frame. */
1553                 if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_T) {
1554                         QPRINTK(qdev, RX_STATUS, DEBUG,
1555                                         "TCP checksum done!\n");
1556                         skb->ip_summed = CHECKSUM_UNNECESSARY;
1557                 } else if ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_U) &&
1558                                 (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_V4)) {
1559                 /* Unfragmented ipv4 UDP frame. */
1560                         struct iphdr *iph = (struct iphdr *) skb->data;
1561                         if (!(iph->frag_off &
1562                                 cpu_to_be16(IP_MF|IP_OFFSET))) {
1563                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1564                                 QPRINTK(qdev, RX_STATUS, DEBUG,
1565                                                 "TCP checksum done!\n");
1566                         }
1567                 }
1568         }
1569
1570         qdev->stats.rx_packets++;
1571         qdev->stats.rx_bytes += skb->len;
1572         skb_record_rx_queue(skb,
1573                 rx_ring->cq_id - qdev->rss_ring_first_cq_id);
1574         if (skb->ip_summed == CHECKSUM_UNNECESSARY) {
1575                 if (qdev->vlgrp &&
1576                         (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) &&
1577                         (vlan_id != 0))
1578                         vlan_gro_receive(&rx_ring->napi, qdev->vlgrp,
1579                                 vlan_id, skb);
1580                 else
1581                         napi_gro_receive(&rx_ring->napi, skb);
1582         } else {
1583                 if (qdev->vlgrp &&
1584                         (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) &&
1585                         (vlan_id != 0))
1586                         vlan_hwaccel_receive_skb(skb, qdev->vlgrp, vlan_id);
1587                 else
1588                         netif_receive_skb(skb);
1589         }
1590 }
1591
1592 /* Process an outbound completion from an rx ring. */
1593 static void ql_process_mac_tx_intr(struct ql_adapter *qdev,
1594                                    struct ob_mac_iocb_rsp *mac_rsp)
1595 {
1596         struct tx_ring *tx_ring;
1597         struct tx_ring_desc *tx_ring_desc;
1598
1599         QL_DUMP_OB_MAC_RSP(mac_rsp);
1600         tx_ring = &qdev->tx_ring[mac_rsp->txq_idx];
1601         tx_ring_desc = &tx_ring->q[mac_rsp->tid];
1602         ql_unmap_send(qdev, tx_ring_desc, tx_ring_desc->map_cnt);
1603         qdev->stats.tx_bytes += tx_ring_desc->map_cnt;
1604         qdev->stats.tx_packets++;
1605         dev_kfree_skb(tx_ring_desc->skb);
1606         tx_ring_desc->skb = NULL;
1607
1608         if (unlikely(mac_rsp->flags1 & (OB_MAC_IOCB_RSP_E |
1609                                         OB_MAC_IOCB_RSP_S |
1610                                         OB_MAC_IOCB_RSP_L |
1611                                         OB_MAC_IOCB_RSP_P | OB_MAC_IOCB_RSP_B))) {
1612                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_E) {
1613                         QPRINTK(qdev, TX_DONE, WARNING,
1614                                 "Total descriptor length did not match transfer length.\n");
1615                 }
1616                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_S) {
1617                         QPRINTK(qdev, TX_DONE, WARNING,
1618                                 "Frame too short to be legal, not sent.\n");
1619                 }
1620                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_L) {
1621                         QPRINTK(qdev, TX_DONE, WARNING,
1622                                 "Frame too long, but sent anyway.\n");
1623                 }
1624                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_B) {
1625                         QPRINTK(qdev, TX_DONE, WARNING,
1626                                 "PCI backplane error. Frame not sent.\n");
1627                 }
1628         }
1629         atomic_inc(&tx_ring->tx_count);
1630 }
1631
1632 /* Fire up a handler to reset the MPI processor. */
1633 void ql_queue_fw_error(struct ql_adapter *qdev)
1634 {
1635         netif_carrier_off(qdev->ndev);
1636         queue_delayed_work(qdev->workqueue, &qdev->mpi_reset_work, 0);
1637 }
1638
1639 void ql_queue_asic_error(struct ql_adapter *qdev)
1640 {
1641         netif_carrier_off(qdev->ndev);
1642         ql_disable_interrupts(qdev);
1643         /* Clear adapter up bit to signal the recovery
1644          * process that it shouldn't kill the reset worker
1645          * thread
1646          */
1647         clear_bit(QL_ADAPTER_UP, &qdev->flags);
1648         queue_delayed_work(qdev->workqueue, &qdev->asic_reset_work, 0);
1649 }
1650
1651 static void ql_process_chip_ae_intr(struct ql_adapter *qdev,
1652                                     struct ib_ae_iocb_rsp *ib_ae_rsp)
1653 {
1654         switch (ib_ae_rsp->event) {
1655         case MGMT_ERR_EVENT:
1656                 QPRINTK(qdev, RX_ERR, ERR,
1657                         "Management Processor Fatal Error.\n");
1658                 ql_queue_fw_error(qdev);
1659                 return;
1660
1661         case CAM_LOOKUP_ERR_EVENT:
1662                 QPRINTK(qdev, LINK, ERR,
1663                         "Multiple CAM hits lookup occurred.\n");
1664                 QPRINTK(qdev, DRV, ERR, "This event shouldn't occur.\n");
1665                 ql_queue_asic_error(qdev);
1666                 return;
1667
1668         case SOFT_ECC_ERROR_EVENT:
1669                 QPRINTK(qdev, RX_ERR, ERR, "Soft ECC error detected.\n");
1670                 ql_queue_asic_error(qdev);
1671                 break;
1672
1673         case PCI_ERR_ANON_BUF_RD:
1674                 QPRINTK(qdev, RX_ERR, ERR,
1675                         "PCI error occurred when reading anonymous buffers from rx_ring %d.\n",
1676                         ib_ae_rsp->q_id);
1677                 ql_queue_asic_error(qdev);
1678                 break;
1679
1680         default:
1681                 QPRINTK(qdev, DRV, ERR, "Unexpected event %d.\n",
1682                         ib_ae_rsp->event);
1683                 ql_queue_asic_error(qdev);
1684                 break;
1685         }
1686 }
1687
1688 static int ql_clean_outbound_rx_ring(struct rx_ring *rx_ring)
1689 {
1690         struct ql_adapter *qdev = rx_ring->qdev;
1691         u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1692         struct ob_mac_iocb_rsp *net_rsp = NULL;
1693         int count = 0;
1694
1695         struct tx_ring *tx_ring;
1696         /* While there are entries in the completion queue. */
1697         while (prod != rx_ring->cnsmr_idx) {
1698
1699                 QPRINTK(qdev, RX_STATUS, DEBUG,
1700                         "cq_id = %d, prod = %d, cnsmr = %d.\n.", rx_ring->cq_id,
1701                         prod, rx_ring->cnsmr_idx);
1702
1703                 net_rsp = (struct ob_mac_iocb_rsp *)rx_ring->curr_entry;
1704                 rmb();
1705                 switch (net_rsp->opcode) {
1706
1707                 case OPCODE_OB_MAC_TSO_IOCB:
1708                 case OPCODE_OB_MAC_IOCB:
1709                         ql_process_mac_tx_intr(qdev, net_rsp);
1710                         break;
1711                 default:
1712                         QPRINTK(qdev, RX_STATUS, DEBUG,
1713                                 "Hit default case, not handled! dropping the packet, opcode = %x.\n",
1714                                 net_rsp->opcode);
1715                 }
1716                 count++;
1717                 ql_update_cq(rx_ring);
1718                 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1719         }
1720         ql_write_cq_idx(rx_ring);
1721         tx_ring = &qdev->tx_ring[net_rsp->txq_idx];
1722         if (__netif_subqueue_stopped(qdev->ndev, tx_ring->wq_id) &&
1723                                         net_rsp != NULL) {
1724                 if (atomic_read(&tx_ring->queue_stopped) &&
1725                     (atomic_read(&tx_ring->tx_count) > (tx_ring->wq_len / 4)))
1726                         /*
1727                          * The queue got stopped because the tx_ring was full.
1728                          * Wake it up, because it's now at least 25% empty.
1729                          */
1730                         netif_wake_subqueue(qdev->ndev, tx_ring->wq_id);
1731         }
1732
1733         return count;
1734 }
1735
1736 static int ql_clean_inbound_rx_ring(struct rx_ring *rx_ring, int budget)
1737 {
1738         struct ql_adapter *qdev = rx_ring->qdev;
1739         u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1740         struct ql_net_rsp_iocb *net_rsp;
1741         int count = 0;
1742
1743         /* While there are entries in the completion queue. */
1744         while (prod != rx_ring->cnsmr_idx) {
1745
1746                 QPRINTK(qdev, RX_STATUS, DEBUG,
1747                         "cq_id = %d, prod = %d, cnsmr = %d.\n.", rx_ring->cq_id,
1748                         prod, rx_ring->cnsmr_idx);
1749
1750                 net_rsp = rx_ring->curr_entry;
1751                 rmb();
1752                 switch (net_rsp->opcode) {
1753                 case OPCODE_IB_MAC_IOCB:
1754                         ql_process_mac_rx_intr(qdev, rx_ring,
1755                                                (struct ib_mac_iocb_rsp *)
1756                                                net_rsp);
1757                         break;
1758
1759                 case OPCODE_IB_AE_IOCB:
1760                         ql_process_chip_ae_intr(qdev, (struct ib_ae_iocb_rsp *)
1761                                                 net_rsp);
1762                         break;
1763                 default:
1764                         {
1765                                 QPRINTK(qdev, RX_STATUS, DEBUG,
1766                                         "Hit default case, not handled! dropping the packet, opcode = %x.\n",
1767                                         net_rsp->opcode);
1768                         }
1769                 }
1770                 count++;
1771                 ql_update_cq(rx_ring);
1772                 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1773                 if (count == budget)
1774                         break;
1775         }
1776         ql_update_buffer_queues(qdev, rx_ring);
1777         ql_write_cq_idx(rx_ring);
1778         return count;
1779 }
1780
1781 static int ql_napi_poll_msix(struct napi_struct *napi, int budget)
1782 {
1783         struct rx_ring *rx_ring = container_of(napi, struct rx_ring, napi);
1784         struct ql_adapter *qdev = rx_ring->qdev;
1785         int work_done = ql_clean_inbound_rx_ring(rx_ring, budget);
1786
1787         QPRINTK(qdev, RX_STATUS, DEBUG, "Enter, NAPI POLL cq_id = %d.\n",
1788                 rx_ring->cq_id);
1789
1790         if (work_done < budget) {
1791                 napi_complete(napi);
1792                 ql_enable_completion_interrupt(qdev, rx_ring->irq);
1793         }
1794         return work_done;
1795 }
1796
1797 static void ql_vlan_rx_register(struct net_device *ndev, struct vlan_group *grp)
1798 {
1799         struct ql_adapter *qdev = netdev_priv(ndev);
1800
1801         qdev->vlgrp = grp;
1802         if (grp) {
1803                 QPRINTK(qdev, IFUP, DEBUG, "Turning on VLAN in NIC_RCV_CFG.\n");
1804                 ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK |
1805                            NIC_RCV_CFG_VLAN_MATCH_AND_NON);
1806         } else {
1807                 QPRINTK(qdev, IFUP, DEBUG,
1808                         "Turning off VLAN in NIC_RCV_CFG.\n");
1809                 ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK);
1810         }
1811 }
1812
1813 static void ql_vlan_rx_add_vid(struct net_device *ndev, u16 vid)
1814 {
1815         struct ql_adapter *qdev = netdev_priv(ndev);
1816         u32 enable_bit = MAC_ADDR_E;
1817         int status;
1818
1819         status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
1820         if (status)
1821                 return;
1822         spin_lock(&qdev->hw_lock);
1823         if (ql_set_mac_addr_reg
1824             (qdev, (u8 *) &enable_bit, MAC_ADDR_TYPE_VLAN, vid)) {
1825                 QPRINTK(qdev, IFUP, ERR, "Failed to init vlan address.\n");
1826         }
1827         spin_unlock(&qdev->hw_lock);
1828         ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
1829 }
1830
1831 static void ql_vlan_rx_kill_vid(struct net_device *ndev, u16 vid)
1832 {
1833         struct ql_adapter *qdev = netdev_priv(ndev);
1834         u32 enable_bit = 0;
1835         int status;
1836
1837         status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
1838         if (status)
1839                 return;
1840
1841         spin_lock(&qdev->hw_lock);
1842         if (ql_set_mac_addr_reg
1843             (qdev, (u8 *) &enable_bit, MAC_ADDR_TYPE_VLAN, vid)) {
1844                 QPRINTK(qdev, IFUP, ERR, "Failed to clear vlan address.\n");
1845         }
1846         spin_unlock(&qdev->hw_lock);
1847         ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
1848
1849 }
1850
1851 /* Worker thread to process a given rx_ring that is dedicated
1852  * to outbound completions.
1853  */
1854 static void ql_tx_clean(struct work_struct *work)
1855 {
1856         struct rx_ring *rx_ring =
1857             container_of(work, struct rx_ring, rx_work.work);
1858         ql_clean_outbound_rx_ring(rx_ring);
1859         ql_enable_completion_interrupt(rx_ring->qdev, rx_ring->irq);
1860
1861 }
1862
1863 /* Worker thread to process a given rx_ring that is dedicated
1864  * to inbound completions.
1865  */
1866 static void ql_rx_clean(struct work_struct *work)
1867 {
1868         struct rx_ring *rx_ring =
1869             container_of(work, struct rx_ring, rx_work.work);
1870         ql_clean_inbound_rx_ring(rx_ring, 64);
1871         ql_enable_completion_interrupt(rx_ring->qdev, rx_ring->irq);
1872 }
1873
1874 /* MSI-X Multiple Vector Interrupt Handler for outbound completions. */
1875 static irqreturn_t qlge_msix_tx_isr(int irq, void *dev_id)
1876 {
1877         struct rx_ring *rx_ring = dev_id;
1878         queue_delayed_work_on(rx_ring->cpu, rx_ring->qdev->q_workqueue,
1879                               &rx_ring->rx_work, 0);
1880         return IRQ_HANDLED;
1881 }
1882
1883 /* MSI-X Multiple Vector Interrupt Handler for inbound completions. */
1884 static irqreturn_t qlge_msix_rx_isr(int irq, void *dev_id)
1885 {
1886         struct rx_ring *rx_ring = dev_id;
1887         napi_schedule(&rx_ring->napi);
1888         return IRQ_HANDLED;
1889 }
1890
1891 /* This handles a fatal error, MPI activity, and the default
1892  * rx_ring in an MSI-X multiple vector environment.
1893  * In MSI/Legacy environment it also process the rest of
1894  * the rx_rings.
1895  */
1896 static irqreturn_t qlge_isr(int irq, void *dev_id)
1897 {
1898         struct rx_ring *rx_ring = dev_id;
1899         struct ql_adapter *qdev = rx_ring->qdev;
1900         struct intr_context *intr_context = &qdev->intr_context[0];
1901         u32 var;
1902         int i;
1903         int work_done = 0;
1904
1905         spin_lock(&qdev->hw_lock);
1906         if (atomic_read(&qdev->intr_context[0].irq_cnt)) {
1907                 QPRINTK(qdev, INTR, DEBUG, "Shared Interrupt, Not ours!\n");
1908                 spin_unlock(&qdev->hw_lock);
1909                 return IRQ_NONE;
1910         }
1911         spin_unlock(&qdev->hw_lock);
1912
1913         var = ql_disable_completion_interrupt(qdev, intr_context->intr);
1914
1915         /*
1916          * Check for fatal error.
1917          */
1918         if (var & STS_FE) {
1919                 ql_queue_asic_error(qdev);
1920                 QPRINTK(qdev, INTR, ERR, "Got fatal error, STS = %x.\n", var);
1921                 var = ql_read32(qdev, ERR_STS);
1922                 QPRINTK(qdev, INTR, ERR,
1923                         "Resetting chip. Error Status Register = 0x%x\n", var);
1924                 return IRQ_HANDLED;
1925         }
1926
1927         /*
1928          * Check MPI processor activity.
1929          */
1930         if (var & STS_PI) {
1931                 /*
1932                  * We've got an async event or mailbox completion.
1933                  * Handle it and clear the source of the interrupt.
1934                  */
1935                 QPRINTK(qdev, INTR, ERR, "Got MPI processor interrupt.\n");
1936                 ql_disable_completion_interrupt(qdev, intr_context->intr);
1937                 queue_delayed_work_on(smp_processor_id(), qdev->workqueue,
1938                                       &qdev->mpi_work, 0);
1939                 work_done++;
1940         }
1941
1942         /*
1943          * Check the default queue and wake handler if active.
1944          */
1945         rx_ring = &qdev->rx_ring[0];
1946         if (ql_read_sh_reg(rx_ring->prod_idx_sh_reg) != rx_ring->cnsmr_idx) {
1947                 QPRINTK(qdev, INTR, INFO, "Waking handler for rx_ring[0].\n");
1948                 ql_disable_completion_interrupt(qdev, intr_context->intr);
1949                 queue_delayed_work_on(smp_processor_id(), qdev->q_workqueue,
1950                                       &rx_ring->rx_work, 0);
1951                 work_done++;
1952         }
1953
1954         if (!test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
1955                 /*
1956                  * Start the DPC for each active queue.
1957                  */
1958                 for (i = 1; i < qdev->rx_ring_count; i++) {
1959                         rx_ring = &qdev->rx_ring[i];
1960                         if (ql_read_sh_reg(rx_ring->prod_idx_sh_reg) !=
1961                             rx_ring->cnsmr_idx) {
1962                                 QPRINTK(qdev, INTR, INFO,
1963                                         "Waking handler for rx_ring[%d].\n", i);
1964                                 ql_disable_completion_interrupt(qdev,
1965                                                                 intr_context->
1966                                                                 intr);
1967                                 if (i < qdev->rss_ring_first_cq_id)
1968                                         queue_delayed_work_on(rx_ring->cpu,
1969                                                               qdev->q_workqueue,
1970                                                               &rx_ring->rx_work,
1971                                                               0);
1972                                 else
1973                                         napi_schedule(&rx_ring->napi);
1974                                 work_done++;
1975                         }
1976                 }
1977         }
1978         ql_enable_completion_interrupt(qdev, intr_context->intr);
1979         return work_done ? IRQ_HANDLED : IRQ_NONE;
1980 }
1981
1982 static int ql_tso(struct sk_buff *skb, struct ob_mac_tso_iocb_req *mac_iocb_ptr)
1983 {
1984
1985         if (skb_is_gso(skb)) {
1986                 int err;
1987                 if (skb_header_cloned(skb)) {
1988                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
1989                         if (err)
1990                                 return err;
1991                 }
1992
1993                 mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB;
1994                 mac_iocb_ptr->flags3 |= OB_MAC_TSO_IOCB_IC;
1995                 mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len);
1996                 mac_iocb_ptr->total_hdrs_len =
1997                     cpu_to_le16(skb_transport_offset(skb) + tcp_hdrlen(skb));
1998                 mac_iocb_ptr->net_trans_offset =
1999                     cpu_to_le16(skb_network_offset(skb) |
2000                                 skb_transport_offset(skb)
2001                                 << OB_MAC_TRANSPORT_HDR_SHIFT);
2002                 mac_iocb_ptr->mss = cpu_to_le16(skb_shinfo(skb)->gso_size);
2003                 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_LSO;
2004                 if (likely(skb->protocol == htons(ETH_P_IP))) {
2005                         struct iphdr *iph = ip_hdr(skb);
2006                         iph->check = 0;
2007                         mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP4;
2008                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2009                                                                  iph->daddr, 0,
2010                                                                  IPPROTO_TCP,
2011                                                                  0);
2012                 } else if (skb->protocol == htons(ETH_P_IPV6)) {
2013                         mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP6;
2014                         tcp_hdr(skb)->check =
2015                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2016                                              &ipv6_hdr(skb)->daddr,
2017                                              0, IPPROTO_TCP, 0);
2018                 }
2019                 return 1;
2020         }
2021         return 0;
2022 }
2023
2024 static void ql_hw_csum_setup(struct sk_buff *skb,
2025                              struct ob_mac_tso_iocb_req *mac_iocb_ptr)
2026 {
2027         int len;
2028         struct iphdr *iph = ip_hdr(skb);
2029         __sum16 *check;
2030         mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB;
2031         mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len);
2032         mac_iocb_ptr->net_trans_offset =
2033                 cpu_to_le16(skb_network_offset(skb) |
2034                 skb_transport_offset(skb) << OB_MAC_TRANSPORT_HDR_SHIFT);
2035
2036         mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP4;
2037         len = (ntohs(iph->tot_len) - (iph->ihl << 2));
2038         if (likely(iph->protocol == IPPROTO_TCP)) {
2039                 check = &(tcp_hdr(skb)->check);
2040                 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_TC;
2041                 mac_iocb_ptr->total_hdrs_len =
2042                     cpu_to_le16(skb_transport_offset(skb) +
2043                                 (tcp_hdr(skb)->doff << 2));
2044         } else {
2045                 check = &(udp_hdr(skb)->check);
2046                 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_UC;
2047                 mac_iocb_ptr->total_hdrs_len =
2048                     cpu_to_le16(skb_transport_offset(skb) +
2049                                 sizeof(struct udphdr));
2050         }
2051         *check = ~csum_tcpudp_magic(iph->saddr,
2052                                     iph->daddr, len, iph->protocol, 0);
2053 }
2054
2055 static int qlge_send(struct sk_buff *skb, struct net_device *ndev)
2056 {
2057         struct tx_ring_desc *tx_ring_desc;
2058         struct ob_mac_iocb_req *mac_iocb_ptr;
2059         struct ql_adapter *qdev = netdev_priv(ndev);
2060         int tso;
2061         struct tx_ring *tx_ring;
2062         u32 tx_ring_idx = (u32) skb->queue_mapping;
2063
2064         tx_ring = &qdev->tx_ring[tx_ring_idx];
2065
2066         if (skb_padto(skb, ETH_ZLEN))
2067                 return NETDEV_TX_OK;
2068
2069         if (unlikely(atomic_read(&tx_ring->tx_count) < 2)) {
2070                 QPRINTK(qdev, TX_QUEUED, INFO,
2071                         "%s: shutting down tx queue %d du to lack of resources.\n",
2072                         __func__, tx_ring_idx);
2073                 netif_stop_subqueue(ndev, tx_ring->wq_id);
2074                 atomic_inc(&tx_ring->queue_stopped);
2075                 return NETDEV_TX_BUSY;
2076         }
2077         tx_ring_desc = &tx_ring->q[tx_ring->prod_idx];
2078         mac_iocb_ptr = tx_ring_desc->queue_entry;
2079         memset((void *)mac_iocb_ptr, 0, sizeof(mac_iocb_ptr));
2080
2081         mac_iocb_ptr->opcode = OPCODE_OB_MAC_IOCB;
2082         mac_iocb_ptr->tid = tx_ring_desc->index;
2083         /* We use the upper 32-bits to store the tx queue for this IO.
2084          * When we get the completion we can use it to establish the context.
2085          */
2086         mac_iocb_ptr->txq_idx = tx_ring_idx;
2087         tx_ring_desc->skb = skb;
2088
2089         mac_iocb_ptr->frame_len = cpu_to_le16((u16) skb->len);
2090
2091         if (qdev->vlgrp && vlan_tx_tag_present(skb)) {
2092                 QPRINTK(qdev, TX_QUEUED, DEBUG, "Adding a vlan tag %d.\n",
2093                         vlan_tx_tag_get(skb));
2094                 mac_iocb_ptr->flags3 |= OB_MAC_IOCB_V;
2095                 mac_iocb_ptr->vlan_tci = cpu_to_le16(vlan_tx_tag_get(skb));
2096         }
2097         tso = ql_tso(skb, (struct ob_mac_tso_iocb_req *)mac_iocb_ptr);
2098         if (tso < 0) {
2099                 dev_kfree_skb_any(skb);
2100                 return NETDEV_TX_OK;
2101         } else if (unlikely(!tso) && (skb->ip_summed == CHECKSUM_PARTIAL)) {
2102                 ql_hw_csum_setup(skb,
2103                                  (struct ob_mac_tso_iocb_req *)mac_iocb_ptr);
2104         }
2105         if (ql_map_send(qdev, mac_iocb_ptr, skb, tx_ring_desc) !=
2106                         NETDEV_TX_OK) {
2107                 QPRINTK(qdev, TX_QUEUED, ERR,
2108                                 "Could not map the segments.\n");
2109                 return NETDEV_TX_BUSY;
2110         }
2111         QL_DUMP_OB_MAC_IOCB(mac_iocb_ptr);
2112         tx_ring->prod_idx++;
2113         if (tx_ring->prod_idx == tx_ring->wq_len)
2114                 tx_ring->prod_idx = 0;
2115         wmb();
2116
2117         ql_write_db_reg(tx_ring->prod_idx, tx_ring->prod_idx_db_reg);
2118         QPRINTK(qdev, TX_QUEUED, DEBUG, "tx queued, slot %d, len %d\n",
2119                 tx_ring->prod_idx, skb->len);
2120
2121         atomic_dec(&tx_ring->tx_count);
2122         return NETDEV_TX_OK;
2123 }
2124
2125 static void ql_free_shadow_space(struct ql_adapter *qdev)
2126 {
2127         if (qdev->rx_ring_shadow_reg_area) {
2128                 pci_free_consistent(qdev->pdev,
2129                                     PAGE_SIZE,
2130                                     qdev->rx_ring_shadow_reg_area,
2131                                     qdev->rx_ring_shadow_reg_dma);
2132                 qdev->rx_ring_shadow_reg_area = NULL;
2133         }
2134         if (qdev->tx_ring_shadow_reg_area) {
2135                 pci_free_consistent(qdev->pdev,
2136                                     PAGE_SIZE,
2137                                     qdev->tx_ring_shadow_reg_area,
2138                                     qdev->tx_ring_shadow_reg_dma);
2139                 qdev->tx_ring_shadow_reg_area = NULL;
2140         }
2141 }
2142
2143 static int ql_alloc_shadow_space(struct ql_adapter *qdev)
2144 {
2145         qdev->rx_ring_shadow_reg_area =
2146             pci_alloc_consistent(qdev->pdev,
2147                                  PAGE_SIZE, &qdev->rx_ring_shadow_reg_dma);
2148         if (qdev->rx_ring_shadow_reg_area == NULL) {
2149                 QPRINTK(qdev, IFUP, ERR,
2150                         "Allocation of RX shadow space failed.\n");
2151                 return -ENOMEM;
2152         }
2153         memset(qdev->rx_ring_shadow_reg_area, 0, PAGE_SIZE);
2154         qdev->tx_ring_shadow_reg_area =
2155             pci_alloc_consistent(qdev->pdev, PAGE_SIZE,
2156                                  &qdev->tx_ring_shadow_reg_dma);
2157         if (qdev->tx_ring_shadow_reg_area == NULL) {
2158                 QPRINTK(qdev, IFUP, ERR,
2159                         "Allocation of TX shadow space failed.\n");
2160                 goto err_wqp_sh_area;
2161         }
2162         memset(qdev->tx_ring_shadow_reg_area, 0, PAGE_SIZE);
2163         return 0;
2164
2165 err_wqp_sh_area:
2166         pci_free_consistent(qdev->pdev,
2167                             PAGE_SIZE,
2168                             qdev->rx_ring_shadow_reg_area,
2169                             qdev->rx_ring_shadow_reg_dma);
2170         return -ENOMEM;
2171 }
2172
2173 static void ql_init_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring)
2174 {
2175         struct tx_ring_desc *tx_ring_desc;
2176         int i;
2177         struct ob_mac_iocb_req *mac_iocb_ptr;
2178
2179         mac_iocb_ptr = tx_ring->wq_base;
2180         tx_ring_desc = tx_ring->q;
2181         for (i = 0; i < tx_ring->wq_len; i++) {
2182                 tx_ring_desc->index = i;
2183                 tx_ring_desc->skb = NULL;
2184                 tx_ring_desc->queue_entry = mac_iocb_ptr;
2185                 mac_iocb_ptr++;
2186                 tx_ring_desc++;
2187         }
2188         atomic_set(&tx_ring->tx_count, tx_ring->wq_len);
2189         atomic_set(&tx_ring->queue_stopped, 0);
2190 }
2191
2192 static void ql_free_tx_resources(struct ql_adapter *qdev,
2193                                  struct tx_ring *tx_ring)
2194 {
2195         if (tx_ring->wq_base) {
2196                 pci_free_consistent(qdev->pdev, tx_ring->wq_size,
2197                                     tx_ring->wq_base, tx_ring->wq_base_dma);
2198                 tx_ring->wq_base = NULL;
2199         }
2200         kfree(tx_ring->q);
2201         tx_ring->q = NULL;
2202 }
2203
2204 static int ql_alloc_tx_resources(struct ql_adapter *qdev,
2205                                  struct tx_ring *tx_ring)
2206 {
2207         tx_ring->wq_base =
2208             pci_alloc_consistent(qdev->pdev, tx_ring->wq_size,
2209                                  &tx_ring->wq_base_dma);
2210
2211         if ((tx_ring->wq_base == NULL)
2212             || tx_ring->wq_base_dma & (tx_ring->wq_size - 1)) {
2213                 QPRINTK(qdev, IFUP, ERR, "tx_ring alloc failed.\n");
2214                 return -ENOMEM;
2215         }
2216         tx_ring->q =
2217             kmalloc(tx_ring->wq_len * sizeof(struct tx_ring_desc), GFP_KERNEL);
2218         if (tx_ring->q == NULL)
2219                 goto err;
2220
2221         return 0;
2222 err:
2223         pci_free_consistent(qdev->pdev, tx_ring->wq_size,
2224                             tx_ring->wq_base, tx_ring->wq_base_dma);
2225         return -ENOMEM;
2226 }
2227
2228 static void ql_free_lbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2229 {
2230         int i;
2231         struct bq_desc *lbq_desc;
2232
2233         for (i = 0; i < rx_ring->lbq_len; i++) {
2234                 lbq_desc = &rx_ring->lbq[i];
2235                 if (lbq_desc->p.lbq_page) {
2236                         pci_unmap_page(qdev->pdev,
2237                                        pci_unmap_addr(lbq_desc, mapaddr),
2238                                        pci_unmap_len(lbq_desc, maplen),
2239                                        PCI_DMA_FROMDEVICE);
2240
2241                         put_page(lbq_desc->p.lbq_page);
2242                         lbq_desc->p.lbq_page = NULL;
2243                 }
2244         }
2245 }
2246
2247 static void ql_free_sbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2248 {
2249         int i;
2250         struct bq_desc *sbq_desc;
2251
2252         for (i = 0; i < rx_ring->sbq_len; i++) {
2253                 sbq_desc = &rx_ring->sbq[i];
2254                 if (sbq_desc == NULL) {
2255                         QPRINTK(qdev, IFUP, ERR, "sbq_desc %d is NULL.\n", i);
2256                         return;
2257                 }
2258                 if (sbq_desc->p.skb) {
2259                         pci_unmap_single(qdev->pdev,
2260                                          pci_unmap_addr(sbq_desc, mapaddr),
2261                                          pci_unmap_len(sbq_desc, maplen),
2262                                          PCI_DMA_FROMDEVICE);
2263                         dev_kfree_skb(sbq_desc->p.skb);
2264                         sbq_desc->p.skb = NULL;
2265                 }
2266         }
2267 }
2268
2269 /* Free all large and small rx buffers associated
2270  * with the completion queues for this device.
2271  */
2272 static void ql_free_rx_buffers(struct ql_adapter *qdev)
2273 {
2274         int i;
2275         struct rx_ring *rx_ring;
2276
2277         for (i = 0; i < qdev->rx_ring_count; i++) {
2278                 rx_ring = &qdev->rx_ring[i];
2279                 if (rx_ring->lbq)
2280                         ql_free_lbq_buffers(qdev, rx_ring);
2281                 if (rx_ring->sbq)
2282                         ql_free_sbq_buffers(qdev, rx_ring);
2283         }
2284 }
2285
2286 static void ql_alloc_rx_buffers(struct ql_adapter *qdev)
2287 {
2288         struct rx_ring *rx_ring;
2289         int i;
2290
2291         for (i = 0; i < qdev->rx_ring_count; i++) {
2292                 rx_ring = &qdev->rx_ring[i];
2293                 if (rx_ring->type != TX_Q)
2294                         ql_update_buffer_queues(qdev, rx_ring);
2295         }
2296 }
2297
2298 static void ql_init_lbq_ring(struct ql_adapter *qdev,
2299                                 struct rx_ring *rx_ring)
2300 {
2301         int i;
2302         struct bq_desc *lbq_desc;
2303         __le64 *bq = rx_ring->lbq_base;
2304
2305         memset(rx_ring->lbq, 0, rx_ring->lbq_len * sizeof(struct bq_desc));
2306         for (i = 0; i < rx_ring->lbq_len; i++) {
2307                 lbq_desc = &rx_ring->lbq[i];
2308                 memset(lbq_desc, 0, sizeof(*lbq_desc));
2309                 lbq_desc->index = i;
2310                 lbq_desc->addr = bq;
2311                 bq++;
2312         }
2313 }
2314
2315 static void ql_init_sbq_ring(struct ql_adapter *qdev,
2316                                 struct rx_ring *rx_ring)
2317 {
2318         int i;
2319         struct bq_desc *sbq_desc;
2320         __le64 *bq = rx_ring->sbq_base;
2321
2322         memset(rx_ring->sbq, 0, rx_ring->sbq_len * sizeof(struct bq_desc));
2323         for (i = 0; i < rx_ring->sbq_len; i++) {
2324                 sbq_desc = &rx_ring->sbq[i];
2325                 memset(sbq_desc, 0, sizeof(*sbq_desc));
2326                 sbq_desc->index = i;
2327                 sbq_desc->addr = bq;
2328                 bq++;
2329         }
2330 }
2331
2332 static void ql_free_rx_resources(struct ql_adapter *qdev,
2333                                  struct rx_ring *rx_ring)
2334 {
2335         /* Free the small buffer queue. */
2336         if (rx_ring->sbq_base) {
2337                 pci_free_consistent(qdev->pdev,
2338                                     rx_ring->sbq_size,
2339                                     rx_ring->sbq_base, rx_ring->sbq_base_dma);
2340                 rx_ring->sbq_base = NULL;
2341         }
2342
2343         /* Free the small buffer queue control blocks. */
2344         kfree(rx_ring->sbq);
2345         rx_ring->sbq = NULL;
2346
2347         /* Free the large buffer queue. */
2348         if (rx_ring->lbq_base) {
2349                 pci_free_consistent(qdev->pdev,
2350                                     rx_ring->lbq_size,
2351                                     rx_ring->lbq_base, rx_ring->lbq_base_dma);
2352                 rx_ring->lbq_base = NULL;
2353         }
2354
2355         /* Free the large buffer queue control blocks. */
2356         kfree(rx_ring->lbq);
2357         rx_ring->lbq = NULL;
2358
2359         /* Free the rx queue. */
2360         if (rx_ring->cq_base) {
2361                 pci_free_consistent(qdev->pdev,
2362                                     rx_ring->cq_size,
2363                                     rx_ring->cq_base, rx_ring->cq_base_dma);
2364                 rx_ring->cq_base = NULL;
2365         }
2366 }
2367
2368 /* Allocate queues and buffers for this completions queue based
2369  * on the values in the parameter structure. */
2370 static int ql_alloc_rx_resources(struct ql_adapter *qdev,
2371                                  struct rx_ring *rx_ring)
2372 {
2373
2374         /*
2375          * Allocate the completion queue for this rx_ring.
2376          */
2377         rx_ring->cq_base =
2378             pci_alloc_consistent(qdev->pdev, rx_ring->cq_size,
2379                                  &rx_ring->cq_base_dma);
2380
2381         if (rx_ring->cq_base == NULL) {
2382                 QPRINTK(qdev, IFUP, ERR, "rx_ring alloc failed.\n");
2383                 return -ENOMEM;
2384         }
2385
2386         if (rx_ring->sbq_len) {
2387                 /*
2388                  * Allocate small buffer queue.
2389                  */
2390                 rx_ring->sbq_base =
2391                     pci_alloc_consistent(qdev->pdev, rx_ring->sbq_size,
2392                                          &rx_ring->sbq_base_dma);
2393
2394                 if (rx_ring->sbq_base == NULL) {
2395                         QPRINTK(qdev, IFUP, ERR,
2396                                 "Small buffer queue allocation failed.\n");
2397                         goto err_mem;
2398                 }
2399
2400                 /*
2401                  * Allocate small buffer queue control blocks.
2402                  */
2403                 rx_ring->sbq =
2404                     kmalloc(rx_ring->sbq_len * sizeof(struct bq_desc),
2405                             GFP_KERNEL);
2406                 if (rx_ring->sbq == NULL) {
2407                         QPRINTK(qdev, IFUP, ERR,
2408                                 "Small buffer queue control block allocation failed.\n");
2409                         goto err_mem;
2410                 }
2411
2412                 ql_init_sbq_ring(qdev, rx_ring);
2413         }
2414
2415         if (rx_ring->lbq_len) {
2416                 /*
2417                  * Allocate large buffer queue.
2418                  */
2419                 rx_ring->lbq_base =
2420                     pci_alloc_consistent(qdev->pdev, rx_ring->lbq_size,
2421                                          &rx_ring->lbq_base_dma);
2422
2423                 if (rx_ring->lbq_base == NULL) {
2424                         QPRINTK(qdev, IFUP, ERR,
2425                                 "Large buffer queue allocation failed.\n");
2426                         goto err_mem;
2427                 }
2428                 /*
2429                  * Allocate large buffer queue control blocks.
2430                  */
2431                 rx_ring->lbq =
2432                     kmalloc(rx_ring->lbq_len * sizeof(struct bq_desc),
2433                             GFP_KERNEL);
2434                 if (rx_ring->lbq == NULL) {
2435                         QPRINTK(qdev, IFUP, ERR,
2436                                 "Large buffer queue control block allocation failed.\n");
2437                         goto err_mem;
2438                 }
2439
2440                 ql_init_lbq_ring(qdev, rx_ring);
2441         }
2442
2443         return 0;
2444
2445 err_mem:
2446         ql_free_rx_resources(qdev, rx_ring);
2447         return -ENOMEM;
2448 }
2449
2450 static void ql_tx_ring_clean(struct ql_adapter *qdev)
2451 {
2452         struct tx_ring *tx_ring;
2453         struct tx_ring_desc *tx_ring_desc;
2454         int i, j;
2455
2456         /*
2457          * Loop through all queues and free
2458          * any resources.
2459          */
2460         for (j = 0; j < qdev->tx_ring_count; j++) {
2461                 tx_ring = &qdev->tx_ring[j];
2462                 for (i = 0; i < tx_ring->wq_len; i++) {
2463                         tx_ring_desc = &tx_ring->q[i];
2464                         if (tx_ring_desc && tx_ring_desc->skb) {
2465                                 QPRINTK(qdev, IFDOWN, ERR,
2466                                 "Freeing lost SKB %p, from queue %d, index %d.\n",
2467                                         tx_ring_desc->skb, j,
2468                                         tx_ring_desc->index);
2469                                 ql_unmap_send(qdev, tx_ring_desc,
2470                                               tx_ring_desc->map_cnt);
2471                                 dev_kfree_skb(tx_ring_desc->skb);
2472                                 tx_ring_desc->skb = NULL;
2473                         }
2474                 }
2475         }
2476 }
2477
2478 static void ql_free_mem_resources(struct ql_adapter *qdev)
2479 {
2480         int i;
2481
2482         for (i = 0; i < qdev->tx_ring_count; i++)
2483                 ql_free_tx_resources(qdev, &qdev->tx_ring[i]);
2484         for (i = 0; i < qdev->rx_ring_count; i++)
2485                 ql_free_rx_resources(qdev, &qdev->rx_ring[i]);
2486         ql_free_shadow_space(qdev);
2487 }
2488
2489 static int ql_alloc_mem_resources(struct ql_adapter *qdev)
2490 {
2491         int i;
2492
2493         /* Allocate space for our shadow registers and such. */
2494         if (ql_alloc_shadow_space(qdev))
2495                 return -ENOMEM;
2496
2497         for (i = 0; i < qdev->rx_ring_count; i++) {
2498                 if (ql_alloc_rx_resources(qdev, &qdev->rx_ring[i]) != 0) {
2499                         QPRINTK(qdev, IFUP, ERR,
2500                                 "RX resource allocation failed.\n");
2501                         goto err_mem;
2502                 }
2503         }
2504         /* Allocate tx queue resources */
2505         for (i = 0; i < qdev->tx_ring_count; i++) {
2506                 if (ql_alloc_tx_resources(qdev, &qdev->tx_ring[i]) != 0) {
2507                         QPRINTK(qdev, IFUP, ERR,
2508                                 "TX resource allocation failed.\n");
2509                         goto err_mem;
2510                 }
2511         }
2512         return 0;
2513
2514 err_mem:
2515         ql_free_mem_resources(qdev);
2516         return -ENOMEM;
2517 }
2518
2519 /* Set up the rx ring control block and pass it to the chip.
2520  * The control block is defined as
2521  * "Completion Queue Initialization Control Block", or cqicb.
2522  */
2523 static int ql_start_rx_ring(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2524 {
2525         struct cqicb *cqicb = &rx_ring->cqicb;
2526         void *shadow_reg = qdev->rx_ring_shadow_reg_area +
2527             (rx_ring->cq_id * sizeof(u64) * 4);
2528         u64 shadow_reg_dma = qdev->rx_ring_shadow_reg_dma +
2529             (rx_ring->cq_id * sizeof(u64) * 4);
2530         void __iomem *doorbell_area =
2531             qdev->doorbell_area + (DB_PAGE_SIZE * (128 + rx_ring->cq_id));
2532         int err = 0;
2533         u16 bq_len;
2534         u64 tmp;
2535
2536         /* Set up the shadow registers for this ring. */
2537         rx_ring->prod_idx_sh_reg = shadow_reg;
2538         rx_ring->prod_idx_sh_reg_dma = shadow_reg_dma;
2539         shadow_reg += sizeof(u64);
2540         shadow_reg_dma += sizeof(u64);
2541         rx_ring->lbq_base_indirect = shadow_reg;
2542         rx_ring->lbq_base_indirect_dma = shadow_reg_dma;
2543         shadow_reg += sizeof(u64);
2544         shadow_reg_dma += sizeof(u64);
2545         rx_ring->sbq_base_indirect = shadow_reg;
2546         rx_ring->sbq_base_indirect_dma = shadow_reg_dma;
2547
2548         /* PCI doorbell mem area + 0x00 for consumer index register */
2549         rx_ring->cnsmr_idx_db_reg = (u32 __iomem *) doorbell_area;
2550         rx_ring->cnsmr_idx = 0;
2551         rx_ring->curr_entry = rx_ring->cq_base;
2552
2553         /* PCI doorbell mem area + 0x04 for valid register */
2554         rx_ring->valid_db_reg = doorbell_area + 0x04;
2555
2556         /* PCI doorbell mem area + 0x18 for large buffer consumer */
2557         rx_ring->lbq_prod_idx_db_reg = (u32 __iomem *) (doorbell_area + 0x18);
2558
2559         /* PCI doorbell mem area + 0x1c */
2560         rx_ring->sbq_prod_idx_db_reg = (u32 __iomem *) (doorbell_area + 0x1c);
2561
2562         memset((void *)cqicb, 0, sizeof(struct cqicb));
2563         cqicb->msix_vect = rx_ring->irq;
2564
2565         bq_len = (rx_ring->cq_len == 65536) ? 0 : (u16) rx_ring->cq_len;
2566         cqicb->len = cpu_to_le16(bq_len | LEN_V | LEN_CPP_CONT);
2567
2568         cqicb->addr = cpu_to_le64(rx_ring->cq_base_dma);
2569
2570         cqicb->prod_idx_addr = cpu_to_le64(rx_ring->prod_idx_sh_reg_dma);
2571
2572         /*
2573          * Set up the control block load flags.
2574          */
2575         cqicb->flags = FLAGS_LC |       /* Load queue base address */
2576             FLAGS_LV |          /* Load MSI-X vector */
2577             FLAGS_LI;           /* Load irq delay values */
2578         if (rx_ring->lbq_len) {
2579                 cqicb->flags |= FLAGS_LL;       /* Load lbq values */
2580                 tmp = (u64)rx_ring->lbq_base_dma;;
2581                 *((__le64 *) rx_ring->lbq_base_indirect) = cpu_to_le64(tmp);
2582                 cqicb->lbq_addr =
2583                     cpu_to_le64(rx_ring->lbq_base_indirect_dma);
2584                 bq_len = (rx_ring->lbq_buf_size == 65536) ? 0 :
2585                         (u16) rx_ring->lbq_buf_size;
2586                 cqicb->lbq_buf_size = cpu_to_le16(bq_len);
2587                 bq_len = (rx_ring->lbq_len == 65536) ? 0 :
2588                         (u16) rx_ring->lbq_len;
2589                 cqicb->lbq_len = cpu_to_le16(bq_len);
2590                 rx_ring->lbq_prod_idx = 0;
2591                 rx_ring->lbq_curr_idx = 0;
2592                 rx_ring->lbq_clean_idx = 0;
2593                 rx_ring->lbq_free_cnt = rx_ring->lbq_len;
2594         }
2595         if (rx_ring->sbq_len) {
2596                 cqicb->flags |= FLAGS_LS;       /* Load sbq values */
2597                 tmp = (u64)rx_ring->sbq_base_dma;;
2598                 *((__le64 *) rx_ring->sbq_base_indirect) = cpu_to_le64(tmp);
2599                 cqicb->sbq_addr =
2600                     cpu_to_le64(rx_ring->sbq_base_indirect_dma);
2601                 cqicb->sbq_buf_size =
2602                     cpu_to_le16((u16)(rx_ring->sbq_buf_size/2));
2603                 bq_len = (rx_ring->sbq_len == 65536) ? 0 :
2604                         (u16) rx_ring->sbq_len;
2605                 cqicb->sbq_len = cpu_to_le16(bq_len);
2606                 rx_ring->sbq_prod_idx = 0;
2607                 rx_ring->sbq_curr_idx = 0;
2608                 rx_ring->sbq_clean_idx = 0;
2609                 rx_ring->sbq_free_cnt = rx_ring->sbq_len;
2610         }
2611         switch (rx_ring->type) {
2612         case TX_Q:
2613                 /* If there's only one interrupt, then we use
2614                  * worker threads to process the outbound
2615                  * completion handling rx_rings. We do this so
2616                  * they can be run on multiple CPUs. There is
2617                  * room to play with this more where we would only
2618                  * run in a worker if there are more than x number
2619                  * of outbound completions on the queue and more
2620                  * than one queue active.  Some threshold that
2621                  * would indicate a benefit in spite of the cost
2622                  * of a context switch.
2623                  * If there's more than one interrupt, then the
2624                  * outbound completions are processed in the ISR.
2625                  */
2626                 if (!test_bit(QL_MSIX_ENABLED, &qdev->flags))
2627                         INIT_DELAYED_WORK(&rx_ring->rx_work, ql_tx_clean);
2628                 else {
2629                         /* With all debug warnings on we see a WARN_ON message
2630                          * when we free the skb in the interrupt context.
2631                          */
2632                         INIT_DELAYED_WORK(&rx_ring->rx_work, ql_tx_clean);
2633                 }
2634                 cqicb->irq_delay = cpu_to_le16(qdev->tx_coalesce_usecs);
2635                 cqicb->pkt_delay = cpu_to_le16(qdev->tx_max_coalesced_frames);
2636                 break;
2637         case DEFAULT_Q:
2638                 INIT_DELAYED_WORK(&rx_ring->rx_work, ql_rx_clean);
2639                 cqicb->irq_delay = 0;
2640                 cqicb->pkt_delay = 0;
2641                 break;
2642         case RX_Q:
2643                 /* Inbound completion handling rx_rings run in
2644                  * separate NAPI contexts.
2645                  */
2646                 netif_napi_add(qdev->ndev, &rx_ring->napi, ql_napi_poll_msix,
2647                                64);
2648                 cqicb->irq_delay = cpu_to_le16(qdev->rx_coalesce_usecs);
2649                 cqicb->pkt_delay = cpu_to_le16(qdev->rx_max_coalesced_frames);
2650                 break;
2651         default:
2652                 QPRINTK(qdev, IFUP, DEBUG, "Invalid rx_ring->type = %d.\n",
2653                         rx_ring->type);
2654         }
2655         QPRINTK(qdev, IFUP, DEBUG, "Initializing rx work queue.\n");
2656         err = ql_write_cfg(qdev, cqicb, sizeof(struct cqicb),
2657                            CFG_LCQ, rx_ring->cq_id);
2658         if (err) {
2659                 QPRINTK(qdev, IFUP, ERR, "Failed to load CQICB.\n");
2660                 return err;
2661         }
2662         return err;
2663 }
2664
2665 static int ql_start_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring)
2666 {
2667         struct wqicb *wqicb = (struct wqicb *)tx_ring;
2668         void __iomem *doorbell_area =
2669             qdev->doorbell_area + (DB_PAGE_SIZE * tx_ring->wq_id);
2670         void *shadow_reg = qdev->tx_ring_shadow_reg_area +
2671             (tx_ring->wq_id * sizeof(u64));
2672         u64 shadow_reg_dma = qdev->tx_ring_shadow_reg_dma +
2673             (tx_ring->wq_id * sizeof(u64));
2674         int err = 0;
2675
2676         /*
2677          * Assign doorbell registers for this tx_ring.
2678          */
2679         /* TX PCI doorbell mem area for tx producer index */
2680         tx_ring->prod_idx_db_reg = (u32 __iomem *) doorbell_area;
2681         tx_ring->prod_idx = 0;
2682         /* TX PCI doorbell mem area + 0x04 */
2683         tx_ring->valid_db_reg = doorbell_area + 0x04;
2684
2685         /*
2686          * Assign shadow registers for this tx_ring.
2687          */
2688         tx_ring->cnsmr_idx_sh_reg = shadow_reg;
2689         tx_ring->cnsmr_idx_sh_reg_dma = shadow_reg_dma;
2690
2691         wqicb->len = cpu_to_le16(tx_ring->wq_len | Q_LEN_V | Q_LEN_CPP_CONT);
2692         wqicb->flags = cpu_to_le16(Q_FLAGS_LC |
2693                                    Q_FLAGS_LB | Q_FLAGS_LI | Q_FLAGS_LO);
2694         wqicb->cq_id_rss = cpu_to_le16(tx_ring->cq_id);
2695         wqicb->rid = 0;
2696         wqicb->addr = cpu_to_le64(tx_ring->wq_base_dma);
2697
2698         wqicb->cnsmr_idx_addr = cpu_to_le64(tx_ring->cnsmr_idx_sh_reg_dma);
2699
2700         ql_init_tx_ring(qdev, tx_ring);
2701
2702         err = ql_write_cfg(qdev, wqicb, sizeof(wqicb), CFG_LRQ,
2703                            (u16) tx_ring->wq_id);
2704         if (err) {
2705                 QPRINTK(qdev, IFUP, ERR, "Failed to load tx_ring.\n");
2706                 return err;
2707         }
2708         QPRINTK(qdev, IFUP, DEBUG, "Successfully loaded WQICB.\n");
2709         return err;
2710 }
2711
2712 static void ql_disable_msix(struct ql_adapter *qdev)
2713 {
2714         if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2715                 pci_disable_msix(qdev->pdev);
2716                 clear_bit(QL_MSIX_ENABLED, &qdev->flags);
2717                 kfree(qdev->msi_x_entry);
2718                 qdev->msi_x_entry = NULL;
2719         } else if (test_bit(QL_MSI_ENABLED, &qdev->flags)) {
2720                 pci_disable_msi(qdev->pdev);
2721                 clear_bit(QL_MSI_ENABLED, &qdev->flags);
2722         }
2723 }
2724
2725 static void ql_enable_msix(struct ql_adapter *qdev)
2726 {
2727         int i;
2728
2729         qdev->intr_count = 1;
2730         /* Get the MSIX vectors. */
2731         if (irq_type == MSIX_IRQ) {
2732                 /* Try to alloc space for the msix struct,
2733                  * if it fails then go to MSI/legacy.
2734                  */
2735                 qdev->msi_x_entry = kcalloc(qdev->rx_ring_count,
2736                                             sizeof(struct msix_entry),
2737                                             GFP_KERNEL);
2738                 if (!qdev->msi_x_entry) {
2739                         irq_type = MSI_IRQ;
2740                         goto msi;
2741                 }
2742
2743                 for (i = 0; i < qdev->rx_ring_count; i++)
2744                         qdev->msi_x_entry[i].entry = i;
2745
2746                 if (!pci_enable_msix
2747                     (qdev->pdev, qdev->msi_x_entry, qdev->rx_ring_count)) {
2748                         set_bit(QL_MSIX_ENABLED, &qdev->flags);
2749                         qdev->intr_count = qdev->rx_ring_count;
2750                         QPRINTK(qdev, IFUP, DEBUG,
2751                                 "MSI-X Enabled, got %d vectors.\n",
2752                                 qdev->intr_count);
2753                         return;
2754                 } else {
2755                         kfree(qdev->msi_x_entry);
2756                         qdev->msi_x_entry = NULL;
2757                         QPRINTK(qdev, IFUP, WARNING,
2758                                 "MSI-X Enable failed, trying MSI.\n");
2759                         irq_type = MSI_IRQ;
2760                 }
2761         }
2762 msi:
2763         if (irq_type == MSI_IRQ) {
2764                 if (!pci_enable_msi(qdev->pdev)) {
2765                         set_bit(QL_MSI_ENABLED, &qdev->flags);
2766                         QPRINTK(qdev, IFUP, INFO,
2767                                 "Running with MSI interrupts.\n");
2768                         return;
2769                 }
2770         }
2771         irq_type = LEG_IRQ;
2772         QPRINTK(qdev, IFUP, DEBUG, "Running with legacy interrupts.\n");
2773 }
2774
2775 /*
2776  * Here we build the intr_context structures based on
2777  * our rx_ring count and intr vector count.
2778  * The intr_context structure is used to hook each vector
2779  * to possibly different handlers.
2780  */
2781 static void ql_resolve_queues_to_irqs(struct ql_adapter *qdev)
2782 {
2783         int i = 0;
2784         struct intr_context *intr_context = &qdev->intr_context[0];
2785
2786         ql_enable_msix(qdev);
2787
2788         if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags))) {
2789                 /* Each rx_ring has it's
2790                  * own intr_context since we have separate
2791                  * vectors for each queue.
2792                  * This only true when MSI-X is enabled.
2793                  */
2794                 for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2795                         qdev->rx_ring[i].irq = i;
2796                         intr_context->intr = i;
2797                         intr_context->qdev = qdev;
2798                         /*
2799                          * We set up each vectors enable/disable/read bits so
2800                          * there's no bit/mask calculations in the critical path.
2801                          */
2802                         intr_context->intr_en_mask =
2803                             INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2804                             INTR_EN_TYPE_ENABLE | INTR_EN_IHD_MASK | INTR_EN_IHD
2805                             | i;
2806                         intr_context->intr_dis_mask =
2807                             INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2808                             INTR_EN_TYPE_DISABLE | INTR_EN_IHD_MASK |
2809                             INTR_EN_IHD | i;
2810                         intr_context->intr_read_mask =
2811                             INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2812                             INTR_EN_TYPE_READ | INTR_EN_IHD_MASK | INTR_EN_IHD |
2813                             i;
2814
2815                         if (i == 0) {
2816                                 /*
2817                                  * Default queue handles bcast/mcast plus
2818                                  * async events.  Needs buffers.
2819                                  */
2820                                 intr_context->handler = qlge_isr;
2821                                 sprintf(intr_context->name, "%s-default-queue",
2822                                         qdev->ndev->name);
2823                         } else if (i < qdev->rss_ring_first_cq_id) {
2824                                 /*
2825                                  * Outbound queue is for outbound completions only.
2826                                  */
2827                                 intr_context->handler = qlge_msix_tx_isr;
2828                                 sprintf(intr_context->name, "%s-tx-%d",
2829                                         qdev->ndev->name, i);
2830                         } else {
2831                                 /*
2832                                  * Inbound queues handle unicast frames only.
2833                                  */
2834                                 intr_context->handler = qlge_msix_rx_isr;
2835                                 sprintf(intr_context->name, "%s-rx-%d",
2836                                         qdev->ndev->name, i);
2837                         }
2838                 }
2839         } else {
2840                 /*
2841                  * All rx_rings use the same intr_context since
2842                  * there is only one vector.
2843                  */
2844                 intr_context->intr = 0;
2845                 intr_context->qdev = qdev;
2846                 /*
2847                  * We set up each vectors enable/disable/read bits so
2848                  * there's no bit/mask calculations in the critical path.
2849                  */
2850                 intr_context->intr_en_mask =
2851                     INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_ENABLE;
2852                 intr_context->intr_dis_mask =
2853                     INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2854                     INTR_EN_TYPE_DISABLE;
2855                 intr_context->intr_read_mask =
2856                     INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_READ;
2857                 /*
2858                  * Single interrupt means one handler for all rings.
2859                  */
2860                 intr_context->handler = qlge_isr;
2861                 sprintf(intr_context->name, "%s-single_irq", qdev->ndev->name);
2862                 for (i = 0; i < qdev->rx_ring_count; i++)
2863                         qdev->rx_ring[i].irq = 0;
2864         }
2865 }
2866
2867 static void ql_free_irq(struct ql_adapter *qdev)
2868 {
2869         int i;
2870         struct intr_context *intr_context = &qdev->intr_context[0];
2871
2872         for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2873                 if (intr_context->hooked) {
2874                         if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2875                                 free_irq(qdev->msi_x_entry[i].vector,
2876                                          &qdev->rx_ring[i]);
2877                                 QPRINTK(qdev, IFDOWN, DEBUG,
2878                                         "freeing msix interrupt %d.\n", i);
2879                         } else {
2880                                 free_irq(qdev->pdev->irq, &qdev->rx_ring[0]);
2881                                 QPRINTK(qdev, IFDOWN, DEBUG,
2882                                         "freeing msi interrupt %d.\n", i);
2883                         }
2884                 }
2885         }
2886         ql_disable_msix(qdev);
2887 }
2888
2889 static int ql_request_irq(struct ql_adapter *qdev)
2890 {
2891         int i;
2892         int status = 0;
2893         struct pci_dev *pdev = qdev->pdev;
2894         struct intr_context *intr_context = &qdev->intr_context[0];
2895
2896         ql_resolve_queues_to_irqs(qdev);
2897
2898         for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2899                 atomic_set(&intr_context->irq_cnt, 0);
2900                 if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2901                         status = request_irq(qdev->msi_x_entry[i].vector,
2902                                              intr_context->handler,
2903                                              0,
2904                                              intr_context->name,
2905                                              &qdev->rx_ring[i]);
2906                         if (status) {
2907                                 QPRINTK(qdev, IFUP, ERR,
2908                                         "Failed request for MSIX interrupt %d.\n",
2909                                         i);
2910                                 goto err_irq;
2911                         } else {
2912                                 QPRINTK(qdev, IFUP, DEBUG,
2913                                         "Hooked intr %d, queue type %s%s%s, with name %s.\n",
2914                                         i,
2915                                         qdev->rx_ring[i].type ==
2916                                         DEFAULT_Q ? "DEFAULT_Q" : "",
2917                                         qdev->rx_ring[i].type ==
2918                                         TX_Q ? "TX_Q" : "",
2919                                         qdev->rx_ring[i].type ==
2920                                         RX_Q ? "RX_Q" : "", intr_context->name);
2921                         }
2922                 } else {
2923                         QPRINTK(qdev, IFUP, DEBUG,
2924                                 "trying msi or legacy interrupts.\n");
2925                         QPRINTK(qdev, IFUP, DEBUG,
2926                                 "%s: irq = %d.\n", __func__, pdev->irq);
2927                         QPRINTK(qdev, IFUP, DEBUG,
2928                                 "%s: context->name = %s.\n", __func__,
2929                                intr_context->name);
2930                         QPRINTK(qdev, IFUP, DEBUG,
2931                                 "%s: dev_id = 0x%p.\n", __func__,
2932                                &qdev->rx_ring[0]);
2933                         status =
2934                             request_irq(pdev->irq, qlge_isr,
2935                                         test_bit(QL_MSI_ENABLED,
2936                                                  &qdev->
2937                                                  flags) ? 0 : IRQF_SHARED,
2938                                         intr_context->name, &qdev->rx_ring[0]);
2939                         if (status)
2940                                 goto err_irq;
2941
2942                         QPRINTK(qdev, IFUP, ERR,
2943                                 "Hooked intr %d, queue type %s%s%s, with name %s.\n",
2944                                 i,
2945                                 qdev->rx_ring[0].type ==
2946                                 DEFAULT_Q ? "DEFAULT_Q" : "",
2947                                 qdev->rx_ring[0].type == TX_Q ? "TX_Q" : "",
2948                                 qdev->rx_ring[0].type == RX_Q ? "RX_Q" : "",
2949                                 intr_context->name);
2950                 }
2951                 intr_context->hooked = 1;
2952         }
2953         return status;
2954 err_irq:
2955         QPRINTK(qdev, IFUP, ERR, "Failed to get the interrupts!!!/n");
2956         ql_free_irq(qdev);
2957         return status;
2958 }
2959
2960 static int ql_start_rss(struct ql_adapter *qdev)
2961 {
2962         struct ricb *ricb = &qdev->ricb;
2963         int status = 0;
2964         int i;
2965         u8 *hash_id = (u8 *) ricb->hash_cq_id;
2966
2967         memset((void *)ricb, 0, sizeof(ricb));
2968
2969         ricb->base_cq = qdev->rss_ring_first_cq_id | RSS_L4K;
2970         ricb->flags =
2971             (RSS_L6K | RSS_LI | RSS_LB | RSS_LM | RSS_RI4 | RSS_RI6 | RSS_RT4 |
2972              RSS_RT6);
2973         ricb->mask = cpu_to_le16(qdev->rss_ring_count - 1);
2974
2975         /*
2976          * Fill out the Indirection Table.
2977          */
2978         for (i = 0; i < 256; i++)
2979                 hash_id[i] = i & (qdev->rss_ring_count - 1);
2980
2981         /*
2982          * Random values for the IPv6 and IPv4 Hash Keys.
2983          */
2984         get_random_bytes((void *)&ricb->ipv6_hash_key[0], 40);
2985         get_random_bytes((void *)&ricb->ipv4_hash_key[0], 16);
2986
2987         QPRINTK(qdev, IFUP, DEBUG, "Initializing RSS.\n");
2988
2989         status = ql_write_cfg(qdev, ricb, sizeof(ricb), CFG_LR, 0);
2990         if (status) {
2991                 QPRINTK(qdev, IFUP, ERR, "Failed to load RICB.\n");
2992                 return status;
2993         }
2994         QPRINTK(qdev, IFUP, DEBUG, "Successfully loaded RICB.\n");
2995         return status;
2996 }
2997
2998 /* Initialize the frame-to-queue routing. */
2999 static int ql_route_initialize(struct ql_adapter *qdev)
3000 {
3001         int status = 0;
3002         int i;
3003
3004         status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
3005         if (status)
3006                 return status;
3007
3008         /* Clear all the entries in the routing table. */
3009         for (i = 0; i < 16; i++) {
3010                 status = ql_set_routing_reg(qdev, i, 0, 0);
3011                 if (status) {
3012                         QPRINTK(qdev, IFUP, ERR,
3013                                 "Failed to init routing register for CAM packets.\n");
3014                         goto exit;
3015                 }
3016         }
3017
3018         status = ql_set_routing_reg(qdev, RT_IDX_ALL_ERR_SLOT, RT_IDX_ERR, 1);
3019         if (status) {
3020                 QPRINTK(qdev, IFUP, ERR,
3021                         "Failed to init routing register for error packets.\n");
3022                 goto exit;
3023         }
3024         status = ql_set_routing_reg(qdev, RT_IDX_BCAST_SLOT, RT_IDX_BCAST, 1);
3025         if (status) {
3026                 QPRINTK(qdev, IFUP, ERR,
3027                         "Failed to init routing register for broadcast packets.\n");
3028                 goto exit;
3029         }
3030         /* If we have more than one inbound queue, then turn on RSS in the
3031          * routing block.
3032          */
3033         if (qdev->rss_ring_count > 1) {
3034                 status = ql_set_routing_reg(qdev, RT_IDX_RSS_MATCH_SLOT,
3035                                         RT_IDX_RSS_MATCH, 1);
3036                 if (status) {
3037                         QPRINTK(qdev, IFUP, ERR,
3038                                 "Failed to init routing register for MATCH RSS packets.\n");
3039                         goto exit;
3040                 }
3041         }
3042
3043         status = ql_set_routing_reg(qdev, RT_IDX_CAM_HIT_SLOT,
3044                                     RT_IDX_CAM_HIT, 1);
3045         if (status)
3046                 QPRINTK(qdev, IFUP, ERR,
3047                         "Failed to init routing register for CAM packets.\n");
3048 exit:
3049         ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
3050         return status;
3051 }
3052
3053 int ql_cam_route_initialize(struct ql_adapter *qdev)
3054 {
3055         int status;
3056
3057         status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
3058         if (status)
3059                 return status;
3060         status = ql_set_mac_addr_reg(qdev, (u8 *) qdev->ndev->perm_addr,
3061                              MAC_ADDR_TYPE_CAM_MAC, qdev->func * MAX_CQ);
3062         ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
3063         if (status) {
3064                 QPRINTK(qdev, IFUP, ERR, "Failed to init mac address.\n");
3065                 return status;
3066         }
3067
3068         status = ql_route_initialize(qdev);
3069         if (status)
3070                 QPRINTK(qdev, IFUP, ERR, "Failed to init routing table.\n");
3071
3072         return status;
3073 }
3074
3075 static int ql_adapter_initialize(struct ql_adapter *qdev)
3076 {
3077         u32 value, mask;
3078         int i;
3079         int status = 0;
3080
3081         /*
3082          * Set up the System register to halt on errors.
3083          */
3084         value = SYS_EFE | SYS_FAE;
3085         mask = value << 16;
3086         ql_write32(qdev, SYS, mask | value);
3087
3088         /* Set the default queue, and VLAN behavior. */
3089         value = NIC_RCV_CFG_DFQ | NIC_RCV_CFG_RV;
3090         mask = NIC_RCV_CFG_DFQ_MASK | (NIC_RCV_CFG_RV << 16);
3091         ql_write32(qdev, NIC_RCV_CFG, (mask | value));
3092
3093         /* Set the MPI interrupt to enabled. */
3094         ql_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16) | INTR_MASK_PI);
3095
3096         /* Enable the function, set pagesize, enable error checking. */
3097         value = FSC_FE | FSC_EPC_INBOUND | FSC_EPC_OUTBOUND |
3098             FSC_EC | FSC_VM_PAGE_4K | FSC_SH;
3099
3100         /* Set/clear header splitting. */
3101         mask = FSC_VM_PAGESIZE_MASK |
3102             FSC_DBL_MASK | FSC_DBRST_MASK | (value << 16);
3103         ql_write32(qdev, FSC, mask | value);
3104
3105         ql_write32(qdev, SPLT_HDR, SPLT_HDR_EP |
3106                 min(SMALL_BUFFER_SIZE, MAX_SPLIT_SIZE));
3107
3108         /* Start up the rx queues. */
3109         for (i = 0; i < qdev->rx_ring_count; i++) {
3110                 status = ql_start_rx_ring(qdev, &qdev->rx_ring[i]);
3111                 if (status) {
3112                         QPRINTK(qdev, IFUP, ERR,
3113                                 "Failed to start rx ring[%d].\n", i);
3114                         return status;
3115                 }
3116         }
3117
3118         /* If there is more than one inbound completion queue
3119          * then download a RICB to configure RSS.
3120          */
3121         if (qdev->rss_ring_count > 1) {
3122                 status = ql_start_rss(qdev);
3123                 if (status) {
3124                         QPRINTK(qdev, IFUP, ERR, "Failed to start RSS.\n");
3125                         return status;
3126                 }
3127         }
3128
3129         /* Start up the tx queues. */
3130         for (i = 0; i < qdev->tx_ring_count; i++) {
3131                 status = ql_start_tx_ring(qdev, &qdev->tx_ring[i]);
3132                 if (status) {
3133                         QPRINTK(qdev, IFUP, ERR,
3134                                 "Failed to start tx ring[%d].\n", i);
3135                         return status;
3136                 }
3137         }
3138
3139         /* Initialize the port and set the max framesize. */
3140         status = qdev->nic_ops->port_initialize(qdev);
3141        if (status) {
3142               QPRINTK(qdev, IFUP, ERR, "Failed to start port.\n");
3143               return status;
3144        }
3145
3146         /* Set up the MAC address and frame routing filter. */
3147         status = ql_cam_route_initialize(qdev);
3148         if (status) {
3149                 QPRINTK(qdev, IFUP, ERR,
3150                                 "Failed to init CAM/Routing tables.\n");
3151                 return status;
3152         }
3153
3154         /* Start NAPI for the RSS queues. */
3155         for (i = qdev->rss_ring_first_cq_id; i < qdev->rx_ring_count; i++) {
3156                 QPRINTK(qdev, IFUP, DEBUG, "Enabling NAPI for rx_ring[%d].\n",
3157                         i);
3158                 napi_enable(&qdev->rx_ring[i].napi);
3159         }
3160
3161         return status;
3162 }
3163
3164 /* Issue soft reset to chip. */
3165 static int ql_adapter_reset(struct ql_adapter *qdev)
3166 {
3167         u32 value;
3168         int status = 0;
3169         unsigned long end_jiffies = jiffies +
3170                 max((unsigned long)1, usecs_to_jiffies(30));
3171
3172         ql_write32(qdev, RST_FO, (RST_FO_FR << 16) | RST_FO_FR);
3173
3174         do {
3175                 value = ql_read32(qdev, RST_FO);
3176                 if ((value & RST_FO_FR) == 0)
3177                         break;
3178                 cpu_relax();
3179         } while (time_before(jiffies, end_jiffies));
3180
3181         if (value & RST_FO_FR) {
3182                 QPRINTK(qdev, IFDOWN, ERR,
3183                         "ETIMEOUT!!! errored out of resetting the chip!\n");
3184                 status = -ETIMEDOUT;
3185         }
3186
3187         return status;
3188 }
3189
3190 static void ql_display_dev_info(struct net_device *ndev)
3191 {
3192         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3193
3194         QPRINTK(qdev, PROBE, INFO,
3195                 "Function #%d, NIC Roll %d, NIC Rev = %d, "
3196                 "XG Roll = %d, XG Rev = %d.\n",
3197                 qdev->func,
3198                 qdev->chip_rev_id & 0x0000000f,
3199                 qdev->chip_rev_id >> 4 & 0x0000000f,
3200                 qdev->chip_rev_id >> 8 & 0x0000000f,
3201                 qdev->chip_rev_id >> 12 & 0x0000000f);
3202         QPRINTK(qdev, PROBE, INFO, "MAC address %pM\n", ndev->dev_addr);
3203 }
3204
3205 static int ql_adapter_down(struct ql_adapter *qdev)
3206 {
3207         int i, status = 0;
3208         struct rx_ring *rx_ring;
3209
3210         netif_carrier_off(qdev->ndev);
3211
3212         /* Don't kill the reset worker thread if we
3213          * are in the process of recovery.
3214          */
3215         if (test_bit(QL_ADAPTER_UP, &qdev->flags))
3216                 cancel_delayed_work_sync(&qdev->asic_reset_work);
3217         cancel_delayed_work_sync(&qdev->mpi_reset_work);
3218         cancel_delayed_work_sync(&qdev->mpi_work);
3219         cancel_delayed_work_sync(&qdev->mpi_idc_work);
3220         cancel_delayed_work_sync(&qdev->mpi_port_cfg_work);
3221
3222         /* The default queue at index 0 is always processed in
3223          * a workqueue.
3224          */
3225         cancel_delayed_work_sync(&qdev->rx_ring[0].rx_work);
3226
3227         /* The rest of the rx_rings are processed in
3228          * a workqueue only if it's a single interrupt
3229          * environment (MSI/Legacy).
3230          */
3231         for (i = 1; i < qdev->rx_ring_count; i++) {
3232                 rx_ring = &qdev->rx_ring[i];
3233                 /* Only the RSS rings use NAPI on multi irq
3234                  * environment.  Outbound completion processing
3235                  * is done in interrupt context.
3236                  */
3237                 if (i >= qdev->rss_ring_first_cq_id) {
3238                         napi_disable(&rx_ring->napi);
3239                 } else {
3240                         cancel_delayed_work_sync(&rx_ring->rx_work);
3241                 }
3242         }
3243
3244         clear_bit(QL_ADAPTER_UP, &qdev->flags);
3245
3246         ql_disable_interrupts(qdev);
3247
3248         ql_tx_ring_clean(qdev);
3249
3250         /* Call netif_napi_del() from common point.
3251          */
3252         for (i = qdev->rss_ring_first_cq_id; i < qdev->rx_ring_count; i++)
3253                 netif_napi_del(&qdev->rx_ring[i].napi);
3254
3255         ql_free_rx_buffers(qdev);
3256
3257         spin_lock(&qdev->hw_lock);
3258         status = ql_adapter_reset(qdev);
3259         if (status)
3260                 QPRINTK(qdev, IFDOWN, ERR, "reset(func #%d) FAILED!\n",
3261                         qdev->func);
3262         spin_unlock(&qdev->hw_lock);
3263         return status;
3264 }
3265
3266 static int ql_adapter_up(struct ql_adapter *qdev)
3267 {
3268         int err = 0;
3269
3270         err = ql_adapter_initialize(qdev);
3271         if (err) {
3272                 QPRINTK(qdev, IFUP, INFO, "Unable to initialize adapter.\n");
3273                 spin_unlock(&qdev->hw_lock);
3274                 goto err_init;
3275         }
3276         set_bit(QL_ADAPTER_UP, &qdev->flags);
3277         ql_alloc_rx_buffers(qdev);
3278         if ((ql_read32(qdev, STS) & qdev->port_init))
3279                 netif_carrier_on(qdev->ndev);
3280         ql_enable_interrupts(qdev);
3281         ql_enable_all_completion_interrupts(qdev);
3282         netif_tx_start_all_queues(qdev->ndev);
3283
3284         return 0;
3285 err_init:
3286         ql_adapter_reset(qdev);
3287         return err;
3288 }
3289
3290 static void ql_release_adapter_resources(struct ql_adapter *qdev)
3291 {
3292         ql_free_mem_resources(qdev);
3293         ql_free_irq(qdev);
3294 }
3295
3296 static int ql_get_adapter_resources(struct ql_adapter *qdev)
3297 {
3298         int status = 0;
3299
3300         if (ql_alloc_mem_resources(qdev)) {
3301                 QPRINTK(qdev, IFUP, ERR, "Unable to  allocate memory.\n");
3302                 return -ENOMEM;
3303         }
3304         status = ql_request_irq(qdev);
3305         if (status)
3306                 goto err_irq;
3307         return status;
3308 err_irq:
3309         ql_free_mem_resources(qdev);
3310         return status;
3311 }
3312
3313 static int qlge_close(struct net_device *ndev)
3314 {
3315         struct ql_adapter *qdev = netdev_priv(ndev);
3316
3317         /*
3318          * Wait for device to recover from a reset.
3319          * (Rarely happens, but possible.)
3320          */
3321         while (!test_bit(QL_ADAPTER_UP, &qdev->flags))
3322                 msleep(1);
3323         ql_adapter_down(qdev);
3324         ql_release_adapter_resources(qdev);
3325         return 0;
3326 }
3327
3328 static int ql_configure_rings(struct ql_adapter *qdev)
3329 {
3330         int i;
3331         struct rx_ring *rx_ring;
3332         struct tx_ring *tx_ring;
3333         int cpu_cnt = num_online_cpus();
3334
3335         /*
3336          * For each processor present we allocate one
3337          * rx_ring for outbound completions, and one
3338          * rx_ring for inbound completions.  Plus there is
3339          * always the one default queue.  For the CPU
3340          * counts we end up with the following rx_rings:
3341          * rx_ring count =
3342          *  one default queue +
3343          *  (CPU count * outbound completion rx_ring) +
3344          *  (CPU count * inbound (RSS) completion rx_ring)
3345          * To keep it simple we limit the total number of
3346          * queues to < 32, so we truncate CPU to 8.
3347          * This limitation can be removed when requested.
3348          */
3349
3350         if (cpu_cnt > MAX_CPUS)
3351                 cpu_cnt = MAX_CPUS;
3352
3353         /*
3354          * rx_ring[0] is always the default queue.
3355          */
3356         /* Allocate outbound completion ring for each CPU. */
3357         qdev->tx_ring_count = cpu_cnt;
3358         /* Allocate inbound completion (RSS) ring for each CPU. */
3359         qdev->rss_ring_count = cpu_cnt;
3360         /* cq_id for the first inbound ring handler. */
3361         qdev->rss_ring_first_cq_id = cpu_cnt + 1;
3362         /*
3363          * qdev->rx_ring_count:
3364          * Total number of rx_rings.  This includes the one
3365          * default queue, a number of outbound completion
3366          * handler rx_rings, and the number of inbound
3367          * completion handler rx_rings.
3368          */
3369         qdev->rx_ring_count = qdev->tx_ring_count + qdev->rss_ring_count + 1;
3370         netif_set_gso_max_size(qdev->ndev, 65536);
3371
3372         for (i = 0; i < qdev->tx_ring_count; i++) {
3373                 tx_ring = &qdev->tx_ring[i];
3374                 memset((void *)tx_ring, 0, sizeof(tx_ring));
3375                 tx_ring->qdev = qdev;
3376                 tx_ring->wq_id = i;
3377                 tx_ring->wq_len = qdev->tx_ring_size;
3378                 tx_ring->wq_size =
3379                     tx_ring->wq_len * sizeof(struct ob_mac_iocb_req);
3380
3381                 /*
3382                  * The completion queue ID for the tx rings start
3383                  * immediately after the default Q ID, which is zero.
3384                  */
3385                 tx_ring->cq_id = i + 1;
3386         }
3387
3388         for (i = 0; i < qdev->rx_ring_count; i++) {
3389                 rx_ring = &qdev->rx_ring[i];
3390                 memset((void *)rx_ring, 0, sizeof(rx_ring));
3391                 rx_ring->qdev = qdev;
3392                 rx_ring->cq_id = i;
3393                 rx_ring->cpu = i % cpu_cnt;     /* CPU to run handler on. */
3394                 if (i == 0) {   /* Default queue at index 0. */
3395                         /*
3396                          * Default queue handles bcast/mcast plus
3397                          * async events.  Needs buffers.
3398                          */
3399                         rx_ring->cq_len = qdev->rx_ring_size;
3400                         rx_ring->cq_size =
3401                             rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3402                         rx_ring->lbq_len = NUM_LARGE_BUFFERS;
3403                         rx_ring->lbq_size =
3404                             rx_ring->lbq_len * sizeof(__le64);
3405                         rx_ring->lbq_buf_size = LARGE_BUFFER_SIZE;
3406                         rx_ring->sbq_len = NUM_SMALL_BUFFERS;
3407                         rx_ring->sbq_size =
3408                             rx_ring->sbq_len * sizeof(__le64);
3409                         rx_ring->sbq_buf_size = SMALL_BUFFER_SIZE * 2;
3410                         rx_ring->type = DEFAULT_Q;
3411                 } else if (i < qdev->rss_ring_first_cq_id) {
3412                         /*
3413                          * Outbound queue handles outbound completions only.
3414                          */
3415                         /* outbound cq is same size as tx_ring it services. */
3416                         rx_ring->cq_len = qdev->tx_ring_size;
3417                         rx_ring->cq_size =
3418                             rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3419                         rx_ring->lbq_len = 0;
3420                         rx_ring->lbq_size = 0;
3421                         rx_ring->lbq_buf_size = 0;
3422                         rx_ring->sbq_len = 0;
3423                         rx_ring->sbq_size = 0;
3424                         rx_ring->sbq_buf_size = 0;
3425                         rx_ring->type = TX_Q;
3426                 } else {        /* Inbound completions (RSS) queues */
3427                         /*
3428                          * Inbound queues handle unicast frames only.
3429                          */
3430                         rx_ring->cq_len = qdev->rx_ring_size;
3431                         rx_ring->cq_size =
3432                             rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3433                         rx_ring->lbq_len = NUM_LARGE_BUFFERS;
3434                         rx_ring->lbq_size =
3435                             rx_ring->lbq_len * sizeof(__le64);
3436                         rx_ring->lbq_buf_size = LARGE_BUFFER_SIZE;
3437                         rx_ring->sbq_len = NUM_SMALL_BUFFERS;
3438                         rx_ring->sbq_size =
3439                             rx_ring->sbq_len * sizeof(__le64);
3440                         rx_ring->sbq_buf_size = SMALL_BUFFER_SIZE * 2;
3441                         rx_ring->type = RX_Q;
3442                 }
3443         }
3444         return 0;
3445 }
3446
3447 static int qlge_open(struct net_device *ndev)
3448 {
3449         int err = 0;
3450         struct ql_adapter *qdev = netdev_priv(ndev);
3451
3452         err = ql_configure_rings(qdev);
3453         if (err)
3454                 return err;
3455
3456         err = ql_get_adapter_resources(qdev);
3457         if (err)
3458                 goto error_up;
3459
3460         err = ql_adapter_up(qdev);
3461         if (err)
3462                 goto error_up;
3463
3464         return err;
3465
3466 error_up:
3467         ql_release_adapter_resources(qdev);
3468         return err;
3469 }
3470
3471 static int qlge_change_mtu(struct net_device *ndev, int new_mtu)
3472 {
3473         struct ql_adapter *qdev = netdev_priv(ndev);
3474
3475         if (ndev->mtu == 1500 && new_mtu == 9000) {
3476                 QPRINTK(qdev, IFUP, ERR, "Changing to jumbo MTU.\n");
3477                 queue_delayed_work(qdev->workqueue,
3478                                 &qdev->mpi_port_cfg_work, 0);
3479         } else if (ndev->mtu == 9000 && new_mtu == 1500) {
3480                 QPRINTK(qdev, IFUP, ERR, "Changing to normal MTU.\n");
3481         } else if ((ndev->mtu == 1500 && new_mtu == 1500) ||
3482                    (ndev->mtu == 9000 && new_mtu == 9000)) {
3483                 return 0;
3484         } else
3485                 return -EINVAL;
3486         ndev->mtu = new_mtu;
3487         return 0;
3488 }
3489
3490 static struct net_device_stats *qlge_get_stats(struct net_device
3491                                                *ndev)
3492 {
3493         struct ql_adapter *qdev = netdev_priv(ndev);
3494         return &qdev->stats;
3495 }
3496
3497 static void qlge_set_multicast_list(struct net_device *ndev)
3498 {
3499         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3500         struct dev_mc_list *mc_ptr;
3501         int i, status;
3502
3503         status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
3504         if (status)
3505                 return;
3506         spin_lock(&qdev->hw_lock);
3507         /*
3508          * Set or clear promiscuous mode if a
3509          * transition is taking place.
3510          */
3511         if (ndev->flags & IFF_PROMISC) {
3512                 if (!test_bit(QL_PROMISCUOUS, &qdev->flags)) {
3513                         if (ql_set_routing_reg
3514                             (qdev, RT_IDX_PROMISCUOUS_SLOT, RT_IDX_VALID, 1)) {
3515                                 QPRINTK(qdev, HW, ERR,
3516                                         "Failed to set promiscous mode.\n");
3517                         } else {
3518                                 set_bit(QL_PROMISCUOUS, &qdev->flags);
3519                         }
3520                 }
3521         } else {
3522                 if (test_bit(QL_PROMISCUOUS, &qdev->flags)) {
3523                         if (ql_set_routing_reg
3524                             (qdev, RT_IDX_PROMISCUOUS_SLOT, RT_IDX_VALID, 0)) {
3525                                 QPRINTK(qdev, HW, ERR,
3526                                         "Failed to clear promiscous mode.\n");
3527                         } else {
3528                                 clear_bit(QL_PROMISCUOUS, &qdev->flags);
3529                         }
3530                 }
3531         }
3532
3533         /*
3534          * Set or clear all multicast mode if a
3535          * transition is taking place.
3536          */
3537         if ((ndev->flags & IFF_ALLMULTI) ||
3538             (ndev->mc_count > MAX_MULTICAST_ENTRIES)) {
3539                 if (!test_bit(QL_ALLMULTI, &qdev->flags)) {
3540                         if (ql_set_routing_reg
3541                             (qdev, RT_IDX_ALLMULTI_SLOT, RT_IDX_MCAST, 1)) {
3542                                 QPRINTK(qdev, HW, ERR,
3543                                         "Failed to set all-multi mode.\n");
3544                         } else {
3545                                 set_bit(QL_ALLMULTI, &qdev->flags);
3546                         }
3547                 }
3548         } else {
3549                 if (test_bit(QL_ALLMULTI, &qdev->flags)) {
3550                         if (ql_set_routing_reg
3551                             (qdev, RT_IDX_ALLMULTI_SLOT, RT_IDX_MCAST, 0)) {
3552                                 QPRINTK(qdev, HW, ERR,
3553                                         "Failed to clear all-multi mode.\n");
3554                         } else {
3555                                 clear_bit(QL_ALLMULTI, &qdev->flags);
3556                         }
3557                 }
3558         }
3559
3560         if (ndev->mc_count) {
3561                 status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
3562                 if (status)
3563                         goto exit;
3564                 for (i = 0, mc_ptr = ndev->mc_list; mc_ptr;
3565                      i++, mc_ptr = mc_ptr->next)
3566                         if (ql_set_mac_addr_reg(qdev, (u8 *) mc_ptr->dmi_addr,
3567                                                 MAC_ADDR_TYPE_MULTI_MAC, i)) {
3568                                 QPRINTK(qdev, HW, ERR,
3569                                         "Failed to loadmulticast address.\n");
3570                                 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
3571                                 goto exit;
3572                         }
3573                 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
3574                 if (ql_set_routing_reg
3575                     (qdev, RT_IDX_MCAST_MATCH_SLOT, RT_IDX_MCAST_MATCH, 1)) {
3576                         QPRINTK(qdev, HW, ERR,
3577                                 "Failed to set multicast match mode.\n");
3578                 } else {
3579                         set_bit(QL_ALLMULTI, &qdev->flags);
3580                 }
3581         }
3582 exit:
3583         spin_unlock(&qdev->hw_lock);
3584         ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
3585 }
3586
3587 static int qlge_set_mac_address(struct net_device *ndev, void *p)
3588 {
3589         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3590         struct sockaddr *addr = p;
3591         int status;
3592
3593         if (netif_running(ndev))
3594                 return -EBUSY;
3595
3596         if (!is_valid_ether_addr(addr->sa_data))
3597                 return -EADDRNOTAVAIL;
3598         memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3599
3600         status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
3601         if (status)
3602                 return status;
3603         spin_lock(&qdev->hw_lock);
3604         status = ql_set_mac_addr_reg(qdev, (u8 *) ndev->dev_addr,
3605                         MAC_ADDR_TYPE_CAM_MAC, qdev->func * MAX_CQ);
3606         spin_unlock(&qdev->hw_lock);
3607         if (status)
3608                 QPRINTK(qdev, HW, ERR, "Failed to load MAC address.\n");
3609         ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
3610         return status;
3611 }
3612
3613 static void qlge_tx_timeout(struct net_device *ndev)
3614 {
3615         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3616         ql_queue_asic_error(qdev);
3617 }
3618
3619 static void ql_asic_reset_work(struct work_struct *work)
3620 {
3621         struct ql_adapter *qdev =
3622             container_of(work, struct ql_adapter, asic_reset_work.work);
3623         int status;
3624
3625         status = ql_adapter_down(qdev);
3626         if (status)
3627                 goto error;
3628
3629         status = ql_adapter_up(qdev);
3630         if (status)
3631                 goto error;
3632
3633         return;
3634 error:
3635         QPRINTK(qdev, IFUP, ALERT,
3636                 "Driver up/down cycle failed, closing device\n");
3637         rtnl_lock();
3638         set_bit(QL_ADAPTER_UP, &qdev->flags);
3639         dev_close(qdev->ndev);
3640         rtnl_unlock();
3641 }
3642
3643 static struct nic_operations qla8012_nic_ops = {
3644         .get_flash              = ql_get_8012_flash_params,
3645         .port_initialize        = ql_8012_port_initialize,
3646 };
3647
3648 static struct nic_operations qla8000_nic_ops = {
3649         .get_flash              = ql_get_8000_flash_params,
3650         .port_initialize        = ql_8000_port_initialize,
3651 };
3652
3653
3654 static void ql_get_board_info(struct ql_adapter *qdev)
3655 {
3656         qdev->func =
3657             (ql_read32(qdev, STS) & STS_FUNC_ID_MASK) >> STS_FUNC_ID_SHIFT;
3658         if (qdev->func) {
3659                 qdev->xg_sem_mask = SEM_XGMAC1_MASK;
3660                 qdev->port_link_up = STS_PL1;
3661                 qdev->port_init = STS_PI1;
3662                 qdev->mailbox_in = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC2_MBI;
3663                 qdev->mailbox_out = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC2_MBO;
3664         } else {
3665                 qdev->xg_sem_mask = SEM_XGMAC0_MASK;
3666                 qdev->port_link_up = STS_PL0;
3667                 qdev->port_init = STS_PI0;
3668                 qdev->mailbox_in = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBI;
3669                 qdev->mailbox_out = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBO;
3670         }
3671         qdev->chip_rev_id = ql_read32(qdev, REV_ID);
3672         qdev->device_id = qdev->pdev->device;
3673         if (qdev->device_id == QLGE_DEVICE_ID_8012)
3674                 qdev->nic_ops = &qla8012_nic_ops;
3675         else if (qdev->device_id == QLGE_DEVICE_ID_8000)
3676                 qdev->nic_ops = &qla8000_nic_ops;
3677 }
3678
3679 static void ql_release_all(struct pci_dev *pdev)
3680 {
3681         struct net_device *ndev = pci_get_drvdata(pdev);
3682         struct ql_adapter *qdev = netdev_priv(ndev);
3683
3684         if (qdev->workqueue) {
3685                 destroy_workqueue(qdev->workqueue);
3686                 qdev->workqueue = NULL;
3687         }
3688         if (qdev->q_workqueue) {
3689                 destroy_workqueue(qdev->q_workqueue);
3690                 qdev->q_workqueue = NULL;
3691         }
3692         if (qdev->reg_base)
3693                 iounmap(qdev->reg_base);
3694         if (qdev->doorbell_area)
3695                 iounmap(qdev->doorbell_area);
3696         pci_release_regions(pdev);
3697         pci_set_drvdata(pdev, NULL);
3698 }
3699
3700 static int __devinit ql_init_device(struct pci_dev *pdev,
3701                                     struct net_device *ndev, int cards_found)
3702 {
3703         struct ql_adapter *qdev = netdev_priv(ndev);
3704         int pos, err = 0;
3705         u16 val16;
3706
3707         memset((void *)qdev, 0, sizeof(qdev));
3708         err = pci_enable_device(pdev);
3709         if (err) {
3710                 dev_err(&pdev->dev, "PCI device enable failed.\n");
3711                 return err;
3712         }
3713
3714         pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3715         if (pos <= 0) {
3716                 dev_err(&pdev->dev, PFX "Cannot find PCI Express capability, "
3717                         "aborting.\n");
3718                 goto err_out;
3719         } else {
3720                 pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &val16);
3721                 val16 &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
3722                 val16 |= (PCI_EXP_DEVCTL_CERE |
3723                           PCI_EXP_DEVCTL_NFERE |
3724                           PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE);
3725                 pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, val16);
3726         }
3727
3728         err = pci_request_regions(pdev, DRV_NAME);
3729         if (err) {
3730                 dev_err(&pdev->dev, "PCI region request failed.\n");
3731                 goto err_out;
3732         }
3733
3734         pci_set_master(pdev);
3735         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
3736                 set_bit(QL_DMA64, &qdev->flags);
3737                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
3738         } else {
3739                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3740                 if (!err)
3741                        err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3742         }
3743
3744         if (err) {
3745                 dev_err(&pdev->dev, "No usable DMA configuration.\n");
3746                 goto err_out;
3747         }
3748
3749         pci_set_drvdata(pdev, ndev);
3750         qdev->reg_base =
3751             ioremap_nocache(pci_resource_start(pdev, 1),
3752                             pci_resource_len(pdev, 1));
3753         if (!qdev->reg_base) {
3754                 dev_err(&pdev->dev, "Register mapping failed.\n");
3755                 err = -ENOMEM;
3756                 goto err_out;
3757         }
3758
3759         qdev->doorbell_area_size = pci_resource_len(pdev, 3);
3760         qdev->doorbell_area =
3761             ioremap_nocache(pci_resource_start(pdev, 3),
3762                             pci_resource_len(pdev, 3));
3763         if (!qdev->doorbell_area) {
3764                 dev_err(&pdev->dev, "Doorbell register mapping failed.\n");
3765                 err = -ENOMEM;
3766                 goto err_out;
3767         }
3768
3769         qdev->ndev = ndev;
3770         qdev->pdev = pdev;
3771         ql_get_board_info(qdev);
3772         qdev->msg_enable = netif_msg_init(debug, default_msg);
3773         spin_lock_init(&qdev->hw_lock);
3774         spin_lock_init(&qdev->stats_lock);
3775
3776         /* make sure the EEPROM is good */
3777         err = qdev->nic_ops->get_flash(qdev);
3778         if (err) {
3779                 dev_err(&pdev->dev, "Invalid FLASH.\n");
3780                 goto err_out;
3781         }
3782
3783         memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
3784
3785         /* Set up the default ring sizes. */
3786         qdev->tx_ring_size = NUM_TX_RING_ENTRIES;
3787         qdev->rx_ring_size = NUM_RX_RING_ENTRIES;
3788
3789         /* Set up the coalescing parameters. */
3790         qdev->rx_coalesce_usecs = DFLT_COALESCE_WAIT;
3791         qdev->tx_coalesce_usecs = DFLT_COALESCE_WAIT;
3792         qdev->rx_max_coalesced_frames = DFLT_INTER_FRAME_WAIT;
3793         qdev->tx_max_coalesced_frames = DFLT_INTER_FRAME_WAIT;
3794
3795         /*
3796          * Set up the operating parameters.
3797          */
3798         qdev->rx_csum = 1;
3799
3800         qdev->q_workqueue = create_workqueue(ndev->name);
3801         qdev->workqueue = create_singlethread_workqueue(ndev->name);
3802         INIT_DELAYED_WORK(&qdev->asic_reset_work, ql_asic_reset_work);
3803         INIT_DELAYED_WORK(&qdev->mpi_reset_work, ql_mpi_reset_work);
3804         INIT_DELAYED_WORK(&qdev->mpi_work, ql_mpi_work);
3805         INIT_DELAYED_WORK(&qdev->mpi_port_cfg_work, ql_mpi_port_cfg_work);
3806         INIT_DELAYED_WORK(&qdev->mpi_idc_work, ql_mpi_idc_work);
3807         mutex_init(&qdev->mpi_mutex);
3808         init_completion(&qdev->ide_completion);
3809
3810         if (!cards_found) {
3811                 dev_info(&pdev->dev, "%s\n", DRV_STRING);
3812                 dev_info(&pdev->dev, "Driver name: %s, Version: %s.\n",
3813                          DRV_NAME, DRV_VERSION);
3814         }
3815         return 0;
3816 err_out:
3817         ql_release_all(pdev);
3818         pci_disable_device(pdev);
3819         return err;
3820 }
3821
3822
3823 static const struct net_device_ops qlge_netdev_ops = {
3824         .ndo_open               = qlge_open,
3825         .ndo_stop               = qlge_close,
3826         .ndo_start_xmit         = qlge_send,
3827         .ndo_change_mtu         = qlge_change_mtu,
3828         .ndo_get_stats          = qlge_get_stats,
3829         .ndo_set_multicast_list = qlge_set_multicast_list,
3830         .ndo_set_mac_address    = qlge_set_mac_address,
3831         .ndo_validate_addr      = eth_validate_addr,
3832         .ndo_tx_timeout         = qlge_tx_timeout,
3833         .ndo_vlan_rx_register   = ql_vlan_rx_register,
3834         .ndo_vlan_rx_add_vid    = ql_vlan_rx_add_vid,
3835         .ndo_vlan_rx_kill_vid   = ql_vlan_rx_kill_vid,
3836 };
3837
3838 static int __devinit qlge_probe(struct pci_dev *pdev,
3839                                 const struct pci_device_id *pci_entry)
3840 {
3841         struct net_device *ndev = NULL;
3842         struct ql_adapter *qdev = NULL;
3843         static int cards_found = 0;
3844         int err = 0;
3845
3846         ndev = alloc_etherdev_mq(sizeof(struct ql_adapter),
3847                         min(MAX_CPUS, (int)num_online_cpus()));
3848         if (!ndev)
3849                 return -ENOMEM;
3850
3851         err = ql_init_device(pdev, ndev, cards_found);
3852         if (err < 0) {
3853                 free_netdev(ndev);
3854                 return err;
3855         }
3856
3857         qdev = netdev_priv(ndev);
3858         SET_NETDEV_DEV(ndev, &pdev->dev);
3859         ndev->features = (0
3860                           | NETIF_F_IP_CSUM
3861                           | NETIF_F_SG
3862                           | NETIF_F_TSO
3863                           | NETIF_F_TSO6
3864                           | NETIF_F_TSO_ECN
3865                           | NETIF_F_HW_VLAN_TX
3866                           | NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_FILTER);
3867         ndev->features |= NETIF_F_GRO;
3868
3869         if (test_bit(QL_DMA64, &qdev->flags))
3870                 ndev->features |= NETIF_F_HIGHDMA;
3871
3872         /*
3873          * Set up net_device structure.
3874          */
3875         ndev->tx_queue_len = qdev->tx_ring_size;
3876         ndev->irq = pdev->irq;
3877
3878         ndev->netdev_ops = &qlge_netdev_ops;
3879         SET_ETHTOOL_OPS(ndev, &qlge_ethtool_ops);
3880         ndev->watchdog_timeo = 10 * HZ;
3881
3882         err = register_netdev(ndev);
3883         if (err) {
3884                 dev_err(&pdev->dev, "net device registration failed.\n");
3885                 ql_release_all(pdev);
3886                 pci_disable_device(pdev);
3887                 return err;
3888         }
3889         netif_carrier_off(ndev);
3890         ql_display_dev_info(ndev);
3891         cards_found++;
3892         return 0;
3893 }
3894
3895 static void __devexit qlge_remove(struct pci_dev *pdev)
3896 {
3897         struct net_device *ndev = pci_get_drvdata(pdev);
3898         unregister_netdev(ndev);
3899         ql_release_all(pdev);
3900         pci_disable_device(pdev);
3901         free_netdev(ndev);
3902 }
3903
3904 /*
3905  * This callback is called by the PCI subsystem whenever
3906  * a PCI bus error is detected.
3907  */
3908 static pci_ers_result_t qlge_io_error_detected(struct pci_dev *pdev,
3909                                                enum pci_channel_state state)
3910 {
3911         struct net_device *ndev = pci_get_drvdata(pdev);
3912         struct ql_adapter *qdev = netdev_priv(ndev);
3913
3914         if (netif_running(ndev))
3915                 ql_adapter_down(qdev);
3916
3917         pci_disable_device(pdev);
3918
3919         /* Request a slot reset. */
3920         return PCI_ERS_RESULT_NEED_RESET;
3921 }
3922
3923 /*
3924  * This callback is called after the PCI buss has been reset.
3925  * Basically, this tries to restart the card from scratch.
3926  * This is a shortened version of the device probe/discovery code,
3927  * it resembles the first-half of the () routine.
3928  */
3929 static pci_ers_result_t qlge_io_slot_reset(struct pci_dev *pdev)
3930 {
3931         struct net_device *ndev = pci_get_drvdata(pdev);
3932         struct ql_adapter *qdev = netdev_priv(ndev);
3933
3934         if (pci_enable_device(pdev)) {
3935                 QPRINTK(qdev, IFUP, ERR,
3936                         "Cannot re-enable PCI device after reset.\n");
3937                 return PCI_ERS_RESULT_DISCONNECT;
3938         }
3939
3940         pci_set_master(pdev);
3941
3942         netif_carrier_off(ndev);
3943         ql_adapter_reset(qdev);
3944
3945         /* Make sure the EEPROM is good */
3946         memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
3947
3948         if (!is_valid_ether_addr(ndev->perm_addr)) {
3949                 QPRINTK(qdev, IFUP, ERR, "After reset, invalid MAC address.\n");
3950                 return PCI_ERS_RESULT_DISCONNECT;
3951         }
3952
3953         return PCI_ERS_RESULT_RECOVERED;
3954 }
3955
3956 static void qlge_io_resume(struct pci_dev *pdev)
3957 {
3958         struct net_device *ndev = pci_get_drvdata(pdev);
3959         struct ql_adapter *qdev = netdev_priv(ndev);
3960
3961         pci_set_master(pdev);
3962
3963         if (netif_running(ndev)) {
3964                 if (ql_adapter_up(qdev)) {
3965                         QPRINTK(qdev, IFUP, ERR,
3966                                 "Device initialization failed after reset.\n");
3967                         return;
3968                 }
3969         }
3970
3971         netif_device_attach(ndev);
3972 }
3973
3974 static struct pci_error_handlers qlge_err_handler = {
3975         .error_detected = qlge_io_error_detected,
3976         .slot_reset = qlge_io_slot_reset,
3977         .resume = qlge_io_resume,
3978 };
3979
3980 static int qlge_suspend(struct pci_dev *pdev, pm_message_t state)
3981 {
3982         struct net_device *ndev = pci_get_drvdata(pdev);
3983         struct ql_adapter *qdev = netdev_priv(ndev);
3984         int err;
3985
3986         netif_device_detach(ndev);
3987
3988         if (netif_running(ndev)) {
3989                 err = ql_adapter_down(qdev);
3990                 if (!err)
3991                         return err;
3992         }
3993
3994         err = pci_save_state(pdev);
3995         if (err)
3996                 return err;
3997
3998         pci_disable_device(pdev);
3999
4000         pci_set_power_state(pdev, pci_choose_state(pdev, state));
4001
4002         return 0;
4003 }
4004
4005 #ifdef CONFIG_PM
4006 static int qlge_resume(struct pci_dev *pdev)
4007 {
4008         struct net_device *ndev = pci_get_drvdata(pdev);
4009         struct ql_adapter *qdev = netdev_priv(ndev);
4010         int err;
4011
4012         pci_set_power_state(pdev, PCI_D0);
4013         pci_restore_state(pdev);
4014         err = pci_enable_device(pdev);
4015         if (err) {
4016                 QPRINTK(qdev, IFUP, ERR, "Cannot enable PCI device from suspend\n");
4017                 return err;
4018         }
4019         pci_set_master(pdev);
4020
4021         pci_enable_wake(pdev, PCI_D3hot, 0);
4022         pci_enable_wake(pdev, PCI_D3cold, 0);
4023
4024         if (netif_running(ndev)) {
4025                 err = ql_adapter_up(qdev);
4026                 if (err)
4027                         return err;
4028         }
4029
4030         netif_device_attach(ndev);
4031
4032         return 0;
4033 }
4034 #endif /* CONFIG_PM */
4035
4036 static void qlge_shutdown(struct pci_dev *pdev)
4037 {
4038         qlge_suspend(pdev, PMSG_SUSPEND);
4039 }
4040
4041 static struct pci_driver qlge_driver = {
4042         .name = DRV_NAME,
4043         .id_table = qlge_pci_tbl,
4044         .probe = qlge_probe,
4045         .remove = __devexit_p(qlge_remove),
4046 #ifdef CONFIG_PM
4047         .suspend = qlge_suspend,
4048         .resume = qlge_resume,
4049 #endif
4050         .shutdown = qlge_shutdown,
4051         .err_handler = &qlge_err_handler
4052 };
4053
4054 static int __init qlge_init_module(void)
4055 {
4056         return pci_register_driver(&qlge_driver);
4057 }
4058
4059 static void __exit qlge_exit(void)
4060 {
4061         pci_unregister_driver(&qlge_driver);
4062 }
4063
4064 module_init(qlge_init_module);
4065 module_exit(qlge_exit);