Pull bugfix into test branch
[linux-2.6] / drivers / infiniband / hw / mthca / mthca_cq.c
1 /*
2  * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
3  * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4  * Copyright (c) 2005, 2006 Cisco Systems, Inc. All rights reserved.
5  * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
6  * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
7  *
8  * This software is available to you under a choice of one of two
9  * licenses.  You may choose to be licensed under the terms of the GNU
10  * General Public License (GPL) Version 2, available from the file
11  * COPYING in the main directory of this source tree, or the
12  * OpenIB.org BSD license below:
13  *
14  *     Redistribution and use in source and binary forms, with or
15  *     without modification, are permitted provided that the following
16  *     conditions are met:
17  *
18  *      - Redistributions of source code must retain the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer.
21  *
22  *      - Redistributions in binary form must reproduce the above
23  *        copyright notice, this list of conditions and the following
24  *        disclaimer in the documentation and/or other materials
25  *        provided with the distribution.
26  *
27  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
28  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
29  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
30  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
31  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
32  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
33  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34  * SOFTWARE.
35  *
36  * $Id: mthca_cq.c 1369 2004-12-20 16:17:07Z roland $
37  */
38
39 #include <linux/hardirq.h>
40
41 #include <asm/io.h>
42
43 #include <rdma/ib_pack.h>
44
45 #include "mthca_dev.h"
46 #include "mthca_cmd.h"
47 #include "mthca_memfree.h"
48
49 enum {
50         MTHCA_MAX_DIRECT_CQ_SIZE = 4 * PAGE_SIZE
51 };
52
53 enum {
54         MTHCA_CQ_ENTRY_SIZE = 0x20
55 };
56
57 /*
58  * Must be packed because start is 64 bits but only aligned to 32 bits.
59  */
60 struct mthca_cq_context {
61         __be32 flags;
62         __be64 start;
63         __be32 logsize_usrpage;
64         __be32 error_eqn;       /* Tavor only */
65         __be32 comp_eqn;
66         __be32 pd;
67         __be32 lkey;
68         __be32 last_notified_index;
69         __be32 solicit_producer_index;
70         __be32 consumer_index;
71         __be32 producer_index;
72         __be32 cqn;
73         __be32 ci_db;           /* Arbel only */
74         __be32 state_db;        /* Arbel only */
75         u32    reserved;
76 } __attribute__((packed));
77
78 #define MTHCA_CQ_STATUS_OK          ( 0 << 28)
79 #define MTHCA_CQ_STATUS_OVERFLOW    ( 9 << 28)
80 #define MTHCA_CQ_STATUS_WRITE_FAIL  (10 << 28)
81 #define MTHCA_CQ_FLAG_TR            ( 1 << 18)
82 #define MTHCA_CQ_FLAG_OI            ( 1 << 17)
83 #define MTHCA_CQ_STATE_DISARMED     ( 0 <<  8)
84 #define MTHCA_CQ_STATE_ARMED        ( 1 <<  8)
85 #define MTHCA_CQ_STATE_ARMED_SOL    ( 4 <<  8)
86 #define MTHCA_EQ_STATE_FIRED        (10 <<  8)
87
88 enum {
89         MTHCA_ERROR_CQE_OPCODE_MASK = 0xfe
90 };
91
92 enum {
93         SYNDROME_LOCAL_LENGTH_ERR        = 0x01,
94         SYNDROME_LOCAL_QP_OP_ERR         = 0x02,
95         SYNDROME_LOCAL_EEC_OP_ERR        = 0x03,
96         SYNDROME_LOCAL_PROT_ERR          = 0x04,
97         SYNDROME_WR_FLUSH_ERR            = 0x05,
98         SYNDROME_MW_BIND_ERR             = 0x06,
99         SYNDROME_BAD_RESP_ERR            = 0x10,
100         SYNDROME_LOCAL_ACCESS_ERR        = 0x11,
101         SYNDROME_REMOTE_INVAL_REQ_ERR    = 0x12,
102         SYNDROME_REMOTE_ACCESS_ERR       = 0x13,
103         SYNDROME_REMOTE_OP_ERR           = 0x14,
104         SYNDROME_RETRY_EXC_ERR           = 0x15,
105         SYNDROME_RNR_RETRY_EXC_ERR       = 0x16,
106         SYNDROME_LOCAL_RDD_VIOL_ERR      = 0x20,
107         SYNDROME_REMOTE_INVAL_RD_REQ_ERR = 0x21,
108         SYNDROME_REMOTE_ABORTED_ERR      = 0x22,
109         SYNDROME_INVAL_EECN_ERR          = 0x23,
110         SYNDROME_INVAL_EEC_STATE_ERR     = 0x24
111 };
112
113 struct mthca_cqe {
114         __be32 my_qpn;
115         __be32 my_ee;
116         __be32 rqpn;
117         __be16 sl_g_mlpath;
118         __be16 rlid;
119         __be32 imm_etype_pkey_eec;
120         __be32 byte_cnt;
121         __be32 wqe;
122         u8     opcode;
123         u8     is_send;
124         u8     reserved;
125         u8     owner;
126 };
127
128 struct mthca_err_cqe {
129         __be32 my_qpn;
130         u32    reserved1[3];
131         u8     syndrome;
132         u8     vendor_err;
133         __be16 db_cnt;
134         u32    reserved2;
135         __be32 wqe;
136         u8     opcode;
137         u8     reserved3[2];
138         u8     owner;
139 };
140
141 #define MTHCA_CQ_ENTRY_OWNER_SW      (0 << 7)
142 #define MTHCA_CQ_ENTRY_OWNER_HW      (1 << 7)
143
144 #define MTHCA_TAVOR_CQ_DB_INC_CI       (1 << 24)
145 #define MTHCA_TAVOR_CQ_DB_REQ_NOT      (2 << 24)
146 #define MTHCA_TAVOR_CQ_DB_REQ_NOT_SOL  (3 << 24)
147 #define MTHCA_TAVOR_CQ_DB_SET_CI       (4 << 24)
148 #define MTHCA_TAVOR_CQ_DB_REQ_NOT_MULT (5 << 24)
149
150 #define MTHCA_ARBEL_CQ_DB_REQ_NOT_SOL  (1 << 24)
151 #define MTHCA_ARBEL_CQ_DB_REQ_NOT      (2 << 24)
152 #define MTHCA_ARBEL_CQ_DB_REQ_NOT_MULT (3 << 24)
153
154 static inline struct mthca_cqe *get_cqe_from_buf(struct mthca_cq_buf *buf,
155                                                  int entry)
156 {
157         if (buf->is_direct)
158                 return buf->queue.direct.buf + (entry * MTHCA_CQ_ENTRY_SIZE);
159         else
160                 return buf->queue.page_list[entry * MTHCA_CQ_ENTRY_SIZE / PAGE_SIZE].buf
161                         + (entry * MTHCA_CQ_ENTRY_SIZE) % PAGE_SIZE;
162 }
163
164 static inline struct mthca_cqe *get_cqe(struct mthca_cq *cq, int entry)
165 {
166         return get_cqe_from_buf(&cq->buf, entry);
167 }
168
169 static inline struct mthca_cqe *cqe_sw(struct mthca_cqe *cqe)
170 {
171         return MTHCA_CQ_ENTRY_OWNER_HW & cqe->owner ? NULL : cqe;
172 }
173
174 static inline struct mthca_cqe *next_cqe_sw(struct mthca_cq *cq)
175 {
176         return cqe_sw(get_cqe(cq, cq->cons_index & cq->ibcq.cqe));
177 }
178
179 static inline void set_cqe_hw(struct mthca_cqe *cqe)
180 {
181         cqe->owner = MTHCA_CQ_ENTRY_OWNER_HW;
182 }
183
184 static void dump_cqe(struct mthca_dev *dev, void *cqe_ptr)
185 {
186         __be32 *cqe = cqe_ptr;
187
188         (void) cqe;     /* avoid warning if mthca_dbg compiled away... */
189         mthca_dbg(dev, "CQE contents %08x %08x %08x %08x %08x %08x %08x %08x\n",
190                   be32_to_cpu(cqe[0]), be32_to_cpu(cqe[1]), be32_to_cpu(cqe[2]),
191                   be32_to_cpu(cqe[3]), be32_to_cpu(cqe[4]), be32_to_cpu(cqe[5]),
192                   be32_to_cpu(cqe[6]), be32_to_cpu(cqe[7]));
193 }
194
195 /*
196  * incr is ignored in native Arbel (mem-free) mode, so cq->cons_index
197  * should be correct before calling update_cons_index().
198  */
199 static inline void update_cons_index(struct mthca_dev *dev, struct mthca_cq *cq,
200                                      int incr)
201 {
202         __be32 doorbell[2];
203
204         if (mthca_is_memfree(dev)) {
205                 *cq->set_ci_db = cpu_to_be32(cq->cons_index);
206                 wmb();
207         } else {
208                 doorbell[0] = cpu_to_be32(MTHCA_TAVOR_CQ_DB_INC_CI | cq->cqn);
209                 doorbell[1] = cpu_to_be32(incr - 1);
210
211                 mthca_write64(doorbell,
212                               dev->kar + MTHCA_CQ_DOORBELL,
213                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
214                 /*
215                  * Make sure doorbells don't leak out of CQ spinlock
216                  * and reach the HCA out of order:
217                  */
218                 mmiowb();
219         }
220 }
221
222 void mthca_cq_completion(struct mthca_dev *dev, u32 cqn)
223 {
224         struct mthca_cq *cq;
225
226         cq = mthca_array_get(&dev->cq_table.cq, cqn & (dev->limits.num_cqs - 1));
227
228         if (!cq) {
229                 mthca_warn(dev, "Completion event for bogus CQ %08x\n", cqn);
230                 return;
231         }
232
233         ++cq->arm_sn;
234
235         cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context);
236 }
237
238 void mthca_cq_event(struct mthca_dev *dev, u32 cqn,
239                     enum ib_event_type event_type)
240 {
241         struct mthca_cq *cq;
242         struct ib_event event;
243
244         spin_lock(&dev->cq_table.lock);
245
246         cq = mthca_array_get(&dev->cq_table.cq, cqn & (dev->limits.num_cqs - 1));
247         if (cq)
248                 ++cq->refcount;
249
250         spin_unlock(&dev->cq_table.lock);
251
252         if (!cq) {
253                 mthca_warn(dev, "Async event for bogus CQ %08x\n", cqn);
254                 return;
255         }
256
257         event.device      = &dev->ib_dev;
258         event.event       = event_type;
259         event.element.cq  = &cq->ibcq;
260         if (cq->ibcq.event_handler)
261                 cq->ibcq.event_handler(&event, cq->ibcq.cq_context);
262
263         spin_lock(&dev->cq_table.lock);
264         if (!--cq->refcount)
265                 wake_up(&cq->wait);
266         spin_unlock(&dev->cq_table.lock);
267 }
268
269 static inline int is_recv_cqe(struct mthca_cqe *cqe)
270 {
271         if ((cqe->opcode & MTHCA_ERROR_CQE_OPCODE_MASK) ==
272             MTHCA_ERROR_CQE_OPCODE_MASK)
273                 return !(cqe->opcode & 0x01);
274         else
275                 return !(cqe->is_send & 0x80);
276 }
277
278 void mthca_cq_clean(struct mthca_dev *dev, struct mthca_cq *cq, u32 qpn,
279                     struct mthca_srq *srq)
280 {
281         struct mthca_cqe *cqe;
282         u32 prod_index;
283         int nfreed = 0;
284
285         spin_lock_irq(&cq->lock);
286
287         /*
288          * First we need to find the current producer index, so we
289          * know where to start cleaning from.  It doesn't matter if HW
290          * adds new entries after this loop -- the QP we're worried
291          * about is already in RESET, so the new entries won't come
292          * from our QP and therefore don't need to be checked.
293          */
294         for (prod_index = cq->cons_index;
295              cqe_sw(get_cqe(cq, prod_index & cq->ibcq.cqe));
296              ++prod_index)
297                 if (prod_index == cq->cons_index + cq->ibcq.cqe)
298                         break;
299
300         if (0)
301                 mthca_dbg(dev, "Cleaning QPN %06x from CQN %06x; ci %d, pi %d\n",
302                           qpn, cq->cqn, cq->cons_index, prod_index);
303
304         /*
305          * Now sweep backwards through the CQ, removing CQ entries
306          * that match our QP by copying older entries on top of them.
307          */
308         while ((int) --prod_index - (int) cq->cons_index >= 0) {
309                 cqe = get_cqe(cq, prod_index & cq->ibcq.cqe);
310                 if (cqe->my_qpn == cpu_to_be32(qpn)) {
311                         if (srq && is_recv_cqe(cqe))
312                                 mthca_free_srq_wqe(srq, be32_to_cpu(cqe->wqe));
313                         ++nfreed;
314                 } else if (nfreed)
315                         memcpy(get_cqe(cq, (prod_index + nfreed) & cq->ibcq.cqe),
316                                cqe, MTHCA_CQ_ENTRY_SIZE);
317         }
318
319         if (nfreed) {
320                 wmb();
321                 cq->cons_index += nfreed;
322                 update_cons_index(dev, cq, nfreed);
323         }
324
325         spin_unlock_irq(&cq->lock);
326 }
327
328 void mthca_cq_resize_copy_cqes(struct mthca_cq *cq)
329 {
330         int i;
331
332         /*
333          * In Tavor mode, the hardware keeps the consumer and producer
334          * indices mod the CQ size.  Since we might be making the CQ
335          * bigger, we need to deal with the case where the producer
336          * index wrapped around before the CQ was resized.
337          */
338         if (!mthca_is_memfree(to_mdev(cq->ibcq.device)) &&
339             cq->ibcq.cqe < cq->resize_buf->cqe) {
340                 cq->cons_index &= cq->ibcq.cqe;
341                 if (cqe_sw(get_cqe(cq, cq->ibcq.cqe)))
342                         cq->cons_index -= cq->ibcq.cqe + 1;
343         }
344
345         for (i = cq->cons_index; cqe_sw(get_cqe(cq, i & cq->ibcq.cqe)); ++i)
346                 memcpy(get_cqe_from_buf(&cq->resize_buf->buf,
347                                         i & cq->resize_buf->cqe),
348                        get_cqe(cq, i & cq->ibcq.cqe), MTHCA_CQ_ENTRY_SIZE);
349 }
350
351 int mthca_alloc_cq_buf(struct mthca_dev *dev, struct mthca_cq_buf *buf, int nent)
352 {
353         int ret;
354         int i;
355
356         ret = mthca_buf_alloc(dev, nent * MTHCA_CQ_ENTRY_SIZE,
357                               MTHCA_MAX_DIRECT_CQ_SIZE,
358                               &buf->queue, &buf->is_direct,
359                               &dev->driver_pd, 1, &buf->mr);
360         if (ret)
361                 return ret;
362
363         for (i = 0; i < nent; ++i)
364                 set_cqe_hw(get_cqe_from_buf(buf, i));
365
366         return 0;
367 }
368
369 void mthca_free_cq_buf(struct mthca_dev *dev, struct mthca_cq_buf *buf, int cqe)
370 {
371         mthca_buf_free(dev, (cqe + 1) * MTHCA_CQ_ENTRY_SIZE, &buf->queue,
372                        buf->is_direct, &buf->mr);
373 }
374
375 static void handle_error_cqe(struct mthca_dev *dev, struct mthca_cq *cq,
376                              struct mthca_qp *qp, int wqe_index, int is_send,
377                              struct mthca_err_cqe *cqe,
378                              struct ib_wc *entry, int *free_cqe)
379 {
380         int dbd;
381         __be32 new_wqe;
382
383         if (cqe->syndrome == SYNDROME_LOCAL_QP_OP_ERR) {
384                 mthca_dbg(dev, "local QP operation err "
385                           "(QPN %06x, WQE @ %08x, CQN %06x, index %d)\n",
386                           be32_to_cpu(cqe->my_qpn), be32_to_cpu(cqe->wqe),
387                           cq->cqn, cq->cons_index);
388                 dump_cqe(dev, cqe);
389         }
390
391         /*
392          * For completions in error, only work request ID, status, vendor error
393          * (and freed resource count for RD) have to be set.
394          */
395         switch (cqe->syndrome) {
396         case SYNDROME_LOCAL_LENGTH_ERR:
397                 entry->status = IB_WC_LOC_LEN_ERR;
398                 break;
399         case SYNDROME_LOCAL_QP_OP_ERR:
400                 entry->status = IB_WC_LOC_QP_OP_ERR;
401                 break;
402         case SYNDROME_LOCAL_EEC_OP_ERR:
403                 entry->status = IB_WC_LOC_EEC_OP_ERR;
404                 break;
405         case SYNDROME_LOCAL_PROT_ERR:
406                 entry->status = IB_WC_LOC_PROT_ERR;
407                 break;
408         case SYNDROME_WR_FLUSH_ERR:
409                 entry->status = IB_WC_WR_FLUSH_ERR;
410                 break;
411         case SYNDROME_MW_BIND_ERR:
412                 entry->status = IB_WC_MW_BIND_ERR;
413                 break;
414         case SYNDROME_BAD_RESP_ERR:
415                 entry->status = IB_WC_BAD_RESP_ERR;
416                 break;
417         case SYNDROME_LOCAL_ACCESS_ERR:
418                 entry->status = IB_WC_LOC_ACCESS_ERR;
419                 break;
420         case SYNDROME_REMOTE_INVAL_REQ_ERR:
421                 entry->status = IB_WC_REM_INV_REQ_ERR;
422                 break;
423         case SYNDROME_REMOTE_ACCESS_ERR:
424                 entry->status = IB_WC_REM_ACCESS_ERR;
425                 break;
426         case SYNDROME_REMOTE_OP_ERR:
427                 entry->status = IB_WC_REM_OP_ERR;
428                 break;
429         case SYNDROME_RETRY_EXC_ERR:
430                 entry->status = IB_WC_RETRY_EXC_ERR;
431                 break;
432         case SYNDROME_RNR_RETRY_EXC_ERR:
433                 entry->status = IB_WC_RNR_RETRY_EXC_ERR;
434                 break;
435         case SYNDROME_LOCAL_RDD_VIOL_ERR:
436                 entry->status = IB_WC_LOC_RDD_VIOL_ERR;
437                 break;
438         case SYNDROME_REMOTE_INVAL_RD_REQ_ERR:
439                 entry->status = IB_WC_REM_INV_RD_REQ_ERR;
440                 break;
441         case SYNDROME_REMOTE_ABORTED_ERR:
442                 entry->status = IB_WC_REM_ABORT_ERR;
443                 break;
444         case SYNDROME_INVAL_EECN_ERR:
445                 entry->status = IB_WC_INV_EECN_ERR;
446                 break;
447         case SYNDROME_INVAL_EEC_STATE_ERR:
448                 entry->status = IB_WC_INV_EEC_STATE_ERR;
449                 break;
450         default:
451                 entry->status = IB_WC_GENERAL_ERR;
452                 break;
453         }
454
455         entry->vendor_err = cqe->vendor_err;
456
457         /*
458          * Mem-free HCAs always generate one CQE per WQE, even in the
459          * error case, so we don't have to check the doorbell count, etc.
460          */
461         if (mthca_is_memfree(dev))
462                 return;
463
464         mthca_free_err_wqe(dev, qp, is_send, wqe_index, &dbd, &new_wqe);
465
466         /*
467          * If we're at the end of the WQE chain, or we've used up our
468          * doorbell count, free the CQE.  Otherwise just update it for
469          * the next poll operation.
470          */
471         if (!(new_wqe & cpu_to_be32(0x3f)) || (!cqe->db_cnt && dbd))
472                 return;
473
474         cqe->db_cnt   = cpu_to_be16(be16_to_cpu(cqe->db_cnt) - dbd);
475         cqe->wqe      = new_wqe;
476         cqe->syndrome = SYNDROME_WR_FLUSH_ERR;
477
478         *free_cqe = 0;
479 }
480
481 static inline int mthca_poll_one(struct mthca_dev *dev,
482                                  struct mthca_cq *cq,
483                                  struct mthca_qp **cur_qp,
484                                  int *freed,
485                                  struct ib_wc *entry)
486 {
487         struct mthca_wq *wq;
488         struct mthca_cqe *cqe;
489         int wqe_index;
490         int is_error;
491         int is_send;
492         int free_cqe = 1;
493         int err = 0;
494
495         cqe = next_cqe_sw(cq);
496         if (!cqe)
497                 return -EAGAIN;
498
499         /*
500          * Make sure we read CQ entry contents after we've checked the
501          * ownership bit.
502          */
503         rmb();
504
505         if (0) {
506                 mthca_dbg(dev, "%x/%d: CQE -> QPN %06x, WQE @ %08x\n",
507                           cq->cqn, cq->cons_index, be32_to_cpu(cqe->my_qpn),
508                           be32_to_cpu(cqe->wqe));
509                 dump_cqe(dev, cqe);
510         }
511
512         is_error = (cqe->opcode & MTHCA_ERROR_CQE_OPCODE_MASK) ==
513                 MTHCA_ERROR_CQE_OPCODE_MASK;
514         is_send  = is_error ? cqe->opcode & 0x01 : cqe->is_send & 0x80;
515
516         if (!*cur_qp || be32_to_cpu(cqe->my_qpn) != (*cur_qp)->qpn) {
517                 /*
518                  * We do not have to take the QP table lock here,
519                  * because CQs will be locked while QPs are removed
520                  * from the table.
521                  */
522                 *cur_qp = mthca_array_get(&dev->qp_table.qp,
523                                           be32_to_cpu(cqe->my_qpn) &
524                                           (dev->limits.num_qps - 1));
525                 if (!*cur_qp) {
526                         mthca_warn(dev, "CQ entry for unknown QP %06x\n",
527                                    be32_to_cpu(cqe->my_qpn) & 0xffffff);
528                         err = -EINVAL;
529                         goto out;
530                 }
531         }
532
533         entry->qp_num = (*cur_qp)->qpn;
534
535         if (is_send) {
536                 wq = &(*cur_qp)->sq;
537                 wqe_index = ((be32_to_cpu(cqe->wqe) - (*cur_qp)->send_wqe_offset)
538                              >> wq->wqe_shift);
539                 entry->wr_id = (*cur_qp)->wrid[wqe_index +
540                                                (*cur_qp)->rq.max];
541         } else if ((*cur_qp)->ibqp.srq) {
542                 struct mthca_srq *srq = to_msrq((*cur_qp)->ibqp.srq);
543                 u32 wqe = be32_to_cpu(cqe->wqe);
544                 wq = NULL;
545                 wqe_index = wqe >> srq->wqe_shift;
546                 entry->wr_id = srq->wrid[wqe_index];
547                 mthca_free_srq_wqe(srq, wqe);
548         } else {
549                 s32 wqe;
550                 wq = &(*cur_qp)->rq;
551                 wqe = be32_to_cpu(cqe->wqe);
552                 wqe_index = wqe >> wq->wqe_shift;
553                 /*
554                  * WQE addr == base - 1 might be reported in receive completion
555                  * with error instead of (rq size - 1) by Sinai FW 1.0.800 and
556                  * Arbel FW 5.1.400.  This bug should be fixed in later FW revs.
557                  */
558                 if (unlikely(wqe_index < 0))
559                         wqe_index = wq->max - 1;
560                 entry->wr_id = (*cur_qp)->wrid[wqe_index];
561         }
562
563         if (wq) {
564                 if (wq->last_comp < wqe_index)
565                         wq->tail += wqe_index - wq->last_comp;
566                 else
567                         wq->tail += wqe_index + wq->max - wq->last_comp;
568
569                 wq->last_comp = wqe_index;
570         }
571
572         if (is_error) {
573                 handle_error_cqe(dev, cq, *cur_qp, wqe_index, is_send,
574                                  (struct mthca_err_cqe *) cqe,
575                                  entry, &free_cqe);
576                 goto out;
577         }
578
579         if (is_send) {
580                 entry->wc_flags = 0;
581                 switch (cqe->opcode) {
582                 case MTHCA_OPCODE_RDMA_WRITE:
583                         entry->opcode    = IB_WC_RDMA_WRITE;
584                         break;
585                 case MTHCA_OPCODE_RDMA_WRITE_IMM:
586                         entry->opcode    = IB_WC_RDMA_WRITE;
587                         entry->wc_flags |= IB_WC_WITH_IMM;
588                         break;
589                 case MTHCA_OPCODE_SEND:
590                         entry->opcode    = IB_WC_SEND;
591                         break;
592                 case MTHCA_OPCODE_SEND_IMM:
593                         entry->opcode    = IB_WC_SEND;
594                         entry->wc_flags |= IB_WC_WITH_IMM;
595                         break;
596                 case MTHCA_OPCODE_RDMA_READ:
597                         entry->opcode    = IB_WC_RDMA_READ;
598                         entry->byte_len  = be32_to_cpu(cqe->byte_cnt);
599                         break;
600                 case MTHCA_OPCODE_ATOMIC_CS:
601                         entry->opcode    = IB_WC_COMP_SWAP;
602                         entry->byte_len  = be32_to_cpu(cqe->byte_cnt);
603                         break;
604                 case MTHCA_OPCODE_ATOMIC_FA:
605                         entry->opcode    = IB_WC_FETCH_ADD;
606                         entry->byte_len  = be32_to_cpu(cqe->byte_cnt);
607                         break;
608                 case MTHCA_OPCODE_BIND_MW:
609                         entry->opcode    = IB_WC_BIND_MW;
610                         break;
611                 default:
612                         entry->opcode    = MTHCA_OPCODE_INVALID;
613                         break;
614                 }
615         } else {
616                 entry->byte_len = be32_to_cpu(cqe->byte_cnt);
617                 switch (cqe->opcode & 0x1f) {
618                 case IB_OPCODE_SEND_LAST_WITH_IMMEDIATE:
619                 case IB_OPCODE_SEND_ONLY_WITH_IMMEDIATE:
620                         entry->wc_flags = IB_WC_WITH_IMM;
621                         entry->imm_data = cqe->imm_etype_pkey_eec;
622                         entry->opcode = IB_WC_RECV;
623                         break;
624                 case IB_OPCODE_RDMA_WRITE_LAST_WITH_IMMEDIATE:
625                 case IB_OPCODE_RDMA_WRITE_ONLY_WITH_IMMEDIATE:
626                         entry->wc_flags = IB_WC_WITH_IMM;
627                         entry->imm_data = cqe->imm_etype_pkey_eec;
628                         entry->opcode = IB_WC_RECV_RDMA_WITH_IMM;
629                         break;
630                 default:
631                         entry->wc_flags = 0;
632                         entry->opcode = IB_WC_RECV;
633                         break;
634                 }
635                 entry->slid        = be16_to_cpu(cqe->rlid);
636                 entry->sl          = be16_to_cpu(cqe->sl_g_mlpath) >> 12;
637                 entry->src_qp      = be32_to_cpu(cqe->rqpn) & 0xffffff;
638                 entry->dlid_path_bits = be16_to_cpu(cqe->sl_g_mlpath) & 0x7f;
639                 entry->pkey_index  = be32_to_cpu(cqe->imm_etype_pkey_eec) >> 16;
640                 entry->wc_flags   |= be16_to_cpu(cqe->sl_g_mlpath) & 0x80 ?
641                                         IB_WC_GRH : 0;
642         }
643
644         entry->status = IB_WC_SUCCESS;
645
646  out:
647         if (likely(free_cqe)) {
648                 set_cqe_hw(cqe);
649                 ++(*freed);
650                 ++cq->cons_index;
651         }
652
653         return err;
654 }
655
656 int mthca_poll_cq(struct ib_cq *ibcq, int num_entries,
657                   struct ib_wc *entry)
658 {
659         struct mthca_dev *dev = to_mdev(ibcq->device);
660         struct mthca_cq *cq = to_mcq(ibcq);
661         struct mthca_qp *qp = NULL;
662         unsigned long flags;
663         int err = 0;
664         int freed = 0;
665         int npolled;
666
667         spin_lock_irqsave(&cq->lock, flags);
668
669         npolled = 0;
670 repoll:
671         while (npolled < num_entries) {
672                 err = mthca_poll_one(dev, cq, &qp,
673                                      &freed, entry + npolled);
674                 if (err)
675                         break;
676                 ++npolled;
677         }
678
679         if (freed) {
680                 wmb();
681                 update_cons_index(dev, cq, freed);
682         }
683
684         /*
685          * If a CQ resize is in progress and we discovered that the
686          * old buffer is empty, then peek in the new buffer, and if
687          * it's not empty, switch to the new buffer and continue
688          * polling there.
689          */
690         if (unlikely(err == -EAGAIN && cq->resize_buf &&
691                      cq->resize_buf->state == CQ_RESIZE_READY)) {
692                 /*
693                  * In Tavor mode, the hardware keeps the producer
694                  * index modulo the CQ size.  Since we might be making
695                  * the CQ bigger, we need to mask our consumer index
696                  * using the size of the old CQ buffer before looking
697                  * in the new CQ buffer.
698                  */
699                 if (!mthca_is_memfree(dev))
700                         cq->cons_index &= cq->ibcq.cqe;
701
702                 if (cqe_sw(get_cqe_from_buf(&cq->resize_buf->buf,
703                                             cq->cons_index & cq->resize_buf->cqe))) {
704                         struct mthca_cq_buf tbuf;
705                         int tcqe;
706
707                         tbuf         = cq->buf;
708                         tcqe         = cq->ibcq.cqe;
709                         cq->buf      = cq->resize_buf->buf;
710                         cq->ibcq.cqe = cq->resize_buf->cqe;
711
712                         cq->resize_buf->buf   = tbuf;
713                         cq->resize_buf->cqe   = tcqe;
714                         cq->resize_buf->state = CQ_RESIZE_SWAPPED;
715
716                         goto repoll;
717                 }
718         }
719
720         spin_unlock_irqrestore(&cq->lock, flags);
721
722         return err == 0 || err == -EAGAIN ? npolled : err;
723 }
724
725 int mthca_tavor_arm_cq(struct ib_cq *cq, enum ib_cq_notify notify)
726 {
727         __be32 doorbell[2];
728
729         doorbell[0] = cpu_to_be32((notify == IB_CQ_SOLICITED ?
730                                    MTHCA_TAVOR_CQ_DB_REQ_NOT_SOL :
731                                    MTHCA_TAVOR_CQ_DB_REQ_NOT)      |
732                                   to_mcq(cq)->cqn);
733         doorbell[1] = (__force __be32) 0xffffffff;
734
735         mthca_write64(doorbell,
736                       to_mdev(cq->device)->kar + MTHCA_CQ_DOORBELL,
737                       MTHCA_GET_DOORBELL_LOCK(&to_mdev(cq->device)->doorbell_lock));
738
739         return 0;
740 }
741
742 int mthca_arbel_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify notify)
743 {
744         struct mthca_cq *cq = to_mcq(ibcq);
745         __be32 doorbell[2];
746         u32 sn;
747         __be32 ci;
748
749         sn = cq->arm_sn & 3;
750         ci = cpu_to_be32(cq->cons_index);
751
752         doorbell[0] = ci;
753         doorbell[1] = cpu_to_be32((cq->cqn << 8) | (2 << 5) | (sn << 3) |
754                                   (notify == IB_CQ_SOLICITED ? 1 : 2));
755
756         mthca_write_db_rec(doorbell, cq->arm_db);
757
758         /*
759          * Make sure that the doorbell record in host memory is
760          * written before ringing the doorbell via PCI MMIO.
761          */
762         wmb();
763
764         doorbell[0] = cpu_to_be32((sn << 28)                       |
765                                   (notify == IB_CQ_SOLICITED ?
766                                    MTHCA_ARBEL_CQ_DB_REQ_NOT_SOL :
767                                    MTHCA_ARBEL_CQ_DB_REQ_NOT)      |
768                                   cq->cqn);
769         doorbell[1] = ci;
770
771         mthca_write64(doorbell,
772                       to_mdev(ibcq->device)->kar + MTHCA_CQ_DOORBELL,
773                       MTHCA_GET_DOORBELL_LOCK(&to_mdev(ibcq->device)->doorbell_lock));
774
775         return 0;
776 }
777
778 int mthca_init_cq(struct mthca_dev *dev, int nent,
779                   struct mthca_ucontext *ctx, u32 pdn,
780                   struct mthca_cq *cq)
781 {
782         struct mthca_mailbox *mailbox;
783         struct mthca_cq_context *cq_context;
784         int err = -ENOMEM;
785         u8 status;
786
787         cq->ibcq.cqe  = nent - 1;
788         cq->is_kernel = !ctx;
789
790         cq->cqn = mthca_alloc(&dev->cq_table.alloc);
791         if (cq->cqn == -1)
792                 return -ENOMEM;
793
794         if (mthca_is_memfree(dev)) {
795                 err = mthca_table_get(dev, dev->cq_table.table, cq->cqn);
796                 if (err)
797                         goto err_out;
798
799                 if (cq->is_kernel) {
800                         cq->arm_sn = 1;
801
802                         err = -ENOMEM;
803
804                         cq->set_ci_db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_CQ_SET_CI,
805                                                              cq->cqn, &cq->set_ci_db);
806                         if (cq->set_ci_db_index < 0)
807                                 goto err_out_icm;
808
809                         cq->arm_db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_CQ_ARM,
810                                                           cq->cqn, &cq->arm_db);
811                         if (cq->arm_db_index < 0)
812                                 goto err_out_ci;
813                 }
814         }
815
816         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
817         if (IS_ERR(mailbox))
818                 goto err_out_arm;
819
820         cq_context = mailbox->buf;
821
822         if (cq->is_kernel) {
823                 err = mthca_alloc_cq_buf(dev, &cq->buf, nent);
824                 if (err)
825                         goto err_out_mailbox;
826         }
827
828         spin_lock_init(&cq->lock);
829         cq->refcount = 1;
830         init_waitqueue_head(&cq->wait);
831         mutex_init(&cq->mutex);
832
833         memset(cq_context, 0, sizeof *cq_context);
834         cq_context->flags           = cpu_to_be32(MTHCA_CQ_STATUS_OK      |
835                                                   MTHCA_CQ_STATE_DISARMED |
836                                                   MTHCA_CQ_FLAG_TR);
837         cq_context->logsize_usrpage = cpu_to_be32((ffs(nent) - 1) << 24);
838         if (ctx)
839                 cq_context->logsize_usrpage |= cpu_to_be32(ctx->uar.index);
840         else
841                 cq_context->logsize_usrpage |= cpu_to_be32(dev->driver_uar.index);
842         cq_context->error_eqn       = cpu_to_be32(dev->eq_table.eq[MTHCA_EQ_ASYNC].eqn);
843         cq_context->comp_eqn        = cpu_to_be32(dev->eq_table.eq[MTHCA_EQ_COMP].eqn);
844         cq_context->pd              = cpu_to_be32(pdn);
845         cq_context->lkey            = cpu_to_be32(cq->buf.mr.ibmr.lkey);
846         cq_context->cqn             = cpu_to_be32(cq->cqn);
847
848         if (mthca_is_memfree(dev)) {
849                 cq_context->ci_db    = cpu_to_be32(cq->set_ci_db_index);
850                 cq_context->state_db = cpu_to_be32(cq->arm_db_index);
851         }
852
853         err = mthca_SW2HW_CQ(dev, mailbox, cq->cqn, &status);
854         if (err) {
855                 mthca_warn(dev, "SW2HW_CQ failed (%d)\n", err);
856                 goto err_out_free_mr;
857         }
858
859         if (status) {
860                 mthca_warn(dev, "SW2HW_CQ returned status 0x%02x\n",
861                            status);
862                 err = -EINVAL;
863                 goto err_out_free_mr;
864         }
865
866         spin_lock_irq(&dev->cq_table.lock);
867         if (mthca_array_set(&dev->cq_table.cq,
868                             cq->cqn & (dev->limits.num_cqs - 1),
869                             cq)) {
870                 spin_unlock_irq(&dev->cq_table.lock);
871                 goto err_out_free_mr;
872         }
873         spin_unlock_irq(&dev->cq_table.lock);
874
875         cq->cons_index = 0;
876
877         mthca_free_mailbox(dev, mailbox);
878
879         return 0;
880
881 err_out_free_mr:
882         if (cq->is_kernel)
883                 mthca_free_cq_buf(dev, &cq->buf, cq->ibcq.cqe);
884
885 err_out_mailbox:
886         mthca_free_mailbox(dev, mailbox);
887
888 err_out_arm:
889         if (cq->is_kernel && mthca_is_memfree(dev))
890                 mthca_free_db(dev, MTHCA_DB_TYPE_CQ_ARM, cq->arm_db_index);
891
892 err_out_ci:
893         if (cq->is_kernel && mthca_is_memfree(dev))
894                 mthca_free_db(dev, MTHCA_DB_TYPE_CQ_SET_CI, cq->set_ci_db_index);
895
896 err_out_icm:
897         mthca_table_put(dev, dev->cq_table.table, cq->cqn);
898
899 err_out:
900         mthca_free(&dev->cq_table.alloc, cq->cqn);
901
902         return err;
903 }
904
905 static inline int get_cq_refcount(struct mthca_dev *dev, struct mthca_cq *cq)
906 {
907         int c;
908
909         spin_lock_irq(&dev->cq_table.lock);
910         c = cq->refcount;
911         spin_unlock_irq(&dev->cq_table.lock);
912
913         return c;
914 }
915
916 void mthca_free_cq(struct mthca_dev *dev,
917                    struct mthca_cq *cq)
918 {
919         struct mthca_mailbox *mailbox;
920         int err;
921         u8 status;
922
923         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
924         if (IS_ERR(mailbox)) {
925                 mthca_warn(dev, "No memory for mailbox to free CQ.\n");
926                 return;
927         }
928
929         err = mthca_HW2SW_CQ(dev, mailbox, cq->cqn, &status);
930         if (err)
931                 mthca_warn(dev, "HW2SW_CQ failed (%d)\n", err);
932         else if (status)
933                 mthca_warn(dev, "HW2SW_CQ returned status 0x%02x\n", status);
934
935         if (0) {
936                 __be32 *ctx = mailbox->buf;
937                 int j;
938
939                 printk(KERN_ERR "context for CQN %x (cons index %x, next sw %d)\n",
940                        cq->cqn, cq->cons_index,
941                        cq->is_kernel ? !!next_cqe_sw(cq) : 0);
942                 for (j = 0; j < 16; ++j)
943                         printk(KERN_ERR "[%2x] %08x\n", j * 4, be32_to_cpu(ctx[j]));
944         }
945
946         spin_lock_irq(&dev->cq_table.lock);
947         mthca_array_clear(&dev->cq_table.cq,
948                           cq->cqn & (dev->limits.num_cqs - 1));
949         --cq->refcount;
950         spin_unlock_irq(&dev->cq_table.lock);
951
952         if (dev->mthca_flags & MTHCA_FLAG_MSI_X)
953                 synchronize_irq(dev->eq_table.eq[MTHCA_EQ_COMP].msi_x_vector);
954         else
955                 synchronize_irq(dev->pdev->irq);
956
957         wait_event(cq->wait, !get_cq_refcount(dev, cq));
958
959         if (cq->is_kernel) {
960                 mthca_free_cq_buf(dev, &cq->buf, cq->ibcq.cqe);
961                 if (mthca_is_memfree(dev)) {
962                         mthca_free_db(dev, MTHCA_DB_TYPE_CQ_ARM,    cq->arm_db_index);
963                         mthca_free_db(dev, MTHCA_DB_TYPE_CQ_SET_CI, cq->set_ci_db_index);
964                 }
965         }
966
967         mthca_table_put(dev, dev->cq_table.table, cq->cqn);
968         mthca_free(&dev->cq_table.alloc, cq->cqn);
969         mthca_free_mailbox(dev, mailbox);
970 }
971
972 int mthca_init_cq_table(struct mthca_dev *dev)
973 {
974         int err;
975
976         spin_lock_init(&dev->cq_table.lock);
977
978         err = mthca_alloc_init(&dev->cq_table.alloc,
979                                dev->limits.num_cqs,
980                                (1 << 24) - 1,
981                                dev->limits.reserved_cqs);
982         if (err)
983                 return err;
984
985         err = mthca_array_init(&dev->cq_table.cq,
986                                dev->limits.num_cqs);
987         if (err)
988                 mthca_alloc_cleanup(&dev->cq_table.alloc);
989
990         return err;
991 }
992
993 void mthca_cleanup_cq_table(struct mthca_dev *dev)
994 {
995         mthca_array_cleanup(&dev->cq_table.cq, dev->limits.num_cqs);
996         mthca_alloc_cleanup(&dev->cq_table.alloc);
997 }