1 #ifndef _ASM_X86_APIC_H
2 #define _ASM_X86_APIC_H
4 #include <linux/cpumask.h>
5 #include <linux/delay.h>
8 #include <asm/alternative.h>
9 #include <asm/cpufeature.h>
10 #include <asm/processor.h>
11 #include <asm/apicdef.h>
12 #include <asm/atomic.h>
13 #include <asm/fixmap.h>
14 #include <asm/mpspec.h>
15 #include <asm/system.h>
18 #define ARCH_APICTIMER_STOPS_ON_C3 1
24 #define APIC_VERBOSE 1
28 * Define the default level of output to be very little
29 * This can be turned up by using apic=verbose for more
30 * information and apic=debug for _lots_ of information.
31 * apic_verbosity is defined in apic.c
33 #define apic_printk(v, s, a...) do { \
34 if ((v) <= apic_verbosity) \
39 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32)
40 extern void generic_apic_probe(void);
42 static inline void generic_apic_probe(void)
47 #ifdef CONFIG_X86_LOCAL_APIC
49 extern unsigned int apic_verbosity;
50 extern int local_apic_timer_c2_ok;
52 extern int disable_apic;
55 extern void __inquire_remote_apic(int apicid);
56 #else /* CONFIG_SMP */
57 static inline void __inquire_remote_apic(int apicid)
60 #endif /* CONFIG_SMP */
62 static inline void default_inquire_remote_apic(int apicid)
64 if (apic_verbosity >= APIC_DEBUG)
65 __inquire_remote_apic(apicid);
69 * Basic functions accessing APICs.
71 #ifdef CONFIG_PARAVIRT
72 #include <asm/paravirt.h>
74 #define setup_boot_clock setup_boot_APIC_clock
75 #define setup_secondary_clock setup_secondary_APIC_clock
78 #ifdef CONFIG_X86_VSMP
79 extern int is_vsmp_box(void);
81 static inline int is_vsmp_box(void)
86 extern void xapic_wait_icr_idle(void);
87 extern u32 safe_xapic_wait_icr_idle(void);
88 extern void xapic_icr_write(u32, u32);
89 extern int setup_profiling_timer(unsigned int);
91 static inline void native_apic_mem_write(u32 reg, u32 v)
93 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg);
95 alternative_io("movl %0, %1", "xchgl %0, %1", X86_FEATURE_11AP,
96 ASM_OUTPUT2("=r" (v), "=m" (*addr)),
97 ASM_OUTPUT2("0" (v), "m" (*addr)));
100 static inline u32 native_apic_mem_read(u32 reg)
102 return *((volatile u32 *)(APIC_BASE + reg));
105 extern void native_apic_wait_icr_idle(void);
106 extern u32 native_safe_apic_wait_icr_idle(void);
107 extern void native_apic_icr_write(u32 low, u32 id);
108 extern u64 native_apic_icr_read(void);
110 #ifdef CONFIG_X86_X2APIC
111 static inline void native_apic_msr_write(u32 reg, u32 v)
113 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR ||
117 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);
120 static inline u32 native_apic_msr_read(u32 reg)
127 rdmsr(APIC_BASE_MSR + (reg >> 4), low, high);
131 static inline void native_x2apic_wait_icr_idle(void)
133 /* no need to wait for icr idle in x2apic */
137 static inline u32 native_safe_x2apic_wait_icr_idle(void)
139 /* no need to wait for icr idle in x2apic */
143 static inline void native_x2apic_icr_write(u32 low, u32 id)
145 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
148 static inline u64 native_x2apic_icr_read(void)
152 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
156 extern int x2apic, x2apic_phys;
157 extern void check_x2apic(void);
158 extern void enable_x2apic(void);
159 extern void enable_IR_x2apic(void);
160 extern void x2apic_icr_write(u32 low, u32 id);
161 static inline int x2apic_enabled(void)
168 rdmsr(MSR_IA32_APICBASE, msr, msr2);
169 if (msr & X2APIC_ENABLE)
174 static inline void check_x2apic(void)
177 static inline void enable_x2apic(void)
180 static inline void enable_IR_x2apic(void)
183 static inline int x2apic_enabled(void)
189 extern int get_physical_broadcast(void);
191 #ifdef CONFIG_X86_X2APIC
192 static inline void ack_x2APIC_irq(void)
194 /* Docs say use 0 for future compatibility */
195 native_apic_msr_write(APIC_EOI, 0);
199 extern int lapic_get_maxlvt(void);
200 extern void clear_local_APIC(void);
201 extern void connect_bsp_APIC(void);
202 extern void disconnect_bsp_APIC(int virt_wire_setup);
203 extern void disable_local_APIC(void);
204 extern void lapic_shutdown(void);
205 extern int verify_local_APIC(void);
206 extern void cache_APIC_registers(void);
207 extern void sync_Arb_IDs(void);
208 extern void init_bsp_APIC(void);
209 extern void setup_local_APIC(void);
210 extern void end_local_APIC_setup(void);
211 extern void init_apic_mappings(void);
212 extern void setup_boot_APIC_clock(void);
213 extern void setup_secondary_APIC_clock(void);
214 extern int APIC_init_uniprocessor(void);
215 extern void enable_NMI_through_LVT0(void);
218 * On 32bit this is mach-xxx local
221 extern void early_init_lapic_mapping(void);
222 extern int apic_is_clustered_box(void);
224 static inline int apic_is_clustered_box(void)
230 extern u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask);
231 extern u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask);
234 #else /* !CONFIG_X86_LOCAL_APIC */
235 static inline void lapic_shutdown(void) { }
236 #define local_apic_timer_c2_ok 1
237 static inline void init_apic_mappings(void) { }
238 static inline void disable_local_APIC(void) { }
240 #endif /* !CONFIG_X86_LOCAL_APIC */
243 #define SET_APIC_ID(x) (apic->set_apic_id(x))
249 * Copyright 2004 James Cleverdon, IBM.
250 * Subject to the GNU Public License, v.2
252 * Generic APIC sub-arch data struct.
254 * Hacked for x86-64 by James Cleverdon from i386 architecture code by
255 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and
262 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id);
263 int (*apic_id_registered)(void);
265 u32 irq_delivery_mode;
268 const struct cpumask *(*target_cpus)(void);
273 unsigned long (*check_apicid_used)(physid_mask_t bitmap, int apicid);
274 unsigned long (*check_apicid_present)(int apicid);
276 void (*vector_allocation_domain)(int cpu, struct cpumask *retmask);
277 void (*init_apic_ldr)(void);
279 physid_mask_t (*ioapic_phys_id_map)(physid_mask_t map);
281 void (*setup_apic_routing)(void);
282 int (*multi_timer_check)(int apic, int irq);
283 int (*apicid_to_node)(int logical_apicid);
284 int (*cpu_to_logical_apicid)(int cpu);
285 int (*cpu_present_to_apicid)(int mps_cpu);
286 physid_mask_t (*apicid_to_cpu_present)(int phys_apicid);
287 void (*setup_portio_remap)(void);
288 int (*check_phys_apicid_present)(int boot_cpu_physical_apicid);
289 void (*enable_apic_mode)(void);
290 int (*phys_pkg_id)(int cpuid_apic, int index_msb);
293 * When one of the next two hooks returns 1 the apic
294 * is switched to this. Essentially they are additional
297 int (*mps_oem_check)(struct mpc_table *mpc, char *oem, char *productid);
299 unsigned int (*get_apic_id)(unsigned long x);
300 unsigned long (*set_apic_id)(unsigned int id);
301 unsigned long apic_id_mask;
303 unsigned int (*cpu_mask_to_apicid)(const struct cpumask *cpumask);
304 unsigned int (*cpu_mask_to_apicid_and)(const struct cpumask *cpumask,
305 const struct cpumask *andmask);
308 void (*send_IPI_mask)(const struct cpumask *mask, int vector);
309 void (*send_IPI_mask_allbutself)(const struct cpumask *mask,
311 void (*send_IPI_allbutself)(int vector);
312 void (*send_IPI_all)(int vector);
313 void (*send_IPI_self)(int vector);
315 /* wakeup_secondary_cpu */
316 int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip);
318 int trampoline_phys_low;
319 int trampoline_phys_high;
321 void (*wait_for_init_deassert)(atomic_t *deassert);
322 void (*smp_callin_clear_local_apic)(void);
323 void (*inquire_remote_apic)(int apicid);
326 u32 (*read)(u32 reg);
327 void (*write)(u32 reg, u32 v);
328 u64 (*icr_read)(void);
329 void (*icr_write)(u32 low, u32 high);
330 void (*wait_icr_idle)(void);
331 u32 (*safe_wait_icr_idle)(void);
335 * Pointer to the local APIC driver in use on this system (there's
336 * always just one such driver in use - the kernel decides via an
337 * early probing process which one it picks - and then sticks to it):
339 extern struct apic *apic;
342 * APIC functionality to boot other CPUs - only used on SMP:
345 extern atomic_t init_deasserted;
346 extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip);
349 static inline u32 apic_read(u32 reg)
351 return apic->read(reg);
354 static inline void apic_write(u32 reg, u32 val)
356 apic->write(reg, val);
359 static inline u64 apic_icr_read(void)
361 return apic->icr_read();
364 static inline void apic_icr_write(u32 low, u32 high)
366 apic->icr_write(low, high);
369 static inline void apic_wait_icr_idle(void)
371 apic->wait_icr_idle();
374 static inline u32 safe_apic_wait_icr_idle(void)
376 return apic->safe_wait_icr_idle();
380 static inline void ack_APIC_irq(void)
383 * ack_APIC_irq() actually gets compiled as a single instruction
387 /* Docs say use 0 for future compatibility */
388 apic_write(APIC_EOI, 0);
391 static inline unsigned default_get_apic_id(unsigned long x)
393 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
396 return (x >> 24) & 0xFF;
398 return (x >> 24) & 0x0F;
402 * Warm reset vector default position:
404 #define DEFAULT_TRAMPOLINE_PHYS_LOW 0x467
405 #define DEFAULT_TRAMPOLINE_PHYS_HIGH 0x469
408 extern struct apic apic_flat;
409 extern struct apic apic_physflat;
410 extern struct apic apic_x2apic_cluster;
411 extern struct apic apic_x2apic_phys;
412 extern int default_acpi_madt_oem_check(char *, char *);
414 extern void apic_send_IPI_self(int vector);
416 extern struct apic apic_x2apic_uv_x;
417 DECLARE_PER_CPU(int, x2apic_extra_bits);
419 extern int default_cpu_present_to_apicid(int mps_cpu);
420 extern int default_check_phys_apicid_present(int boot_cpu_physical_apicid);
423 static inline void default_wait_for_init_deassert(atomic_t *deassert)
425 while (!atomic_read(deassert))
430 extern void generic_bigsmp_probe(void);
433 #ifdef CONFIG_X86_LOCAL_APIC
437 #define APIC_DFR_VALUE (APIC_DFR_FLAT)
439 static inline const struct cpumask *default_target_cpus(void)
442 return cpu_online_mask;
444 return cpumask_of(0);
448 DECLARE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid);
451 static inline unsigned int read_apic_id(void)
455 reg = apic_read(APIC_ID);
457 return apic->get_apic_id(reg);
460 extern void default_setup_apic_routing(void);
464 * Set up the logical destination ID.
466 * Intel recommends to set DFR, LDR and TPR before enabling
467 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
468 * document number 292116). So here it goes...
470 extern void default_init_apic_ldr(void);
472 static inline int default_apic_id_registered(void)
474 return physid_isset(read_apic_id(), phys_cpu_present_map);
477 static inline unsigned int
478 default_cpu_mask_to_apicid(const struct cpumask *cpumask)
480 return cpumask_bits(cpumask)[0];
483 static inline unsigned int
484 default_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
485 const struct cpumask *andmask)
487 unsigned long mask1 = cpumask_bits(cpumask)[0];
488 unsigned long mask2 = cpumask_bits(andmask)[0];
489 unsigned long mask3 = cpumask_bits(cpu_online_mask)[0];
491 return (unsigned int)(mask1 & mask2 & mask3);
494 static inline int default_phys_pkg_id(int cpuid_apic, int index_msb)
496 return cpuid_apic >> index_msb;
499 extern int default_apicid_to_node(int logical_apicid);
503 static inline unsigned long default_check_apicid_used(physid_mask_t bitmap, int apicid)
505 return physid_isset(apicid, bitmap);
508 static inline unsigned long default_check_apicid_present(int bit)
510 return physid_isset(bit, phys_cpu_present_map);
513 static inline physid_mask_t default_ioapic_phys_id_map(physid_mask_t phys_map)
518 /* Mapping from cpu number to logical apicid */
519 static inline int default_cpu_to_logical_apicid(int cpu)
524 static inline int __default_cpu_present_to_apicid(int mps_cpu)
526 if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu))
527 return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu);
533 __default_check_phys_apicid_present(int boot_cpu_physical_apicid)
535 return physid_isset(boot_cpu_physical_apicid, phys_cpu_present_map);
539 static inline int default_cpu_present_to_apicid(int mps_cpu)
541 return __default_cpu_present_to_apicid(mps_cpu);
545 default_check_phys_apicid_present(int boot_cpu_physical_apicid)
547 return __default_check_phys_apicid_present(boot_cpu_physical_apicid);
550 extern int default_cpu_present_to_apicid(int mps_cpu);
551 extern int default_check_phys_apicid_present(int boot_cpu_physical_apicid);
554 static inline physid_mask_t default_apicid_to_cpu_present(int phys_apicid)
556 return physid_mask_of_physid(phys_apicid);
559 #endif /* CONFIG_X86_LOCAL_APIC */
562 extern u8 cpu_2_logical_apicid[NR_CPUS];
565 #endif /* _ASM_X86_APIC_H */